經濟部中央標準局—工消費合作社印製 ^270 5 8 A7 B7 五、發明説明（） 癸明镅域= 本發明係有關於一種感知放大器電路，用以堪動固態 記憶體元件’特別是有關於一種用於多埠SRAM記憶元件 中之高速電流模式感知器之電路。 瘀明背景： 現今微電子元件及其市場要求的趨勢為低電耗電與高 元件密度’以縮小元件尺寸降低單位面積的製造成本，並 改進元件的性能。特別是半導體記憶元件’諸如DRAM與 SRAM即為兩種廣泛運用於個人電腦中以儲存影音資料之 記憶體元件。由於此種高密度而低耗電之記憶元件的需求 曰益增高’因此，一般位元線常要求是要連接幾十個記憶 胞的位元線。因此，流經位置記憶胞的之〇或1資料的電 流僅會在數十// A間變化。此外，一個指定位置資料的資 料匯流排（data bus )上被感測到也僅是小至數十或數百 mV的電壓而已。一般而言，一適當之感知放大器有必要用 以放大那些定址的資料以形成可分辨的數位信號。 第1圖為依照用於RAM與DRAM中習知技藝之感知 放大器電路200的實施例。感知放大器200包含電流指向 感知放大器電路（current-direction sense-amplifier circuit) 300 ’ 於差分放大器（differential amplifier) 400 ° NMOS電晶體Ml、M2、M3、M4、M5，與M6構成了電流 本紙張尺度通用中國國家橾準（CNS ) Α4規格（2[0X297公釐） I I IJ1 I I 1 i、1τ' r -!! <請先-Μ讀背面之注項再试寫本頁) 經濟部中夬標隼局员工消費合作社印製 &度適用 4?7〇58 A7 ________B7__ 五、發明説明（） 指向感知放大器電路300。電晶體M 1與M2互相以閘極耦 合’用以接收一訊號以開啟電路3〇〇，同時其汲極相耦合 以接收來自電源供應器的電壓Vdd ^電晶體M1與M2的猓 極則分別與節點nl與n0連接。電晶體M3與M4的汲極與 閘極分別交叉棒合於輸出節點nl與n〇。電晶體M5與M6 則以類似Μ 1、M2的方式以閘極相耦合用以接收電壓Vdd， 而以源極相Μ合以接收參考電壓VSS ^電晶體M5與M6的 汲極則與電晶體M3與M4的源極相連。另外，電晶體M3 的源極與輸入資料節點IN相連，用以接收來自與單端 C singal end )位元線相耦合之節點in的資料。 電流指向感知放大器電路3〇〇接收來自位元線1〇〇流 入或流出的電流，以產生兩個差分電位n〇、nl至差分放大 器 400。 差为放大器電路400包括兩個pm〇s電晶體U7與 U8，其中U7與U8形成一電流鏡像電路（current mirror circuit )，兩個NMOS電晶體U9與U10 ,其中U9與ul〇 係用以接收來自電流指向感知放大器3〇〇的輸出電壓n〇與 η卜而NMOS電晶體UU則用以接收—開啟訊號。差分放 大Is 400藉由一致能（enable)訊號開啟NM〇s電晶體⑴！ 而進行其功能運作。 電流指向感知放大器的操作，係以節點IN處的電流方 向為基礎。當電流流入節點IN，電晶體M3的源極電壓將 上升。這樣的結果造成了電晶體M3之電壓vgs (閘極至源 極的電壓）的下降，與電晶體M1之源極電壓的上升。因 中國國家標準（CNS > Α4規格（2丨0X297公釐） i T 1 In n 1.1 訂 .—Ϊ 線 (請先閱讀背面之注意事項再續寫本買) 經濟部中央標準局員工消費合作社印製 427〇58 A7 B7 五、發明説明（） 此，nl或Vnl節點的電歷上升。同時，電晶體M4之電壓 Vgs上升’如此增加了電晶艘M4的没極電流並造成了電晶 鱧M2之源極電屋的下降β因此節點n〇之電麼下降。節點 HO舆電晶趙M3的閘極相連’當VnO下降，電晶體M3之 Vgs的電壓將會進一步的下降，然後Vnl將更進一步的升 高。因此建立了一個正回销迴路。一介於nl與nO間的差 分電壓Δνΐ將會出現》 同理，當電流自IN流出時，電晶體M3的源極電壓會 降低。如此’造成了電晶體M3之Vgs的電壓增高與電晶 體Ml之源極電壓的降低。因此’節點ni的電壓下降，同 時’電晶體M4之Vgs的電壓會下降，於焉造成電晶體M4 之及極電流的降低與電晶體M3之Vgs的電屋更進一步的 增加。節點nl的電壓更進一步的降低。再一次，正回饋迴 路被建立而節點nl與nO間的差分電壓AV2將會出現。 然而’此正回饋電路電壓增益僅約為！，而n〇的電壓 變化則小於節點nl處的電壓變化》因此，當節點in處出 現增加電壓ΔΥ，其中一增多的差分電壓AV1=Vnl-VnO。 另一方面，當節點IN出現電壓降Δν，其中將產生一降低 的差分電壓Δ V2 = VnO-Vnl。故，增多電壓增益與降低電壓 迴路增益將不勻稱。 以電腦模擬的結果如第2圖到第5圖所示。在這些圈 中，資料訊號160由資料輸入端IN處被接收，然後訊號 170與180則分別自節點n0與nl處輸出。然後將訊號17〇 與180再輪入差分感知放大器400中，以自輸出端獲得數 本紙張尺度適用宁國國家標準（CNS ) A4规格（2丨〇 X 297公釐） -----------^------*玎------線 (請先却讀背面之注意事項再填寫本頁) ' 427〇S8 五、發明説明（） 位資料訊號190。第2明表示了典型之分別接收自節點ιΝ 的資料訊號之Δνΐ與AV2的變化。差分電壓Δνι與 的最大值分別只有大約0.35V與0.25V。為了達到產生對稱 差分增益的目標’吾人嘗試以一種調整位於電流感知放大 器電路300中NMOS電晶體通道寬度的方法來做電腦模 擬。然而，如同第3圖與第4圖所示，節點nO的電壓變化 相當小。節點η 1處較大的電壓變化，造成了較大差分電壓 Δνΐ與較小差分電壓AV2的現象。感知放大器200的輸出 數位訊號’特別當資料為’，低”時，將形成一尖突狀 (spike-like)的波型。另一方面’減量差分電壓的降 低給予了數位資料輸出”1，，較窄的寬度，如第5圖所表示。 而所有藉由調整電晶體尺寸’以增加nO處電壓變化的動作 都將無效。小迴珞電壓增益（如<〇·2ν之差分電壓）與非 對稱回路電壓增益將使電路承受製程變異的風險與雜訊的 干擾°因此，如何能增加迴路電壓增益與產生對稱的迴路 電壓增益’已經成為業界越來越重要的課題^ ---------袭------V (諳先閲讀背面之注意事項再域寫本頁) 述概及 的 S 明 Λ/t 經濟部中央標準局貝工消費合作衽印製 用感正 ， 向 一 器指第 大流之 放電中 知該其 感 。。 向號路 指訊迴 流料饋 電資回 種之正 1 取的 供讀合 提所耦 在線互 為元相 的位個 目胞兩 之憶含 明記包 發由器 本大大 放放 以知 出節 輸一 I 第 第於 、 號 號訊 訊的 料大 資放 收經 接個 以兩 用生 端產 入以 輪用 料點 資節 一 出 括輸 包二 路第 迴 、 饋點 回節 本紙張尺度適用中國國家標準（CNS) 规格（210x297公嫠〉 427058 A7 _____ _____B7_____ } 二節點。第二正回饋迴路包含第一 CMOS電容與第 點興沪 ,cM〇s電容。第一 CM〇S電容與第二CM〇s電容分別藉 問極输入端與輸出端而交又耦合。第二正回饋迴路則與 由zjt面饋迴路耦合於第一輸出節點以及第二輸出節點， 第進〆夕強化放大迴路電壓增益並使輸出端之電壓變化 用以& 對稱a 前述的内容與本發明伴隨而來的利益，將藉由圖示的 説明而更容易讓人明白，下面則為本發明的圖示說明。 第！圖為習知技藝中用於記憶體元件中的感知放大器； 第2圖為第1圖表示之電路的模擬結果； 第3圖為第1圖中之電晶體尺寸經調整過後的電路之 模擬結果； 第4圖為第1圊中之電晶體尺寸經調整過後的電路之 模擬結果； 第5圖為第1圖中之電晶體尺寸經調整過後的電路之 模擬結果； 第6圖為本發明中用於記憶體元件中的感知放大器；及 第7圖為第6圖表示之電路的模擬结果。 f明线細說明： 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0‘X297公釐） ----_-----裝------訂------線 f請先間讀背兩之注意事項再填寫衣頁j 經濟部中夬標準局員工消費合作社印裝 427058 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（） 如發明背景中所描述，其問題在於上述實施例中的單 正回饋迴路之電壓增益只約為1β另外，於兩輸出端點之 電壓變化為非對稱迴路電壓增益，該增益將使電路承擔製 程變異的風險與雜訊的干擾。因此，上述發明存在著増加 避路電壓增益與產生對稱迴路電壓增益的空間。 本發明組構了記憶體感知放大器電路，該電路包含差 分放大器電路400與修正之電流指向感知放大器電路 500。修正之電流指向感知放大器電路5〇〇包含第一正回饋 迴路520與第二正回饋迴路5 5〇，如第6圊所示。在一較 佳實施例中’與前述習知技藝中的正回销迴路3〇〇相同， 正回饋迴路300被用於本發明中的第一正回饋迴路520。 第一正回馈迴路具有兩個輸出節點n〇、nl與一個輸入節點 IN。輸入卽點in用以自記憶體元件的單端（sjng〖e_end ) 位元線接收資料訊號（圈中未表示）。在本較佳實施例中 的第二正回饋迴路550包含第一 CMOS電晶體551 (電晶 體MP丨與MN7 )與第二CMOS電晶體5 52 (電晶體MP2 與MN8 )。第一CMOS電晶體551與第二CMOS電晶體552 分別藉由閘極輸入端與輸出端相交又耦合。第一與第二 CMOS電晶體551與552的輸出端分別以標號kl與k0所 表示’並分別與節點nl與n0相耦合。pm〇S電晶體MP1 與MP2的源極接至電壓Vdd，而NMOS電晶體MN7與MN8 的源極接至電壓Vss。本發明之操作程序將如下所述： 與上述之習知技藝相類似，當電流流入節點IN，電晶 體MN8的閘極電壓的升高，增加了電晶體MNS之Vgs的 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 1 n 裝 訂 H 線 (請先聞讀背面之注意事項再填寫本頁) [4270 58 A7 B7 經濟部中央標準局貝工消費合作杜印製 五、發明説明（ 電壓，這樣的情形將有助於使電晶體MN8與MN4將節點 nO的電壓拉下。同時電晶體MPI之V§s的電壓的升高，增 加了電晶體MPI的源極電流’如此更增加了節點nl的電 壓。因此，節點nO與nl的電壓變化將會變得更大。 另一方面，當電流自資料輸入端IN流出時，資料輸入 端IN處電壓將減低△ V。電晶體MN3與MN4的操作與第ι 圖中的電晶體M3與M4相同。位於資料輪入端In處的電 壓降落Δν會造成輸出節點nl處的電壓降落，如此增加了 電晶體MP2之Vgs的電壓與降低了電晶體MN8之Vgs的 電壓。因此電晶體MP2源極電流的增加進一步致使輪出節 點nO處電壓的上升。亦即，電晶體MP2與電晶體MN2的 電壓拉高了輸出節點nO的電壓。同時，位於輸出節點nO 處電壓的升高，會降低電晶體MP1之Vgs的電壓同時增加 電晶體MN7之Vgs的電壓；因此，電晶體MN7會幫助電 晶體MN3拉下輸出節點nO處的電壓。亦即建立了 一第二 正回饋迴路，而輸出節點nl與nO處的電壓變化則會變得 更大。較大的迴路增益電壓於焉達成。第7圖為本發明的 模擬結果。在第7圖中資料訊號560係作為資料訊號之用， 其中該訊號乃接收自資料輸入端IN，然後訊號570與580 自節點11〇(或1:0)與111(或1^)輸出。之後訊號570與 5 80輸入差分感知放大器400中以獲得來自ouT端之數位 資料訊號。輸出資料”0”或”厂’的頻寬幾乎相同.位於節點 nO處的電壓增益則被強化，而差分電壓增益avi與AV2 亦同時被增強（例如，自約 0.3V(習知技藝）增強至約 (誇先閲讀背面之注意事項鼻4寫本頁) •赛. 本紙張尺度適用中國國家標準（CNS ) A4洗格（2丨OX297公釐） ^27058 A7 _ B7______ 五、發明説明（） 〇_6V(本發明）》 此外’對稱迴路電壓增益的調整可以更有弹性的藉著 適當調整電晶艘MP1、MP2、MN7與MN8的尺寸而完成。 本發明所帶來的利益有： (1) 差分電壓的下降或上升幅度都會被放大’因此可避 免製程變異的問題。 (2) 對稱迴路電壓增益可以很簡單的獲得。 本發明以一較佳實施例說明如上，僅用於藉以幫助了 解本發明之實施，非用以限定本發明之精神，而熟悉此領 域技藝者於領悟本發明之精神後，在不脫離本發明之精神 範圍内，當可作些許更動潤飾及等同之變化替換，其專利 保護範圍當視後附之申請專利範圍及其等同領域而定。 ---------裝-----一—訂------線 (請先^,讀背面之注意事項再填寫本頁) 經濟部中央橾隼局貝工消f合作社印裝 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Printed by the Central Standards Bureau of the Ministry of Economic Affairs—Industrial and Consumer Cooperatives ^ 270 5 8 A7 B7 V. Description of the invention () Guiming 镅 Domain = The present invention relates to a sense amplifier circuit used to move solid-state memory elements. In particular, there are A circuit for a high-speed current mode sensor used in a multi-port SRAM memory element. Background of stasis: The current trend of microelectronic components and their market requirements is low power consumption and high component density 'to reduce component size, reduce manufacturing costs per unit area, and improve component performance. In particular, semiconductor memory elements such as DRAM and SRAM are two types of memory elements which are widely used in personal computers to store audiovisual data. Because of the demand for such high-density and low-power memory elements, it is often required that bit lines be connected to dozens of memory cells. Therefore, the current flowing through the 0 or 1 data of the position memory cell will only change between tens of // A. In addition, only a voltage as small as tens or hundreds of mV is sensed on a data bus of a specified position data. In general, a suitable sense amplifier is necessary to amplify the addressed data to form a distinguishable digital signal. FIG. 1 is an embodiment of a sense amplifier circuit 200 according to a conventional technique used in RAM and DRAM. The sense amplifier 200 includes a current-direction sense-amplifier circuit 300 ′ and a differential amplifier 400 ° NMOS transistors Ml, M2, M3, M4, M5, and M6 constitute the current paper size General China National Standards (CNS) Α4 specification (2 [0X297 mm) II IJ1 II 1 i, 1τ 'r-!! < Please read the note on the back first and try to write this page) Ministry of Economic Affairs Printed by the Standards Bureau Consumer Cooperatives & Degree Applicable 4-7058 A7 ________B7__ V. Description of the invention () Pointing to the sense amplifier circuit 300. Transistors M 1 and M2 are gate-coupled to each other to receive a signal to turn on the circuit 300, and their drains are coupled to receive the voltage Vdd from the power supply. The transistors M1 and M2 have 猓 poles respectively. Connected to nodes nl and n0. The drains and gates of the transistors M3 and M4 are cross-connected to the output nodes nl and n0, respectively. Transistors M5 and M6 are coupled in a gate-like manner to receive the voltage Vdd in a similar manner to M1 and M2, while the source M is combined to receive the reference voltage VSS. The drains of the transistors M5 and M6 are connected to the transistor. M3 is connected to the source of M4. In addition, the source of the transistor M3 is connected to the input data node IN for receiving data from a node in coupled with a single-ended Csingal end bit line. The current is directed to the sense amplifier circuit 300 to receive the current flowing in or out from the bit line 100 to generate two differential potentials n0 and nl to the differential amplifier 400. The difference is that the amplifier circuit 400 includes two pMOS transistors U7 and U8, where U7 and U8 form a current mirror circuit, and two NMOS transistors U9 and U10, where U9 and ul〇 are used for receiving The output voltages no and n from the current-directed sense amplifier 300 are used for receiving and turning on the NMOS transistor UU. The differential amplifier Is 400 turns on the NMOS transistor with an enable signal! And perform its functional operation. The current is directed to the operation of the sense amplifier based on the direction of the current at node IN. When current flows into node IN, the source voltage of transistor M3 will rise. As a result, the voltage vgs (gate-to-source voltage) of transistor M3 decreases and the source voltage of transistor M1 increases. Due to Chinese National Standards (CNS > Α4 specifications (2 丨 0X297 mm) i T 1 In n 1.1 order.-Ϊ (please read the precautions on the back before continuing to write this). Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Printed 427〇58 A7 B7 V. Explanation of the invention () Therefore, the electric calendar of the node nl or Vnl rises. At the same time, the voltage Vgs of the transistor M4 rises', which increases the non-polar current of the transistor M4 and causes the transistor.源 The source of the M2's source house drops β, so the power of node n0 decreases. The node HO node's crystal M3's gate is connected. 'When VnO drops, the voltage of Vgs of transistor M3 will further decrease, and then Vnl It will increase further. Therefore, a positive return pin circuit is established. A differential voltage Δνΐ between nl and nO will appear. Similarly, when the current flows from IN, the source voltage of transistor M3 will decrease. In this way, the voltage of the Vgs of the transistor M3 is increased and the source voltage of the transistor M1 is reduced. Therefore, the voltage of the node ni is lowered, and at the same time, the voltage of the Vgs of the transistor M4 is lowered. The reduction of the polar current and the transistor M3 The electric house of Vgs is further increased. The voltage at node nl is further reduced. Once again, a positive feedback loop is established and a differential voltage AV2 between nodes nl and nO will appear. However, the voltage gain of this positive feedback circuit is only about For !, and the voltage change at no is smaller than the voltage change at node nl. Therefore, when the node Δ increases the voltage ΔΥ, one of the increased differential voltages AV1 = Vnl-VnO. On the other hand, when the voltage at node IN appears Drop Δν, which will produce a reduced differential voltage Δ V2 = VnO-Vnl. Therefore, increasing the voltage gain and decreasing the voltage loop gain will be uneven. The results of computer simulation are shown in Figure 2 to Figure 5. In these In the circle, the data signal 160 is received by the data input terminal IN, and then the signals 170 and 180 are output from the nodes n0 and nl, respectively. Then the signals 170 and 180 are rotated into the differential sensing amplifier 400 to self-output Obtained several paper standards applicable to Ningguo National Standard (CNS) A4 specification (2 丨 〇X 297 mm) ----------- ^ ------ * 玎 ------ Line (please read the precautions on the back before filling out this page) '' 427〇S8 2. Description of the invention () Bit data signal 190. The second display shows the typical changes of Δνΐ and AV2 of the data signal received from the node ιN, respectively. The maximum value of the differential voltage Δνι and the value are only about 0.35V and 0.25V, respectively. The goal of generating a symmetric differential gain 'I tried to do a computer simulation with a method to adjust the channel width of the NMOS transistor located in the current sense amplifier circuit 300. However, as shown in Figures 3 and 4, the voltage change at node nO is comparable small. The larger voltage change at node η 1 causes the phenomenon of larger differential voltage Δνΐ and smaller differential voltage AV2. When the output digital signal of the sense amplifier 200 is' especially when the data is' low ', a spike-like waveform will be formed. On the other hand, the reduction of the reduced differential voltage gives digital data output "1, , Narrower width, as shown in Figure 5. All actions that increase the voltage change at nO by adjusting the size of the transistor will have no effect. Small loop voltage gain (such as < 0 · 2ν differential voltage) and asymmetric loop voltage gain will make the circuit bear the risk of process variation and noise interference. Therefore, how can we increase the loop voltage gain and generate a symmetrical loop voltage Gain 'has become an increasingly important topic in the industry ^ --------- Attack -------- V (谙 Read the notes on the back before writing this page) S Summarized Λ / t The sense of printing is positive for the production cooperation of shell workers and consumers in the Central Bureau of Standards of the Ministry of Economic Affairs. . The road to the No. 1 road refers to the return material of the feed material, and the return of the feedstock is positive. The data for reading and reading is coupled to the individual cells of each other. The memory of the two contains the memorandum, and the package is greatly released to learn the festival. Lost a large amount of material for the first and the second signals of No.1 and No.1, and the production of the dual-use raw materials will be used to produce the materials at the point of rotation. The dimensions apply to the Chinese National Standard (CNS) specifications (210x297) 427058 A7 _____ _____B7_____} two nodes. The second positive feedback loop includes the first CMOS capacitor and the first point Xinghu, cM0s capacitor. The first CMOS capacitor and The second CMOS capacitor is coupled to the input terminal and the output terminal of the second pole respectively. The second positive feedback circuit and the zjt surface feedback circuit are coupled to the first output node and the second output node. The loop voltage gain allows the voltage change at the output to be used for & symmetry a. The benefits that accompany the foregoing and the present invention will be more easily understood by the illustrated description. The following is a diagram of the present invention Explanation! The picture shows the know-how The sensing amplifier used in the memory element; Figure 2 is the simulation result of the circuit shown in Figure 1; Figure 3 is the simulation result of the circuit with the transistor size adjusted in Figure 1; Figure 4 is The simulation result of the circuit after the transistor size is adjusted in Fig. 1; Fig. 5 is the simulation result of the circuit after the transistor size is adjusted in Fig. 1; Fig. 6 is used in the memory element in the present invention Fig. 7 is the simulation result of the circuit shown in Fig. 6. f The detailed description of the line: This paper size applies the Chinese National Standard (CNS) A4 specification (2 丨 0'X297 mm) ----_ ----- Equipment ------ Order ------ Line f Please read the two notes before you fill in the clothing page j Printed by the Consumers' Cooperatives of the China Standards Bureau of the Ministry of Economy 427058 A7 B7 Economy Printed by the Consumer Standards Cooperative of the Ministry of Standards of the People's Republic of China 5. Description of the invention () As described in the background of the invention, the problem is that the voltage gain of the single positive feedback loop in the above embodiment is only about 1β. In addition, the voltage at the two output terminals Change to an asymmetric loop voltage gain, which will make the It bears the risk of process variation and noise interference. Therefore, the above invention has a space for increasing the avoidance voltage gain and generating a symmetrical loop voltage gain. The present invention constitutes a memory sensing amplifier circuit, which includes a differential amplifier circuit 400 and The modified current is directed to the sense amplifier circuit 500. The modified current is directed to the sense amplifier circuit 500, which includes a first positive feedback loop 520 and a second positive feedback loop 5 50, as shown in Figure 6). In a preferred embodiment 'Same as the positive return circuit 300 in the prior art, the positive feedback circuit 300 is used for the first positive feedback circuit 520 in the present invention. The first positive feedback loop has two output nodes no, nl and one input node IN. The input point in is used to receive data signals from the single-ended (sjng 〖e_end) bit line of the memory element (not shown in the circle). The second positive feedback loop 550 in the present preferred embodiment includes a first CMOS transistor 551 (transistors MP1 and MN7) and a second CMOS transistor 5 52 (transistors MP2 and MN8). The first CMOS transistor 551 and the second CMOS transistor 552 are respectively intersected and coupled by a gate input terminal and an output terminal. The output terminals of the first and second CMOS transistors 551 and 552 are denoted by reference numerals kl and k0, respectively, and are coupled to nodes nl and n0, respectively. The sources of the pMOS transistors MP1 and MP2 are connected to the voltage Vdd, and the sources of the NMOS transistors MN7 and MN8 are connected to the voltage Vss. The operation procedure of the present invention will be described as follows: Similar to the above-mentioned conventional technique, when the current flows into the node IN, the gate voltage of the transistor MN8 rises, which increases the Vgs of the transistor MNS. Standard (CNS) A4 size (210 X 297 mm) 1 n Binding H thread (please read the precautions on the back before filling out this page) [4270 58 A7 B7 The Central Bureau of Standards of the Ministry of Economy Description of the invention (Voltage, such a situation will help the transistors MN8 and MN4 pull down the voltage at the node nO. At the same time, the increase in the voltage V§s of the transistor MPI increases the source current of the transistor MPI 'This further increases the voltage at node nl. Therefore, the voltage changes at nodes nO and nl will become larger. On the other hand, when the current flows from the data input terminal IN, the voltage at the data input terminal IN will decrease △ V The operation of the transistors MN3 and MN4 is the same as that of the transistors M3 and M4 in the figure. The voltage drop Δν at the input end of the data wheel In will cause the voltage drop at the output node nl, thus increasing the Vgs of the transistor MP2. And voltage The voltage of Vgs of the crystal MN8. Therefore, the increase of the source current of the transistor MP2 further causes the voltage at the node nO to increase. That is, the voltage of the transistor MP2 and the transistor MN2 increases the voltage of the output node nO. At the same time, The increase of the voltage at the output node nO will decrease the voltage of Vgs of transistor MP1 and increase the voltage of Vgs of transistor MN7; therefore, transistor MN7 will help transistor MN3 pull down the voltage at output node nO. That is, A second positive feedback loop is established, and the voltage changes at the output nodes nl and nO will become larger. A larger loop gain voltage is reached at 焉. Figure 7 shows the simulation results of the present invention. Figure 7 The data signal 560 is used as a data signal, where the signal is received from the data input terminal IN, and then the signals 570 and 580 are output from the nodes 11 (or 1: 0) and 111 (or 1 ^). Then the signals 570 and 5 80 input into the differential sense amplifier 400 to obtain digital data signals from the ouT terminal. The bandwidth of the output data "0" or "factory" is almost the same. The voltage gain at the node nO is enhanced, and the differential voltage gain avi and AV2 It is also enhanced at the same time (for example, from about 0.3V (know-how) to about (explain the precautions on the back to read the page on this page) • Race. This paper size applies the Chinese National Standard (CNS) A4 wash grid ( 2 丨 OX297mm) ^ 27058 A7 _ B7______ 5. Explanation of the invention () _6V (the invention) In addition, the adjustment of the symmetrical loop voltage gain can be more flexible by appropriately adjusting the transistor MP1, MP2, MN7 Finished with the size of MN8. The benefits brought by the present invention are: (1) The falling or rising amplitude of the differential voltage will be amplified 'so that the problem of process variation can be avoided. (2) The voltage gain of the symmetrical loop can be easily obtained. The present invention is described above with a preferred embodiment, and is only used to help understand the implementation of the present invention, and is not intended to limit the spirit of the present invention. Those skilled in the art will not depart from the present invention after understanding the spirit of the present invention. Within the scope of the spirit, when it can be modified and replaced with equivalent changes, the scope of patent protection shall depend on the scope of the attached patent application and its equivalent fields. --------- Equipment ----- One-Order ------ line (please ^, read the notes on the back, and then fill in this page) Cooperative printed 9 This paper size applies to China National Standard (CNS) A4 (210X297 mm)