^25815 五、發明說明（ •本發明關於供視頻裝置之水平掃福系統之範固，特別關 於可以數個水平择描頻率作業之系統之控制。 在一視頻顯示裝置中，掃描電路與一同步組件同步，或 與自輸入視頻信號導出之同步組件同步。因爲，一可以多 個水平掃描頻率作業之視頻顯示裝置必能與標稱丨5 · 7 3 4 KHz(標準清晰度NTSCMf號水平掃描頻率同步，或與一高 清晰度之標稱^柳他及腦有效線及交錯掃描㈠刪） 之水平掃描頻率之ATSC信號同步。除對廣播視頻信號同步 夕卜―，此裝置可能需要顯示電腦非廣播視頻信號，如 超視頻圖形附加器信號或具有37 88〇 KHz水平頻率之 SVGA。 利用鎖相迴路控制之水平頻率振盪器久已知名並應用於 視頻顯示裝置中。雙相及三相鎖迴路亦知名並用以提供同 步與掃描波形產生之相反需求間之功能隔離。在雙迴路構 型中，第一迴路可能爲一傳統鎖相迴路，其中，一電壓控 制之輸出，或自該處分得之輸出與得自視頻信號待顯示之 水平同步脈衝比較。第二鎖相迴路以同一頻率操作，將自 第一迴路I振盥器輸出與得自或代表一不良電流流動之水 平頻率脈衝，例如，回掃脈衝電壓比較。自第二相位比較 t誤差電壓用來產生一寬度調變脈衝信號，該信號決定偏 轉輸出裝置關閉之開始，及隨後，回掃開始，或在垂直掃 描内每條線之相位。 第一鎖相迴路之響應對於接收遭遇不良信號雜波比之廣 播視頻信號之條紋區可能最佳。此種信號指出第一鎖相迴 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） !!-裝！ I訂！！線 {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 425815 B7 ------ 五、發明說明f ) 路之響應可能相當低。因此，第一迴路可有狹窄帶寬以使 相位跳動降低最佳。但，因爲視頻顯示裝置需要以來自不 同源之信號及不同水平頻率操作。第—鎖相迴路之響應代 表-狹窄帶寬以降低相位跳動’及—寬帶寬，即能迅^恢 復迴路響應之帶寬之間之-折衷。例如，一狹窄帶寬迴路 適於對由低噪音，非廣播電腦產生之信號響應，而寬帶寬 迅速迴路響應，能迅速相位恢復之帶寬適於對視頻卡式綠 音機（VCR)中繼信號同步，其中，在水平同步，脈衝相位 中-有劇烈變化’在垂直遮沒之開與終止間有多達1〇微秒 t變化。在各迴路響應中可以折衷以提供適當弱信號之性 能不致使接收機性能全面退化。第二鎖相迴路通常有—快 迴路響應=因此，第二鎖相迴路可有—較寬帶寬，可使盆 追蹤由於水平輸出電晶體存儲時間變化，或高壓變壓器調 諧效應引起之不良電流中之變化。此種緊密追蹤可產生一 直而不彎曲之光柵而與束電流負載無關。 利用電壓控制之振盪器以產生水平頻率信號已爲人熟 知。亦知利用在許多輸入水平同步，頻率操作之振盪器以 有可選擇計數之計數器達到同步。但直接掃接電路會在掃 描頻率電流，在掃描時被計數選擇而中斷時失效。 掃描時由計數選擇導致之掃描電路失效可由一新穎之裝 置予以防止。一可在數個水平掃描頻率作業之掃描產生器 含一產生巷號之振盪器。具有至少二可選計數之分 合至振盪器，並由第一計數分開以產生水平驅動信號。— 水平掃描放大器產生—掃描信號以響應耦合之水平驅動信 -5- 本紙張尺度_巾關家^^NS)A4規格（210 X 297公f (請先閱讀背面之注意事項再填寫本頁) 裝 -線· 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 42581 5 λ； — 一 B7 五、發明說明（3 ) 號。一控制器耦合至掃描放大器及分壓器。爲響應選擇另 —複數個水平掃描頻率，及響應一存在，控制器禁止選擇 至少二可選計數之第二告。在無掃描信號時，控制器可選 擇至少可選計數之第二告，分壓器產生一水平驅動信號， 其代表另一許多個掃描頻率。 圖1爲利用三個鎖相迴路及不同新穎組件之水平頻率振盪-器方塊圖。 圖2爲圖1之部份略圖及顯示一新穎交換主動濾波器。 _圖3爲一電壓控制振盪器包成圖1 一部份之新穎特 性。 圖4爲構成圖1一部份之新穎交換聯鎖之方塊圖。 圖5 A爲一曲線説明圖2之新穎交換主動濾波器之增益對 頻率特性。 圖5B爲一曲線説明圖2之新穎交換主動濾波器之相位對 頻率特性。 圖1顯示一水平頻率振盪器及利用三個鎖相迴路及可在複 數個頻率操作之偏轉放大器《在第一鎖相迴路10，一輸入 視頻顯示信號，例如，一標準清晰度NTSC信號耦合至同步 分離器，SS，其中一水平同步信號成份被分隔。一電壓控 制振盪器之頻率爲NTSC水平頻率之3 2倍，1 Fh，在一計數 器中被32所除，以+ 32表之。被除後振盪器信號耦合至相 位檢波器PD作爲一輸入，以第二輸入耦合至分隔之同步组 件。在被除後振盪器信號及分隔之同步組件間之合成相位 誤差，自相位檢波器PD耦合以同步32Fh電壓控制振盪 -0 - 本紙張尺度適用中固國家標準（CNS)A4規格（210 X 297公釐） ---；—--------裝— t請先B3讀背面之注意事項再填寫本頁) 訂 -線 經濟部智慧財產局員工消費合作社印製 4258 1 5 Λ7 ---B7 五、發明說明（4 ) 器。PLL10形成匯流排控制基體電路，如TA1276型。自 PLL10之標準清晰度水平同步组件耦合至一同步源選擇器 開關SW15 ’其提供在複數個同步信號作爲輸入源耦合以同 步第二及第三控制水平振盪器迴路1〇〇及41〇。選擇器開關 S W 1 5以三個範例同步源説明，即標準清晰度NTSC同步信 號’高清晰度同步信號如ATSC1080I，及電腦產生之SVGA-同步信號’但供水平振盪器同步信號之同步選擇不限於此 等範例。同步開關S W i 5由開關信號！ 5 a控制，該信號由微 笔制器800產生以響應—用户控制指令，例如，由遙控發 射機RC所產生，該發射機由無線與接收機IRR，通 信，其輸入遙控資料至微控制器800 ^遙控RC可作顯示信 號源之選擇，例如，改變在HD及SD間之廣播TV頻道或觀 看有可選擇顯示清晰度之電腦程式。 圖1中説明之三個鎖相振盪器可被控制以提供最佳之性 能’不僅以不同頻率之輸入信號，並且以受時序干擾之信 號均可有良好性能。在NTSC信號顯示期間，利用迴路 10,100及410。但NTSC信號可源自一廣播源或一 VCR。後 者之源可能受到同步相位干擾，因此，此種信號干擾由低 通滤波器特性之控制選擇方式有益的在PLL100中得以調 節。高清晰度信號輸入之選擇，例如ATSC或SVGA造成 PLL10被旁路，因此減少同步系統爲二控制迴路，例如， PLL100及PLL410。因此微控制器800必須控制輸入視頻顯 示選擇以響應用户指令，以控制同步源選擇以響應顯示選 擇’控制振盪器頻率，振盪器除法器，及鎖相振盪器低通 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----ί—丨丨丨！ •裝.丨丨丨丨tl —訂.-------•線 (請先閱請背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制^ 4258 丨 5 A7 ___B7_ 五、發明說明（6 ) 濾波器特性。 自開關15選擇之同步信號5轉合至相位檢波器5〇以方便 第二鎖相迴路100之同步。至相位檢波器5〇之第二輸入信 號爲得自電壓控制振盪器信號301所除之信號4〇ι ^合成之 相位誤差信號1 1被低通濾波並供應以控制Vc〇3〇〇，因而 與輸入視頻顯示信號水平同步達成同步。第三鎖相迴路 410將自電壓控制振盪器VC0300之信號與掃描相關之信號^ 25815 V. Description of the invention (• The present invention relates to the standard of the horizontal scanning system for video devices, especially to the control of a system that can perform several horizontal scanning frequency selection operations. In a video display device, the scanning circuit is synchronized with a Synchronization of components, or synchronization components derived from the input video signal. Because a video display device that can operate with multiple horizontal scanning frequencies must be able to work with the nominal 丨 5 · 7 3 4 KHz (standard definition NTSCMf horizontal scanning frequency) Synchronization, or with a high-definition ATSC signal with a horizontal scan frequency (nominal line, brain effective line, and interlaced scanning). Except for synchronizing broadcast video signals, this device may need to display a computer Broadcast video signals, such as super video graphic adder signals or SVGA with a horizontal frequency of 37 88kHz. Horizontal frequency oscillators controlled by phase-locked loops have long been known and used in video display devices. Two-phase and three-phase locked loops are also Well-known and used to provide functional isolation between the opposite requirements of synchronization and sweep waveform generation. In a dual-loop configuration, the first loop may be A conventional phase-locked loop, in which a voltage-controlled output, or the output derived therefrom, is compared with a horizontal synchronization pulse obtained from a video signal to be displayed. The second phase-locked loop operates at the same frequency and will start from the first loop I The vibrator output is compared with a horizontal frequency pulse derived from or representing a bad current flow, for example, a flyback pulse voltage comparison. From the second phase comparison, the error voltage is used to generate a width modulated pulse signal that determines the deflection output device. The beginning of the shutdown, and then, the start of the flyback, or the phase of each line in the vertical scan. The response of the first phase-locked loop may be best for receiving the fringe area of a broadcast video signal that encounters a poor signal-to-clutter ratio. The signal indicates that the first phase-locked back -4- This paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 public love) !!-installed! I order !!! Line {Please read the precautions on the back before filling in this Page) Printed by A7, 425815, B7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs-5. Description of Invention f) The response of Road may be quite low. Therefore, the first loop may have a narrow bandwidth to optimize the reduction in phase jitter. However, because video display devices need to operate with signals from different sources and different horizontal frequencies. The response of the first phase-locked loop represents-a compromise between-narrow bandwidth to reduce phase jump 'and-wide bandwidth, that is, the bandwidth that can quickly restore the loop response. For example, a narrow bandwidth loop is suitable for responding to signals generated by low-noise, non-broadcasting computers, while a wide bandwidth is fast for loop response, and a bandwidth capable of rapid phase recovery is suitable for synchronizing the video card green sound machine (VCR) relay signal Among them, in the horizontal synchronization, there is a drastic change in the pulse phase 'as much as 10 microseconds t between the opening and ending of the vertical mask. A compromise can be made in the response of each loop to provide adequate weak signal performance without causing overall degradation of receiver performance. The second phase-locked loop usually has-fast loop response = Therefore, the second phase-locked loop can have-a wider bandwidth, which can make the basin track one of the bad currents caused by the horizontal output transistor storage time change or the high-voltage transformer tuning effect. Variety. This close tracking results in a straight, unbent grating independent of beam current loading. It is known to use a voltage controlled oscillator to generate a horizontal frequency signal. It is also known that by using synchronization at many input levels, a frequency-operated oscillator is synchronized with a counter that has a selectable count. However, the direct scan circuit will scan the frequency and current, and will be invalidated when selected by counting during scanning. The failure of the scanning circuit caused by the counting selection during scanning can be prevented by a novel device. A scan generator that can operate at several horizontal scan frequencies includes an oscillator that generates lane numbers. The division with at least two selectable counts is combined to the oscillator and divided by the first count to generate a horizontal drive signal. — Horizontal scanning amplifier generation—scanning signal in response to coupled horizontal drive letter-5- This paper size _ towel Guanjia ^^ NS) A4 size (210 X 297 male f (Please read the precautions on the back before filling this page) Assembly-line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed 42581 5 λ; —B7 V. Invention Description (3). A controller is coupled to the scan amplifier and voltage divider In response to the selection of another-a plurality of horizontal scanning frequencies, and in response to the existence, the controller prohibits the selection of at least two optional counts. In the absence of a scanning signal, the controller can choose at least two optional counts. The voltage divider generates a horizontal drive signal, which represents another many scanning frequencies. Figure 1 is a block diagram of the horizontal frequency oscillator-divider using three phase-locked loops and different novel components. Figure 2 is a schematic diagram of a part of Figure 1 And shows a novel switching active filter. _Figure 3 is a novel characteristic of a voltage-controlled oscillator package as part of Figure 1. Figure 4 is a block diagram of the novel switching interlock that forms part of Figure 1. Figure 5 A A curve illustrates the gain versus frequency characteristics of the novel switched active filter of Figure 2. Figure 5B is a curve illustrating the phase versus frequency characteristics of the novel switched active filter of Figure 2. Figure 1 shows a horizontal frequency oscillator and the use of three locks Phase loop and deflection amplifiers that can operate at multiple frequencies. In the first phase-locked loop 10, an input video display signal, for example, a standard definition NTSC signal is coupled to a sync separator, SS, where a horizontal sync signal component is The frequency of a voltage-controlled oscillator is 32 times the horizontal frequency of NTSC, 1 Fh, divided by 32 in a counter, and expressed by + 32. After the division, the oscillator signal is coupled to the phase detector PD as a Input, the second input is coupled to the separated synchronous component. The synthesized phase error between the divided oscillator signal and the separated synchronous component is coupled from the phase detector PD to synchronize the 32Fh voltage-controlled oscillation-0-This paper size applies China solid national standard (CNS) A4 specification (210 X 297 mm) ---; ---------- install-t please read the notes on the back of B3 before filling this page) Order-Ministry of Economics Printed by the Intellectual Property Bureau's Consumer Cooperatives 4258 1 5 Λ7 --- B7 V. Description of Invention (4). PLL10 forms a bus control base circuit, such as TA1276. The standard-definition horizontal synchronization component from PLL10 is coupled to a synchronization source selector switch SW15 'which provides a plurality of synchronization signals as input sources coupled to synchronize the second and third control horizontal oscillator circuits 100 and 41. The selector switch SW 1 5 is explained with three example synchronization sources, namely standard definition NTSC synchronization signal 'high definition synchronization signal such as ATSC1080I, and computer-generated SVGA-synchronization signal'. Limited to these examples. The synchronous switch S W i 5 is signaled by the switch! 5 a control, the signal is generated by the micro pen controller 800 in response to user control instructions, for example, generated by the remote control transmitter RC, which is wirelessly communicated with the receiver IRR, which inputs remote control data to the microcontroller 800 ^ Remote RC can be used to select the display signal source, for example, change the broadcast TV channel between HD and SD or watch a computer program with selectable display resolution. The three phase-locked oscillators illustrated in Figure 1 can be controlled to provide the best performance. Not only can input signals with different frequencies, but also signals with timing interference have good performance. During NTSC signal display, circuits 10, 100 and 410 are used. However, the NTSC signal can originate from a broadcast source or a VCR. The latter source may be subject to synchronous phase interference. Therefore, this type of signal interference can be adjusted in the PLL 100 by the control selection method of the characteristics of the low-pass filter. The choice of high-definition signal input, such as ATSC or SVGA, causes PLL10 to be bypassed, so reducing the synchronization system to two control loops, such as PLL100 and PLL410. Therefore, the microcontroller 800 must control the input video display selection in response to user instructions, and control the synchronization source selection in response to the display selection. 'Control oscillator frequency, oscillator divider, and phase-locked oscillator. (CNS) A4 specifications (210 X 297 mm) ---- ί— 丨 丨 丨! • Packing. 丨 丨 丨 丨 tl —Order .------- • Line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs ^ 4258 丨 5 A7 ___B7_ 5. Description of the invention (6) Filter characteristics. The synchronization signal 5 selected from the switch 15 is switched to the phase detector 50 to facilitate the synchronization of the second phase-locked loop 100. The second input signal to the phase detector 50 is a signal obtained by dividing the voltage-controlled oscillator signal 301 with a phase error signal 11 which is low-pass filtered and supplied to control Vc0300. Synchronize with the horizontal synchronization of the input video display signal. The third phase-locked loop 410 combines the signal from the voltage-controlled oscillator VC0300 with the scanning-related signal.
Hrt，例如由掃描放大器500產生之掃描電流之水乎掃描脈 衝比較。 水平振盛器300之中心頻率由控制匯流排42〇，如〗2匸匯 流排決定，其能優異的改變振盪器頻率及低通濾波器特 性。除了優異的保護電路600可防止由電子聯鎖掃描期間 意外’誤差及不良除法器交換引起之電路損壞。 第二及第三水平振盪器遊路及圖1之掃描放大器之作業如 下。一水平同步信號5，爲一正脈衝係由開關1 5自PLL1 〇或 得自複數個輸入顯示信號選出。同步信號5加至相位檢波 器50，該處，與自電壓控制振盪器vc〇300以線鎖時脈信 號LLC301相除所產生之水平頻率信號4〇1相比較。段4〇〇代 表範例偏轉處理基體電路IC400，如TDA9151型。基體電路 400由匯流排控制，例如由c匯流排420，亦包括相位檢 波器PLL3，及除法器415及415A。除法器415A由信號402 控制以提供432及864之除法比値，因此產生二頻帶，及 1 Fh及2 Fh之水平頻率信號。控制信號402耦合至開關 412，其將除法器415A插入或旁入以提供二除法比値。因 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） III--Μ-----HI --------訂 *---I ---- (請先閱讀背面之注意事項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 42581 5 A7 B7 五、發明說明（6 ) 此’電壓控制振盪器VC0300僅操作於約13.6 MHz之頻 帶，但與相差大於2比1之水平頻率同步。此種非整數相關 之水平頻率之例證如NTSC信號，其中由lFh代表水平頻率 爲15,73 4 KHz及以2.14Fh或33,670 KHz代表之NTSC信號之 水平頻率之ATSC10801。在顯示NTSC影像期間，開關412 選擇除法器415A，其提供一除法比率864比1，產生一 NTSC水平頻率lFh之標稱頻率。同理，顯示水平頻率2Fh 或更大頻率’如ATSC1080I信號影像時，開關412將除法器 4fA旁入’導致除法比率432，_爸產生31,468 KHz之水平 頻率2Fh，爲NTSC標準之二倍》但ATSC1080I水平頻率並 非NTSC信號lFh之整數倍數，事實上爲NTSC頻率之2.14 倍。因此’欲達成與10801輸入信號或任何非2Fh同步頻率 同步時，VCO頻率必須改變爲一頻率，當以432相除時產 生可與ATSC1080I，或選擇之輸入信號水平頻率同步之頻 率。 除後線鎖時脈信號401亦由相位檢波器pll3耦合以與第 三迴路410同步’其將時脈信號401與得自脈衝Hrt，501之 掃描電流比較。自PLL3之輸出信號403經驅動器級450竊合 至水平掃描級500 ’其在一顯示器裝置或電子束偏轉線圈 產生一掃描相之電流。除耦合至PLL3外，掃描脈衝Hrt亦 耦合至電路以保護電路600及X光保護電路69〇。 如上所述，第二及第三鎖相迴路可由除法器交換在比率 2 : 1中可以改變。如欲VC0以其他共振相關之頻率同步， 如與2.14 Fh之ATSC 10801頻率或2.4Fh水平頻率之信 -9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） !!1!裝！!訂---I--! ·線 (請先閱讀背面之注意事項再填寫本頁) 425S15 A7 ________B7 五、發明說明（7 ) {請先閱讀背面之注意事項再填寫本頁) 號同步時’需要第二鎖相迴路控制VCO以達到非整數水平 頻率’通常爲NTSC水平頻率之2.14 - 2‘4倍間之水平頻 率。在電整控制振遠器3 00中，一良好頻率設定DC電位， FREQ. S ET，302決定一振盪器頻率，當被除時，產生一標 稱水平頻率。頻率設定DC電位由一類比至數位轉換器產 生’並加至一電壓可變電容器或變容二極體，其構成振盛 器頻率決定網路之一部份。此振盪器由相位檢波器誤差信 號與輸入同步信號同步’其被過濾並加至構成VC〇3 00之頻 气決定網路之一部份之一電感器。簡言之，一頻率設定d C 加至一串聯調諧網路之變容二極體末端，相位誤差信號加 土電感器末端。因此’頻率及相位控制信號被跨加至頻率 決定調諧電路。 經濟部智慧財產局員工消費合作社印製 電壓控制振盘器300在圖1予以説明並在圖3中以略圖説 明。優異之電壓控制振盪器300之作業如下。微控制器8〇〇 及s己憶體（未示出）存取並經資料匯流排420如12 C匯流排輸 出頻率設定資料，如圖1所示。12 C匯流排連接至數位同步 處理器400以提供不同控制功能，及至數位至類比轉換器 700 ’其將資料隔離及轉換爲類比電壓β數位至類比轉換 器700產生頻率交換控制信號1 Η - S W，701，及VCO頻率 設定電壓FREQ.SET3〇2。圖3中，頻率設定電壓 FREQ.SET300經R1耦合至R3，R4及C3之接點，其與R1 共同構成低通滤波器至地。電阻器R1及R3構成一電位分 壓器，而電阻器R3連接至DAC700參考電壓Vref)。類比電 壓302爲DAC參考電壓（Vref)之半，並加一標稱電壓約 -10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 425815 。 A7 __B7 五、發明說明（8 ) + 3.8V之偏壓至變容二極體D1 »電阻器R1，r3及電容器 C3之接點經電阻器R4耦合至變容二極體D1之陰極。得自 電塵（Vref)之標稱d C電壓値加上自ADC700之資料決定頻 率設定電壓302加至振盪器頻率決定網路之變容二極體 D1。頻率設定電壓302在1Fh及2Fh模式時，標稱爲〇伏， 當操作在2.4Fh時，如SVGA，升至+ 7V。 振盪器由PNP電晶體q3構成，其射極經電阻器R7連接至 正電壓，其集極經電阻器Rs及電容器C4並聯组合聯接至 A。但晶體Q 3之基極經電阻器兰土連接至正電壓，及經電 容器C5耦合至地。振盪器之頻率多決定於一 _聯共振網路 決定，該網路由可調電感器L1及變容二極體1)1與電容器 C4所構成。電阻器尺4二極體D1及電容gC4之接點經電容 器C6耦合至電晶體q3之基極。電晶體〇3之集極經電容器 C8連接至電感器li及圖2中之電阻器R6之接點，其供應處 理之相位誤差信號2〇 1供振產器同步之用。頻率控制及相 位同步信號被供應至由元件〇1，C4 , ^構成之串聯共振 ‘菊路。共振器之初步調諸可設定D A c電壓302爲標稱零 伏’及lFh水平頻率同步信號耦合至相位檢波器電感匕丨調 整至其作業範圍之相位檢波器之誤差信號之中心而達成。 在另一振盪器設定方法中，利用一非可調電感器L丄a 1 Fh 之水平頻率同步信號加至相位檢波器，DAC電壓302 —直 &化直到相位檢波器誤差信號已在中心β與電壓3之中 心値對應I資料値被存儲。爲決定在2.4Fh之作業之頻率設 疋電壓’以存儲之迴路中心之資料値將之前之方法重復。 _____- 11 - 本紙張尺度W中國國家標準 !1—1!11—. ·!1111 訂·11!蠢 ί * (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 42Si j 5 A. A/ _______B7___ 五、發明說明f ) 振盪器輸出信號自電晶體q3之電阻器尺7處摘取，並經 由電容器C6耦合至PNP電晶體Q4。電晶體Q4之構型爲一 接地基極放大器，其基極由電容器C7除耦合至地，並電阻 器R 1 1連接至正電壓。電晶體Q4經電阻器R丨〇接地。因 此，振盪器輸出信號跨電阻器R1〇商發展而成，並耦合至 同步處理IC400作爲·-線鎖時脈，LLC301。 控制除法器415a之頻率交換信號SEL H FREQ，2〇2/4〇2 亦耦合至新穎之低通主動濾波器2〇〇，如圖2，其功能如 下一相位誤差信號係獲自信號4〇1，除後 VCO及輸入信號同步5間之相位比較，耦合至輸入電阻器 R1。輸入電阻R1與電阻器R2_聯至積體電路放大器21〇之 反相輸入。電阻器尺丨及尺：之接點連接至開關51之固定接 點1 Fh。開關s 1之移動接點連接至電阻器R 3及電容器c 3 之並聯組合及電阻器尺4及電容器C4之並聯組合。負回輸 自輸出放大器210經由一電容器C2及電阻器R4及電容器 C4，電阻器尺3及電容器C3之並聯網路及串聯連接组合之 頻率相關網路，供應至反相輸入。並聯網路r 3，c 3連接 至開關si滑動片與放大器210之反相輸入之間。當開關s i 選擇位置lFh，電阻器R2與電阻器R3電容器C3之並聯组 合成並聯’結果由R2，R3，C3形成之新並聯網路對放大 器增益或頻率響應決定上影響甚小。因此，當以1 Fh同步 時’開關位置選爲IFh ’放大器增益由輸入電阻器ri決 定’頻率響應則由電容器C2及並聯網路R2，C3決定。+ 田 顯示器以大於1 Fh之水平頻率操作，開關s !選擇2 Fh，電 ___ - 12- 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） 1!1! (請先閱讀背面之注意事項再填寫本頁) A7 4258 1 5 五、發明說明（10 ) 阻器R 2 .又成重要之増盈決定组件，頻率響應則由電容器 C2及R3 ’ C3及R4 ’ C4之並聯網路決定。訪放大器2〇1之 非反相輸入被偏壓爲约2.5 V之正電位。 自放大器210之輸出經串聯之電阻器115及116耦合以形成 處理後之相位誤差信號，PR〇c 〇ERR〇R , 2〇1以耦合以同 步VC0300 ^電阻器R5及R6之接點由電容器c丨除耦合至_ 地，其構成低通濾波器以防止由交換模式電源供應作業產 生（向頻噪音產生亂眞VC〇相位調變。電阻器R5，尺6之 接—點亦連接至由PNP電晶體Q i ^ρΝ電晶體Q 2之射極構 成之峰至峰限制器或箝位器。電晶體Q 1之集極連接至地， 電晶體Q2之集極經電阻器尺9連接至正電壓。電晶體〇2之 基極連接至串聯電阻器尺⑺及尺？之接點。電阻器R1〇連接 至地，電阻器R7經電阻器尺8連接至正電壓。電阻器尺7及 R8之接點連接至電晶體qi之基極^因此，電阻器R7，尺8 及R10形成一電位分壓器’其決定峰至峰箝位値約爲 + 0.3V + 2.2V ’處理後誤差信號2〇1限制於該値。 在鎖相迴路中，相位檢波器輸出濾波之選擇係在靜態及 動癌性能間之一折衷。例如，同步一電腦產生SVGA信號 可能需要或獲益自一窄帶寬VC〇控制信號，其可提供高相 位穩定振盪器及水平頻率。但如前所述，VCR回放同步信 號在垂直同步之附近及垂直遮沒期間可能包括突然之水平 同步相位改變。爲防止或緩和相位改變之效應，迴路需要 較電腦i生之SVGA信號或廣播信號爲寬之帶寬。因廣播 信號不受突然相位干擾。優異之放大器21〇安棑成—主動 -13- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） I I ί !-裝 ---!| 訂 -----I — ·線 ♦ t (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印契 425 8 1 5 A/ B7 五、發明說明（11 ) 低通濾波器，其輸出信號成份經頻率相關串聯網路C 2， C3，C4及R3，R4回輸至反相輸入。開關S1被控制以響應 選擇之水平振盡器頻率，俾在開關位置IFh時，電阻器R2 並聯連接至並聯組合R2 ’ C3以構成與反相輸入串聯之阻 抗。電阻器R2，R3及C3之並聯组合對濾波器增益或頻率 響應產生之效應甚小。在開關位置爲1 F h時，渡波器增益 網路C2，C1及R4之阻抗除以輸入電阻器ri之値所決定。 非常清楚’當迴路作業頻率接近DC時，電容器C2變大， 及—迴路增益接近如圖5A所示之占上條件。當操作在非1Fh 時，水平頻率開關S 1被控制以選擇位置2Fll。在開關位置 爲2Fh時’濾波器增益由回輸網路R3，C2，C1及R4之阻 抗除以串聯電阻器R1及R2組合所決定。因爲電阻器R2較 R3爲大，在2Fh時之增益較開關位置lFh時爲小。因此， 主動爐波器增益及帶寬被控制爲不同以響應水平作業頻率 之選擇。 在水平頻率爲2Fh*更高作業期間，開關Si選擇2Fh位 置’結果，接近D C頻率之增益約爲1 0 d B，如圖5 A之虛線 中波幅對頻率曲線所説明者。在頻率約爲10Hz時，增益於 是降低至零且約爲1〇〇 Hz時繼續降達-20 dB。因此，以 2Fh模式操作，開關S丨在2Fh位置時，零增益帶寬約爲 10 Hz。圖5B顯示相位對頻率曲線圖，以説明二水平頻率 其中虛線表示2Fh模式。當操作在NTSC頻率lFh時，開關 S1被控制以選擇1Fh位置，其可增加濾波器増益及提供超 過10 KHz之零増益帶寬。參考圖5A，其中説明在以lFh作 -14- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -- --«5, (請先閱讀背面之注意事項再填寫本頁) "& r 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作杜印製 4 2581 5 A7 B7 五、發明說明（12 ) 業期間使用較高水平頻率作業期間爲大之低頻率滤波器。 除濾波器產生較在2 F h模式所得之爲寬之相位誤差信號帶 寬。主動濾波器增益及頻率響應交換可由單一開關接點達 成，其可提供印刷電路板面積之節省，因此，可降低誤差 場拾起及寄生相位不穩定之敏感性。 用户輸入信號選擇導致許多水平頻率間之一對應選擇 其被微控制器800發送至同步源選擇器開關〗5及同步處理 IC400。微控制器800產生一特殊控制指令LFSS，其被尋址 ^同步處理IC400以開始或停止水平及ψ貞產生。水平驅動輸 出信號403被處理器800控制而終止，如輸出開關412a所 示。因此，在無水平驅動信號403時，水平掃描放大器5〇0 停止產生掃描電流，結果，脈衝Hrt不再產生。在水平指令 (LFSS )停止後，微控制器發出控制字至數位至類比轉換器 DAC700。第一 DAC700控制字可能代表水平頻率開關指 令’其自DAC700輸出作舄類比控制信號iH SW，701， 並耦合至交換聯鎖650。DAC亦接生第二控制字，其產生 類比頻率設定電位FREQ.SET302。 微處理器產生之指令LFSS將水平驅動403關閉，結果停 止產生脈衝Hrt。在無脈衝Hrt時代表掃描停止，因而使控 制仏號1 H_S W被搞合以形成頻率交換信號。 因此，信號SEL.H.FREQ.402可以改變狀態，因而選擇在同 步處理器400中之一不同除法比値，因此迴路1〇〇及41〇之 不同水平頻率。由於掃描被指令LFSS所停止’除法器415A 可被自除法器鏈插入或旁路，而不會損失水平驅動器45〇 __-15- 本紙張尺度適用中關家標準（CNS)A4規格（210 X 297公裴) ~ — — — — ——I!· — I I *1 — — (請先閱讀背面之注意事項再填寫本頁) 4258 1 5 A7 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（13 ) 或水平掃描放大器500 ^微控制器在發射水平頻率開關指 令之前發射水平關閉指令，以確保水平掃描放大器5〇〇^ 靜態，因此可避免電路損壞。此一優異保護電路6〇〇可提 供進一步之保護，即經由監視以決定由微處理器產生之數 位指令LFSS，及由I2C匯流排所發射之數位指令是否已解 多工及由同步處理器400實施。保護電路6〇〇可證實匯流排 心令之實施及允許在兴水平知描脈衝Hrt時，可作水平頻率 選擇。除同步處理器400及掃描放大器5〇0可被保護以防由 產_生之寄生信號，例如由DAC701誤差電路功能及電源供 應負載或CRT電孤引起之錯誤除法器改變。 優異之保護電路600如圖4所示，其提供與掃描電流存在 及不存在相關之控制功能，如脈衝Hrt，501之偵出所示。 電路段610偵出脈衝501之有無，及產生一主動低中斷， SCAN-LOSS INTR.615 ’ 其耦合至微控制器，"c〇NT.800 〇 在第一保遵功能中，電路600證實同步處理器指令LFSS 已终止水平驅動之產生，如無脈衝Hrt所示β因此，將水平 頻率選擇與掃描存在聯鎖，在脈衝Hrt出現時’頻率交換被 禁止。水平頻率選擇資料自微控制器8〇〇被匯流排42〇耦 合。匯流排被去多工及頻率選擇資料由〇八(：700將數位轉換 成類比，以形成交換信號1H_SW以被耦合至電路段650。 該電路段650允許信號iH_SW之邏輯狀態被耦合，僅在掃 描放大器500未生產脈衝Hrt時供頻率選擇。因此，水平頻 率改變被聯鎖及防止，直到相關脈衝掃描停止。 -16- -I ----I----I 裝 ------- 訂 i I I---I* 線 {請先閱讀背面之注意事項再填寫本頁) 格 4 A λ ^ J ί Μ 公 7 9 2 4258 ? 5Hrt, for example, the scan current generated by the scan amplifier 500 is compared with the scan pulse. The center frequency of the horizontal vibrator 300 is determined by the control bus 42. For example, it can be determined by the 2 bus, which can excellently change the oscillator frequency and low-pass filter characteristics. In addition to the excellent protection circuit 600, circuit damage caused by accidental 'errors during electronic interlock scanning and poor divider exchanges can be prevented. The operation of the second and third horizontal oscillator paths and the scan amplifier of FIG. 1 is as follows. A horizontal synchronizing signal 5 is selected as a positive pulse by the switch 15 from the PLL 10 or a plurality of input display signals. The synchronizing signal 5 is applied to a phase detector 50, where it is compared with a horizontal frequency signal 401 which is generated by dividing the voltage-controlled oscillator vc 300 by the line-locked clock signal LLC 301. Segment 400 represents an exemplary deflection processing base circuit IC400, such as a TDA9151 type. The base circuit 400 is controlled by a bus, such as a c bus 420, and also includes a phase detector PLL3, and dividers 415 and 415A. The divider 415A is controlled by the signal 402 to provide a division ratio 432 of 432 and 864, thus generating a two-band, and horizontal frequency signals of 1 Fh and 2 Fh. The control signal 402 is coupled to a switch 412, which inserts or bypasses the divider 415A to provide a two division ratio. Because -8- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) III--M ----- HI -------- Order * --- I --- -(Please read the notes on the back before filling this page >> Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives 42581 5 A7 B7 V. Description of the invention (6) This' voltage controlled oscillator VC0300 only operates at about 13.6 MHz Frequency band, but synchronized with a horizontal frequency with a phase difference greater than 2 to 1. Examples of such non-integer-related horizontal frequencies are NTSC signals, where 1Fh represents a horizontal frequency of 15,73 4 KHz and NTSC represented by 2.14Fh or 33,670 KHz The horizontal frequency of the signal is ATSC10801. During the display of the NTSC image, the switch 412 selects the divider 415A, which provides a division ratio of 864 to 1, which produces a nominal frequency of the NTSC horizontal frequency lFh. Similarly, the horizontal frequency of the display is 2Fh or greater The frequency 'as in the image of the ATSC1080I signal, the switch 412 bypasses the divider 4fA' causes the division ratio of 432, _ Da produces 31,468 KHz horizontal frequency 2Fh, which is twice the NTSC standard "but the ATSC1080I horizontal frequency is not an integer multiple of the NTSC signal lFh , In fact, 2.1 of NTSC frequency 4 times. Therefore, 'to achieve synchronization with the 10801 input signal or any non-2Fh synchronization frequency, the VCO frequency must be changed to a frequency. When divided by 432, a frequency that can be synchronized with ATSC1080I, or the horizontal frequency of the selected input signal is generated. In addition to the post-lock clock signal 401 is also coupled by the phase detector pll3 to synchronize with the third loop 410 'It compares the clock signal 401 with the scanning current obtained from the pulses Hrt, 501. The output signal 403 from PLL3 passes through the driver stage 450 is coupled to the horizontal scanning level 500 'which generates a scanning phase current in a display device or an electron beam deflection coil. In addition to being coupled to PLL3, the scanning pulse Hrt is also coupled to the circuit to protect the circuit 600 and the X-ray protection circuit 69. As mentioned above, the second and third phase-locked loops can be changed by a divider exchange in a ratio of 2: 1. If VC0 is to be synchronized with other resonance related frequencies, such as ATSC 10801 frequency of 2.14 Fh or 2.4Fh horizontal frequency Zhixin-9- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) !! 1! Pack!! Order --- I--! · Line (Please read the precautions on the back before (Fill in this page) 4 25S15 A7 ________B7 V. Description of the invention (7) {Please read the precautions on the back before filling this page) No. 'Requires the second phase-locked loop to control the VCO to achieve a non-integer horizontal frequency' during synchronization. Usually it is 2.14 of the NTSC horizontal frequency- Horizontal frequency between 2'4 times. In the electric remote control remote control 3 00, a good frequency sets the DC potential, FREQ. S ET, 302 determines an oscillator frequency, and when divided, generates a nominal horizontal frequency. The frequency setting DC potential is generated by an analog-to-digital converter and is added to a voltage variable capacitor or a varactor diode, which constitutes a part of the oscillator frequency determining network. This oscillator is synchronized by the phase detector error signal with the input synchronization signal ’, which is filtered and added to the frequency forming the VC0300 inductor which is part of the network. In short, a frequency setting d C is added to the end of a varactor diode of a series tuning network, and a phase error signal is added to the end of the inductor. Therefore, the frequency and phase control signals are applied across the frequency to determine the tuning circuit. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economics, the voltage-controlled vibrator 300 is illustrated in FIG. 1 and schematically illustrated in FIG. 3. The operation of the excellent voltage controlled oscillator 300 is as follows. Microcontroller 800 and memory (not shown) access and output frequency setting data via data bus 420 such as 12 C bus, as shown in Figure 1. The 12 C bus is connected to the digital synchronous processor 400 to provide different control functions, and to the digital-to-analog converter 700 'which isolates and converts data to an analog voltage β digital-to-analog converter 700 generates a frequency exchange control signal 1 Η-SW , 701, and VCO frequency setting voltage FREQ.SET302. In Figure 3, the frequency setting voltage FREQ.SET300 is coupled to the contacts of R3, R4 and C3 via R1, which together with R1 form a low-pass filter to ground. The resistors R1 and R3 form a potential voltage divider, and the resistor R3 is connected to the DAC700 reference voltage Vref). The analog voltage 302 is half of the DAC reference voltage (Vref), plus a nominal voltage of about -10-. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed 425815. A7 __B7 V. Description of the invention (8) + 3.8V bias to the varactor D1 »The contacts of resistors R1, r3 and capacitor C3 are coupled to the cathode of varactor D1 via resistor R4. The nominal d C voltage obtained from the electric dust (Vref) plus the data from the ADC 700 determines the frequency setting voltage 302 to the oscillator frequency determining network varactor diode D1. When the frequency setting voltage 302 is in 1Fh and 2Fh mode, it is nominally 0 volts. When operating at 2.4Fh, such as SVGA, it rises to + 7V. The oscillator is composed of a PNP transistor q3, whose emitter is connected to a positive voltage via a resistor R7, and its collector is connected to A via a resistor Rs and a capacitor C4 in parallel. However, the base of crystal Q 3 is connected to a positive voltage via a resistor blue earth, and is coupled to ground via capacitor C5. The frequency of the oscillator is mostly determined by a resonant network, which consists of a tunable inductor L1 and a varactor diode 1) 1 and a capacitor C4. The contact of the resistor D4 diode D1 and the capacitor gC4 is coupled to the base of the transistor q3 via a capacitor C6. The collector of the transistor 03 is connected to the contact point of the inductor li and the resistor R6 in FIG. 2 through the capacitor C8, and the phase error signal 201 for the supply process is used for synchronizing the oscillator. The frequency control and phase synchronization signals are supplied to a series resonance ‘daisy path’ composed of components 〇1, C4, ^. The preliminary adjustment of the resonator can be achieved by setting the D A c voltage 302 to the center of the error signal of the phase detector coupled to the phase detector inductor, with the nominal zero volt 'and lFh horizontal frequency synchronization signals adjusted. In another oscillator setting method, a non-tunable inductor L 丄 a 1 Fh horizontal frequency synchronization signal is applied to the phase detector, and the DAC voltage 302 is straightened until the phase detector error signal is at the center β. The I data corresponding to the center 电压 of the voltage 3 is stored. To determine the frequency of operation at 2.4Fh, set “voltage” to store the data of the loop center and repeat the previous method. _____- 11-This paper is a Chinese national standard! 1—1! 11—. ·! 1111 Order · 11! Stupid * (Please read the precautions on the back before filling out this page) Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative Printed 42Si j 5 A. A / _______B7___ 5. Description of the invention f) The output signal of the oscillator is taken from the resistor ruler 7 of transistor q3, and is coupled to PNP transistor Q4 via capacitor C6. Transistor Q4 is configured as a grounded base amplifier whose base is coupled to ground by a capacitor C7, and a resistor R 1 1 is connected to a positive voltage. Transistor Q4 is grounded via a resistor R1. Therefore, the oscillator output signal is developed across the resistor R10 and is coupled to the synchronous processing IC400 as the line lock clock, LLC301. The frequency exchange signal SEL H FREQ, 2 0 2/4 2 of the control divider 415a is also coupled to the novel low-pass active filter 2 00, as shown in Fig. 2. Its function is as follows. A phase error signal is obtained from the signal 4 0. 1. Phase comparison between VCO and input signal synchronization after division 5 is coupled to input resistor R1. The input resistor R1 and the resistor R2_ are connected to the inverting input of the integrated circuit amplifier 21o. Resistor ruler 丨 and ruler: The contacts are connected to the fixed contact 1 Fh of switch 51. The moving contact of the switch s 1 is connected to the parallel combination of the resistor R 3 and the capacitor c 3 and the parallel combination of the resistor rule 4 and the capacitor C4. The negative feedback self-output amplifier 210 is supplied to the inverting input through a capacitor C2 and a resistor R4 and a capacitor C4, a parallel network of a resistor ruler 3 and a capacitor C3 and a frequency-dependent network of a series connection combination. The parallel network r 3, c 3 is connected between the switch si slider and the inverting input of the amplifier 210. When the switch si selects the position lFh, the parallel combination of the resistor R2 and the resistor R3 and the capacitor C3 forms a parallel connection. As a result, the new parallel network formed by R2, R3, and C3 has little effect on the amplifier gain or frequency response. Therefore, when 1 Fh is synchronized, the switch position is selected as IFh. The amplifier gain is determined by the input resistor ri. The frequency response is determined by the capacitor C2 and the parallel networks R2 and C3. + Tian display operates at a horizontal frequency greater than 1 Fh, switch s! Select 2 Fh, electricity ___-12- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 public) 1! 1! ( Please read the precautions on the back before filling this page) A7 4258 1 5 V. Description of the invention (10) Resistor R 2. It also becomes an important component for determining profitability, and the frequency response is determined by capacitors C2 and R3 'C3 and R4' C4 parallel network decision. The non-inverting input of the access amplifier 201 is biased to a positive potential of about 2.5 V. The output from the amplifier 210 is coupled by series resistors 115 and 116 to form a processed phase error signal. PR0c 〇ERR〇R, 201 is coupled to synchronize VC0300 ^ The contacts of resistors R5 and R6 are connected by capacitors In addition to coupling to _ ground, it constitutes a low-pass filter to prevent it from being generated by switching mode power supply operations (frequency noise is erratic and VC0 phase modulation. Resistor R5, the connection of the 6-foot point is also connected to the The peak to peak limiter or clamp of the emitter of PNP transistor Q i ^ ρN transistor Q 2. The collector of transistor Q 1 is connected to ground, and the collector of transistor Q 2 is connected to resistor 9 Positive voltage. The base of transistor 02 is connected to the series resistor and contact. Resistor R10 is connected to ground. Resistor R7 is connected to positive voltage via resistor ruler 8. Resistor ruler 7 and The contact of R8 is connected to the base of the transistor qi. Therefore, the resistors R7, ruler 8 and R10 form a potential divider 'which determines the peak-to-peak clamping 値 approximately + 0.3V + 2.2V'. Error after processing The signal 201 is limited to this signal. In the phase-locked loop, the selection of the phase detector output filtering is static and A compromise between dynamic cancer performance. For example, synchronizing a computer to generate an SVGA signal may require or benefit from a narrow bandwidth VC0 control signal, which provides a high phase stable oscillator and horizontal frequency. But as mentioned earlier, VCR playback The synchronization signal may include a sudden horizontal synchronization phase change near the vertical synchronization and vertical blanking period. In order to prevent or mitigate the effect of the phase change, the loop needs a wider bandwidth than the SVGA signal or broadcast signal generated by the computer. Because the broadcast signal No sudden phase interference. Excellent amplifier 21〇 安 〇 成 —Active-13- This paper size applies to China National Standard (CNS) A4 (21〇X 297mm) II ί!-装 ---! | Order ----- I — · Line ♦ t (Please read the notes on the back before filling out this page) Seal of Deed of Consumer Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs 425 8 1 5 A / B7 V. Description of Invention (11) Low Pass The output signal of the filter is fed back to the inverting input via the frequency-dependent series network C2, C3, C4 and R3, R4. The switch S1 is controlled in response to the selected horizontal exciter frequency, when the switch position IFh ,Resistor R2 is connected in parallel to the parallel combination R2 'C3 to form an impedance in series with the inverting input. The parallel combination of resistors R2, R3 and C3 has little effect on the filter gain or frequency response. When the switch position is 1 F h , The impedance of the wave gain network C2, C1 and R4 divided by the input resistor ri is determined. It is very clear 'When the loop operating frequency is close to DC, the capacitor C2 becomes larger, and the loop gain is close to that shown in Figure 5A This is the prerequisite. When the operation is not 1Fh, the horizontal frequency switch S 1 is controlled to select the position 2F11. When the switch position is 2Fh, the filter gain is determined by the impedance of the return network R3, C2, C1, and R4 divided by the combination of the series resistors R1 and R2. Because the resistor R2 is larger than R3, the gain at 2Fh is smaller than that at the switch position 1Fh. Therefore, the gain and bandwidth of the active furnace are controlled to be different in response to the selection of the horizontal operating frequency. During the operation with a horizontal frequency of 2Fh * higher, the switch Si selects the 2Fh position. As a result, the gain close to the DC frequency is about 10 d B, as shown by the amplitude versus frequency curve in the dashed line in Figure 5A. At a frequency of approximately 10 Hz, the gain is then reduced to zero and continues to decrease to -20 dB at approximately 100 Hz. Therefore, when operating in 2Fh mode, when the switch S 丨 is in the 2Fh position, the zero gain bandwidth is approximately 10 Hz. Figure 5B shows a phase vs. frequency curve to illustrate two horizontal frequencies, where the dashed line represents the 2Fh mode. When operating at the NTSC frequency lFh, the switch S1 is controlled to select the 1Fh position, which can increase the filter benefit and provide a zero benefit bandwidth exceeding 10 KHz. Refer to Figure 5A, which shows that in the case of lFh, -14- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)--«5, (Please read the precautions on the back before filling in this Page) " & r Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumers ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economics, printed by 2 2581 5 A7 B7 V. Description of the invention (12) The period of operation using higher-level frequencies Large low frequency filter. The division filter produces a wider phase error signal bandwidth than that obtained in the 2 F h mode. Active filter gain and frequency response exchange can be achieved by a single switch contact, which can provide savings in printed circuit board area. Therefore, it can reduce the sensitivity of error field pickup and parasitic phase instability. The user input signal selection results in a corresponding selection among many horizontal frequencies which is sent by the microcontroller 800 to the synchronization source selector switch 5 and the synchronization processing IC 400. The microcontroller 800 generates a special control instruction LFSS, which is addressed ^ Synchronously processing the IC 400 to start or stop the level and to generate ψ. The horizontal drive output signal 403 is terminated by control of the processor 800, as shown by the output switch 412a. Therefore, when there is no horizontal driving signal 403, the horizontal scanning amplifier 500 stops generating the scanning current, and as a result, the pulse Hrt is no longer generated. After the level instruction (LFSS) is stopped, the microcontroller sends a control word to the digital-to-analog converter DAC700. The first DAC700 control word may represent a horizontal frequency switching instruction, which is output from the DAC700 as an analog control signal iH SW, 701, and is coupled to the swap interlock 650. The DAC also generates a second control word, which generates the analog frequency setting potential FREQ.SET302. The instruction LFSS generated by the microprocessor turns off the horizontal drive 403, and as a result stops generating the pulse Hrt. When there is no pulse Hrt, it means that the scanning is stopped, so that the control signal 1 H_S W is combined to form a frequency exchange signal. Therefore, the signal SEL.H.FREQ.402 can change state, and thus one of the different division ratios 値 in the synchronization processor 400 is selected, and thus different levels of frequencies of the loops 100 and 41 are used. As the scan is stopped by the command LFSS, the 'divider 415A can be inserted or bypassed by the self-divider chain without losing the horizontal drive 45〇 __- 15- This paper standard applies the Zhongguanjia Standard (CNS) A4 specification (210 X 297 Male Pei) ~ — — — — — I! · — II * 1 — — (Please read the notes on the back before filling out this page) 4258 1 5 A7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 Five Explanation of the invention (13) or the horizontal scanning amplifier 500 ^ microcontroller sends a horizontal shutdown command before transmitting the horizontal frequency switching command to ensure that the horizontal scanning amplifier 500 is static, thus avoiding circuit damage. This excellent protection circuit 600 can provide further protection by monitoring to determine whether the digital instruction LFSS generated by the microprocessor and the digital instruction transmitted by the I2C bus are demultiplexed and synchronized by the synchronous processor 400. Implementation. The protection circuit 600 can confirm the implementation of the bus barring order and allow the horizontal frequency selection when the pulse Hrt is detected. The synchronization processor 400 and the scan amplifier 500 can be protected from parasitic signals generated, such as changes to the erroneous divider caused by the DAC701 error circuit function and the power supply load or CRT electrical isolation. The excellent protection circuit 600 is shown in Fig. 4, which provides control functions related to the presence and absence of the scanning current, as shown by the detection of the pulses Hrt, 501. Circuit segment 610 detects the presence or absence of pulse 501 and generates an active low interrupt, SCAN-LOSS INTR.615 'which is coupled to the microcontroller, " c〇NT.800 〇 In the first compliance function, circuit 600 confirms The synchronization processor instruction LFSS has terminated the generation of horizontal drive, as shown by β without pulse Hrt. Therefore, there is an interlock between horizontal frequency selection and scanning, and 'frequency exchange is prohibited when pulse Hrt appears. The horizontal frequency selection data is coupled from the microcontroller 800 to the bus 42. The bus is demultiplexed and the frequency selection data is converted from 08 to 700 by analogy to form the exchange signal 1H_SW to be coupled to the circuit segment 650. This circuit segment 650 allows the logic state of the signal iH_SW to be coupled, only when Scanning amplifier 500 provides frequency selection when pulse Hrt is not produced. Therefore, the horizontal frequency change is interlocked and prevented until the relevant pulse scanning is stopped. -16- -I ---- I ---- I Installation ----- -Order i I I --- I * line {Please read the notes on the back before filling this page) Box 4 A λ ^ J ί Ｍ Public 7 9 2 4258? 5
五、發明說明（14 經濟郤智慧財產局員工消費合作社印製 圖4中之段61 〇 ’掃描演繹之脈衝时被二極體〇 1及充電 電容器C"里電阻器尺2向正電壓正向整流。電阻器r ，㈣之接點與PNP電晶體Q1之基極連接，結果，跨電容 备C1上發展（正電荷使電晶體在偏轉相闞脈衝出現時關 閉。電晶體Q1之射極經二極體02耦合至正電壓供應，其 可防止基極射極稽納擊穿，及保證電晶體卩丨在跨電容器 C!上之脈衝電荷約爲h4V或更少時關閉。電晶體…之集 極氬_如又電阻器R3及R4耦合至地。電阻器之接點耦合 至—NPN電晶體(^之基極，電晶射極接地，其集極經電 阻器R7賴合以構成—開路集極輸出信號。當脈衝此出現 時，電晶體Q 1關閉，並使電晶體Q2關閉，使輸出信號 615，掃描損失中斷爲—開路。當無掃描相關之脈衝時， 結果，匯流排演繹之控制功能電路失效，或χ光保護，跨 電容器ci上發展之正電荷經電阻器R1aR2組合被消耗， 因此使電容器ci向地電位充電。當跨電容器C1之電位 才帝稱1 _4V，电印體q 1導電，其集極端點之標稱電位爲二 體D1陰極之電位。電晶體〇1集極之正電位7乂經由電阻 R3及R4组成之電位分壓器加至電晶體〇2之基極，其導 而使集極及輸出信號615爲標稱地電位。信號615爲一中斷 信號，當其甚低時，通知微控制器8〇〇在範例顯示器或線 圈中無掃描電流。 圖4中電晶體Q1之集極亦耦合至電路段65〇 ,其優異的 許或禁止水平頻率之改變，該水平頻率係源自微控制器 及經由匯流排420以資料字發送至數位至類比轉換 ·<· 局 允 器 I— ------I · in —-------------*5^ (請先閱讀背面之注意事項再填寫本頁) -17- 私紙張尺度遶用中國國家標準（CNS)A4規格（210 χ 297公釐） /5 A7 B7 五、發明說明（15 DAC70Q纟位至類比轉換器7()G將資料字轉換並產生類比 控#miH一 SW ’其具有2V電壓値。當控制信號1H — SW 標稱在ον時（Veesat)，被處理器4〇〇之二級所除，並被旁 路，除法器415將·輸出信號咖，3〇1除以432以產生 ，平頻率之較高頻帶—等於或大於2Fh之頻率。當控制信 號1H_SW約爲9.6V時’選擇除以二級415A，其產生864之 結合除法。因此，VC0產生之線鎖時脈LLC3〇i除以864而 產生標私頻率IFh。電晶體(^之集極經構成電位分壓器之 串聯電阻器R5及R6耦合至地。&且器R5&R6之接點耦合 至NPN電晶體Q3之基極，該電晶體有一接地之射極。電晶 體Q3之集極經一負載電阻器尺8連接至正電壓，亦經電阻 器R10耦合至NPN電晶體Q4之基極《電晶體Q4<射極耦 合至電位分壓器之接點，該分壓器在正電壓及地間形成， 該處’電阻器R9連接至供應電壓，電阻器r 1 1連接至地。 因此’電晶體Q 4之射極被约4 V電壓所偏壓。故電晶體q 4 在基極電壓超過4_7V時導電，使集極爲標稱射極電位。電 晶體Q4之集極直接連至控制信號iH-SW,，及觸發器輸入 TRr及基體電路U1，如I.C.LMC555之輸入TH之門限輸入 之接點。因此’箝位至4 V之觸發及門限輸入在控制信號 1H-SW中改變，結果，匯流排產生之指令.或錯誤信號拾起 得以避免而不致改變I. C . U 1之輸出狀態《基體電路u 1之 門限輸入在控制信號1H_SW電壓値超過5.3V時響應，並 導至選擇lFh之掃描頻率。I.C.U1之觸發器輸入在電壓値 小於2.6V時，響應控制信號1H —SW之負渡越，導致選擇 -18- 本紙張尺度適用中固國家標準（CNS)A4規格（210 X 297公釐） --------------裝--- (請先閱讀背面之注意事項再填寫本頁) 幻· 經濟部智慧財產局員工消費合作社印製 425815 A7 Β7 16 五、發明說明（ 2 Fh之掃描頻率。 電路650之作業如下。耦合至電路61〇之沿丨脈衝使電晶體 Q1關閉，其基極經串聯電阻SR3&R4及串聯之電阻器&5 及R6之並聯組合爲地電位。電晶體Q3亦關閉，其集極經 電阻器R8爲標稱供應電壓，此正電位供應至電晶體〇4之 基極而導電，將㈣信號1H_SW信號與積體電路^之接 點連接至約十4V之電位。以+4V之電位加在ί(：⑴之觸發 器及門限輸入，υι被防止而不響應控制信號1H，之改 變_。因此’選擇水平頻率控制·2〇2/4〇2之目前狀態得以 維持，在掃描脈衝Ηη存在時不會改變。在掃描脈衝不在 時’電晶體Q1導電及其集極爲標稱供應電位。此坻電位經 串聯電阻器R5及R6耦合並將電晶體…導電，而使卩4關 閉。當電晶體Q4關閉，積體電路w之禁制，由於心作 業信號1H — SW爲高電壓値，及IC⑴爲低電壓値而被移 去。同理，當2Fh作業被選擇時，㈣信號1H —sw爲低壓 値而U1輸出爲高壓値。因此’水平頻率之改變在相關脈衝V. Description of the invention (14 The Economic and Intellectual Property Bureau employee consumer cooperative prints paragraph 61 in Figure 4. The pulse deduced by the scan is deflected by the diode 01 and the charging capacitor C " in the positive voltage direction. Rectification. The contacts of resistor r and ㈣ are connected to the base of PNP transistor Q1. As a result, the transcapacitor C1 develops (positive charge causes the transistor to close when the deflection phase chirp pulse appears. The emitter of transistor Q1 Diode 02 is coupled to a positive voltage supply, which prevents base-emitter puncture breakdown and ensures that the transistor 关闭 丨 turns off when the pulse charge on the transcapacitor C! Is about h4V or less. The transistor ... The collector argon is coupled to the resistors R3 and R4 to the ground. The contacts of the resistor are coupled to the -NPN transistor (the base of the transistor, the emitter of the transistor is grounded, and the collector is formed by the combination of the resistor R7- Open collector output signal. When the pulse appears, transistor Q1 is turned off, and transistor Q2 is turned off, so that the output signal 615 and the scanning loss are interrupted as open circuit. When there is no scanning-related pulse, as a result, the bus line is deduced Control function circuit failure, or χ light protection, The positive charge developed on the transcapacitor ci is consumed by the resistor R1aR2 combination, so the capacitor ci is charged to the ground potential. When the potential of the transcapacitor C1 is called 1_4V, the electroprinted body q 1 is conductive, and its set extreme point is marked The potential is called the potential of the cathode of the two-body D1. The positive potential of the transistor 01 collector is added to the base of the transistor 02 through a potential divider composed of resistors R3 and R4, which leads to the collector and output Signal 615 is the nominal ground potential. Signal 615 is an interrupt signal, when it is very low, the microcontroller 800 is notified that there is no scanning current in the example display or coil. The collector of transistor Q1 in Figure 4 is also coupled to Circuit section 65, with its excellent permission or prohibition of the change of the horizontal frequency, which is derived from the microcontroller and the data word is sent to the digital-to-analog conversion via the bus 420. < ---- I · in —------------- * 5 ^ (Please read the precautions on the back before filling in this page) -17- Private paper standards use China National Standard (CNS ) A4 specification (210 x 297 mm) / 5 A7 B7 V. Description of the invention (15 DAC70Q bit-to-analog converter 7 () G will The material word is converted and generates an analog control #miH 一 SW 'which has a voltage of 2V. When the control signal 1H-SW is nominally ον (Veesat), it is divided by the second stage of the processor 400, and is bypassed. The divider 415 divides the output signal by 301 and divides it by 432 to generate, the higher frequency band of the flat frequency-a frequency equal to or greater than 2Fh. When the control signal 1H_SW is about 9.6V ', it is selected to divide by the second stage 415A, which A combined division of 864 is generated. Therefore, the linear locked clock LLC30i generated by VC0 is divided by 864 to generate a standard private frequency IFh. The collector of the transistor (^ is coupled to ground via a series resistor R5 and R6 constituting a potential divider. The junction of the resistor R5 & R6 is coupled to the base of the NPN transistor Q3, which has a grounded Emitter. The collector of transistor Q3 is connected to a positive voltage via a load resistor ruler 8. It is also coupled to the base of NPN transistor Q4 via resistor R10. "Transistor Q4 < emitter is coupled to the potential divider. Point, the voltage divider is formed between the positive voltage and ground, where 'resistor R9 is connected to the supply voltage, and resistor r 1 1 is connected to ground. Therefore, the emitter of' transistor Q 4 is biased by a voltage of about 4 V Therefore, the transistor q 4 conducts when the base voltage exceeds 4_7V, making the collector nominal emitter potential. The collector of transistor Q4 is directly connected to the control signal iH-SW, and the trigger input TRr and the base circuit U1 , Such as ILMMC555 input TH threshold input contact. Therefore 'clamp to 4 V trigger and threshold input change in the control signal 1H-SW, as a result, the command generated by the bus. Or error signal pick up to avoid Without changing the output state of I. C. U 1 "the threshold input of the base circuit u 1 is controlled The signal 1H_SW responds when the voltage 値 exceeds 5.3V and leads to the scanning frequency of 1Fh. The trigger input of ICU1 responds to the negative crossing of the control signal 1H —SW when the voltage 控制 is less than 2.6V, resulting in the selection of -18- Paper size applies to China Solid State Standards (CNS) A4 (210 X 297 mm) -------------- install --- (Please read the precautions on the back before filling this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Intellectual Property Bureau's Consumer Cooperative Society. 425815 A7 B7 16 V. Description of the invention (2 Fh scanning frequency. The operation of circuit 650 is as follows. Coupled to the edge of circuit 61o, the pulse causes transistor Q1 to turn off, and its base The parallel combination of the electrodes via the series resistor SR3 & R4 and the series resistors & 5 and R6 is the ground potential. Transistor Q3 is also turned off, and its collector via resistor R8 is the nominal supply voltage. This positive potential is supplied to the transistor The base of 〇4 is conductive, and the contact of the ㈣ signal 1H_SW signal and the integrated circuit ^ is connected to a potential of about ten 4V. The potential of + 4V is applied to ί (: ⑴ trigger and threshold input, υι is prevented Does not respond to the control signal 1H, the change _. Therefore 'select horizontal frequency control The current state of 2〇2 / 4〇2 is maintained and will not change when the scan pulse Ηη is present. When the scan pulse is absent, the transistor Q1 is conductive and its collector is at the nominal supply potential. This 坻 potential is passed through a series resistor R5 Coupling with R6 and conducting the transistor ... to turn off 卩 4. When transistor Q4 is turned off, the integrated circuit w is forbidden, because the heart operation signal 1H-SW is high voltage 値, and IC ⑴ is low voltage 値 and is moved go with. Similarly, when 2Fh operation is selected, ㈣ signal 1H —sw is low voltage 低压 and U1 output is high voltage 値. So the change in horizontal frequency
Hrt存在時可被防止，因而防止水平掃描級5〇〇之可能失 效。 圖1及圖4中之電路段655中，積體電路ΙΠ優異的提供進 -步保護功能，其係以控制電源供應選擇以保證高供應電 ®僅在水平掃㈣率2Fh或更高頻率被選擇時啓動。除了 電路655可防止，在標準清晰度速率掃描期間，不良控制 指令或寄生信號而啓動較高供應電壓。此種較高電壓掃描 電壓之錯誤啓動造成掃描放大器5〇〇之可能破壞。 -19- 本紙張尺度財關家群(CNS)A4規格⑵0 X 297公ίίΤ — li1—!—!·裝！！ I— 訂 *----- - -線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 4258 / 5 B7__ 五、發明說明（17 ) 圖4中，自DAC700之電源供應交換指令2H_VCC供應至 串聯電阻器R13及R14，該串聯電阻器形成電壓分壓器至 地°串聯電阻器之接點連接至電晶體Q5之基極，該電晶體 之射極接地，其集極連接至一開路集極輸出以產生電源供 應控制信號SEL.1H 一 VCC，656。電晶體Q5之基極亦連接 至I.C.U1之放電輸出。電路段655之操作如下。爲響應選__ 擇掃描頻率2Fh或更高頻率，一電源供應啓動指令由微控 制器800產生，並由匯流排420發射。電源供應啓動指令由 &位至類比轉換器DAC700去多工，該轉換器產生一電源供 應控制信號2H一VCC，702。當控制信號702爲高時，例 如，約+9.6V，電晶體Q5導電及集極及電源供應控制信號 SEL.1H一VCC，656之電壓爲電晶體Q5之0V。因此，在電 源供應控制信號656爲低時，較高電壓供應被啓動以供較 高水平頻率掃描作業之用。但較高電源供應電壓之啓動被 控制或聯鎖以防止在以NTSC速率掃描時較高電源供應之錯 *吳啓動。此種錯误電源供應啓動可產生過度之掃描電流， 增加回掃脈衝Hrt波幅，及結果造成掃描放大器5〇〇失效。 電晶體Q5由ICU1之放電輸出電路控制，其在NTSC速率 掃描期間爲飽和低阻抗。因此，IC⑴之放電輸出電路可防 止誤差高供應電壓之啓動，其方法爲在丨F h速率掃描期 間，將電晶體Q 5之基極至地電位，以禁止產生信號 2 H_VCC j因此，鬲供應電壓之啓動可以防止，而信號 SEL.1H—VCC，656可保持爲高，維持低作業電壓之1Fh電 源供應條件。I.C.U1之放電電路在Ui之輸出電路改變狀 -20- 本紙張尺度適用中因國家標準（CNS)A4規格(21^297公爱） I--11----1----^ . ----------------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 ^25815 _____B7 五、發明說明（18 ) 態時成爲無能，即輸出信號SEL H Freq變高之響應選擇 2Fh作業模式。Hrt can be prevented when it is present, thus preventing the possible failure of the horizontal scanning level 500. In circuit segment 655 in Figures 1 and 4, the integrated circuit III provides excellent step-by-step protection. It controls the power supply selection to ensure high power supply. Only at the horizontal sweep rate of 2Fh or higher Start when selected. Except for the circuit 655, it is possible to prevent a bad control command or a parasitic signal from starting a higher supply voltage during a standard definition rate scan. Such an incorrect start of the higher voltage scan voltage may cause the scan amplifier 500 to be damaged. -19- This paper is a paper size (CNS) A4 specification (0 X 297) ίί — li1 —! —! Installed! !! I—Order * -------Line (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 4258/5 B7__ 5. Description of the invention (17) Figure 4 The power supply exchange instruction 2H_VCC from DAC700 is supplied to the series resistors R13 and R14. The series resistor forms a voltage divider to ground. The connection point of the series resistor is connected to the base of transistor Q5. The electrode is grounded, and its collector is connected to an open collector output to generate a power supply control signal SEL.1H-VCC, 656. The base of transistor Q5 is also connected to the discharge output of I.C.U1. The operation of circuit segment 655 is as follows. In response to selecting a scanning frequency of 2Fh or higher, a power supply start command is generated by the microcontroller 800 and transmitted by the bus 420. The power supply start command is multiplexed by the & bit-to-analog converter DAC700, which generates a power supply control signal 2H-VCC, 702. When the control signal 702 is high, for example, about + 9.6V, the transistor Q5 is conductive and the collector and power supply control signals SEL.1H-VCC, and the voltage of 656 is 0V of the transistor Q5. Therefore, when the power supply control signal 656 is low, the higher voltage supply is activated for a higher level frequency scanning operation. However, the start of the higher power supply voltage is controlled or interlocked to prevent the fault of the higher power supply when scanning at the NTSC rate * Wu starts. Such an incorrect power supply startup can generate excessive scanning current, increase the flyback pulse Hrt amplitude, and as a result cause the scanning amplifier to fail 500. Transistor Q5 is controlled by the discharge output circuit of ICU1, which is saturated with low impedance during the NTSC rate scan. Therefore, the discharge output circuit of IC⑴ can prevent the start of the supply voltage with high error. The method is to turn the base of transistor Q 5 to ground during the F h rate scan to prohibit the generation of the signal 2 H_VCC j. Therefore, The start of the voltage can be prevented, and the signal SEL.1H-VCC, 656 can be kept high, maintaining the 1Fh power supply condition of low operating voltage. The discharge circuit of ICU1 is changed in the output circuit of Ui-20- This paper is applicable due to the national standard (CNS) A4 specification (21 ^ 297 public love) I--11 ---- 1 ---- ^. ---------------- line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ^ 25815 _____B7 V. Description of the invention (18 ) State becomes incapable, that is, the response of the output signal SEL H Freq goes high selects the 2Fh operating mode.
水平頻率選擇與掃描存在間之新穎聯鎖可證實匯流排發 射之指令之實施。此外，電路損壞可由新穎電路防止，該 電路可防止誤差水平交換或電壓供應啓動。 A 1 ϋ n n It «I I I 1— 1 n I t ·1 I <請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 格 規 -4 ,)A S l(CN i準 標 I家 I國 一國 |中 -用 j適 I度 尺 一張 紙 I本 釐 公 7 9 :2A novel interlock between the horizontal frequency selection and the presence of the scan confirms the implementation of the commands issued by the bus. In addition, circuit damage can be prevented by a novel circuit that prevents error level switching or voltage supply startup. A 1 ϋ nn It «III 1— 1 n I t · 1 I < Please read the precautions on the back before filling out this page) The Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumption Cooperatives, prints the code-4,) AS l (CN i quasi-standard I home I country one country | Chinese-use j appropriate I rule a piece of paper I centimeter 7 9: 2