425755 Λ' 五、發明説明（1 ) (發明所屬之技術領域） 本發明係關於一種振盪電路。 (以往之技術） 以往，連接將水晶振動件設於外面所使用之CMO S 反相器等所構成之振盪電路I C與緩衝電路I C時，在振 盪電路內之CMO S反相器之輸出部外設A C耦合電容器 ，並經由此連接緩衝電路之輸入端子。 (解決課題所用之手段） 在緩衝電路之輸入端子設有保護電路|而該保護電路 係具有約5 p F之靜電電容。因此，作爲A C耦合電容器 ，需要消除該保護電路具有之靜電電容分量之程度的靜電 電容，例如約lOOpF之大小者。故，須外設之AC耦 合電容器之構成會變大，而具有增大電路規模之問題。 (解決課題所用之手段） 經濟部中央標準局貝工消費合作社fp·裝 (請先閱讀背面之注意事項再填艿本頁) 本發明係將振盪用之CM〇 S反相器與A C耦合電容 器及緩衝電路形成於一晶片上，由於可以不需要設於緩衝 零路之輸入端子部的保護電路，因此，可減小A C耦合電 容器之靜電電容，並.可減小電路規模 又，將A C耦合電容器及緩衝電路形成於一晶片上， 也可得到與上述同樣之效果。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公犮> -4- 42575 5 Β' ___ 五、發明説明$ ) (發明之實施形態） 本案之申請專利範圍第1項之發明’係在輸入輸出間 具備連接水晶振動件之CMO S反相器，及將該CM〇 S 反相器之輸出經由A C耦合電容器輸入之緩衝電路的振盪 電路，其特徵爲：將上述A C耦合電容器與上述CMO S 反相器及上述緩衝電路形成於一晶片上者。 本案之申請專利範圍第2項之發明，係在輸入輸出間 具備連接水晶振動件之CMO S反相器’及將該CMO S 反相器之輸出經由A C耦合電容器輸入之緩衝電路的振盪 電路，其特徵爲：將上述A C耦合電容器與上述緩衝電路 形成於一晶片上者。 (實施例） 經濟部中央標準局—工消費合作社印策 以下，依照表示於圖式之實施例具體地說明本發明。 在第1圖中，在CMO S反相器1之輸入輸出間，連 接有回饋電阻2，水晶振動件3，在CMOS反相器1之 輸入側，輸出側分別連接有負載電容4、5。又，以 CMOS反相器1，回饋電阻2，水晶振動件3，負載電 容4、5構成振盪電路。 CMO S反相器1之輸出經由A C耦合電容器6及信 號調節電路7連接於緩衝電路8之輸入。緩衝電路8之輸 出係連接於分頻電路等之後段之電路1 2。 又，CMOS反相器1 ，回饋電阻2，負載電容4、 5，AC耦合電容器6，信號調節電路7，及緩衝電路8 -5- (請先閱讀背而之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2!ΟΧ297公釐） 五、發明説明0 ) 係形成於一晶片上，而水晶振動件3係被外設。 緩衝電路8之兩個電源瑞子，係爲了減低耗電分別經 由定電流電路9連接於電源。爲了將CMO S反相器1之 振盪輸出之振幅中心對準緩衝電路8之動作點，在本例子 係設於信號調節電路7。信號調節電路7係由串聯地連接 於電源間之電阻1 0、1 1所構成，調整電阻1 0與電阻 1 1之電阻比，來調整CMOS反相器1之輸出位準。亦 即，調整成將CMO S反相器1之輸出之振幅中心對準緩 衝電路8之動作點。 經濟部中央標率局員工消費合作社印製 {讀先閱讀背面之注意事項再填舄本頁) 如此，由於緩衝電路8與A C耦合電容器6形成於一 晶片上，因此，可以不需要設於以往所需要之緩衝電路8 之輸入端子部的保護電路。又，由於不需要保護電路所具 有之電容成分，因此，可減小A C耦合電容器6之電容値 。具體而言，以往需要約1 0 0 P F者則約1 p F即可。 亦即，可減小AC耦合電容器6之構成》又，將AC耦合 電容器若介經例如鉬等之金屬或鉬等之金屬與聚矽酮所形 成•則可更減小構成，而且，電容値之正確對準成爲可能 。又，由於將AC耦合電容器6設在晶片上，因此，成爲 不需要外設作業。 又，代替信號調節電路7，在緩衝電路8之輸入輸出 端子間設置回饋電阻2也可以。 又，CMOS反相器1之兩個電源端子中之其中一方 或雙方經由用以低耗電化之定電流電路，電阻等連接於電 源，構成振盪電路時，亦爲本發明係有用之電路。 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） .g .425755 Λ 'V. Description of the invention (1) (Technical field to which the invention belongs) The present invention relates to an oscillation circuit. (Conventional technology) In the past, when an oscillation circuit IC and a buffer circuit IC composed of CMO S inverters and the like used to install crystal resonators outside were connected, the output of the CMO S inverter in the oscillation circuit was external Set an AC coupling capacitor and connect the input terminal of the buffer circuit through this. (Means used to solve the problem) A protection circuit is provided at the input terminal of the buffer circuit. The protection circuit has an electrostatic capacitance of about 5 p F. Therefore, as the AC coupling capacitor, it is necessary to eliminate an electrostatic capacitance to the extent that the electrostatic capacitance component of the protection circuit has, for example, a magnitude of about 100 pF. Therefore, the configuration of the AC coupling capacitor that needs to be externally becomes large, and there is a problem of increasing the circuit scale. (Means used to solve the problem) FPC · Assembly of Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs (Please read the precautions on the back before filling this page) The present invention is a CM0S inverter and AC coupling capacitor for oscillation The buffer circuit is formed on a chip. Since the protection circuit provided in the input terminal of the buffer zero circuit is not required, the electrostatic capacitance of the AC coupling capacitor can be reduced, and the circuit scale can be reduced. The capacitor and the snubber circuit are formed on a single chip, and the same effects as described above can be obtained. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 Gong > -4- 42575 5 Β '___ V. Description of the invention $) (Implementation mode of the invention) The invention of the scope of patent application No. 1 in this case' system An oscillation circuit including a CMO S inverter connected to a crystal vibrator between the input and output, and a buffer circuit inputting the output of the CMOS inverter through an AC coupling capacitor is characterized in that the AC coupling capacitor and the above are coupled. The CMO S inverter and the buffer circuit are formed on a chip. The invention of item 2 in the scope of the patent application for this case is an oscillation circuit provided with a CMO S inverter connected to a crystal vibrator between the input and output, and a buffer circuit that outputs the CMO S inverter through an AC coupling capacitor. It is characterized in that the AC coupling capacitor and the buffer circuit are formed on a chip. (Example) The policy of the Central Bureau of Standards of the Ministry of Economic Affairs-Industrial and Consumer Cooperatives The present invention will be specifically described with reference to the examples shown in the drawings. In the first figure, a feedback resistor 2 and a crystal resonator 3 are connected between the input and output of the CMO S inverter 1, and load capacitors 4 and 5 are connected to the input side and the output side of the CMOS inverter 1, respectively. An oscillating circuit is constituted by a CMOS inverter 1, a feedback resistor 2, a crystal resonator 3, and a load capacitor 4,5. The output of the CMO S inverter 1 is connected to the input of the buffer circuit 8 via an AC coupling capacitor 6 and a signal conditioning circuit 7. The output of the buffer circuit 8 is a circuit 12 connected to a subsequent stage such as a frequency division circuit. In addition, CMOS inverter 1, feedback resistor 2, load capacitance 4, 5, AC coupling capacitor 6, signal conditioning circuit 7, and buffer circuit 8 -5- (Please read the precautions before filling this page) The paper size applies the Chinese National Standard (CNS) A4 specification (2.0 × 297 mm). 5. Description of the invention 0) is formed on a wafer, and the crystal vibrating part 3 is external. The two power sources of the snubber circuit 8 are respectively connected to the power source through the constant current circuit 9 in order to reduce power consumption. In order to align the amplitude center of the oscillation output of the CMO S inverter 1 with the operating point of the buffer circuit 8, the signal conditioning circuit 7 is provided in this example. The signal conditioning circuit 7 is composed of resistors 10 and 11 connected in series between the power sources, and adjusts the resistance ratio of the resistors 10 and 11 to adjust the output level of the CMOS inverter 1. That is, it is adjusted so that the amplitude center of the output of the CMO S inverter 1 is aligned with the operating point of the buffer circuit 8. Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (read the precautions on the back and then fill out this page) So, since the buffer circuit 8 and the AC coupling capacitor 6 are formed on a single chip, they do not need to be installed in the past A protection circuit for the input terminal portion of the buffer circuit 8 is required. In addition, since the capacitance component of the protection circuit is not required, the capacitance 値 of the AC coupling capacitor 6 can be reduced. Specifically, in the past, about 1 p F was required for about 100 P F. That is, the structure of the AC coupling capacitor 6 can be reduced. Furthermore, if the AC coupling capacitor is formed by a metal such as molybdenum or a metal such as molybdenum and polysilicon, the structure can be further reduced, and the capacitance 値Correct alignment is possible. Moreover, since the AC coupling capacitor 6 is provided on the chip, no external work is required. Instead of the signal conditioning circuit 7, a feedback resistor 2 may be provided between the input and output terminals of the buffer circuit 8. In addition, one or both of the two power supply terminals of the CMOS inverter 1 are connected to a power source through a constant-current circuit, a resistor, or the like for reducing power consumption, and are also circuits useful in the present invention when constituting an oscillation circuit. This paper size is applicable to Chinese National Standard (CNS) Λ4 specification (210X297 mm) .g.
1 Ο K 、，“ Λ 7 1Γ 五、發明説明θ ) 又，將CMOS反相器1，回饋電阻2，負載電容4 、5，AC耦合電容器6，信號調節電路7，及緩衝電路 8形成於一晶片上，惟將A C耦合電容器6，信號調節電 路7，及緩衝電路8形成於一晶片上，而將CMOS反相 器1，回饋電阻2，負載電容4、5作爲另一晶片也可以 。由於此時也不需要設於以往緩衝電路之輸入端子部的保 護電路，因此，具有與上述同樣之效果。 (發明之效果） 依照本發明，由於可以不需要以往設於緩衝電路8之 輸入端子部的保護電路，因此，可減小A C耦合電容器之 電容·並可減小電路規模。 (圖式之簡單說明） 第1圖係表示本發明之實施例的電路圖》 (記號之說明） (誚先間讀背面之注意事項再填巧本頁) 經濟部中央標準局負工消t合作社印犁 1 C Μ 0 S反相器 3 水晶振動件 6 A C耦合電容器 8 緩衝電路 本紙張尺度適用中國國家標準（CNS ) A4说格（210X297公茇）1 〇 K, "Λ 7 1Γ V. Description of the invention θ) Furthermore, a CMOS inverter 1, a feedback resistor 2, a load capacitor 4, 5, an AC coupling capacitor 6, a signal conditioning circuit 7, and a buffer circuit 8 are formed in On one chip, the AC coupling capacitor 6, the signal conditioning circuit 7, and the buffer circuit 8 are formed on one chip, and the CMOS inverter 1, the feedback resistor 2, and the load capacitors 4, 5 can be used as another chip. Since a protection circuit provided in the input terminal portion of the conventional buffer circuit is not required at this time, it has the same effect as described above. (Effect of the Invention) According to the present invention, the input terminal provided in the buffer circuit 8 in the past can be eliminated. Therefore, the capacitance of the AC coupling capacitor can be reduced, and the circuit scale can be reduced. (Simplified description of the diagram) Fig. 1 is a circuit diagram showing an embodiment of the present invention "(Description of Symbols) (诮Please read the precautions on the back before filling in this page.) The Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperative Cooperatives, Cooperative Printing Plough 1 C Μ 0 S Inverter 3 Crystal Oscillator 6 AC Coupling Capacitor 8 Buffer Circuit National Standards country (CNS) A4 said grid (210X297 male betel)