TW425672B - Forming HV-CMOS with grading doping electrode - Google Patents

Abstract

A structure and manufacturing method for high voltage semiconductor device which can form N-well 1 and N-well 2 as two types of different doping densities as the grading doping in drift region so as to increase the current drive capability and breakdown voltage. The structure further comprises a buried spacer oxide used as a focal point on the edge of a buried poly gate to prevent the premature occurrence of breakdown voltage; lastly, because the gate is formed by pattern etching with trench isolation method that not only the length of the gate channel increases, but also the position of the channel and drift region are changed to vertical direction instead of the conventional horizontal direction so that the occupied chip area by the device can be greatly reduced.

Description

4256 7 2 V. Description of the invention (1) 5-1 Field of the invention The present invention relates to a structure and manufacturing method of a semiconductor device, and particularly to a structure and manufacturing of a device that improves current driving capability and reduces the area occupied by the device. method. 5-2 Background of the Invention: With the development of time and the evolution of technology, integrated circuits are gradually moving towards the goal of south density. This also makes the volume of semiconductor components and the distance between components also gradually shrink. Therefore, even if the semiconductor components are as small as Angstroms as the measurement unit, it still needs to maintain the best use of the components. Importantly, especially under high voltage operation, high current drive capability can still be easily achieved. The traditional high-voltage CMOS (HV-CMOS) element structure 'its channel and dr 1 ft region are easy to occupy a large chip area in the horizontal direction, and it is not easy to achieve high current driving capability under high voltage operation . Therefore, the need for more advanced manufacturing technologies and better component structures is urgent. The first circle A is a cross-sectional view of a conventional CMOS transistor structure, and its structure includes a p-type conduction substrate 丨 〇, an N + source 丨 丨, an N + drain 丨 2, and a drift region 13 ′ field An oxide layer (Fox) 14, a gate oxide layer 15 ', and a gate electrode 16.

Page 4 425672 V. Description of the invention (2) The above-mentioned traditional CMOS transistor structure has channels and drift regions in the horizontal direction and only the source and non-electrode regions are located in the semiconductor substrate. Such a structure makes the channels and The drift area is even shorter. When the channel length of CMOS is shortened, ‘Hot Carrier Effects will become more severe’, and there are many ways to solve the thermal carrier effects of short-channel CMOS. The simplest of these is to lower the operating voltage of the CMOS transistor. For example, reducing from 5V to 3.3 V, or 2.5 V, reduces the transverse electric field strength of the channel so that hot carriers cannot be formed. Although the phenomenon of "carrier multiplication" can be greatly reduced in this way, it cannot be used in high-voltage operation. If you want to avoid reducing the operating voltage of CMOS transistors and also solve the hot-carrier effect of short-channel CMOS, then Need to lengthen the CMOS channel. Both the horizontal structure and the lengthened CMOS channel will occupy a larger chip area, which will not be able to dissolve into the semiconductor device and shrink the volume. Another widely used method to solve the hot carrier effect is to add a set of doping concentration to the source and drain of the original CMOS that is lower than the original N + source and drain concentration. N-type region, this design a is called slightly doped; and pole (Lightly Doped Drain), or LDD for short. The use of LDD is not entirely without its drawbacks. First, it will complicate the fabrication of CMOS. Second, because the LDD has a lower doping level, the resistance is higher, which increases the series resistance from drain to source (S e r e e s Resistance). This will lead to a reduction in the operating speed of the components and an increase in power consumption.

Page 5 42567 2 V. Description of the invention (3) Furthermore, the lighter ^ ^ under the field oxide layer brings it back and results in a weaker current drive capability. „,... (Current Drive ι The source and non-polar structures are symmetrical, with doping concentrations on both sides. The overall current driving capability is weaker. Finally, this transistor structure is prone to parasitic bipolar under high voltage. 5-3 Purpose and Summary of the Invention: In view of the many shortcomings of the traditional high-voltage component structure in the above background of the invention, the main purpose of the present invention is to propose a structure and manufacturing method for high-voltage semiconductor components, with two different The doping concentration is used as the gradient doping of the drift region to improve the current driving capability of the device and increase the Breakdown Voltage. Another oxide spacer “氧化. ^ × ide” is used as the polycrystalline silicon gate (P 〇ly Gate) at the edge of the force to avoid the collapse of high voltage early. Furthermore, by changing the position of the channel and drift region of its components, the traditional horizontal direction is changed to the vertical direction, so that the area occupied by the chip is greatly reduced. The invention is a method for forming a transistor element. Its special structure includes at least the following components. In the first diagram B, first, a p-type silicon semiconductor substrate 100 is provided, in which a first trench 14o has been formed, and The second trench 170 is deeper than the first trench. Next, a pair of source (200, 130, and 120) and drain (21, 131, and 121) regions are formed on the first

Page 6 4 2567 2 ·. Description of the Five 'Invention (4) The grooves and the second grooves have the same depth. In the semiconductor substrates on both sides, the depth is about the same as that of the second trench, and the continuity of the conduction type is greater than that on and on the first, first, and first concentrations of the pair. A pole and a doping pattern are formed in a first and the same as the first doped region to form a third and second doped region. The three doped region—the doped region—and the polar region have formed a qualitative conduction system. Conversely, the concentration of the first and second doped regions 130 and 1 31 of the pair of source and drain regions. Finally, after the impurity regions 200 and 210 are completely pushed, the surface of the third dopant is on-conducting type and its first doped regions 120 and 121 are doped in the semiconductor substrate and in the first doped region. The second dopant on-type in the hetero-region, and its doped source and drain regions are complete. The pair of source and drain regions is a source / drain surface-type system. The structure of the element, which is the same as the above-mentioned first concentration is greater than the second doped region, further includes a sidewall of the trench, which is used as an interlayer. Furthermore, a gate oxide layer and the bottom surface, and there are a plurality of oxide layers and fill the first trench with the same source and drain surfaces. Including the silicon oxide barrier wall i 6 〇 at the edge of the first electrode electrode and an insulation 180 formed in the side wall of the second trench spar burial gate electrode 19 formed in the groove and the second Grooves, the surface of which is about the same as the above-mentioned special structure, at least the way to place the gate electrode, and the following include the following advantages. First, the groove wall and the position of the channel and drift region are changed.

Page 7 —425672 V. Description of the invention (5) Change from horizontal to. The length of the channel is also greatly increased as the length of the font is converted to the length of the present invention. If the first doping is light, the device can hold the voltage of the high-voltage doped region and the second doped region but its current can drive the doping. Miscellaneous concentration, from shallow to thick. Finally, the upper layer of the "between the invention" is not lower than the 11-concave groove-shaped reduced region of the vertical direction of the lower layer and the second, but its current doping concentration force will be stronger to compensate for the early collapse of the gap wall. Both can be gated and the driving energy of the hot-loaded source-doped region is equivalent. Therefore, the above-mentioned arrangement can avoid reducing the occupation length, and the sub-effect / drain doping force is weak but very strong. ¾. Also, the crystals do not have the same doping concentration as traditionally produced. If the element is used, the "to increase the chipping area of the chip" is "one" because the channel concentration is the same and the first doping is not much different. Figure 5-4 shows the breakdown voltage early. The first diagram A shows a typical CMOS source / drain cross-section structure. The first diagram B shows the cross-sectional structure of a high-voltage element in one embodiment of the present invention. Brother A Figure A shows a semiconductor substrate. FIG. 2B shows a semiconductor substrate with epitaxial S1 Hcon selectively added. FIG. 2C shows that an oxide layer is formed on the surface of the semiconductor substrate. The second D diagram shows a first doped region in the semiconductor substrate that is doped with n-type dopants.

Page 8 4 256 7 2 V. Description of the invention (6) The second E diagram shows the second doped region in the semiconductor substrate that is approaching the n-type dopant. FIG. 2F shows that a first trench is formed in the semiconductor substrate. Figure G shows a conformal deposition of an oxide layer. The second figure shows the formation of a spacer wall and a second trench. FIG. 2I shows that a gate oxide layer is formed on the surface and the sidewall of the bottom of the second trench. The second J figure shows that a polycrystalline silicon layer is deposited and fills the first trench and the second trench. The second K diagram shows a third doped region in the semiconductor substrate, which is an n-type dopant, which is a cross-sectional structure pattern of a high-voltage device according to another embodiment of the present invention. The second L pattern is the same as the first B pattern. Representative symbols of main parts: 10 ρ-type semiconductor substrate 11 source 12 drain 13 drift region 14 field oxide layer (FOX) 1 5 gate oxide 16 gate 100 ρ type semiconductor substrate 101 p ~ epi type semiconductor substrate

425672 V. Description of the invention (7) 110 silicon oxide layer (silicon oxide) 1 2 0 source first doped region (n-well 1) 1 2 1 drain first doped region (N-well) 130 source Second doped region (N-well 2) 131 Drain second doped region (N-well 2) 140 first trench 1 5 0 silicon oxide layer 1 6 0 spacer 1 7 0 Two trenches 1 8 0 gate oxide layer 190 polysilicon gate electrode 2 0 0 source third doped region 2 1 0 drain third doped region 5-5 invention Detailed description: In the present invention, an embodiment order provides a gradient doped source / sink, = structure and manufacturing method for forming a still-complementary complementary metal oxide semiconductor (HV-CM0S), and a process for its special structure Detailed descriptions in the second A to the first FIG. 1 First, a p-type semiconductor substrate ι ′ is provided, such as the second A ::. FIG. 2B shows the first embodiment of the present invention, which can selectively add epitaxial silicon and the substrate 101 to prevent latch-up from occurring in the complementary metal oxide semiconductor device. In order to simplify the structure of the invention The following device structures will not include epitaxial silicon semiconductor substrates (p-epi

I! 1

IH No. 0 page 425672 V. Description of the invention (8) substrate) 101 ° In figure 2c, a silicon oxide layer 11 is formed on the semiconductor substrate by a plasma chemical vapor deposition (p) asma Enhanced CVD method. On the surface, the thickness of the silicon oxide layer is between about 900 and 3500 angstroms. The oxidized stone layer mentioned above can be formed by any of the chemical vapor deposition methods (Chenucal Vapor Deposition). For example, Ap is limited to PECVD. This oxidized stone layer 11 series uses "as a second plant"

Im = V day or Λ thermal diffusion process me · 1 ... ㈣-) The sacrifice layer (bacriiiciai Layer) that reduces the damage during ion implantation 〇 The map of the pole 'uses the famous lithography technology to determine the source / No thermal diffusion process goes to the first dopant, the first type of conductive type is opposite to the above semiconductor substrate = the second doping is shown, the source electrode is formed using the same steps " and the pole: the same = (, Γ) 130 and 131 'The conduction type of the second dopant within the conduction type of the first-doped region'1 has a doping degree greater than the doping concentration of t 雊 &. During the engraving, the curtain cover layer is formed with a trench trench isolation pattern U0, the depth of which is equal to the depth of ^^ well but does not exceed. Page 11 44s72 V. Explanation of the invention (9) In the second G chart, 'a silicon oxide layer 1 50 is formed along the edge using a conformal covering (conf ormai) type deposition method.' This layer can also be made of silicon nitride. The material 'far silicon oxide layer covers the bottom surface and sidewalls of the first trench 140 and the top surface of the source / drain. This silicon oxide layer 50 cannot be formed by chemical vapor deposition, otherwise the entire first trench] 40 will be filled, which will affect the contact area of the gate in the rear. Therefore, a structure with higher adhesion should be used because its fluidity is lower. In the second} {figure, the silicon oxide layer 1-50 on the top surface of the source / drain is etched back to a height of 110. Subsequently, a mask layer is generated and a second trench 171 is etched with a trench isolation method pattern, the depth of which exceeds the depth of the first trench 140, and its width is narrower than that of the first trench. The length of the side wall and the bottom of the second trench 1 70 is equivalent to the length of the gate. When the second trench 170 is generated, a spacer 160 is also formed on the side wall and a part of the bottom of the first trench 400. On the surface, the spacer is an insulating layer, which is used as the point of force for the edge of the gate electrode. 180 in the second trench In the second I picture, a gate oxide layer 170 is formed along the edge on the bottom surface and on the sidewall. ί 1 η Ϊ Command, etch back the silicon oxide layer Ϊ top surface of the source / drain top surface. After that, a low-pressure chemical vapor deposition method was used to replace a 亓 -type doped polycrystalline silicon (UoPed Polysilicon) layer on the surface and fill the first trench and the second trench.

Page 12 425672 V. Description of the invention (ίο) _____ Carved the polycrystalline cutting layer: to form 1 layer; ^ — the same height as the top surface of N well 2. The exposed surface is made of silicon compounds or metal materials. The i-gate electrode can also be polycrystalline. Finally, as shown in Fig. -K, ions with heteroconcentrations are formed to form-筮 = edge & And N + -type drain electrode 2 Η & it is on the surface of the original electrode and in the diode region, that is, the surface of the pole region, the conductivity of the dopant in the third doped region leads to the type 1 pole / not mentioned above The first and second doped regions, and their doping concentration is greater than 1 can not only reduce the occupation = = Example and can increase the breakdown voltage and prevent the breakdown voltage from occurring earlier: violent force 'J hair: another implementation The example is described in the second L diagram, and its knot is very similar to the first one described above. The only difference is that the depth of the first trench is excavated to the bottom of N well 2 and the second trench does not exceed N well 1. The layer only makes the structure have smaller partition walls but longer passages. However, j is structurally different but has the same functions and advantages. The above description is only a preferred embodiment of the present invention, and is not intended to determine the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit of the limits disclosed by the present invention should be included below Said within the scope of the patent. sf

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Claims (1)

425672 1. A high-voltage element includes at least: a semiconductor substrate having a first trench and a second trench formed therein; and a pair of source and drain regions formed on the first trench and the second phase, respectively. The semiconductor substrates on both sides have a depth approximately equal to the depth of the second trench. The first doped region is formed in the pair of source and wave regions, and the conduction type of the first dopant is opposite to the semiconductor substrate; A first doped region is formed in the pair of source electrodes; and a second dopant in the electrode region and above the first region has the same conduction type as the first doped region, and Its doping concentration is greater than the concentration of the first doped region; the second doped region is formed in the pair of source and drain regions and above the second hetero region; its surface is the source / drain region; On the surface of the polar region, the conduction type of the third dopant in the third region is the same as that of the first and second t regions, and its doping concentration is greater than the concentration of the second doped region; A barrier wall is formed on the sidewall of the first trench; a gate oxide layer is formed on the bottom surface of the second trench and on the sidewall 丨Trench to. A buried gate electrode is formed on the gate oxide layer and the second trench, and the surface of the gate electrode is approximately above the source and fills the surface of the first and non-polar regions. 'Where the above = semiconductor ...' is used as the edge of the buried closed-electrode = force point and an insulating layer. test 425672 6. Scope of patent application 3. For the element of scope 2 of the patent application, the above-mentioned spacer is between the source / drain region and the buried closed electrode. 4. As for the element in the second patent application scope, the above-mentioned spacers include at least one of the following: silicon oxide, nitride nitride. 5. For the device according to item 1 of the patent application scope, wherein the above semiconductor substrate includes at least silicon. 6. As for the element in the scope of the patent application, the above-mentioned buried gate electrode contains at least one of the following:-polysilicon 'polysilicon compound' metal. 7. The element in the scope of patent application, in which the above-mentioned semiconductor substrate is a p-type conduction type. 8. The device according to item 1 of the scope of patent application, wherein the first, second and third doped regions of the above source / drain regions include at least n-type doped semiconductors 9. Manufacturing of a high-voltage element structure Method 'at least includes: providing a semiconductor substrate; covering an oxide layer on a surface of the semiconductor substrate; Page 15 4 256 7 2 The scope of the patent application forms a region over the pair of source ^ conduction systems to form a doped region ~ a doped region to form a doped region above the doped region, and Forming one forming one forming one and forming a slot and the first pair of source and pole and non-electrode are opposite to the upper second doping 'within and its doping third doping' and its surface third doping > In the polar region, the semiconducting region is in the second doped concentration region, and is thus the guide of the substance, which is the source impurity of the pair of source to the first body substrate and the source / pass type of the first pair of substrates. The doping concentration greater than the second first trench spacer on the gate oxide layer and a first two trenches of the first trench in the second trench rarely include a first formed in a first doped impurity region. The dopant concentration is the same as that of the first doped region in the first conduction type and in the first conduction type; the third is the same as the above in the non-polar region and on the surface of the second non-polar region. The concentration of the first and second doped regions; at the same position; on the sidewall; the bottom surface and On the wall; the buried gate electrode is on the gate oxide layer and fills the first and second trenches, the surface of which is about the same as the surface of the source and drain regions, such as the manufacturing method of item 9 in the scope of patent application, Among them, epitaxial silicon can be added to the semiconductor I-plate. 11. The manufacturing method according to item 9 of the scope of patent application, wherein the above-mentioned oxide layer> 'includes silicon oxide. 6. Scope of patent application 1 2. The manufacturing method according to item 9 of the scope of patent application, wherein the above-mentioned oxide layer can be formed by any chemical vapor deposition method (C hemica 1 V a ρ 〇 Deposition), such as APCVD, LPCVD , PECVD. 1 3. The manufacturing method according to item 9 of the scope of patent application, wherein the above-mentioned first trench is formed by an etching process, and its depth is equivalent to the depth of the first doped region but does not exceed. 14 · The manufacturing method according to item 9 of the scope of patent application, wherein the above-mentioned second groove is formed by a last name engraving process, and its depth exceeds the depth of the first groove. 15 · The manufacturing method according to item 9 of the scope of patent application, wherein the width of the second groove is narrower than that of the first groove. 16. The manufacturing method according to item 9 of the scope of patent application, wherein the above-mentioned spacer is an insulating layer formed by a conformal covering method (conformation) and etch-back. 17: The manufacturing method according to item 16 of the scope of patent application, wherein the above-mentioned insulating layer 疋 is formed in the semiconductor substrate and is used as a point of force for the buried gate edge. 4 1 8 · The manufacturing method according to item 16 of the scope of patent application, wherein the above-mentioned insulating layer is interposed between the source / drain region and the buried gate electrode. Page 17 425672_ VI. Scope of Patent Application 19 · For the manufacturing method of Item 16 in the scope of patent application, the above-mentioned insulating layer includes at least one of the following: silicon oxide, silicon nitride. 20 The manufacturing method according to item 9 of the scope of patent application, wherein the above-mentioned part of forming the buried gate electrode includes at least a step of depositing a polycrystalline silicon gate electrode. 21 The manufacturing method of claim 20 in the scope of patent application, wherein the step of forming the buried gate electrode includes: depositing a polycrystalline silicon conductive layer on the gate oxide layer, which fills the first trench and the second The trench extends to the surface of the semiconductor substrate on both sides of the first trench and the second trench; and etch back the conductive layer until the surface of the semiconductor substrate is exposed. 2 2. The manufacturing method according to item 9 of the scope of patent application, wherein the above source and non-electrode regions are formed by an ion approach (d r i v e-i η) procedure. 2 3. According to the manufacturing method of item 9 in the scope of patent application, the above-mentioned dopant is selected from the group consisting of arsenic, phosphorus, and boron. Page 18