TW425575B - Address space manager for assigning part of address space to data storage without non-addresable cell, semiconductor memory device with built-in address space manager and memory system - Google Patents

Abstract

An address space manager (31c/31d) assigns address sub-spaces forming parts of an address space to memory units (31a/31b) at least one (31b) of which stores m (6M) pieces of data information where m is greater than (n-1)<SP>th</SP> power of 2 and less than n<SP>th</SP> power of 2, wherein the address space manger (31c/31d) converts external address bits (A21/A22) to internal address bits (A22'/A22') in such a manner that the addresses are respectively assigned to the memory cells of the memory units (31a/31b) without non-addressable memory cell.

Description

L 4 2 5 5 7 5 'V. Description of the Invention u) [Field of the Invention] The present invention relates to address space management technology, and more particularly, to designating a portion of the address space to a data storage device such as a semiconductor memory device. Address space manager, a semiconductor memory device with a built-in address space manager and a memory system. [Explanation of Related Technology] A typical example of a semiconductor memory device is disclosed in Japanese Patent Laid-Open Publication No. 6 2-5 2 7 9 4. The prior art semiconductor memory device is classified as a read-only memory device, and the prior art semiconductor read-only memory device includes a memory cell array and an address decoder for the memory cell array. The memory cell array includes a plurality of memory cells, and the plurality of memory cells form an address space. The input address signal represents an address space larger than the address space of the memory cell array and is supplied to the address decoder. The program component is further incorporated into a prior art semiconductor read-only memory device, and converts a combination of address decoded signals into another combination of address decoded signals. The user can program this conversion and freely specify a portion of the address space represented by the input address signal to the memory cell array. FIG. 1 illustrates the configuration of a prior art memory system 1. The microprocessor 2 is accompanied by a prior art memory system 1. The prior art memory system 1 includes a semiconductor memory device 1 a / 1 b / 1 c / 1 d and an address decoder 1 e, and each semiconductor memory device 1-1 d is assumed to have two data elements for storing two data. Memory cell array of group M 0 / M 1 1 fng / 1 h / 1 j. The microprocessor 2 supplies the address signal A 0 and the address signal A 1 / A 2 to the semiconductor memory device, respectively.

Page 5 1 425575 ^ _____ ________ _ — V. Description of the invention (2) The address input port lk / lm / ln / lo of la / lb / lc / ld and the address decoder le ° address signal A 0 indicates The address assigned to the memory unit used to store one of the two types of M 0 / M 1. On the other hand, the address signal A 1 / A 2 represents one of the semiconductor memory devices la-ld. The address decoder le includes inverters IV1 / IV2 and NAND gates ND1 / ND2 / ND3 / ND4. The inverters IV1 / IV2 generate inverted phase address signals AB 1 / AB 2 from the address signals A1 / A2, respectively, and the address signals A 1 / A 2 and the inverted phase address signals AB 1 / AB 2 form four combinations. . The four combinations of the address signals A 1 / A 2 and the inverted phase address signals AB 1 / AB 2 are supplied to the NAND gates ND 1-ND 4 respectively, and the NAND gates ND1-ND4 generate decoded signals DE1 / from the four combinations. DE2 / DE3 / DE4. Only one of the four combinations has two inputs that are both logic &quot; 1 &quot; and the associated NAND idler causes the decoded signal to change to an active low level. NAND gates ND 1-ND 4 are connected to semiconductor memory respectively Chip select / output enable port 0E1 / 0E2 / 0E3 / 0E4 of device 1 a-1 d. The low-level effective level decoded signal causes the associated one of semiconductor memory devices 1 a-1 d to respond to address 彳 s No. A 0, and any type Μ 0 / Μ 1 is read from the data output port of the semiconductor memory device 〇1] 11/011 丁 2/01] 丁 3/01 ^ 4 into the microprocessor 2 ^. Although half The lead aa 5 device has other control signal pins such as write enable pins, but the semiconductor memory device i a_ 丨 d shown in Figure 1 is omitted. Figure 2 illustrates the address signal A0 / A1 / A2 Relation to the bit of the data being accessed. The address signals A 2 = 0 and A 1 = 0 cause the address decoder 1 e to activate the semi-conductor memory device 1 a, and the semiconductor memory device 1 a according to the address signal aq. Logic level makes type MO / Ml accessible. When address signals A2 / A1 are low

V. Description of the invention (3) On-time and high-time, the semiconductor memory device 1 b will respond to the address signal A 0, and the data tuple M 0 / M 1 is selective according to the logic level of the address signal A 0 Ground is read from the semiconductor memory device 1b. If the address signal A 2 / A 1 is changed to the high level and the low level, respectively, the address decoder 1 e will start the semiconductor memory device 1 c, and the data byte M 0 / M 1 is based on the address signal A0. Logical level and selective access. Finally, when the address signals A2 / A1 are both high level, the address decoder 1e will select the semiconductor memory device 1d, and the data byte M0 / M1 will be based on the logical bit of the address signal A0 Read from the semiconductor memory device 1 d accurately and selectively. The prior art semiconductor read-only memory device disclosed in this Patent Publication No. 6 2-5 2 7 9 4 is equivalent to any semiconductor memory having a built-in address decoder equivalent to the address decoder 1 e Device 1 a / 1 b / 1 c / 1 d. The memory storage capacity of semiconductor memory devices has increased dramatically in the past ten years, and accordingly, the address space has become wider. Semiconductor memory devices are used in various electric / electronic systems, and the data storage capacity required between these electric] »/ electronic systems is different. Manufacturers have increased the data storage capacity of prior art semiconductor memory devices by a factor of two. For example, manufacturers have increased the data storage capacity of semiconductor memory devices by more than 32 kilobytes and 64 kilobytes to 128 kilobytes. Data stores denoted as powers of n are often suitable for general purpose data storage. The set of program-controlled scripts is stored in the semiconductor read-only memory device of the prior art, and the set of program-controlled scripts can occupy 4 to 8 thousand bytes of memory space, while the set of another program-controlled script can occupy 9 to 6 thousand Group memory space. This collection of program control scripts is sometimes used in computer games. Not represented η times

42557 5 V. Description of the invention (4) The data storage capacity of Party F is hereinafter referred to as "data storage capacity below 2 to the nth power". When the address signal is supplied to n address pins of the semiconductor memory device, the semiconductor memory device provides an address space expressed as 2η. If another semiconductor memory device has a data storage capacity between 2n and 2nM under the same environment, the semiconductor memory device will provide an address space called "data storage capacity below the power of n". Computer designers can use semiconductor read-only memory devices with different memory spaces to organize memory spaces below the nth power. In addition, computer designers may use semiconductor read-only memory devices that have more memory space than needed. For example, if a computer designer needs 9 6 thousand tuples of memory space in his program-controlled instruction code, he must use a semiconductor read-only memory device with a 6 4 thousand tuples memory space and a 3 2 Semiconductor read-only memory device with thousands of tuples of memory space. In addition, he had to use a semiconductor read-only memory device with a memory space of 128 bytes. In any case, the memory system of these two program-controlled scripts is not economical. Similarly, when a part of the memory cell array is defective, the prior art semiconductor memory device cannot be used as a data storage because the designer organizes the address space based on the data storage capacity represented by the power of n expressed as 2. The prior art semiconductor read-only memory device disclosed in this patent publication provides a memory space denoted by a power of n. Even if the program component converts the combination of the address decoded signal into another combination of the address decoded signal, the address decoded signal still only manages the memory space represented by the power of n to the power of 2 and said that this patent publication does not adopt the power of 2 Data storage capacity below the power. When a computer designer manages a data store with a power of 2n or less

7 4 2 5 5 7 5 'V. Description of the invention (5) The memory space of the semiconductor delta memory device of the capacity and the memory space of another semiconductor memory device having a data storage capacity of the power of n expressed as 2. As described below, the system will have a portion of the address space that is not designated by any address and / or a portion of the address space that is designated by multiple addresses. Figure 3 illustrates a prior art memory system 10. The prior art memory system 10 includes a semiconductor memory device 10a / 10b and an address decoder iQc '/ single address bit A 0 supplied to the address pins a 0 of the semiconductor memory device 1 q &amp; and The semiconductor memory device 10a provides a memory space for two data tuples M1. Therefore, the data storage capacity of the semiconductor memory device 10 a is represented as 21-tuples', and the semiconductor memory device i 0a has a type of data that is represented by a power of π. On the other hand, the three address bits A 0 / A 1 / A 2 are supplied to the address pins a0 / al / a2 'of the semiconductor memory device 10b and the semiconductor memory device provides about six data bytes M0 / M1 / M2 / M3 / M4 / M5 memory space. The data storage capacity of the semiconductor memory device i0b is expressed as (22 + 2), which is less than 23. Therefore, the semiconductor memory device 10b is a type having a data storage capacity expressed as a power of n or less. The semiconductor memory devices 10a / 10b respectively have data output ports OUT1 / 0UT2 * and are connected to a common data bus BSi. The address resolver 10 C has 0 r gate 0 d and inverter 10 e. The address bit AJ / A2 is supplied to the turn-on node of the gate IOd, and the output node of the gate 〇0d enables the output enable / chip selection signal to be supplied to the semiconductor memory device 10a Output enable / chip selection pin OE1 and anti-point. Inverter !, the output enable / wafer select signal is generated, and the inverse # is supplied to the semiconductor memory device. The output enable / crystal

Page 9 ^ 425575 V. Description of the invention (6) Pin selection pin 0E2. When the address bits A 1 / A 2 are both at the logic level “0”, the gate 1 0 d keeps the output enable / chip selection signal at a low valid level, and the semiconductor memory device 10a will In response to address bit A0. On the other hand, when at least one of address bits A1 / A2 is at a high level, the gate} 0d will change the output enable / chip selection signal to a high state invalid level and reverse The phaser 10 e will cause another semiconductor memory device 10 b to respond to the address bits A 0 / A 1 / A 2. Although the memory cell in the prior art memory system 10 is equal to 8 data bytes, But memory system 10 only provides address space for 6 data bytes. As shown in Figure 4, address bits A2, A1, A0 are sequentially increased. When address bits A2, A1 When A0 is [〇, 0, 0] and [〇, 〇, 1], the data bytes M 0 and M 1 in the semiconductor memory device 10 a become accessible. When the external device makes the address bit When elements A 2 / A 1 / A 0 increase from [0,1,0] to [1, 〇, 1], the data tuples M2, M3, M4, and M5 will become accessible sequentially. Address bits Yuan [0, 〇, 0] The combination of [0, 0, 1] has been assigned to the semiconductor memory device 10a. Therefore, the address bits A2, A1, and A0 cannot select the data byte group M0 from the semiconductor memory device 10b Figure 5 illustrates another prior art memory system 20. The prior art caution system 20 includes two semiconductor memory devices 20a / 2b and an address decoder c '. Although one address bit The elements A 0 / A 1 are supplied to the address pins a0 / al of the semiconductor memory device 20 a ′ but the semiconductor memory device 20 a provides ′ a memory space for three data tuples M 0 / M 1 / M 2. Therefore, the data storage capacity of 'semiconductor device 2 0a' is expressed as (22-1) number of tuples, and the semiconductor memory device 2 0a has a data storage capacity of 2 to the power of η or less.

4 2 5 5 7 5 V. Description of the invention (7) Type of quantity. On the other hand, the two address bits A 0 / A 1 are supplied to the address pins a 0 / ai of the semiconductor memory device 20b, and the semiconductor memory device 2 01 provides information about four data bytes M 4 / Memory space of Μ 5 / Μ 6 / Μ 7 The data storage capacity of the semiconductor memory device 20b is expressed as. Therefore, the semiconductor memory device 20b is of a type having a data storage capacity of the n-th power. The semiconductor memory devices 20 a / 2 0 b each have a data output port 0 U T 1/0 U T 2 ′ and are connected to a common data bus B s!. The address decoder 2 0 c has an inverter 2 0 d. The address bit A 2 is supplied to the output enable / chip selection pin OE 1 of the semiconductor memory device 20 a as an output enable / chip selection signal. The inverter 2 0 d generates an inverted signal of the output enable / chip selection signal, and supplies the inverted signal to the output enable / chip selection pin 0E 2. Therefore, the address decoder 20c causes one of the semiconductor memory devices 20a / 20b to respond to the address bits A0 / A1. As shown in FIG. 6, the address bits A2, A1, and A0 are sequentially changed. When the address bit A 2 is at the logic “0” level, the address decoder 2 0 c will cause the semiconductor memory device 2 0 a to respond to the address bit A 0 / A 1. On the other hand, a logic 1 &quot; address bit A 2 allows another semiconductor memory device 2 0 b to respond to the address bits A 0 / A 1. When the address bits A 0 / A 1 increase from [〇, 〇] to [1,1], the data byte groups M4 / M5 / M6 / M7 will become accessible sequentially. However, the semiconductor memory device 20a does not have any memory cell with respect to the data element address µ3, and no data byte group is read out from the semiconductor memory device 20a. If the data tuples M 0-M 3 represent program-controlled instructions, the incorrect program-controlled instruction code will be changed from the memory unit of the semiconductor memory device 2 0 a specified by the address [A 1, A 0] = [1, 1] Read out.

Page U ’, 4 2557 5 I_ V. Description of the invention (8) Computer programs: Human computers develop computer programs in computer languages’ and editors convert computer programs into a set of program-controlled instruction codes. Based on the assumption that addresses are continuous in the memory system, the program-controlled instruction code is written into the semiconductor read-only memory device of the memory system. If the memory unit designated by one of the addresses as shown in FIG. 5 does not exist, the program control script will be lost and the computer program will become incomplete. [Overview of development] 'For this reason, an important object of the present invention is to provide an address space manager, which specifies a portion of the address space to a data storage device with a storage capacity of 2 to the power of η without waste. . Another important object of the present invention is to provide a semiconductor memory device having a built-in address space manager. Another important object of the present invention is to provide a memory system which continuously assigns a series of addresses to more than one data storage, and at least one of the data storages has a storage capacity of 2 to the power of n or less. According to one aspect of the present invention, an address space manager is provided, which is used to specify an address subspace of an address space defined by (η 1 + η 2) address bits to store the in The data storage of the data of 1 segment Gongxun 'here nl, η2 and ml are the first natural number, the second natural number and the third natural number, and the ml is equal to or greater than 2 (nl ~ l) and less than 2nl , Which includes an address converter to convert the η 1 address bit, and supplies the converted address bit to a data storage so that the address subspace is positioned in one of the 2η1_χ positions in the address • space First, where X is the equation 2nl-ml = 2X, and the address

Page 425425 &quot; V. Description of the invention (9) A decoder for generating a decoded signal from an address signal containing at least the n 2 address bits, and supplying the decoded signal to a data storage device for storage from the address Select the sub-section data information from the m 1 section data information in the sub-space. According to another aspect of the present invention, a semiconductor memory device is provided, which is provided with (η 1 + η 2) address bits defining an address space, where η 1 and η 2 are first natural numbers. And the second natural number, which includes more than one memory bank, one of which stores m 1 segment data information in the address space of the address space, where the Ώ 1 is a third natural number and is equal to or Greater than 2 (n &quot; and less than 2nI, the address converter converts the n 1 address bit and supplies the converted address bit to one of the more than one memory bank to locate the address in the subspace In one of the positions in the address space, here X satisfies a formula 2 &quot; 1-1111 = 2 &quot; and an address decoder for generating a selection signal from an address signal containing the 112 address bits And decode the signal, selectively activate more than one memory bank with the selection signal, and supply the decoded signal to the data storage to select the sub-segment data information from the m 1-segment data information stored in the address sub-space. Another aspect of the present invention provides a The memory system includes a plurality of memory units, which are respectively designated by the address subspace of the address space to store data information, and are used to read at least the data information in response to the address signal. The plurality of memory units One is to store the data information of the m 1 section, where m 1 is the power of (η-1) greater than 2 and the power of η less than 2 and η is a natural number, and the address space manager responds to bits. The higher address bits of the address signal are used to selectively enable multiple memory units, and selectively convert the higher address bits to modify the addresses forming part of the address signal

Page 13 V. Description of the invention (10) bits instead of higher address bits, and the address subspace is made continuous by not having unaddressable memory cells in the plurality of memory units. [Brief description of the icons] The features and advantages of the memory system, semiconductor memory device, and address converter can be more clearly understood from the description with the icons below. The icons are as follows: Block diagram of Figure 1 Figure 2 shows the configuration of the prior art memory system; Figure 2 shows the relationship between the address signal and the accessed byte; Figure 3 is a circuit diagram showing the configuration of the first prior art memory system; Figure 4 shows the address The relationship between bits and bytes of accessed data; Figure 5 is a circuit diagram showing the configuration of the second prior art memory system; Figure 6 is the relationship between address bits and bytes of accessed data; FIG. 7 is a circuit diagram showing a configuration of a memory system according to the present invention; FIG. 8 ′ is a diagram showing an address conversion implemented by an address converter incorporated in the memory system; FIG. 9 is a circuit diagram showing another embodiment according to the present invention Configuration of the memory system; FIG. 10 shows the address assigned to the semiconductor memory device incorporated in the memory system; FIG. 11 is a circuit diagram showing the circuit configuration of the semiconductor memory device according to the present invention;

Page 14 V. Description of the invention (11) Figures 1 2 to 1 2 D show the selection of transistors, external address bits and internal address bits that are turned on; the circuit diagram of Figure 3 shows another circuit according to the present invention. The circuit configuration of a semiconductor memory device; Figures 14A and 14B show the relationship between the control signals, the external address bits and the internal address bits, and Figures 15A and 15D show the control signals and The relationship between the sub-address space of the semiconductor memory device is not specified. The circuit diagram of FIG. 16 is a circuit diagram of another semiconductor memory device according to the present invention. [Explanation of symbols] 1 ~ memory system 2 ~ microprocessor 1 0 ~ memory system 2 0 ~ memory system 3 0 ~ microprocessor 31 ~ memory system 3 1 a / 3 1 b ~ semiconductor memory device 3 1 c ~ bit Address decoder 3 1 d ~ address converter 3 1 e / 3 1 g ~ memory cell array 3 1 f / 3 1 h ~ data buffer 31j ~ OR gate 3 1 k ~ inverter

Page 15-425575 ^ V. Description of the invention (12) 31m-Mutual exclusion-N 0 R gate 3 1 η ~ inverter 3 2 ~ address bus 3 3 ~ data bus 4 1 ~ memory system 4 1 a / 4 1 b ~ semiconductor memory device 4 1 c ~ address decoder 4 1 d ~ address converter 4 1 e / 4 1 g ~ memory cell array 4 1 f / 4 1 h ~ data buffer 41j / 41k / 41m ~ NOR gate 4 1 η ~ Inverter 4 1 ρ-Inverter 41q ~ Mutual exclusion—NOR Question 4 2 ~ Address bus 4 3 ~ Data bus 5 0 ~ Semiconductor chip 5 1/5 2 ~ Memory bank 5 3 ~ address decoder 5 4 ~ programmable address converter 54a / 54b ~ NOR gate 54c / 54d ~ inverter 54e ~ mutually exclusive-NOR gate 54i / 54g / 54h ~ inverter

Page 16 425575 V. Description of the invention (13) 54j / 54k / 54m / 54n / 54p / 54q ~ Use transistor 54r / 54s / 54t / 54u ~ Inverter 5 5 ~ Data buffer 5 6 ~ Data port 6 0 ~ Semiconductor wafer 6 1/6 2 ~ Memory bank 6 3 ~ Address decoder 6 4 ~ Address converter 64a / 64b / 64c / 64d ~ Inverter 64e / 64f / 64g / 64h / 64j / 64k people 64m / 64n / 64p / 64q ~ NAND gate 6 5 ~ data buffer 7 0 ~ semiconductor chip 7 1/7 2 ~ memory bank 7 3 ~ address decoder-7 4 ~ address converter 7 5 ~ data buffer [Compared Detailed description of the preferred embodiment] Referring to FIG. 7, the first embodiment of the memory system, the memory system 31 and the microprocessor 30 implementing the present invention form a part of a data processing system, and the microprocessor 30 is through an address The bus 32 2 and the data bus 33 are connected to the memory system 3 1. The address bus 32 sends a 23-bit address signal A00-A22 to the memory system 31, and the data sink

-〇〇 / 5 &quot; V. Description of the invention (14) The stream line 3 3 transmits a 16-bit data code from the memory system 3 1 to the microprocessor 30. In the following description, the term "math" means a 16-bit data code. The memory system 3 1 includes a semiconductor memory device 3 1 a / 3 1 b, an address decoder 3 1 c, and an address converter 3 1 d. The address bits A 2 1 / A 2 2 are supplied to the address decoder 3 1 c, and the address decoder 3 1 c is selectively selected by an external chip select / output enable signal with a low active level Ground-enabling semiconductor memory devices 31a / 31b. The address converter 3ld converts the address bits A21 / A22 to the address bits A2Γ / Α22 'and supplies the address bits A2Γ / Α22 to the semiconductor memory device 3 1b. Therefore, 'the address space of the memory system 3 丨 is divided into two address subspaces', and the semiconductor memory device 3 丨 a / 3 丨 b respectively provide the address subspace defined by the lower address and Address subspace defined by higher addresses. When the address decoder 3 1 c enables the semiconductor memory device 3 丨 a by an external chip selection / output enable signal with a low active level, the semiconductor memory device 31 a responds to the address bits aqo — A2. And send a data code to the data bus 3 3. On the other hand, 'when the address decoder 3 丨 ^ is enabled by an external crystal moon selection / output enable signal with a low state effective level, the other semiconductor memory device 3 1b will respond. At the address bits A 0 0-A 2 0 / A 2 1 / A 2 2, and send a data code to the data bus 33. The semiconductor memory device 3 1 a includes a memory cell array 3.1 e and a data buffer 31 f, and the address port API, the control signal port 0E] and the data port are all incorporated into the semiconductor memory device 3 1 a. The cell array 3e includes 2 million = 1 6-bit addressable memory cells, and provides a memory subspace of 2 million bytes of data or 32 million bits. Semiconductor memory device 3 丨 a

Page 18 _ 4 -25 5.7LS- V. Description of the Invention (15) The memory subspace is expressed as "2th power of η". The data buffer 3 1 f is connected between the memory cell array 3 1 e and the data port 0 U T 1, and the data port ◦ U T 1 is connected to the data bus 33. The address bits A 0 0-A 2 0 are supplied to the address port AP 1, and the external chip select / output enable signal is supplied to the control signal port 0E 1. When the external chip select / output enable signal at the control signal port 0 E 1 is changed to the low effective level, the 16-bit data code will be read from the memory unit designated by the address, which is equivalent to At the address represented by address bits A 0 0-A 2 0, and transfer to the data buffer 3 1 f. Therefore, a 16-bit data code is transmitted from the data buffer 3 1 to the data bus 3 3. The other semiconductor memory device 31b includes a memory cell array 31g and a data gamma buffer 31h, and the address port AP2, the control signal port 0E2, and the data port OUT2 are all incorporated into the semiconductor memory device 31b. The memory cell array 3 lg contains 6 million X 1 6-bit addressable memory cells and provides about 6 million bytes of data or 9 6 million bits of memory subspace. The memory subspace of the semiconductor memory device 3 1 b is greater than the (η− 1) th power and less than the nth power. For this reason, the memory cell array 31 g provides a memory subspace of 2 to the power of n. The data buffer 31 h is connected between the memory cell array 3 i g and the data port OUT2, and the data port OUT2 is connected to the data bus 33. Address Bits 00-80 20 / Eight 21 '/ Eight 22' are supplied to the address port eight? 2, and the external chip select / output enable signal is supplied to the control signal port 0E2. When the external chip select / output enable signal at the control signal port 0E2 is changed to the low effective level, the 16-bit data code will be read from the memory unit designated by the address, which is equivalent to Address Bits A 0 0-A 2 0

Page 19 v 425575 &quot; —_____, '&quot; 1 I-.-_ _ V. Description of the Invention (16) &quot;-ί 不 之 Address' and transfer to the data buffer 3 1 h. Therefore, the 16-bit code is sent from the data buffer 31 h to the data bus 33. a The address decoder 3 1 c includes an OR gate 3 1 j and an inverter 3 1 k, and the external chip select / output enable signal is selectively supplied to the control signal port from the OR gate 31 j and the inverter 31k. 0 E 1 and another control signal port 0E 2. The address bits A 21 / A 2 2 are supplied to the input node of the OR gate 3 I j, and the output node of the OR gate 3 1 j is connected to the control signal port OE 1 and the inverter 3 1 k. Enter the node. The output node of the inverter 31k is connected to the control signal port 0 £ 2. When the address bits A 2 1 / A 2 2 are both low, the OR gate 3 1 j will supply an external chip select / output enable signal with a low effective level to the control signal port 0E1 'and enable the semiconductor The memory device 3ia responds to the address bits AOO-A20. However, another semiconductor memory device 3U did not respond to the address signal. Therefore, the 'semiconductor memory device 3a' provides a memory subspace represented by the external address signals [0, 0 '*, *, ...., *]. The asterisk [*] stands for "quote" or "丨 丨". On the other hand, if at least one of the address bits A 2 1 / A 2 2 is at a high level, then 0 R gate 3 1 j will supply high The external chip select / output enable signal of the inactive level is controlled to the control signal port 0E 1 'and the inverter 3 1 k will supply the external chip select / output enable signal of the high state active level to the control signal port 0 E 2. The semiconductor memory device 3 1 a does not respond to the address bits A 〇〇- A 2 0, and the other semiconductor memory device 31b transmits a 16-bit data code from the memory unit to the data bus 33, the memory The unit is specified by the address bits A00-Α20 / Α2Γ / Α22 '. Therefore, the semiconductor memory device 3lb provides the address signals [1, 1, *, *, ...,..., *], [〇, 1, *, *, ..._ ·, *] or

Page 20 425575 V. Description of the invention (17) The memory subspace represented by [1, 0, *, *, ....., *]. The address converter 3 1 d includes a mutex-NOR gate 3 1 m and an inverter 3 1 n. The address bit A 2 1 / A 2 2 is supplied to the input node of the mutex-NOR gate 3 1 m, and the address bit A 2 1 is supplied to the input node of the inverter 3 1 η. The mutually exclusive-N 0 R gate 3 1 m and the inverter 3 1 η supply address bits A 2 2 ′ and A 2 1 ′ to the semiconductor memory, and the address port AP2 of the device 31 b. Although the mutually exclusive -N 0 R gate 3 1 m is logical from all the π 0 &quot; level address bits A22, A21 generates logic "〇 &quot; level, the combination of address bits A22, A21 makes the external chip The selection / output enable signal disables the semiconductor memory device 3 1 b, and does not consider the combination of address bits [Α22, A21] = [〇, 〇]. Therefore, the mutually exclusive-NOR gate 31m is derived from the address bit A21 / Α22 generates three combinations of address bits A2Γ / Α22 ', and the address converter 3 1 d changes the address bits A22' / Α2Γ as shown in Fig. 8. Between the address bits A22 / A21 and the bit The logical relationship between the address bits A2Γ / Α22 'is expressed as A22, = Α22 · A21 + A 22 A 21, A2Γ and A 21 where A means the inverse of A, which is usually expressed by drawing a line above A. Bit The combination of address bits A22 '/ A21' represents an address equal to [A22, A21]-1. All are logical "〇 &quot; The address bits A22 / A21 represent the semiconductor memory device 31a, and the bit The combination of address bits A22 / A21 is not used as an address on the memory cell array 3 1 g. If the address converter 3 1 d is not integrated into the memory system 3 1, similar to the prior art shown in FIG. 3, the computer designer cannot use the semiconductor memory device 31 b with [A22, A21, A20, ..., A00 ] = [〇, 〇, * ... ·. *] Indicates the memory unit specified by the address. The inventor noticed that because the memory subspace is 96 million-bits,

Page 21

/ M 5. Description of the invention (18) The semiconductor memory device 3 1 b does not have any memory unit represented as [A22, A21, A20…. A00] = [1, 1, *… · *]. In order to understand how to save the memory unit specified by [A22, A21, A20,… .., a〇〇] = [〇, 〇, *… ·, *], the present inventor provides an address converter 31d , And the address converter 31d will be sequentially expressed as [A22, A21] = [1,1], [Α22, A21] = [1,0], and [A22, A21] = [0,1] The addresses are converted into addresses expressed as [A22, A21] = [1, 0], [A22, A21] = [0, 1], and [A 2 2, A 2 1] = [0, 0]. Therefore, an unspecified address, that is, [A 2 2, A 2 1] = [1,1] will be converted into an address that has been assigned to the memory unit, that is, [A22, A21] = [1, 0] , And the address [A22, A21] = [0,1] will be assigned to the memory unit not specified by the address [A 2 2, A 2 1] = [0,0]. It will be understood from the foregoing invention that the address converter 3 1 d according to the present invention sequentially shifts the address indicated by the external address, and makes all the memory cells of the semiconductor memory device 3 1 b. Addresses can be easily added using the D microprocessor 30. The semiconductor memory device 31b has a defective memory cell, and accordingly, only 96 million-bit memory cells remain in the memory cell array 31g. However, the address converter 3 1 d rescues these partially defective semiconductor memory devices 3 1 b, and the production cost of the data processing system is reduced. In this example, the address decoder 3 1 c and the address converter 3 1 d integrally constitute an address space manager. The function of the address converter 3 d is, in a broad sense, the value represented by the address bits A 2 1 / A 2 2 minus the value represented by the highest address in the memory cell array 3 丨 e. »

Page 22 425575 V. Description of the Invention (19) Second Embodiment Referring to FIG. 9, another memory system 4 implementing the present invention includes a semiconductor memory device 41a / 41b, an address decoder 41c, and an address converter 41d. The memory system 41 and the microprocessor (not shown) form part of the data processing system, and the microprocessor is connected to the memory system 41 through the address bus 4 2 and the data bus 4 3. The address bus 42 transmits a 24-bit address signal A 0 0-A 2 3 to the memory system 41, and the data bus 43 transmits the bit data code from the memory system 4 to the microprocessor. In the following description, the term "matrix" also means a 16-bit data code. The memory system 41 includes a semiconductor memory device 4a / 4b, an address decoder 41c, and an address converter 41d. The address bits A 2 丨 / A 2 2 / A 2 3 are supplied to the address decoder 4 1 c 'and the address decoder 4 丨 c is enabled by an external chip selection / output enable at a low active level Signals to selectively energize the semiconductor memory device 4 1 a / 4 1 b. The address converter 4 1 d converts the address bits A21 / A22 to the address bits A2Γ / Α22 ,. The address bits A00-A22 are supplied to the semiconductor memory device 41a 'and the address bits α〇〇-Α22 / Α2Γ / Α22 are supplied from the address bus 4 2 and the address converter 4 1 d to the semiconductor memory Device 4 丨 b. Therefore, the address space of the 'memory system 41' is divided into two address subspaces. When the address decoder 4 1 c enables the semiconductor memory device 4 a through the external chip selection / output enable signal of the low-active level, the semiconductor memory device 41 a will respond to the address bit A〇〇_ A22, and transmit 6_bit data to data bus 43. On the other hand, when the address decoder 4 is enabled by another external chip select / output enable signal with low active level

Page 23; 4 2 5 5 7 5 &quot; _ ^ _ Five 'invention description (20) When the semiconductor memory device 4 1 b, the semiconductor memory device 4 1 b will respond to the address bits A 0 0-A 2 0 / A 2 1 '/ A 2 2', and send a 16-bit data code to the data bus 4 3. The semiconductor memory device 41a includes a memory cell array 41e and a data buffer 41f, and the address port AP3, the control signal port OE3, and the data port OUT3 are all incorporated into the semiconductor memory device 41a. The memory cell array 4 1 e contains 6 million X 1 6-bit addressable memory cells and provides about 6 million bytes of data or 9 6 million bits of memory subspace. The memory cell array 4 1 e falls within a range between the (η-1) power of 2 and the η power of 2 and the memory subspace of the semiconductor memory device 4 1 a is a type of η or less expressed as 2 Data storage. The data buffer 41 is connected between the memory cell array 41 and the data port OUT3, and the data port OUT3 is connected to the data bus 43. Address bits A00-A22 are supplied to address port AP3, and an external chip select / output enable signal is supplied to control signal port OE3. When the external chip select / output enable signal at the control signal port OE3 is changed to the low effective level, the 16-bit data code will be read from the memory unit designated by the address, which is equivalent to The addresses represented by bits A00-A2 2 are transferred to the data buffer 4 1 f. The internal chip select / output enable signal IOE3 is generated from the external chip select / output enable signal, and the data buffer 41f has been enabled. Therefore, the 16-bit data code is transmitted from the data buffer 41 to the data bus 43. The other semiconductor memory device 41b includes a memory cell array 41g and a data buffer 41h, and the address port AP4, the control signal port 0E4, and the data port OUT4 are all merged into the semiconductor memory device 41b. Memory cell array 41g contains

Page 24 V. Description of the invention (21) 6 million X 1 6-bit addressable memory units, and provide about 6 million bytes of data or 9 6 million bits of memory subspace. The memory subspace of the semiconductor memory device 4 1 b is greater than 2 (η-1) power and less than 2 η power. For this reason, the memory cell array 41g is a kind of data storage device which is less than or equal to the power of n. The data buffer 41 h is connected between the memory cell array 41 g and the data port OUT4, and the data port OUT4 is connected to the data bus 43. The address bits A00-Α20 / Α2Γ / Α22 ′ are supplied to the address 皡 AP4, and the external chip select / output enable signal is supplied to the control signal port 0E4. When the external chip selection / output enable signal at the control signal port 0E4 is changed. When it becomes the low effective level, the 16-bit data code will be read from the memory unit designated by the address, which is equivalent to At the address represented by address bits A00-Α20 / Α21 '/ Α22', and transferred to the data buffer ii41h. The internal chip select / output enable signal I 0 E 4 ′ is generated from the external chip select / output enable signal and the data buffer 41 h has been enabled. Therefore, the 16-bit data code is transmitted from the data buffer 41 h to the data bus 43 ° The address decoder 4 1 c contains the N 0 R gate 4 1 j / 4 1 k / 4 1 m and the inverse And the external chip select / output enable signal is selectively supplied from the NOR gate 4 1 m and the inverter 41 η to the control signal port OE3 and another control signal port 0E4 Ί address bit A21 / A22 / A23 is selectively supplied to the input node of gate 41j / 41k 'and the output node of N 0 R gate 4 1 j / 4 1 k is connected to the input of another gate 4 1 m. point. The output node of N 0 R gate 4 1 m is connected to the input node of control signal port 0E3 and inverter 4 I η. The output node of the inverter 4 1 n is connected to the control signal port 0E4.

425575 ^ __ V. Description of the invention ¢ 22) When the address bits A 2 1 / A 2 3 are both low level, N 〇 gate 4 丨] will change its output node to a high level, and at the input node Keep the output node low when one or both levels are high. Similarly, when both address bits A22 / A23 are at low level, NOR gate 41k will change its stomach output node to high level 'and other kinks of address bit A22 / A23 will make NOR ask 41k Generate low level. When the NOR gate 41 j / 41k changes its output node to / level ', the NOR gate 4 1 m will change its output node to a high level, and the inverter 4 1 m will supply the external chip selection / output of the low state effective level Enabling number ^ control signal port 0E4. Other combinations of the standard at the output node of the NOR gate 4 1j / 41k will cause the N 0 R gate 4 1 m to change its output node to a low level, and the external chip select / output enable signal of the low-state effective level from N 〇R idle '4 1 m is supplied to the signal control port 0E 3. Therefore, the address decoder 4 丨 c selectively starts the semiconductor memory according to the address bits A23 / A22 / A21, and the device 4 1 a / 4 1 b. The relationship between the address bits A23 / A22 / A21 and the activated semiconductor memory device 4 1 a / 4 1 b is shown in circle 10. If the address bits A 2 3 / A 2 2 / A 2 1 fall within the range between [0,0,0] and [0,1,0], the address decoder 4 1c will start the semiconductor Memory device 4 1 a. On the other hand, if the address bits A23 / A22 / A21 fall within the range between [0, 1,1] and [1, 0, 1], the address decoder 4 1 c will supply the low state valid A level external chip select / output enable signal to the semiconductor memory device 4 1 b. The address converter 41d includes a mutex-NOR gate 41q and an inverter 41p. The address bit A21 / A22 is supplied to the input node of the mutex-NOR gate 41q 'and the address bit A21 is supplied to the input node of the inverter 41p. Mutual exclusion-NOR gate

Page 26 425575 V. Description of the invention (23) 4 lq and inverter 4 lp supply address bits A 22 ′ and A 2Γ to the address port AP4 of the semiconductor memory device 41b. The function of the address converter 41 d is expressed as A22 '= A22 · A 21 + A 22 · A21, A21' = A 21. Therefore, the address converter 4 1 d is the address bit [A 2 2, A 2 1] = [1,1], [〇, 〇] and [Ο, 1] are converted into address bits [A 2 2 ', A 2 1'] = [〇, 〇], [0,1 ] And [1, Ο]. In other words, the address converter 4 1 d adds 1 to the address bits [A 2 2, A 2 1]. The 24-bit address signal a 〇 〇-A 2 3 can manage an address space of about 16 million bytes' and the semiconductor memory device 41 a / 4 lb provides 12 million bytes of data storage. In this case, except for address bits [A23, A22, A21, A20-A00] = [1,1,1, *, *, ... *, *] and [ΐ, ι, 〇 ,. t *, …, *, *] Are all addressable. Therefore, the address bit A 2 3 is only used for selective activation of the semiconductor memory devices 4 1 a and 4 1 b 'and the address bits A 2! 3, A 2 2, A are shown in FIG. 10 2 The remaining six combinations are selectively assigned to the memory unit array 4 丨 e / 4 丨 g. The microprocessor (not shown) does not transmit data with [A23, A22, A21] = [I, 〆. With the address signal of [1, 1, 0] to the address bus 4 2. However, the pseudo-designer needs to use these addresses, and the address decoder 4 1 c will be designed to force the data output port OUT4 into a high impedance state when these addresses appear. When the memory system 41 further includes 16 million-bit semiconductor devices, the system designer will need to use these addresses. As will be understood from the foregoing description, the address decoder 4 1 c and the address converter 4 1 d cooperate with each other to selectively assign the address subspace to the semiconductor memory devices 41a / 41b 'the two semiconductor memory devices are classified Below 2 to the power of η

Page 27 -42557 5 ,, ___ V. The data storage capacity of invention description (24). The microprocessor makes the address signals A 0 0-A 2 3 sequentially increase from [0, 0, 0, * wood ***] to [1, 0, 1, ****] and Does not have non-addressable memory cells. Even if the 16-bit program-controlled instruction code is stored in the semiconductor memory device 4 1 a / 4 1 b, because the address is not discontinuous, the program sequence will not be disturbed by branch instructions such as jumping to the address. Some defective products of semiconductor memory devices such as 16 million-tuple semiconductor memory devices can be used in memory systems, and the production cost of memory systems will be reduced. In this example, the address decoder 4 1 c and the address converter 4 1 d integrally constitute an address space manager. Semiconductor Memory Device First Embodiment Referring to FIG. 11, a semiconductor read-only memory device embodying the present invention is fabricated on a semiconductor wafer 50. The semiconductor read-only memory device includes a memory bank 5 1/5 2 and the memory bank 5 1/5 2 provides a data storage about the address space. The memory bank 5 1 has an addressable memory unit for storing 3 C tuples. And, another memory bank 52 has a memory unit for storing a 1 C tuple, a 2 C tuple, a 3 C tuple, and a 4C tuple. C is expressed as an integer of 2 to the power of n. For this reason, the data storage capacity of memory 51 is less than 4 C bytes. Higher-order addresses in the address space are assigned to bank 5 1, and lower-order addresses are assigned to another bank 5 2. The semiconductor read-only memory device further includes an address decoder 5 3, a programmable address converter 54 and a data buffer 55. The external address bits A 00-Αχ or A 0 0 — A χ + 1 are supplied to the address according to the data storage capacity of the memory 5 2

Page 28 425575 V. Description of the invention (25) Decoder 5 3 'and the external address bits a X-1 and a X are supplied to the programmable address converter 5 4 ◊ Address decoder 5 3 series response The external address bits AOO-Ax / AOO-Ax + 1 are used to generate the selection signal SEL1 and the internal address bits. The selection signal SEL1 selectively causes the memory bank 5 1/5 2 to respond to the internal address bit 'and the data byte is read from the memory unit, which is represented by the address equivalent to the internal address bit The address of the apartment is specified. The data byte is transferred to the data buffer 5 5 and then transmitted to the data port 5 6. The programmable address converter 54 is enabled by the chip enable signal CE and converts the external address bits A X / A X-1 into the internal address bits a x and ax-1. Programmable address converter 54 includes NOR gates 54a / 54b, inverters 54c / 54d, mutex-NOR gates 54e, inverters 54f / 54g / 54h, and electric crystals 54j / 54k / 54m / 54n / 54p / 54q and inverter 54r / 54s / 54t / 54u. The NOR gates 54a / 54b are energized by the low-level active-level wafer enable signal CE, and generate out-of-phase address bits cAχ and CAx-1. The inverters 54c / 54d respectively regenerate the address bits Aχ and

Ax -1 ° depends on whether the channel is doped, so that the transistor 54 j-54q is selected as the semiconductor fuse element, and a conductive channel is provided. The transistor 5 4b 5 4 q # is selected as follows. μ If the memory bank 5 2 provides data storage for 1 C tuples, rectification is used. The transistors 54m / 5 4q are selected to provide conduction, and the other selected π crystals 54j / 54k / 54n / 54p are turned off. $ Is used. If the transistor 52 is used to provide information about 2C tuples, the transistors 54k / 54p are all turned on to provide conductive channels.

Page 425575

5. Description of the invention (26) The bodies 54j / 54m / 54n / 54q are all closed. If the memory bank 5 2 provides data storage for 3 C tuples, the transistors 54n / 54q are all turned on to provide a conductive channel, and the other ’s are selected, and the body 54j / 54k / 54m / 54p is turned off. 1. If the transistor is used, the transistor is used. If the memory bank 5 2 provides data storage about the 4 c tuples, the transistors 54j / 54p are all turned on to provide a conductive channel ’, while the others, the curved body 54k / 54m / 54n / 54Q are all closed. When the transistor 54m / 5 4q is used to provide a conductive channel, the function will indicate

Ax = A x · A x ~ 1 + A x · A x -1, ax'l = Ax-1 When a transistor 54k / 54p is used to provide a conductive channel, the function will indicate ax = Ax, ax-1 = Αχ- 1 When the transistor 54n / 54q is used to provide a conductive channel, the function will represent ax II Ax · A X-1 + A x · Αχ-1, ax-1 = Ax-1 When a transistor 54j / 54p is used to provide a conductive channel , The function will indicate ax = Ax, ax-1 = Αχ -1 Programmable address converter 5 4 is based on the selection of the transistor 5 4 j-5 4 q to specify the address subspace to the memory 5 1/5 2. When the transistor 54m / 54ti is selected to be turned on, the address space is divided into the first embodiment similar to the memory system as shown in FIG. 12A, which will not be described further below. When the transistor 54n / 54Q is turned on, as shown in M2C

Page 30; 425575 V. Description of the invention (27) 1 ~~ The address space is divided into a second embodiment similar to the memory system, and the description is omitted. It is assumed that the transistor 5 4 k / 5 4 P is selected to be turned on. When the external address bits Ax + 1, Ax, Ax, l…, A00 increase the address sequentially from [0, 〇, 〇, **… **] to [0 '^, 1, * H] At this time, the address decoder 5 3 will select the memory bank 5 2 ′ and the data tuples will be read from it (see figure 丨 2 b). After the external address bits Αχ + 1, Αχ, Αχ-1 ..., Α0ϋ exceed [0,0,1, ** ... * wood]: the address decoder 5 3 will select another memory bank 5丨, and in the period between the external address bits Aχ + 1, Aχ 'Ax-ι ..., A00 between [0, 1, 0, ** ... **] and [1, 0 ^ ^]' The data tuple is read from it. ，，，， If the transistor 5 4 j / 5 4 p is selected to be turned on, the address decoder 5 3 will select the memory bank 52 based on the &quot; 〇 &quot; outside address bit Ax + 1, and the data $ The group will read from the memory unit specified by [0, 〇, **, ..., **] to [丨, 丨, &quot; ,, **] and f == Ax / Ax'i Out (see Figure 14). η plane ^ When the external address bit ^ + 丨 makes the address from full, U, and ... sequentially increase to [1,1, 〇, **. ·. **] with ^^-1 The address solution M3 is $ Yu &quot; 丨, and the other locations are Αχ + ι and the other is selected—the memory bank and the number of poor data sets will be from [0, 〇, to ...] to [1, 0 , * * ... Mu 氺] internal bit phase correction-'' 6 „β" 内 内 #Address bit TLax, ax] ..... a00 refers to &amp; . The I-type address converter 5 4 and the address decoder 5 3 form an address space as a whole, and the NOR gate 54 &amp; / 5 # 'inverter 54C / 54d' mutually exclusive X ^ and inverter 54 Bu 54h cascade to form a logic circuit. The electric crystals 54 to 54q are selected to provide a plurality of rupturable conductive channels, respectively.

425575 Description of the invention ¢ 28) Because the manufacturer can program the external address bit system after making ^ ^ element ΑχΗ-ΑχΜ, select ^ self-memory unit, so the programmable address location address bits ax-ax ~ i Distinguish defective products. The address system 54 can use the memory bank 5 of the semiconductor memory device's 52/52 to designate the serial number to have no non-addressable memory list. Second embodiment ... Referring to FIG. 13, the solid pulse * is on the semiconductor wafer 60. The other semiconductor memory device of the Ming Dynasty is made of an address decoder 6 3. The address M body δ memory device includes a memory bank 6 1/6 2. It has a key element ^ = 64 and a buffer 5. The memory 61 is in the wrong memory of the 1C tuple, and the other memory 62 has the key ^ ^ ^ fM / fi 9 ', plagiarism. In this example, the read-only memory unit B is an address decoder 63 and the data buffer 65 are similar to the address decoder 53 and the data buffer 55. For the sake of simplicity, no further description is added below. . The second embodiment is characterized by the address converter 64, and accordingly, the address converter 64 is focused on the address converter 64. The address converter 64 changes the address designation in accordance with the control signal "". It is assumed that the external address bits A 0-Αχ define an address space, and three-quarters of the address space are assigned differently to the memory bank 6 j.

The address converter 64 includes inverters 64a / 64b / 64c / 64d and NAND gates 64e / 64f / 64g / 64h / 64j / 64k / 64m / 64n / 64p / 64Q. The inverters 64a / 64b generate the inverted signals of the external address bits Ax / Ax-1, and the inverters 64c / 64d generate the inverted signals of the control signals OPT1 / OPT2. The external address bits Αχ / Ax-1, its inversion signal, control signal OPT 1 / OPT2, and its anti-trust signal are selected. They are supplied to the NAND gates 64e-64h and 64k-64p, and NAND

Page 32 ^ 425575 V. Description of the invention (29) Question 64e-64h output node and 64k_64p output node between NAND are connected to the input node of NAND idle 6 4 j and μ a ND gate 6 4 q input node . The internal address bits ax / ax — 1 are generated at the output nodes of the NAND gate 64 j / 64q, respectively. The address converter 64 performs the following logical functions on the internal address bits ax and -1. ax = A x · ΑχΊ · 〇ΡΤ1 · 0ΡΤ2 + Αχ-1 · 0ΡΤ1 · 0ΡΤ2 + Αχ · Αχ-1 + Αχ · 〇ΡΤ2 ax-Ι-Αχ-1. 〇ΡΤ1 · 〇ΡΤ2 + α χΊ · ό ΤΤ1 · ΟΡΤ2 + Α χ · Αχ-1 · ΟΡΤ1 + Αχ · Αχ-1 · ΟΡΤ1 where 0 PT1 and ό PT2 are the reverse signals of ATP1 and TP2, respectively. The logic function changes the internal address bit a χ as shown in FIG. 14A and changes the other internal address bit a χ-1 as shown in FIG. 14B. As shown in FIG. 15A, if the control signal 0 PT 1 / 〇p τ 2 is [〇, 〇], then from [0,0, ** · _ **] to [1, G, ** ... **] Address bits outside the address will cause the address decoder 63 and the address converter 64 to specify from [0, 0, ** .. **] via [0, 1, ** .. **] to [1, 0, * *.-* *] Address space to the memory 6 1., And the remaining external address bits [1, 1, ** _. **] make the address decoder 6 3 and the address converter 6 4 designate the remaining address subspace to another memory 6 2. As shown in FIG. 15B, if the control signal 0PT1 / 0PT2 is [〇,;! ], Then from [〇, 1 ,, to [1, 1, Mumu * 氺], the address bits will cause the address decoder 63 and the address converter 64 to specify from [0, 0, ** . · **] via [〇, 1, **. **] to — [1, 〇, ** .. **] to the memory space 6 1 and the remaining external address bits [0, 0, ** .. **] make the address decoder 6 3 and the address converter 6 4

Page 33 4 2 5 5 7 5 &quot; ---------- ----------! V. Description of the invention (30) Set the remaining address space to another memory bank 6 2. As shown in FIG. 15C, if the control signal OPT1 / OPT2 is [ii], then two [〇, 〇, * 木. · **] and from [1, 0, ** .. **] to [1, 1, ** ·. **] causes the address decoder 63 and the address converter 64 to specify [〇, 〇, ** ._ **] and [0,1, ** . · **] to [1, 0, ** .. **] to the memory space 61, and the remaining external address bits [0, 1, **., **] enable The address decoder 6 3 and the address converter 6 4 designate the remaining address subspace to another bank 6 2. As shown in Figure 1D, if the control signal ορή / ορτ 2 is [1, 0], then from [0, 0, wood * _ _ **] to [0, 1, * wood, and [1, 1 , ** .. **] outside the address bit will cause the address decoder 63 and address converter 6 4 to specify from [〇, 〇, ** ·. **] to [0,1, * * .. **] and [1, 0, ** ·. **] address space to memory 6 1, one and the remaining external address bits [1, 0, ** .. ** ] Make the address decoder 6 3 and the address converter 6 4 assign the remaining address subspaces to another bank 6 2. Therefore, the manufacturer freely assigns the address space to the memory bank 6 1/62 by using the control signal OPT 1 / 0PT2. Even if the address space on memory 62 separates the address space on memory 62 into two, the addresses are continuous, and memory 6 1/62 does not have any non-addressable memory cells. Third Embodiment Referring to FIG. 16, another semiconductor memory device embodying the present invention is fabricated on a semiconductor wafer 70. The semiconductor memory device includes a memory bank 71/72, an address decoder 7 3, an address converter 74, and a data buffer 75. Memory bank 7 1/7 2. The operations of the address decoder 7 3 and the data buffer 75 are similar to those of the memory bank 6 1/62 2. The address. Decoder 6 3 and the data buffer 65. So below

Page 34-/ ¾ P557 5_ 5. The description of the invention (31) will not explain these components 7 1/7 2/7 3/7 5 to avoid repetition. The address converter 7 4 is similar to the address converter 6 4 according to the control signal 0 PT 1 / 〇 PT 2 and changes from the address bit AX / AX-1 to the internal address bit ax / ax-1. Address translation. 14A / 14B are related to the third embodiment of Figs. 15A-15D. With the mutex-0 R gate, the wiring between the logic gates is simplified compared to the wiring of the address converter 64. The address decoder 7 3 and the address converter 7 4 integrally constitute an address space manager, and the address space manager achieves all the advantages of the address space manager 6 3/6 4. As will be understood from the foregoing description, the address space manager specifies a portion of the continuous address space to a semiconductor memory device having a data storage capacity of 2 to the power of n without all addressable memory cells. Even if the product of the semiconductor memory device is detected as a partial defect, the product can still be used in a semiconductor memory device with a data storage capacity of less than 2 η to increase the product yield. When a program about a microprocessor is sequentially stored in a memory bank or a memory system, the address space manager assigns an address subspace to the memory bank or the memory system without an unaddressable memory unit, and any instruction such as jump More and more will not disturb the execution of the program sequence. The address manager 6 3/6 4 allows the system manager to specify a part of the continuous address sub-space to different types of memory devices, and the system manager can use the bit Address space manager to build a unique memory system. ,

Although specific embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes and modifications can be made without departing from the spirit and scope of the present invention.

Page 35 425575 V. Description of the invention (32) For example, the address converter and the semiconductor memory must be separately and separately integrated on the semiconductor wafer. The semiconductor memory devices 3 1 a / 3 1 b, the address decoder 3 1 c and the address converter 3 1 d are accumulated on the semiconductor wafer. Similarly, the semiconductor memory device 4 1 a / 4 1 b, the address decoder 4 1 c and the address converter 4 1 d are integrated on a semiconductor wafer. A part of the address decoder 53 of the selection signal SEL1 and / or the programmable address converter 54 can be separated from the semiconductor memory device corresponding to the memory bank 5 2/51 and accumulated on the semiconductor chip. Similarly, a part of the address decoder 63 and the address converter 64 can be separated from the semiconductor memory device corresponding to the memory bank 61/62 and accumulated on the semiconductor gamma chip. The memory bank 6 2 must be separated from the memory bank 61 and the address space manager 6 3/6 4 and accumulated on the semiconductor wafer. In this example, the type of the memory cells in the memory bank 62 is different from the memory cells in the memory bank 61. If the memory bank 61 is a read-only memory, the system designer may specify the remaining address times and space to a random access memory or a programmable read-only memory that replaces the read-only memory. In the second and third embodiments of the semiconductor memory device and the first embodiment of the semiconductor memory device, the memory bank 52 provides data storage about 1 C tuples, and the address space manager specifies four of the address space. Three-thirds to the memory bank 5 1/6 1/7 1. Based on this, two external address signal lines are required. However, if the address space manager divides the address space into 8 to specify M (natural number) / 8 to an address library, three external address lines are required. If the address space is divided into 16 then four address lines are needed. So connect to

Page 36 ^ -4255 7 5 V. Description of the invention (33) The address lines outside the address converter are changed according to the ratio of the data storage capacity below 2 to the η position relative to the 2η address space. In the foregoing embodiment, the lowest address is zero, that is, [0, 0, 0, ..., 0]. In any case, the lowest address is by no means limited to zero. In the memory system according to the present invention or the semiconductor memory device according to the present invention, the lowest address can be n-th power of 2, which is any of 2, 4, 8,.... Part of the address space may be assigned to different types of data storage such as hard drives or interfaces.

Page 37

Claims (1)

^ 4 2 5 5 7 5 6. Scope of patent application 1. An address space manager that specifies the address subspace of the address space defined by (η 1 + η 2) address bits to data storage (3 1 b; 41b; 51; 61; 71), the data storage is used to store the data information of the m 1 section, where the η 1, the η 2 and the m 1 are the first natural number and the second natural Number and the third natural number, and the ml is equal to or greater than and less than 2nl; it is characterized by including: an address converter (3 1 d; 4 1 d; 5 4; 6 4; 7 4), which converts the η 1 address bit (A 2 1 / A 2 2; AX / AX-1), and supply the converted address bit (A 2 1 '/ A 2 2'; a X / a X-1) To the data storage so that the address subspace is positioned on one of the 2nl_x positions in the address space, where the X system satisfies the equation 2nl-ml = 2X; and the address decoder (3 1 c / 3 2; 4 1 c / 4 2; 5 3; 6 3; 7 3), which generates a decoded signal (ΑΟ0-Α20; aO-ax-2) from an address signal containing the n 2 address bits, and Supply the decoded signal to the data storage to Select sub section data feed information from the data stored in the address m times of a space section. 2. For example, the address space manager of the first scope of the patent application, wherein the address subspace includes a series of addresses, and the consecutive _addresses are addresses that are consecutive to the remaining address subspaces in the address space. 3. For example, the address space manager of the first patent application range, wherein the address converter includes: a logic circuit (5 4 a-5 4 h), which is supplied with the η 1 bit: bit (Ax / Ax-1), and a candidate for the converted address bit (aX / aX-1) is generated from the n1 address bits, and Page 38 42557 5 々. The scope of the patent application is a plurality of rupturable conductive channels (5 4 j-5 4 q), which are respectively associated with the candidate and are selectively turned on to supply the converted address bits to The data store. 4. The address space manager of item 3 of the patent application, wherein the plurality of rupturable conductive channels respectively form a plurality of electric crystals (54j-54q) connected in parallel with each other. 5. The address space manager of item 4 in the patent application scope, wherein the plurality of transistors (5 4 j-5 4 q) are selectively formed into a normal on type to select the converted from the candidates Address bit. 6. The address space manager of item 5 in the scope of patent application, in which normally-on transistors (5 4 j-5 4p) are determined by channel doping achieved during the manufacturing process. 7. The address space manager of item 3 of the patent application scope, wherein the plurality of rupturable conductive channels (5 4 j-5 4q) are selectively turned on to make a series of addresses in the address subspace. Consecutive addresses in the remaining address subspaces of that address space. 8. If the address space manager of item 1 of the patent application scope, wherein the address converter (64; 74) contains a logic circuit (64a-64q), the logic circuit responds to indicate one of the 2 nl_x positions The nl address bits (Ax / Ax-1) and the control signal (0PT1 / 0PT2) to determine the converted address bits (a X / a X-1) in one of a plurality of ranges One of the plurality of ranges corresponds to-one corresponding to each of the 2nl-x positions. 9. The address space manager of item 8 in the patent application scope, wherein the control signal (0PT1 / 0PT2) changes the representation of one of the 2nl_x positions. Page 39 Zl 2 5 5 7 5 __ VI. Patent application scope 10. For example, the address space manager of the first patent application scope, wherein the semiconductor memory device (3 1 b; 4 1 b) is used as the data storage device. . 11. The address space manager of item 10 in the patent application scope, wherein the semiconductor memory device (31b; 41b) has an addressable read-only memory unit. 12. If the address space manager of item 1 of the patent application scope, wherein the address decoder (3 1 c; 4 1 c; 53; 6 3; 7 3) select the data storage and receive the address One of the other data storage designated by the space. 13. For example, the address space manager of item 12 in the patent application scope, wherein the other data storage is used to store the data information of the m2 section, where m2 is the fourth natural number, and the ml and the m2 The sum is equal to or greater than 2nH and less than 2ηί. 14. If the address space manager of item 13 of the scope of patent application is applied, one series of addresses and another series of addresses are respectively merged into the address subspace and the other address subspace, and the series of bits The address is consecutive to the other series of addresses. 15. For example, the address space manager of the 13th scope of the patent application, wherein the data storage (5 1; 6 1; 7 1) and the other data storage (5 2; 6 2; 7 2) All are a kind of semiconductor memory device. 16. For example, the address space manager of item 15 of the patent application scope, wherein the semiconductor memory device is a read-only memory device. 17. If the address space manager of item 13 of the patent application scope, wherein the data storage (6 1) and the other data storage (6 2) are not Page 40 d255T5 VI. Scope of Patent Application Semiconductor memory devices of the same type. 18. The address space manager of item 17 in the patent application scope, wherein one of the different types of semiconductor memory devices is a read-only memory device. 19. A semiconductor memory device that is supplied with (η 1 + η 2) address bits defining an address space, where η 1 and η 2 are a first natural number and a second natural number, including : More than one memory bank (5 1/5 2; 6 1/6 2; 7 1/7 2), one of which (5 1; 6 1; 7 1) stores m 1 section data information in the bit In the address space of the address space, here m 1 is the third natural number and is equal to or greater than 2⑷- 丨) and less than 2n]; and the address used to generate the internal address signal (a 0-a X) The space management is characterized by: The address space manager includes: an address converter (5 4; 6 4; 7 4), which is used to convert the n 1 address bits and supply the converted bits Address bit (a X / a X-1) to one of the one or more memories, so that the address subspace is positioned at one of the 2nl_x positions in the address space, where X satisfies the equation 2nI -m 1 2 2X, and an address decoder (5 3; 6 3; 7 3), generates a selection from an address signal (ΑΟΟ-Αχ + 1; ΑΟΟ-Αχ) containing at least the η 2 address bits. Signal (SEL1) and decoded signal, selectively activate the one or more memory banks with the selection signal, and supply the decoded signal to the data storage so as to extract from the m 1 section data information stored in the address subspace Select subsection Page 41 4 2 5 5 7 5 VI. Patent application scope Material information. 20. For a semiconductor memory device according to item 19 of the patent application, wherein the address subspace includes a series of addresses, the series of addresses are consecutive addresses in the remaining address subspace in the address space, and the remaining bits The address of the address space is assigned to another one of the more than one memory bank. 2 1. The semiconductor memory device according to item 20 of the patent application scope, wherein the address converter (5 4) includes a logic circuit (5 4 a-5 4 h), and is supplied with the η 1 address bit And the candidate of the converted address bit and the plurality of rupturable conductive channels (5 4 j-5 4 q) are generated from the n 1 address bits, which are respectively associated with the candidate, and are selected It is conductively supplied to supply the converted address bits to the data storage. 22. The semiconductor memory device of claim 21, wherein the plurality of rupturable conductive channels respectively form a plurality of transistors (54 4 5 4 q) connected in parallel with each other. 23. The semiconductor memory device as claimed in claim 22, wherein the plurality of transistors (5 4 j-5 4 q) are selectively formed into a normal on type so as to select the converted bit from the candidate. Address bit, and the normal on-type transistor system is determined by channel doping achieved during its manufacturing process. 24. The semiconductor memory device of item 19 in the scope of patent application, wherein the address converter (64; 74) is in response to a control signal (OPT1 / OPT2) indicating one of the 2nI_x positions so that One of the range Page 42 6. Scope of patent application Determine the converted address bits. One of the plurality of ranges corresponds to one of the 2 η 1-X positions, respectively. 25. The semiconductor memory device of claim 19, wherein one of the more than one memory bank has an addressable read-only memory unit. 2 6. — A memory system, including: a plurality of memory units (3 1 a / 3 1 b; 4 1 a / 4 1 b), which are respectively designated by the address subspace of the address space to store data Information and responds to the address signal (A0〇-A22 / A00-A20 / A21 '/ A22') to read at least the data information, one of the plurality of memory units stores m 1 section data information, this Where m 1 is a power of (η-1) greater than 2 and a power of η less than 2 and η is a natural number; and an address space manager that responds to a higher address bit of the address signal ( A 2 1- A 2 2; A 2 1-A 2 3) to selectively enable the plurality of memory units and selectively convert the lower address bits to modify and form one of the address signals Part of the address bit (A 2 Γ / A 2 2 ') instead of the higher address bit; its characteristics are: the address space manager (3 1 c / 3 1 d; 4 1 c / 4 1 d) The higher address bit is converted into the modified address bit, and the address subspace is connected in such a manner that there is no unaddressable memory unit in the plurality of memory units. Continued. 27. The memory system according to item 26 of the patent application scope, wherein the other one of the plurality of memory units is designated by the other one of the sub-spaces of the address having the highest address indicated as K, and the The highest address is consecutive 425575 6. The scope of the patent application is expressed as (K + 1) the lowest address of the one in the address subspace. 28. For the memory system of scope 27 of the patent application, the address space manager The value of the higher address bit is subtracted from the K to determine the modified address bit. 29. For example, the memory system of item 27 in the scope of patent application, wherein the other unit of the memory unit stores m2 section data information, and the m2 is a k-th power of 2, where k is a natural number. 30. For example, the memory system of item 27 in the scope of patent application, wherein the other unit of the memory unit stores m 2 section data information, and the m 2 is greater than 2 (j-1) to the power of less than 2 jth power] is a natural number. Page 44