JPH02139797A - Variable field content reading memory - Google Patents

Abstract

PURPOSE: To prevent waste of a memory bit by containing a content-addressable memory(CAM) word segment, a programer and a field selector. CONSTITUTION: The data are loaded to a four bits memory part 26 of a CAM word segment 12 through a memory bit line 22 when a word line selection signal 24 from a word address decoder is activated. The programer 14 decides a size of field, that is, the number of bits in the field of one word, and divides the field or cascade connects the field to a next unit cell according to logic levels of a field division signal 36 and its auxiliary signal 38. The output of the programer 14 is connected to a field selector 16, and selects a required field output (F1-F5) according to a field decoding signal 40 (FD1-FD5) generated by a field decoder. Thus, the waste of the bit is eliminated.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a content readout memo'J (CAM), and more particularly relates to a novel programmable variable field content readout memory. Memory word - A memory device in which a search word is stored in a location and in which a search word is compared simultaneously with all stored data words. A match signal is generated when a match occurs between the search word and the stored data word or words. If only a partial match of the stored data words is desired, masking techniques are used, but this results in a significant waste of storage bits because the storage word locations are constant width.0 Window Read Memory (WAM) is a memory device that stores multiple windows having fields selected by multiple users.

During operation, the WAM generates a pointer indicating which window, if necessary, will bound the input data word. Considering the interior of the window, all fields of the input word must be less than the upper bound and must be greater than the lower bound of the window. The output of the WAM device is a match signal indicating that the word presented at the input falls into one of the windows. Addresses of matched words can be read out. When multiple matches occur, a prioritization method is used to allow the addresses to be read out sequentially. WAM devices can be connected together to create larger WAM memory systems; however, WAM is the only metallization mask that is programmable to select field boundaries before assembly; It can be used to change the size, but this method wastes bits.

CAMs can be modified to perform limit operation comparisons on input data; however, their operation requires additional comparators and arithmetic circuits, which use considerable semiconductor chip area.Q Associative comparators (ACs) Devices (IBM, Federal
Systems Division.

(Developed by Manassas, Virginia)
It is.

The AC chip compares the two 16-pit parameters to 32 sets of upper and lower limits and generates a 5-bit match address. Each of the two parameter comparisons in each of the 32 comparison cells can be independently programmed for in-limit or out-of-limit comparisons. Each comparison cell can be independently activated or deactivated, and either of the two parameters can be globally disabled, ie, ignored for all 32 comparison cells. Several AC devices can be cascaded horizontally to accommodate any number of parameters and vertically cascaded to provide any number of comparison cells. The match read circuit is pipelined so that matches from previous comparisons can be read while the current comparison is in progress. However, A
C devices do not have the ability to change the location of field boundaries.

(Summary of the Invention) According to the present invention, the variable field content readout memo IJ (
VFCAM) cell is provided, the cell having at least one storage bit for storing a data word or a portion of the data word, each storage bit being connected to a word selection line and a data line. at least one memory means in said memory means coupled to said memory means corresponding to a field of said data word in response to a field partition signal;
field size determining means for determining the size of one field or a portion of the field;
field selection means coupled to the sizing means and responsive to the field decode signal for directing a match signal from the memory means to the field output line. The memory means has comparator means coupled to each storage bit for generating said match signal when each data line of the search word is equal to a corresponding bit of the data word stored in said memory means. .

In accordance with the present invention, a VFCAM array is provided that is comprised of a plurality of VFCAM cells coupled together vertically and horizontally to form an Y-word by X-bit array of storage locations. Terminator means are coupled to each unused field output line of the VFCAM array to achieve a known logic state.

The present invention further provides a VFCAM system, the system comprising a memory array means for storing a plurality of data words in a plurality of storage locations, each storage location having the same partition for one or more fields. memory array means having a field corresponding to a field of the data association word; and a memory array means coupled to the memory array means for accessing each of the storage locations within the memory array means in response to an address input. address-decoder means for transferring data to and from the memory array means in accordance with said address input;
field partitioning means for selecting the number of fields in each storage location of the array means and the number of bits in each field in response to a code; and encoding means for generating an address for each field.

Further in accordance with a feature of the invention, the data is transferred to and from the memory array means in accordance with the address input, and a plurality of data arrays within the memory array means of the memory system are provided.
a field partitioning means for storing a data word, the data word having a field corresponding to a field partitioning of the memory array system, and field partitioning means responsive to a programmable field code; VFCAM comprising the steps of selecting the number of fields and the number of bits in each field and generating an address for each field in the stored data word by encoding means coupled to the output of the memory array means. A method is provided for programming the system.

Embodiment Referring to FIG. 1, a 4-bit variable field content readout memory (VFCAM) unit according to the present invention - cell 1
0 is indicated, and the cell 10 is a content read memory (CAM).
It includes a word segment 12, a programmer 14 and a field-selector 16. A plurality of 4-bit unit cells are arranged in a vFCAM array 50 consisting of Y words and X bits (Y words and XX bits) as shown in FIG.
It is possible to incorporate them into one unit cell matrix to form a. Data is loaded into the 4-bit memory section 26 of the CAM word segment 12 through the memory bit lines 22 when the word line select signal 24 from the word address decoder is active. Data is provided to memory Φ bit line 22 for comparison with data previously stored in CAM word segment 12. The comparison is based on the 4-bit memory circuit 26α in the CAM word segment 12.
〜26d, respectively.
~24d, and when all bits are compared, a sign or match is detected by matching NAND gate 20. The inputs to NAND game 20 are the match signal on line 30 in that unit cell and the match input signal 32 from the adjacent cascaded unit cell.
It consists of If there are no adjacent unit cells, the adult line 32 is connected to vDD and provides a constant logic one. The output of NAND gate 20 is coupled to programmer 14.

Programmer 14 determines the field size, ie, the number of bits in a word field. Depending on the logic level of field partition signal 36 (and its complement 38), programmer 14 either partitions the field or cascades the field to the next unit cell.

The output of programmer 14 is coupled to field selector 16 which selects the desired field output (Fl-F5) according to field decode signal 40 (FDI-FD5) generated by field decoder 64 shown in FIG. Select. The size of one field is variable from X bits to q bits in X bit increments, and the number of fields in one word is 1.
~ m. Unit cell 10 provides one field of 4 bits (Z:4) or
It is part of a larger field consisting of two or more cascaded unit cells. Furthermore, a unit cell 10 can be part of a word with up to 5 fields (m=5). Although a unit cell can theoretically have any number of bits, unit cell 10 provides the best implementation of a unit cell with minimal overhead circuitry. VFCAM unit cell 10 is fabricated from VLSI Complementary Metal Oxide Semiconductor (0MO8) chips designed by the assignee of the present application using CMO8 technology well known to those skilled in the art.

Further, in FIG. 1, all four bits of data in CAM word segment 12 are present on memory bit line 2.
If it matches the incoming data on NAND gate 20, the logic level of N1 of NAND gate 20 remains at logic 1 as before. If one or more of the four bits of data do not match the incoming data, the Nl input will be a logic O. When field partition signal 36 is a logic O, the field is extended to the next VFCAM unit cell.

The result of the match at node N1 is output to match output line 34 via NAND gate 20, transfer gate 47 and inverter 48 when T2 transistor 43 is off as a result of field partition signal 36 being a logic O.
will be forwarded to.

If a match occurs, the -spread output signal 34 is a logic 1; otherwise, it is a logic O. - The dispersion output signal 34 is connected to the coincident inputs of the cascaded unit cells as shown in FIG. When field partition signal 36 is a logic one, the field ends in that unit cell. The result of the match at node N1 is field output 44
01 (transfer fist gate 46, inverter 45
and field select transfer gates 49α-49 determined by field decode lines 40.
g. Additionally, match output 34 will be a logic 1 when field partition signal 36 is a logic 1 (turning T2 ON) and transistor 43 is in the ON state. The drain of T2 is set to logic 0 and inverter 4
8, causing the match output 34 to be a logic I. Then, the next field can be started.

Referring now to FIG. 2, the module configuration VFCA
M unit cell lO is shown, four such cells 10 are used, VFCAM-A52, VFCAM-B 54, V
The FCAM-C 56 and VFCAM-D 58 form a 2×2 matrix of VFCAM arrays 50 having a storage capacity of 2 words×8 bits. OVFC whose unit cell interconnections are shown in Figure 2.
AM-A52 word line selection signal 24 is VFC
Connected to the same signal line of AM-B54. VFCA
The coincidence output 34α from M-A is connected to the coincidence output 34 line of VFCAM-B 54. field output 44
are connected to respective corresponding signal lines of VFCAM-B54.

Memory bit line 22 of VFCAM-A52 is V
Connected to the same signal line of FCAM-C56. VF
Field decode line 40 of CAM-A 52 is connected to the same signal line of V.FCAM-C 56.

Precharge Life 46 and Field Division Fi 73
6 and 38 are connected to corresponding lines in the VFCAM-C56. The interconnection between VFCAM-B54, VFCAM-C56 and VFCAM-B58 is VFCAM-A5
2. The interconnection is similar to that of VFCAM-B54 and VFCAM-C56. A VFCAM array of larger word capacity (Y) and larger bit length CX') is constructed by vertically and horizontally adding the desired number of VFCAM unit cells 10 into the unit cell matrix shown in FIG. It can be easily configured by adding

Next, referring to FIGS. 1 and 3, the VF shown in FIG.
CAM unit-cell 10 contains B and B memory bits.
Limit memory-to-memory comparison (C
BLM). The outputs B and B of bit masking circuit 80 are connected to corresponding pairs of memory bit lines 220, such as B and B shown in FIG. For example, in a 4-bit VFCAM, a 4-bit masking circuit 8
0 is connected to the memory bit line 22, and if 3 pits are masked and MSB=O, a match occurs when the incoming signal is between O and 7, and if MSB=1,
A match occurs when the incoming signal is between 8 and 15. Table 1 shows the 4 bits V when 1, 2 and 3 bits are masked.
Each binary number of FCAM and its associated bracket range are shown.

Tables 6-8- Now referring to FIG. 4, programmable VFCAM
A block diagram of system 70 is shown.

Address decoder 60 loads data into the addressed storage location of VFCAM array 50 and decodes address 61 to read the loaded data. The VFCAM array 50 has Y words and X bits of storage locations, and includes multiple VFCs cascaded vertically and horizontally as shown in FIG.
It can be configured by an AM unit cell 10. Field code register 62 stores field code control words 63 to program a plurality of identical fields within the Y word storage locations of array 50.

Field fist decoder 64 decodes field code control word 63 and generates field decode signal 40.
This decode signal 40, in conjunction with field partition logic 65, selects one or more fields within a storage location for a data word. VFC
An encoder 68 coupled to the output of AM array 50 generates a select output signal 69 that indicates the state of any one or more fields within VFCAM array 50. I10 register 66 stores data in VFCAM
Load into array 50 and read from it or VFC
Receives data that is compared to data stored within AM array 50. Additionally, mask register 67 couples mask-bits to memory bit lines 22 of VFCAM array 50 through bit masking logic shown in FIG. 3 to perform masking operations. VFCAM system 70
The operation of includes the following steps.

1. Load data into the memory circuits 26cL to 26d via the I10 register 66.

2. Field code word 63
By loading into code register 62, programmable field partition control 71 selects the number of fields and number of bits within a field, thereby creating partitions or boundaries for one or more fields within a VFCAM storage location. Set 0 3 to compare the data stored in CAM 12 with the incoming data on memory bit line 22 in comparator 24 and generate a match output signal 34 as the comparison is made for each field 0 4 , encoder 68 encodes the field outputs 44, 45, etc. based on each search word and provides information based on the contents of the selected field outputs.

Here, referring to FIG. 4 and FIG. 5, FIG.
A detailed block diagram of the field division control unit 71 shown in the figure is shown. The programmable field partitioning of the VFCAM 50 is shown in FIG. 5, where the control logic functional blocks are generalized to allow any number of field outputs (m) 44 to be drawn from an array of Y VFCAM words. . Each VFCAM word has n programmable partitions across CAM word segments, each segment being X bits wide (where n is greater than or equal to m) o CAM word segment ( 12α,
12b, etc.) can have different bit widths. Fifth
In the figure, a single VFCAM word is segmented into n sections of equal width for a total of 7Lπ bits.

Referring now to FIGS. 1, 4, and 5, the CAM word unit cell 10α in FIG. 5 corresponds to the 4-bit VFCAM unit cell 10 shown in FIG. 4 and the number of fields m is equal to 5. The field partition control unit 71 includes m field code registers 62α to 62, (m-1) field decoders 64α to 64(?7L-1), and n partition logic elements 65α to 65s. Become. Field code registers 62α to 62m are VFCAM
A field code is stored specifying the bit width or partition size of each variable field of the word. field·
Decoders 64α-64(?7L-1) select particular field boundaries and corresponding field outputs 44 in the order indicated in response to field code registers 62α-62m. Partition logic elements 65a to 65n are 0 filters that sample the state of the outputs of field decoders 64a to 64(m-1) that operate programmers 14a, 14b, etc. that provide signals to each CAM word unit group cell 10a. In addition to the field partition control section 71, the V
Each set of m field outputs 44 from an FCAM word requires a field terminator 59. The field terminator 59 logic sets the state of the unused field output 44 when less than m fields are being used. Fields that are not used can be set to a logic 1 state or a logic 0 state. If the terminator logic circuit is not provided,
Field outputs 44 that are not used are not revealed.

For a particular VFCAM, by determining the number of fields (?L) in the VFCAM variable field word, the number of bits in each field (2) or CAM word segments, and the number of field outputs (m). The field configuration is completed.

Further referring to FIG. 5, generally each field selector, eg, FSl in vFCAM unit cell 10α, has n field selection inputs and associated logic selection circuitry. 1 and 2 illustrate an embodiment of the invention in which the number of field outputs 44 is five. For m outputs, the required field-code register 62
The number of a to 627FL is also always equal. These field-code registers 62α to 62m consist of one or more D-type flip-flops of bit length αi;
The hex field codes 62α-62m are stored, and the number of bits in the field code register is determined by knowing the desired number of boundaries. Therefore, 2”=n or a
ilog2=1ogn and are therefore arranged in the indicated order starting with field (m=1). The first field can be placed at any of the n border locations.

The number of bits in the first field register is determined by . For example, when m=16, α! =4. However, when n=20, α+=4.32 and 9 integer value 5 is assigned as the number of bits in the field code register.

The second field (m=2) has a maximum number of assignable border locations of 7L-1. The reason is that the first field is required to have a minimum n=1 boundary. Therefore, it becomes. Here n is the number of boundaries on which a particular field can be defined. If αi is not an integer, the next largest integer is selected as αi.

The field decoders 62α to 6277L are connected to the first (7th
L-1) Field meeting code register 62α to 62n
This process of determining the magnitude of is continued until n2Cm-1), at which point it becomes.

Each field code register output is Cm-1)
field decoders 64α to 64(?L−1), and these decoders perform the necessary combinational decoding to input one field from n (1of n ), (n−1).
One from (1of(fL-1)), -・-・・−・(n
-m+ 1 ) to one (1of (?L-??L+
1) Select a possible boundary location for (m-1) in the total field of ). The last field can only be located in one position, namely at the end boundary. Therefore, the FR1rL field number code register is only 1 bit (one D-type slip flop) and has a logic value of 1'' when m field placements are to be determined, and any field placement less than m is determined. Since the logic value is "0" when it should be 0, the FRm register directly provides input to the FSn logic and does not have an intermediate combinatorial selection logic circuit.

In all cases where fewer than m field placements are chosen, the field must coincide with the last boundary,
The highest order output line that is not selected must be terminated. These highest unselected fields are 1
one code (binary) must be stored, and the code does not provide valid boundary selection from the corresponding field decoder. This is easily accomplished by setting all of those registers to zero.

The field terminator logic unit 59 outputs all unused field outputs to logic ``0'' as shown in FIG.
Configured to set the state.

This logic is located at the end of the nzVFcAM word.

If only one field is selected, the FDt output feeding the FSn input is set to a logic '1'' level and the F
D2...FD, m-, and FR, rrL
is set to logic ``0''. Thus, rttVF
The entire CAM word contains only one field of data;
The associated output is provided to the Fl output line through the FSn selector. As shown in FIG. 6, all high order field output lines are terminated to ground by TI transistors.

Once a complete m-field configuration is selected, FR,rrL
is set to logic t*1n, and FDI......FDm-, which gives a signal to the F'S7L selector, is set to logic ``0'' state.0 In this state, FD,...・
...Field selection for FDfi-1 should have been performed sequentially at the previous FSz boundary. Here, all the termination transistors (T1.T2...
...T3-t) is held "off", ie, non-conducting. When fewer fields than usual are selected, the highest order field is output from its associated field output line (Fj; here i
= 1 to m), and all unused outputs Fi+1...F, rrL are terminated to ground.

Referring again to FIG. 5, the partition logic elements/toro 5a to fi
5n samples the state of the input to the field selector (FSi; j=1 to n) and prepares the program logic input to the programming element (pi) 14cL, 14b, etc. Since it is also explicit at the boundaries, a simple "OR" logic function is required to sample the m inputs to the FSj field selector at each boundary. However, PLi
Logic elements can adopt certain simplifications depending on their location. Since the FSI can make only one selection (first field), there is only one (i.e. FI) 1) of the FDi (j:1~(77Z-1)) signal lines providing this boundary. do. Therefore, P.L.
I is a single direct wire through connection. For PL2, a two-person “OR” function is required, and for PL3, a three-person “OR” function is required.
Requires "OR" function, and when n = m, m input "OR" is required.
functionality is required. All P after that (i≧rn)
i requires an m-input "OR" function.

Two examples of field partitioning are n=16, m-5 and α
It is shown in FIGS. 7 and 8 for i=4. CA
The M word segments (12a-12m) can be constructed of any bit length.

Field code register FRi (z=1~trL
) are loaded in Table 2.
is selected from simple binary numbers representing field boundary locations, as shown in FIG.

Table 2 Binary Field Codes nth Boundary In the example shown in Figure 7, there are 16 programmable partitions (n=16) and the VFCAM word consists of 5 fields loaded into the field number code register (FRz). - It has five fields (Field A to Field E) programmed by C'(FC'). Each field is programmed for a different total number of bits per field, and outputs F1-F5 monitor each field. The number of bits in each VFCAM word segment is arbitrary based on the desired performance characteristics and efficient use of area on the silicon chip, and is shown in FIG.
A unit cell has 4 bits. In the example shown in FIG. 8, there are 16 programmable sections Cn=16), and V
FCAM word is field code register FRi
It has three fields (Field A to Field C) that are programmed by the three field codes that are loaded into the field. Each field is programmed for a different total number of bits per field, and there are 5 field output lines with 3 fields, so
Two of the output lines (F4 and F5) are terminated to ground by the terminator circuit shown in FIG.

Although a preferred embodiment has been described, many changes and modifications will be apparent to those skilled in the art without departing from the scope of this invention. For example, a VFCAM unit cell may consist of one or more bits depending on design goals and performance characteristics;
The AM array is composed of multiple VFCAM unit cells depending on the size of the array being assembled.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the present invention showing a four pit variable field CAM unit cell. FIG. 2 is a block diagram of a 2.times.2 unit cell matrix using the present invention showing the interconnections for a 2 word 8 bit variable field CAM array. FIG. 3 is a circuit diagram of a bit masking logic circuit. FIG. 4 is a block diagram of a preferred embodiment of the variable field CAM system of the present invention. FIG. 5 is a generalized block diagram of the variable field control logic of the present invention. FIG. 6 is a circuit diagram of a field terminator for field output signals. FIG. 7 shows an example VFCAMO with 16 programmable partitions programmed for 5 fields in a VFCAM word storage location with 5 field outputs to monitor each field. FIG. 8 shows a VFCAM with 16 programmable partitions that provides 5 field outputs but is programmed for 3 fields in a VFCAM word storage location with 3 field outputs to monitor each field.
Here is an example. (Other 4 people) 1. Indication of the case 1986 Patent Application No. 312778 or 2. Name of the invention variable field content reading memory 6. Address of the person making the amendment related to the case

Claims (1)

Claims: 1. Memory means having at least one storage bit for storing a data word or a portion of the data word, each storage bit being coupled to a word selection line and a data line. a field coupled to said memory means for determining the size of at least one field or portion of said field in said memory means corresponding to a field of said data word in response to a field partition signal; - a variable field content reading memory comprising size determining means; and field selection means coupled to said field size determining means for directing a match signal from said memory means to a field output line in response to a field decode signal; (VF
CAM) cell. 2. said memory means having comparator means coupled to each storage bit, said comparator means such that each data line of a search word is equivalent to a corresponding bit of a data word stored in said memory means; 2. The VFCAM cell of claim 1, wherein the VFCAM cell generates the coincidence signal when. 3. The field size determining means is configured to determine the size of the adjacent memory.
2. The VFC of claim 1, further comprising means for transmitting said match signal to said adjacent memory cell when said cell comprises a portion of said field responsive to said field partition signal.
AM cell. 4. Consisting of a plurality of VFCAM cells coupled together vertically and horizontally to form an array of Y words and X bits of memory storage locations, each said cell containing (α) a data word or (6) memory means having at least one storage bit for storing a portion of the data word, each storage bit being coupled to a word selection line and a data line; a field which is coupled to and responsive to a field partition signal to determine the size of at least one field or part of said field in said memory means corresponding to a field of said data word;
(c) field selection means coupled to said field sizing means for directing a match signal from said memory means to a field output line in response to a field decode signal; A variable field content read memory (VFCAM) array having terminator means coupled to a field output line for setting each unused field output line to a known logic state. 5. said memory means having comparator means coupled to each storage bit, said comparator means such that each data line of a search word is equivalent to a corresponding bit of a data word stored in said memory means; 5. The VFCAM array of claim 4, wherein the VFCAM array generates the coincidence signal when. 6. The field size determining means is configured to determine the size of the adjacent memory.
5. The VFC of claim 4, further comprising means for transmitting said match signal to said adjacent memory cell when said cell comprises a portion of said field responsive to said field partition signal.
AM array. 7. Memory array means for storing a plurality of data words in a plurality of storage locations, each of said storage locations having the same partitioning for one or more fields, said fields having said data - memory array means corresponding to a field of words; and address decoder means coupled to said memory array means for accessing each of said storage locations within said memory array means in response to an address input; means for transferring data to and from said memory array means in accordance with said address input; and means for transferring data to and from said memory array means in response to a field code; field partitioning means for selecting the number of fields and the number of bits within each field; and encoding means coupled to the output of the memory array means for generating an address for each field in the stored data word. Variable field content read memory (VF) configured
CAM) system. 8. The system of claim 7, further comprising means coupled to said transfer means for masking one or more bits of data being transferred to said memory array means. 9. The memory array means of claim 7, wherein said memory array means comprises a plurality of memory cells coupled together vertically and horizontally to form a Y word by X bit array of said memory storage locations. system. 10. The system of claim 9, wherein each of said memory cells includes means for determining the size of each field within said storage location in response to a field partitioning signal from said field partitioning means. 11. Each of said memory cells has field selector means coupled to said field sizing means, and in response to a field decode signal generated by said field partitioning means, said memory cells - The system of claim 10, wherein the coincidence signal generated within the cell is directed to a field output line. 12. each of said memory cells having comparator means coupled to each storage bit within said memory cell;
Each data line of a search word is data stored in said memory means. 12. The system of claim 11, wherein the system generates the match signal when corresponding bits of a word are equal. 13. transferring data to and from the memory array means in accordance with an address input; storing a plurality of data words in the memory array means of the memory system; and storing a plurality of data words in the memory array means; - field partitioning means responsive to a programmable field code having fields corresponding to the field partitioning of the system, each of the storage locations of said memory array means having the same number of fields and bits within each field; a variable field content reading memory comprising the steps of: selecting a number and generating an address for each field in said stored data word by encoding means coupled to the output of said memory array means;
How to program the system.