424324 A7 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 五 '發明說明（/ ) 1.發明之技術領域： 本發明係有關於i用於製造高密度動 憶體電路之冠狀電容器結構的方法α 子取5己 2·發明背景： 半導體產業持續不斷地改良半導體元件的性 時試圖降低該半導體元件的製造成本。隨著】獻 次，特徵尺寸之製程技術以製造半導體記憶體晶^業= 目軚已部份實現。使財微倾徵尺寸歧 電容量及電阻率。此外’使用較小的 ^較小的“ ’惟其财㈣集度仍與以較大特徵尺寸所 製仏的較大料體晶片具相同水平。此舉將允許在特定尺寸 的起始基板上獲得更大量之密度更高且更小的晶片，因 低各別晶片的製造成本。 然而在部份領域中，次微米特徵尺寸的使用將對動態 隨機存取記題元件賴能有貞面影._賴存取記憶 體元件通常包含一堆疊電容器（STC)結構，其位於傳遞閘 極電晶體(Transfer Gate Transistor)上方並被連接至傳遞 閑極電晶體的源極。然而，減少傳遞閘極電晶體的尺寸將限 =堆疊電容器結構的尺寸。為增加電容量以提昇堆疊電容器 、〜構（其包含以-介電層隔離的二個電極）的性能，則必須 ，法降低介電層的厚度或增加電容器的面積。然而欲降低介 電層的厚度’必須承擔可靠度與良率下降的風險。此外，該 堆叠電容is結構的面積係受限於底下傳遞間極電晶體的面 積。當動癌隨機存取記憶體的技術邁入每晶粒256百萬位元 請 先 閲 讀 背 意 亊 項 再 填 I 1 訂 本紙張&料用〒國國家標準(cNsuTii" 2 (210 X 297 *1 ) 424324 B7 五、發明說明（>) 或者更高的領域後，已使用—種較 :憶胞，致使其上⑽形成堆疊電讓二=:: 一種維持或增加堆疊電容器雷 被使用於以冠狀儲存節絲 合I構，其中該冠狀儲存節點結構由連接至 =直石=部份以及覆蓋在儲存節點接觸插塞頂端表1 = 底下傳遞閘極電晶體的源極區接觸）並接觸之的 f成° f冠狀結構的垂直部份所增加的表面積將增;容 而無須增加電容器結構的橫向尺寸。該冠狀儲存節點处 構的形成可精由首先形成—電容器開口於—介電 沉積並刻劃一複晶石夕層，以形成—複晶 ^ 構。形成電容器開口於介電層中的製程係以覆蓋 層完成’而該電容關口的_製程賴選擇性地停止或線 止於該第二介電層上。在進行電容器開口的爛製程時，必 須避免第二介電層被舰或移除’因為該第二介電層被用以 保護底下的動態隨機存取記憶體單元元件。 本發明將說明-種用於製造動態隨機存取記憶體裝置 的冠狀儲神點結構_新方法’其觀為在進行電容器開 口的侧製程時使職氧_ (siGA)層做為_级止層， 而該_y層將覆蓋並保護用祕護特定動態隨機存取記憶 體早Μ件的介電層。諸如驗er所發表的美國專利第 5, 518, 948號等習知技藝說明使用於電容器製造的氣化石夕阻 絕層。然而，使用氮氧化挪提供多種超過習知技藝的優點， 本紙張尺㈣财賴家鮮（CNS)A4祕(i^ x 297U7 (請先間讀背面之注意事項再填寫本頁) 裝--------訂--------- Λ 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 424324 Λ Α7 五、發明說明（}) 諸如：在電容器節點接觸開口製程的微影時做為經改良的抗 反射塗覆(ARC) ’在電各器開口製程終止時做為經改良的終 點偵測；降低硼磷矽酸鹽玻璃層中的應力，以減少薄膜破裂 的可能性，-帛於隔離如猶存節點結構與底下摻雜介電層 的阻障層；以及在用於電容器開口的乾式顧刻製程期間之 少的負載現象。 本發明之概要： 本發明之主要目的係為製造冠狀儲存節點結構，以增 加動態隨機存取記憶體電容器結構的表面積。 q 本發明之另一個目的為藉由沉積並刻劃置於電容器開 口表面上之複晶發層’而於介電層中形成冠狀儲存節點結 構。 本發明的又另-個目的為在介電層中形成電容器開口 的蝕刻製程係使用氮氧化矽層做為蝕刻终止層。 根據本發明细於形成靴儲存節點結構的方法 已被開發’其重點為在介電層巾形成電容賴口_刻製程 係使用氮氧化石夕層做為餘刻終止層。在形成傳遞閑極電晶體 後’形成-層第-介電層並進行平坦化製程，且接著沉積第 二=電層其中各傳遞_電晶體包含:―_職介電層、 -亂化料、複晶雜金屬（金屬耗物_複晶⑺閑極結 構、-淡摻雜源極/沒極區、位於複晶賴極結構側壁上的 氮化石夕間隙壁以及-源極/；:及極區。在開啟第二介電層盘第 —介電層t的接觸孔’以裸露出傳遞閘極電晶體之間ς 原極 /沒極區後’於所述接觸孔中形成做為後續位元線接觸结構 (請先閱讀背面之注意事項再填寫本頁) 裝 ΐ-β424324 A7 Printed by the Consumers 'Cooperative of the Ministry of Intellectual Property of the Ministry of Economic Affairs of the People's Republic of China on the 5' Invention (/) 1. Technical Field of the Invention: The present invention relates to a method for manufacturing a crown capacitor structure for a high-density dynamic memory circuit. 2. Background of the Invention: When the semiconductor industry continuously improves the properties of semiconductor devices, it attempts to reduce the manufacturing cost of the semiconductor devices. Along with this time, the process technology of feature size to manufacture semiconductor memory crystals has been partially realized. Make money trace the size of capacitance and resistivity. In addition, 'use smaller ^ smaller' but still have the same level of financial density as larger bulk wafers made with larger feature sizes. This will allow access to specific size starting substrates A larger number of higher density and smaller wafers, due to lower manufacturing costs of individual wafers. However, in some areas, the use of sub-micron feature sizes will have a positive impact on dynamic random access problem components._ The access memory device usually includes a stacked capacitor (STC) structure, which is located above the transfer gate transistor and is connected to the source of the pass transistor. However, the transfer gate transistor is reduced. The size will be limited to the size of the stacked capacitor structure. In order to increase the capacitance to improve the performance of the stacked capacitor, which includes two electrodes separated by a -dielectric layer, it is necessary to reduce the thickness of the dielectric layer or Increase the area of the capacitor. However, if you want to reduce the thickness of the dielectric layer, you must bear the risk of decreasing the reliability and yield. In addition, the area of the stacked capacitor is structure is limited by the bottom electrode. The area of the crystal. When the technology of moving cancer random access memory enters 256 million bits per die, please read the intent and then fill in the I 1 booklet & national standard (cNsuTii " 2 (210 X 297 * 1) 424324 B7 V. Description of the invention (>) or higher, it has been used-a kind of comparison: memory cell, causing its upper to form a stack electricity let two = :: a kind of maintaining or increasing the stack Capacitor mines are used in a crown-shaped storage node wire structure. The crown-shaped storage node structure is connected to = straight stone = part and covers the top of the contact plug of the storage node. Table 1 = Source of the gate transistor Area contact) and the contact angle f will increase. The increased surface area of the vertical portion of the crown structure will increase; the capacity does not need to increase the lateral dimension of the capacitor structure. The formation of the crown storage node structure can be precisely formed first-capacitor opening In-dielectric deposition and scoring a polycrystalline stone layer to form a -multicrystalline structure. The process of forming a capacitor opening in the dielectric layer is completed with a cover layer ', and the process of the capacitor gate depends on selectively Stop or stop at On the second dielectric layer. During the process of rotating the capacitor opening, the second dielectric layer must be prevented from being removed or removed because the second dielectric layer is used to protect the underlying dynamic random access memory unit The present invention will explain a crown storage point structure for manufacturing a dynamic random access memory device _ a new method 'its view is to use the siGA layer as a _ Level stop layer, and the _y layer will cover and protect the dielectric layer that protects the early M pieces of specific dynamic random access memory. For example, U.S. Patent No. 5,518, 948 published by Ernst et al. Explain the gas barrier used in capacitor manufacturing. However, the use of nitric oxide provides a variety of advantages over known techniques. The size of this paper is based on the secret of CNS A4 (i ^ x 297U7 (please read the precautions on the back before filling out this page). Pack- ------ Order --------- Λ Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 424324 Λ Α7 V. Description of the invention (}) Such as: in Improved anti-reflective coating (ARC) when the lithography of the capacitor node contacts the opening process' Improved endpoint detection at the end of the opening process of the electrical reactor; reduces stress in the borophosphosilicate glass layer In order to reduce the possibility of film cracking, it is difficult to isolate the barrier layer such as the existing node structure and the underlying doped dielectric layer; and the small load phenomenon during the dry-type etching process for the capacitor opening. Summary: The main purpose of the present invention is to manufacture a crown-shaped storage node structure to increase the surface area of the dynamic random access memory capacitor structure. Q Another object of the present invention is to deposit and score the capacitor on the surface of the capacitor opening. Polycrystalline hair layer A crown-shaped storage node structure is formed in the dielectric layer. Another aspect of the present invention is an etching process for forming a capacitor opening in the dielectric layer using a silicon oxynitride layer as an etching stop layer. The method of bootstrap storage node structure has been developed. Its focus is to form a capacitor in the dielectric layer. The engraving process uses an oxynitride layer as the remaining stop layer. After the formation of the passivation transistor, it is formed- Layer-dielectric layer and a planarization process, and then deposit a second = electric layer where each transfer_transistor includes: __ dielectric layer,-disordered material, polycrystalline heterometal (metal consumables_ complex The crystal structure, the lightly-doped source / dead region, the nitride nitride spacer on the side wall of the compound crystal structure, and the -source /; and polar regions. When the second dielectric layer disk is turned on, The contact hole of the dielectric layer t is formed by exposing between the gate electrode transistors and the original / non-electrode region in the contact hole as a subsequent bit line contact structure (please read the (Please fill out this page again)
A7 4 2 43 2 4 ^ ------- --B7_____ 五、發明說明（[^) 與後續儲存節點接觸結構之元件的下複晶石夕插塞《形成第三 介電層’並在所述第三介電層中形成位元線接觸孔，以裸露 出下複晶石夕插塞。在形成金屬位元線結構於位元線接觸孔中 並覆蓋於第三介電層上表面部份後，形成一層第四介電層且 接著沉積一覆蓋在上面的氮氧化矽層。在所述氮氧化矽層 中’以及第四介電層與第三介電層中形成開口，以裸露出做 為儲存節點接觸之下複晶矽插塞的頂部表面。形成上複晶矽 插塞，以形成由上複晶矽插塞與下複晶矽插塞所組成的儲存 節點接觸結構。其次，沉積一第五介電層，並接著進行微影 與乾式餘刻製程，以在所述第五介電層中形成電容器開口， 以裸露出儲存節點接觸結構的頂部表面並裸露出氮氧化矽層 的表面。在沉積一複晶矽層後，使用化學機械研磨法由該第 五介電層的上表面移除所述複晶石夕層，以在電容器開口中形 成冠狀儲存節點結構；其中該冠狀儲存節點結構包含位於電 容器開口之第五介電層邊緣上的垂直複晶矽，而該垂直複晶 矽係與覆蓋並接觸儲存節點接觸結構之上表面並覆蓋在電容 器開口底部之氮氧化矽層的水平複晶矽連接。在選擇性地移 除第五介電層（以所述氣氧化石夕層做為侧終止層）並接著 改變蝕刻參數以移除該氮氧化矽層後，形成一電容器介電層 於該冠狀儲存節點結構上，接著形成覆蓋在上面的複晶石夕上 電極板’而元成用於形成動態隨機存取記憶體電容器結構的 製程。 圖式說明： 圖一是本發明中形成場氧化層的剖面示意圖。 __ 5 --------.----裝--------訂， (請先間讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印：^ 本纸張尺度適用中國國家標準（CNS)A4規格（21〇 297公釐） B7 424324 五、發明說明（f) 圖二是本發明中形成具氮化矽頂蓋之閘極結構的剖面 示意圊β 圖三是本發明中形成場氧化層的剖面示意圖。 圖四是本發明中形成第一層間介電層的剖面示意圖。 圖五是本發明中形成開口的剖面不意圖。 圖六是本發明中形成下複晶破插塞的剖面示意圖。 圖七是本發明中形成位元線結構的剖面示意圖。 圖八是本發明中形成氮氧化石夕層的剖面示意圖。 圖九是本發明中形成開口的剖面示意圖。 圖十是本發明中形成上複晶矽插塞的剖面示意圖。 圖十一是本發明中形成電容器窗口的剖面示意圖。 圖十二是本發明中形成複晶矽層的剖面示意圖。 圖十三是本發明中形成電容器下電極板的剖面示意 圖。 圖十四是本發明中去除氧化矽層的剖面示意圖。 圖十五是本發明中完成電容器結構的剖面示意圖。 圖號說明： 2 場氧化矽層 4 複晶矽層 6 介電層 8 閘極結構 10閘極結構 12閘極結構 Μ淡摻雜源極/汲極區 -----------•裝--------訂· (請先閱讀背面之注意事項再填窩本頁) 經濟部智慧財產局員工消費合作社印製 1半導體基板 3 閘極介電層 5 金屬矽化物層 7閘極結構. 9閘極結構 11閘極結構 13閘極結構A7 4 2 43 2 4 ^ ------- --B7 _____ V. Description of the invention ([^) The lower polycrystalline stone plug of the element that is in contact with the subsequent storage node structure "forming the third dielectric layer" and A bit line contact hole is formed in the third dielectric layer to expose the lower polycrystalline stone plug. After the metal bit line structure is formed in the bit line contact hole and covers the upper surface portion of the third dielectric layer, a fourth dielectric layer is formed and then a silicon oxynitride layer is deposited thereon. Openings are formed in the silicon oxynitride layer and in the fourth dielectric layer and the third dielectric layer to expose the top surface of the polycrystalline silicon plug under the storage node contact. An upper polycrystalline silicon plug is formed to form a storage node contact structure composed of an upper polycrystalline silicon plug and a lower polycrystalline silicon plug. Next, a fifth dielectric layer is deposited, and then a lithography and dry-etching process is performed to form a capacitor opening in the fifth dielectric layer to expose the top surface of the storage node contact structure and the nitrogen oxide. The surface of the silicon layer. After depositing a polycrystalline silicon layer, the polycrystalline stone layer is removed from the upper surface of the fifth dielectric layer using a chemical mechanical polishing method to form a crown-shaped storage node structure in the capacitor opening; wherein the crown-shaped storage node The structure includes a vertical polycrystalline silicon on the edge of the fifth dielectric layer of the capacitor opening, and the vertical polycrystalline silicon is in contact with the upper surface of the storage node and contacts the upper surface of the structure with the silicon oxynitride layer at the bottom Polycrystalline silicon connection. After selectively removing the fifth dielectric layer (using the aerosol layer as a side stop layer) and then changing the etching parameters to remove the silicon oxynitride layer, a capacitor dielectric layer is formed in the crown shape. On the storage node structure, a polycrystalline spar upper electrode plate is then formed, and Yuan Cheng is used to form a process of forming a dynamic random access memory capacitor structure. Description of the drawings: FIG. 1 is a schematic cross-sectional view of a field oxide layer formed in the present invention. __ 5 --------.---- Equipment -------- Order, (please read the precautions on the back before filling this page) ^ This paper size applies the Chinese National Standard (CNS) A4 specification (21,297 mm) B7 424324 V. Description of the invention (f) Figure 2 is a schematic cross-sectional view of a gate structure with a silicon nitride cap in the present invention圊 β Figure 3 is a schematic cross-sectional view of a field oxide layer formed in the present invention. FIG. 4 is a schematic cross-sectional view of forming a first interlayer dielectric layer in the present invention. FIG. 5 is a schematic cross-sectional view of an opening formed in the present invention. FIG. 6 is a schematic cross-sectional view of forming a lower multiple crystal break plug in the present invention. FIG. 7 is a schematic cross-sectional view of a bit line structure formed in the present invention. FIG. 8 is a schematic cross-sectional view of forming a oxynitride layer in the present invention. FIG. 9 is a schematic cross-sectional view of an opening formed in the present invention. FIG. 10 is a schematic cross-sectional view of forming an upper polycrystalline silicon plug in the present invention. FIG. 11 is a schematic cross-sectional view of a capacitor window formed in the present invention. FIG. 12 is a schematic cross-sectional view of forming a polycrystalline silicon layer in the present invention. Fig. 13 is a schematic sectional view of a capacitor lower electrode plate formed in the present invention. FIG. 14 is a schematic cross-sectional view of removing a silicon oxide layer in the present invention. FIG. 15 is a schematic sectional view of a completed capacitor structure in the present invention. Description of figure number: 2 field silicon oxide layer 4 polycrystalline silicon layer 6 dielectric layer 8 gate structure 10 gate structure 12 gate structure M lightly doped source / drain region ------------ -• Equipment -------- Order · (Please read the precautions on the back before filling in this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperative, 1 Semiconductor substrate 3 Gate dielectric layer 5 Metal silicide Layer 7 gate structure. 9 gate structure 11 gate structure 13 gate structure
297公釐） 424324 A7 五 發明說明（b) 15氮化矽間隙壁 17第一層間介電層 19光阻 21下複晶矽插塞 23下複晶矽插塞 25下複晶矽插塞 27位元線接觸窗 29第四層間介電層層 31光阻 33開口 35上複晶矽插塞 37上複晶矽插塞 39光阻 41複晶梦層 43電容器上電極板 16源極/汲極區 18第二層間介電層 20開口 22下複晶矽插塞 下複晶矽插塞 26第三層間介電層層 28位元線結構 3〇氮氧化矽層 32開口 34開口 36上複晶梦插塞 38介電層 4〇電容器窗口 42電容器介電層 44電容器結構 ------------裝 ----1 訂- • r (請先閱讀背面之注意事項再填寫本頁) 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 本發明係揭露-種形成魏㈣存節職構之動態隨 機存取A’ft體上電容㈣方法。本發明的特徵為糊電蒙银 刻技術在-層氧切層上職電容關口時，存在—層氣氧 化石夕層做為_終止層。本實蘭仙N通道元件做為動態 隨機存取si’ff體元件的傳遞閘極電晶體。然而，本發明亦可 被應用於由P通道傳遞_電晶體所組成_態隨機存取記 憶體記憶單元。 首先請參考圖一，本實施例使用具有<1〇〇>晶向之p型 本紙張尺度翻巾 經濟部智慧財產局員工消費合作社印«']衣 4^4324 " A7 ------- B7__ 五、發明說明（^ ) 半導體基板1。做為隔離用途之場氧化矽層（F0X)2係以熱氧 化製程所形成，在該熱氧化製程中係使用經刻劃的氮化矽一 氧化發複合介電層做為抗氧化罩幕，以保護主動元件區不被 乳化。此外’亦可使用淺渠溝隔離(Shaii〇wTrench Isolation; STI)做為隔離各元件之用。在形成厚度介於2000至5000A 之間的場氧化矽層2之後，使用熱磷酸移除所述氮化矽層並 以緩衝氫氟酸移除底下的氧化矽層。在一連串的清洗後，以 熱氧化法形成閘極介電層3。所述閘極介電層3係一層氧化 矽層，於氧氣環境中以750至1050eC的溫度進行熱氧化製 程所形成’其厚度介於40至200A之間。接下來請參考圖 一 ’利用低壓化學氣相沉積法(Low Pressure Chemical Vapor Deposition; LPCVD)在介於500至70(TC的溫度下形成一 層複晶石夕層4，其厚度介於500至3000 A之間。所述複晶 矽層4的摻雜有兩種方法，其中之一係以砷或磷摻入反應氣 體石夕烧(Silane)中’使神或磷與矽同步沉積；另一方法係先 沉積一本質複晶矽層’再以離子佈植的技術將砷或磷摻雜入 該複晶石夕層内。所述離子佈植的的植入能量介於1〇至8〇KeV 之間’其植入濃度介於1E13至1E16離子/平方公分之間。 接下來’使用矽烷與六氟化鎢做為反應氣體，利用低壓化學 氣相沉積法沉積一厚度介於500至3000人之金屬矽化物層 5。所述金屬矽化物層5係一層矽化鎢層，與其下方的複晶 石夕層4構成複晶石夕金屬層（p〇lycide Layer)。其次，以低壓 化學氣相沉積法或電漿輔助式化學氣相沉積法（Plasma Enhanced Chemical Vapor Deposition; PECVD)形成一介電 8 ----------丨-裝--------訂- (請先閱讀背面之泫意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 «297公釐） 424324 * A7 ---—--- B7_______ 五、發明說明（$ ) 層6，以做為閘極結構的頂蓋。所述介電層6係一層氤化矽 層，其厚度介於600至2〇〇〇人之間。接著利用傳統的微影 以及反應式離子蝕刻技術’形成具氮化矽頂蓋的閘極結構 7-13 ’如圖二所示。所述反應式離子蝕刻技術係利用C{^做 為介電層6的蝕刻反應物質，並使用Cl2做為金屬矽化物層 5與複晶矽層4的蝕刻反應物質。接下來以電漿氧氣灰化法 及濕式清洗法’進行光阻的移除。 接下來’利用離子佈植技術形成淡摻雜源極/沒極區 (Lightly Doped Drain/Source; LDD)14。所述離子佈植技 經濟部智慧財產局員工消費合作社印製 ------- - - - 1·裝 i I ! i — I 訂· (請先閱讀背面之注意事項再填寫本頁) 術係楂入磷離子，其植入能量介於5至60KeV之間，其植入 劑量介於1E13至1E15離子/平方公分之間。後續，在所述 具氣化石夕頂蓋之閘極結構7-13的側壁上形成氮化石夕間隙壁 (Mitride Spacer)15。所述形成氮化矽間隙壁15的方法， 係先在介於400至850t之間的溫度下，以低壓化學氣相沉 積法或電漿增強式化學氣相沉積法形成由氣化梦所組成之厚 度介於1500至4000A的介電層，接著以CF4做為蝕刻物質 進行非等向性反應性離子蝕刻製程以形成氮化矽間隙壁 15。接下來’利用離子佈植技術形成源極/沒極區丨6。所述 離子佈植技術係植入砷離子，其植入能量介於3〇至i〇〇KeV 之間，其植入劑量介於1E14至5E16離子/平方公分之間， 如圖三所示。 接下來’使用低壓化學氣相沉積法或電漿增強式化學 氣相沉積法形成一層由硼磷矽酸鹽玻璃(BPSG)所組成之厚度 介於2000至8000A的第一層間介電層（inkrievei 9 ^紙張尺度適用>國國家標準（CNS)A1規格(2〗〇χ"297公釐厂 --- 在24324 A7 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（y)297 mm) 424324 A7 Five invention descriptions (b) 15 silicon nitride spacer 17 first interlayer dielectric layer 19 photoresistor 21 polycrystalline silicon plug 23 polycrystalline silicon plug 25 polycrystalline silicon plug 27-bit line contact window 29 Fourth interlayer dielectric layer 31 Photoresist 33 Opening 35 on polycrystalline silicon plug 37 on polycrystalline silicon plug 39 photoresist 41 polycrystalline dream layer 43 capacitor upper electrode plate 16 source / Drain region 18 second interlayer dielectric layer 20 opening 22 polycrystalline silicon plug under polycrystalline silicon plug 26 third interlayer dielectric layer layer 28 bit line structure 30 silicon oxide layer 32 opening 34 opening 36 Polycrystalline dream plug 38 dielectric layer 40 capacitor window 42 capacitor dielectric layer 44 capacitor structure ------------ install ---- 1 order-• r (Please read the note on the back first Please fill in this page again) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics This invention discloses a dynamic random access A'ft body capacitor method that forms the Weiji Cunjie structure. The feature of the present invention is that when the paste-silver masking technology is used at the -capacitor barrier of the -layer oxygen-cutting layer, the -layer gas-oxidized fossil layer is used as the _stop layer. The real Lanxian N-channel element is used as a pass gate transistor for a dynamic random access si'ff body element. However, the present invention can also be applied to a random access memory cell composed of a P-channel transfer transistor. First, please refer to FIG. 1. In this embodiment, a p-type paper with a crystal orientation of < 1OO > is used. The paper is turned over. The print is printed on the employee ’s cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. ---- B7__ 5. Description of the invention (^) Semiconductor substrate 1. The field silicon oxide layer (F0X) 2 used for isolation is formed by a thermal oxidation process. In this thermal oxidation process, a etched silicon nitride oxide composite dielectric layer is used as an anti-oxidation mask. To protect the active element area from being emulsified. In addition, you can also use shallow trench isolation (STI) as an isolation device. After the field silicon oxide layer 2 having a thickness between 2000 and 5000 A is formed, the silicon nitride layer is removed using hot phosphoric acid and the underlying silicon oxide layer is removed with buffered hydrofluoric acid. After a series of cleaning, the gate dielectric layer 3 is formed by a thermal oxidation method. The gate dielectric layer 3 is a silicon oxide layer, which is formed by performing a thermal oxidation process at a temperature of 750 to 1050eC in an oxygen environment, and has a thickness between 40 and 200A. Next, please refer to FIG. 1 'using a Low Pressure Chemical Vapor Deposition (LPCVD) method to form a polycrystalline spar layer 4 at a temperature of 500 to 70 (TC), and a thickness of 500 to 3000 Between A. There are two methods for doping the polycrystalline silicon layer 4, one of which is doping arsenic or phosphorus into the reactive gas Silane to 'synchronously deposit the god or phosphorus and silicon; the other The method is to deposit an essential polycrystalline silicon layer first, and then dope the arsenic or phosphorus into the polycrystalline stone layer by an ion implantation technique. The implantation energy of the ion implantation is between 10 and 80. Between KeV ', the implantation concentration is between 1E13 and 1E16 ions / cm 2. Next, using silane and tungsten hexafluoride as the reaction gases, a low pressure chemical vapor deposition method is used to deposit a thickness of 500 to 3000. Human metal silicide layer 5. The metal silicide layer 5 is a tungsten silicide layer, and the polycrystalline stone layer 4 below it constitutes a polycrystalline silicon metal layer (pOlycide Layer). Secondly, a low-pressure chemical gas is used. Phase deposition or plasma-assisted chemical vapor deposition (Plasma Enhanced Chemical V apor Deposition; PECVD) to form a dielectric 8 ---------- 丨 -install -------- order- (please read the intention on the back before filling this page) This paper size Applicable to China National Standard (CNS) A4 specification (210 «297 mm) 424324 * A7 -------- B7_______ V. Description of the invention ($) Layer 6 is used as the top cover of the gate structure. The electrical layer 6 is a silicon oxide layer with a thickness between 600 and 2000 people. Then, the traditional lithography and reactive ion etching techniques are used to form a gate structure with a silicon nitride cap 7- 13 'as shown in Figure 2. The reactive ion etching technology uses C {^ as an etching reaction material for the dielectric layer 6, and uses Cl2 as an etching reaction for the metal silicide layer 5 and the polycrystalline silicon layer 4. Substances. The photoresist is removed by plasma oxygen ashing and wet cleaning. Next, lightly doped drain / source (LDD) is formed by ion implantation. ) 14. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics of Ion Planting Technology ------------1 · Install i I! I — I Order · (Please read the note on the back first Please fill in this page again) The implantation energy of the hawthorn system is between 5 and 60KeV, and the implantation dose is between 1E13 and 1E15 ions / cm 2. A nitride nitride spacer (Mitride Spacer) 15 is formed on a side wall of the gate structure 7-13 of the top cover. The method for forming the silicon nitride spacer wall 15 is firstly formed by a low-pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method at a temperature between 400 and 850 t. A dielectric layer having a thickness of 1500 to 4000 A is then subjected to an anisotropic reactive ion etching process using CF4 as an etching substance to form a silicon nitride spacer 15. The next step is to use the ion implantation technique to form source / dead regions. The ion implantation technology is implanted with arsenic ions, the implantation energy is between 30 and 100 KeV, and the implantation dose is between 1E14 and 5E16 ions / cm 2, as shown in FIG. 3. Next, a low-pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method is used to form a first interlayer dielectric layer composed of borophosphosilicate glass (BPSG) with a thickness of 2000 to 8000 A ( inkrievei 9 ^ Paper size applicable> National Standard (CNS) A1 Specification (2〗 〇χ " 297 mm factory --- printed on 24324 A7 Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative B. V. Description of the invention (y)
Dielectric; ILD)17。所述第一層間介電層係在添加二硼烷 與鱗化氫至四乙基正矽酸鹽(TEOS)的環境中所形成，因而含 有介於0. 5至3. 0重量百分比的B2〇3以及0. 5至3. 0重量百 分比的P205。接著利用化學機械研磨法(CMP)進行平坦化處 理’而形成平坦的第一層間介電層17，如圖四所示。其次， 再度以先前形成第一層間介電層17所使用之相同濃度的二 硼烷與磷化氫及四乙基正矽酸鹽，藉由低壓化學氣相沉積法 或電漿增強式化學氣相沉積法製程形成一層厚度介於1〇〇〇 至3000A的第二層間介電層18，所述第二層間介電層18亦 由硼磷矽酸鹽玻璃所絚成。其次，使用光阻丨9做為罩幕， 利用選擇性非等向性離子蝕刻製程在所述第二層間介電層 18與第一層間介電層17上形成開口 2〇。所述開口 2〇係形 成於閘極結構7-13之間’並裸露出源極/汲極區丨6的頂部 表面。 藉由氮化石夕介電層6與氮化石夕間'壁15抵抗CHp3選擇 性反應性離子餘刻製程的能力，所形成 具氣化石夕頂蓋之閑極結構之間的空間為大。此舉可 置於開〇 20中的複晶石夕插塞自行對準於該具氮化石夕頂蓋之 閘極結構，如圖五所示。 以電裂氧氣灰化及濕式清洗法移除光阻後，藉由低 塵化學氣相沉積法製程軸—層複晶齋其厚度介於勘〇 =_A之間’並於沉積期間添加坤或碟化氫至魏環境 雜’以完成填充開口2〇。藉由化學機械研 磨製程或使用Cl2做為姓刻物質的登 貝α選擇性反應性離子蝕刻製 10 k紙張尺度適用中國國家標準(CNS)A4^ (21〇 X 297^7 --------^----!裝-------—訂- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 424324 * Α7 ____Β7 _五、發明說明（卩） 程，自第二層間介電層18之上表面移除所不欲的複晶矽， 而於開口 20中形成下複晶矽插塞21-25，如圖六所示。下 複晶矽插塞21及下複晶矽插塞24將於後續被使用為上層之 位元線結構與下層源極/汲極區之間的接觸；而下複晶矽插 塞22, 23,25將被使用為儲存節點接觸結構的元件，而允許 後續上層電容器結構與下層源極/汲極區之間的接觸。接著 以使用二硼烷、填化氫及四乙基正矽酸鹽的低壓化學氣相沉 積法或電漿增強式化學氣相沉積法製程形成一層厚度介於 1000至3000Α之間的第三層間介電層26 (亦由棚攝石夕酸鹽 玻璃所組成）’其包含介於0.5至3.0重量百分比的β2〇3以 及介於0_ 5至3. 0重量百分比的ρ2〇5。 接下來利用傳統的微影與反應性離子蝕刻技術在所述 第三層間介電層26上開啟位元線接觸窗27a，27b，並分別 裸露出下複晶矽插塞21，24的頂部表面。所述反應性離子蝕 刻係利用CHF3做為反應氣體。 以電漿氧氣灰化及濕式清洗法移除開啟位元線接觸窗 所用的光阻後，以六氟化鎢及矽烷做為反應物質，利用低壓 化學氣相沉積法製程沉積一矽化鎢層至介於〗〇⑽至 之間的厚度，以完全填充位元線接觸窗27a，27b。再利用傳 統的微影與反應性離子餘刻技術’分別在所述啟位元線接觸 窗27a, 27b内形成位元線結構28a，28b，並分別接觸下複 曰曰發插塞21，24的頂部表面，如圖七所述。所述反應性離子 蝕刻係利用CL做為反應氣體。最後再以電漿氧氣灰化及濕 式清洗法移除光阻。 - 11 (請先閱讀背面 <注意事項再填寫本頁> •裝 11 I . 111 — — — — — 1 - 本纸張尺度適用中國國家標準（CNS)A1規格⑽χ 297公爱） 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（（/) 接下來，使用電漿增強式化學氣相沉積法或低壓化學 氣相沉積法形成由硼磷矽酸鹽玻璃所組成之第四層間介電層 層29至介於4000至10000A之間的厚度，其係再度使用二 硼烷、磷化氫與TEOS形成包含介於至3.0重量百分比 的Bz〇3與介於〇. 5至3. 0重量百分比的p2〇5之硼碟矽酸鹽玻 璃層《其次’以低壓化學氣相沉積法或電漿增強式化學氣相 》几積法形成一層氣氧化梦層30於所述第四層間介電層層29 的上表面達300至1500A的厚度，如圖八所述。形成所述 氮氧化石夕層30係使用30-60 seem的N20及60-150 seem的Dielectric; ILD) 17. The first interlayer dielectric layer is formed in an environment where diborane and hydrogen chloride are added to tetraethylorthosilicate (TEOS), and therefore contains between 0.5 to 3.0 weight percent of B205 and P205 at 0.5 to 3.0 weight percent. Then, a chemical mechanical polishing method (CMP) is used for planarization 'to form a flat first interlayer dielectric layer 17, as shown in FIG. Secondly, the same concentrations of diborane, phosphine, and tetraethyl orthosilicate used in the formation of the first interlayer dielectric layer 17 were again used by low pressure chemical vapor deposition or plasma enhanced chemistry The vapor deposition process forms a second interlayer dielectric layer 18 having a thickness between 1000 and 3000 A. The second interlayer dielectric layer 18 is also formed of borophosphosilicate glass. Next, a photoresist 9 is used as a mask, and an opening 20 is formed in the second interlayer dielectric layer 18 and the first interlayer dielectric layer 17 by a selective anisotropic ion etching process. The opening 20 is formed between the gate structures 7-13, and the top surface of the source / drain region 6 is exposed. By virtue of the ability of the nitrided nitride dielectric layer 6 and the nitrided nitride 'wall 15 to resist the selective reactive ion etching process of CHp3, the space between the idler structures with the top of the gasified stone is large. This can be placed in the polycrystalline stone plug in Kai 20 to align itself with the gate structure of the nitrided stone cap, as shown in Figure 5. After removing the photoresist by means of cleavage oxygen ashing and wet cleaning, the process of low-dust chemical vapor deposition is used to process the axis-layer complex crystal, whose thickness is between 〇0 and _A ', and Kun is added during the deposition. Or dish hydrogenated to Wei's environment to complete filling the opening 20. 10 k paper produced by chemical mechanical polishing process or using Denmberg α-selective reactive ion etching using Cl2 as the engraved substance. Applicable to China National Standard (CNS) A4 ^ (21〇X 297 ^ 7 ----- --- ^ ----! Install --------- Order- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 424324 * Α7 ____ Β7 _Fifth, In the process of the invention (ii), unwanted polycrystalline silicon is removed from the upper surface of the second interlayer dielectric layer 18, and lower polycrystalline silicon plugs 21-25 are formed in the opening 20, as shown in FIG. The lower polycrystalline silicon plug 21 and the lower polycrystalline silicon plug 24 will be subsequently used as the contact between the upper bit line structure and the lower source / drain region; and the lower polycrystalline silicon plug 22, 23 , 25 will be used as a component of the storage node contact structure, which allows subsequent contact between the upper capacitor structure and the lower source / drain region. Diborane, hydrogen filling and tetraethyl orthosilicate are then used. Low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition process to form a third interlayer dielectric with a thickness between 1000 and 3000 A 26 (also composed of sparite glass) ′ It contains β 2 0 3 between 0.5 and 3.0 weight percent and ρ 2 05 between 0 5 and 3.0 weight percent. Next, the traditional micro The shadow and reactive ion etching technology opens bit line contact windows 27a and 27b on the third interlayer dielectric layer 26 and exposes the top surfaces of the lower polycrystalline silicon plugs 21 and 24, respectively. The reactive ions The etching system uses CHF3 as the reaction gas. After removing the photoresist used to open the bit line contact window by plasma oxygen ashing and wet cleaning, tungsten hexafluoride and silane are used as the reaction material, and low-pressure chemical gas is used. A phase deposition process is used to deposit a tungsten silicide layer to a thickness of between 0 and 100% to completely fill the bit line contact windows 27a and 27b. Then, the traditional lithography and reactive ion etching techniques are used in The bit line structures 28a, 28b are formed in the open bit line contact windows 27a, 27b, and contact the top surfaces of the plugs 21, 24, respectively, as shown in Figure 7. The reactive ion etching system Use CL as the reaction gas. Finally, plasma oxygen ash And wet cleaning method to remove the photoresist.-11 (Please read the back page < Precautions before filling out this page > • Install 11 I. 111 — — — — — 1-This paper size applies to Chinese National Standard (CNS ) A1 specification ⑽χ 297 public love) A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention ((/) Next, a plasma enhanced chemical vapor deposition method or a low pressure chemical vapor deposition method is used to form The fourth interlayer dielectric layer composed of borophosphosilicate glass has a thickness of 29 to between 4000 and 10000 A. It is again formed by using diborane, phosphine and TEOS to contain Bz〇3 and p2O5 borosilicate glass layer between 0.5 and 3.0 weight percent "Second 'by low pressure chemical vapor deposition or plasma enhanced chemical vapor phase" A gas oxide dream layer 30 is formed on the upper surface of the fourth interlayer dielectric layer 29 to a thickness of 300 to 1500 A, as shown in FIG. To form the oxynitride layer 30 series use 30-60 seem N20 and 60-150 seem
SiH4做為反應物質而獲得，以做為後續钱刻製程的蝕刻終止 層。其次，使用光阻31做為罩幕’使用Cl2做為氮氧化矽 層30的蝕刻物質及使用做為第四層間介電層的 與第三層間介電層層26的蝕刻物質，進行非等向性反應性 離子蝕刻製程，以形成開口 32, 33, 34並裸露出下複晶矽插 塞22, 23, 25的頂部表面，如圖九所示。在以電漿氧氣灰化 法及濕式清洗移除光阻3丨後，接下來於開口 32, 33,34中形 成上複晶矽插塞35,36,37。所述形成上複晶矽插塞 35, 36, 37 ’係首先藉由健化學氣相沉積法臟—層複晶珍 層完全填充開口 32, 33, 34,其厚度介於1500至4000Α之間， 在沉積過程並將砷或磷化氫添加至矽烷環境◊接著以化學機 械研磨法或使用CL做為钱刻物質的選擇性反應性離子餘刻 製程由氮氧化石夕層30的頂部表面移除所述複晶矽層，以形 成上層複晶矽插塞35, 36, 37。覆蓋下層複晶矽插塞22, 23,烈 的上層複晶矽插塞35,36,37包含儲存節點接觸結構’其可 12 ,---^----!裝--------訂· (請先閱讀背面之注意事項再填寫本頁) 卜纸張尺度適用令國國家標準（CNS)A4 x 297公找 經濟部智慧財產局員工消費合作社印製 424324 · λ. --------------------------- 五、發明說明（丨>) 使得後續覆蓋在上©的電容躲構射關雜/汲極區接 觸，如圖十所示a 其次’使用健化學氣她積法或電㈣強式化學氣 相沉積法形成由氧切或_魏鹽_層（具有介於〇 5 至3. 0重量百分比的民〇3以及介於〇·5至3 〇重量百分比的 PA)所組成的介電層38’其厚度介於_至15〇〇〇A之間。 形成光阻39 ’做制料等向性反應⑽子_製程(使用 0¾做為蝴物質），麵述介電層38上軸電容關口 4〇 的餘刻罩幕’以裸露出由上複晶碎插塞35,36, 37及下複晶 石夕插塞22’23,25所组成的複晶梦儲存節點接觸结構。利用 ^應性電漿_製程的侧選擇性（其包含—過度侧循 環）’允許在未移除氮氧化石夕層31的情況下，移除所裸露的 介電層38，如圖十-所示。再以電毁氧氣灰化及濕式酬 移除光阻39。 请參考圖十二至圖十四’接下來形成冠狀儲存節點結 構。以健化學氣相沉積法製程沉積一複晶石夕層也，其厚 度)ι於300至1500A之間。該複晶珍層41a在沉積期間藉 由添加碑或峨化氫至石夕域境中以進行即時捧雜。如圖十二 所示，複晶矽層41a被保形地沉積於介電層38之頂部表面 $所裸露的電容器窗口 4〇表面上，且複晶石夕層41a沉積於 電容器窗口 40底部，因而覆蓋在所述氮氧化石夕層30的上方 ，與上複晶矽插塞接觸。接下來進行化學機械研磨製程，自 "電層38之頂部表面移除複晶石夕層41a，以形成置於電容 器開口 4G中的冠狀儲存節點結構41b;而各冠狀儲存節點 本紙^緖準（CNS)A4祕⑵ t請先閲讀背面之注意事項再填寫本頁) —裝--------訂----------f* A7 ---SZ___ 五、發明說明（p) 、、’。構包含位於電容器開口 4〇邊緣上以及與位於電容器開口 4〇底部的水平複晶;ε夕部份連接的垂直複晶梦部份，而該水 平複晶石夕部份將覆蓋在氣氧化石夕層3〇上並與上複晶石夕插塞 的頂部表面接觸，如圖十三所示。接下來請參考圖十四，使 ，緩衝氫驗溶液選擇性地移除介電層38。無法溶於緩衝 氩氟酸溶液中之氮氧化石夕層30將保護底下的第四層間介電 層29 ’因而不裸露出位元線結構，且不會造成冠狀儲存節 點結構底切(Undercut)現象的發生。 請參考圖十五’接下來將形成以冠狀健存節點結構為 特徵的動態隨機存取記憶體之電容器結構。在該冠狀儲存節 點結構41b上形成諸如ΟΝΟ (經氡化的-氮化矽_氧化矽）等 具有兩介電常數的電容器介電層42。該電容器介電層42的 形成係藉由首先形成一層二氧化矽層於該複晶矽冠狀儲存節 點結構上，其厚度介於10至50Α之間，並接著沉積一個厚 度介於10至60Α之間的氤化石夕層，再進行一個熱氧化步驟， 在所述I彳匕矽層之上再形成一層氧化矽層，其等效厚度介於 40至80Α之間’如圊十五所示。其次，以低壓化學氣相沉 積法形成一層複晶矽層，其厚度介於1000至2000α之間。 藉由在沉積期間添加砷或磷化氫至矽燒或二矽烧環境中，以 進行即日守摻雜。藉由微影及反應性離子钕刻製程形成複晶石夕 上電極板43，而完成動態隨機存取記憶體電容器結構的 製程，如圖十五所示。再度藉由電漿氧氣灰化及濕式清洗將 光阻移除。 雖然本發明已被特別地揭示並參考其較佳實施例而被 14 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) ------ f請先閲讀背面之>i意事項再填寫本頁) 裝-----I--訂 - -----!^ 經濟部智慧財產局員工消費合作求印製 ^24324 A7 _B7_ 五、發明說明（丨f) 說明’然而應為熟習本技藝之人士所瞭解的是各種形式與細 節的改變將可於不背離本發明之精神與範疇下為之。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製SiH4 is obtained as a reactive material, and is used as an etching stop layer for a subsequent coining process. Secondly, using photoresist 31 as a mask, using Cl2 as the etching material of the silicon oxynitride layer 30, and using the etching material as the fourth interlayer dielectric layer and the third interlayer dielectric layer layer 26, etc. Anisotropic reactive ion etching process to form openings 32, 33, 34 and expose the top surfaces of the lower polycrystalline silicon plugs 22, 23, 25, as shown in FIG. After removing the photoresist 3 by the plasma oxygen ashing method and wet cleaning, an upper polycrystalline silicon plug 35, 36, 37 is formed in the openings 32, 33, 34. The formation of the upper polycrystalline silicon plug 35, 36, 37 is firstly filled with the openings 32, 33, and 34 by a dirty-layer polycrystalline layer with a chemical vapor deposition method, and the thickness is between 1500 and 4000 A. During the deposition process, arsenic or phosphine is added to the silane environment. Then, a chemical reactive polishing method or a selective reactive ion post-etching process using CL as a money engraving material is moved from the top surface of the oxynitride layer 30. The polycrystalline silicon layer is removed to form upper polycrystalline silicon plugs 35, 36, 37. Covering the lower polycrystalline silicon plugs 22, 23, and the fierce upper polycrystalline silicon plugs 35, 36, 37 contain the storage node contact structure, which can be 12, --- ^ ----! --Order. (Please read the notes on the back before filling this page.) Paper size is applicable to the national standard of the country (CNS) A4 x 297. Printed at the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative. 324324 · λ.- ------------------------- V. Description of the invention (丨 >) Make the subsequent capacitors dodge the structure / drain electrodes covered by © Area contact, as shown in Fig. 10a Secondly, the formation of an oxygen-cutting or _wei salt_ layer (having a range of 0 to 3.0 weight percent) is formed by using a chemical chemical gas deposition method or an electro-enhanced chemical vapor deposition method. The thickness of the dielectric layer 38 ′ composed of Zn (3) and PA (0.5 to 30% by weight) is between ˜150,000A. Formation of photoresist 39 'Isotropic reaction process for making materials _ process (using 0¾ as butterfly material), describing the remaining mask of the axis capacitance barrier 40 on the dielectric layer 38' to expose the compound crystal from the top The contact structure of the polycrystalline dream storage node composed of the broken plugs 35, 36, 37 and the lower polycrystalline plugs 22'23,25. The use of side-selective plasma_process side selectivity (which includes-excessive side cycle) 'allows the exposed dielectric layer 38 to be removed without removing the oxynitride layer 31, as shown in Figure 10- As shown. The photoresist 39 was removed by ashing and wet oxidizing with electrical destruction. Please refer to FIG. 12 to FIG. 14 'to form a crown storage node structure next. A polycrystalline spar layer is also deposited by a chemical vapor deposition process, and its thickness is between 300 and 1500A. During the deposition, the compound crystal layer 41a is added to the stone evening realm by adding steles or elder hydrogen for immediate inclusion. As shown in FIG. 12, the polycrystalline silicon layer 41a is deposited conformally on the surface of the capacitor window 40 exposed by the top surface $ of the dielectric layer 38, and the polycrystalline silicon layer 41a is deposited on the bottom of the capacitor window 40. Therefore, it is covered above the oxynitride layer 30 and is in contact with the upper polycrystalline silicon plug. Next, a chemical mechanical polishing process is performed, and the polycrystalline stone layer 41a is removed from the top surface of the "electrical layer 38" to form a crown storage node structure 41b placed in the capacitor opening 4G. (CNS) Secret of A4 t Please read the notes on the back before filling this page) —Installation -------- Order ---------- f * A7 --- SZ___ V. Invention Explanation (p), '. The structure includes a horizontal polycrystal located on the edge of the capacitor opening 40 and a horizontal polycrystal located on the bottom of the capacitor opening 40; a vertical polycrystalline dream portion connected to the epsilon portion, and the horizontal polycrystalline stone portion will be covered with a gas oxide stone The upper layer 30 is in contact with the top surface of the upper polyspar plug, as shown in FIG. 13. Next, please refer to FIG. 14, so that the dielectric layer 38 is selectively removed by the buffer hydrogen test solution. The oxynitride layer 30, which cannot be dissolved in the buffered argon fluoride acid solution, will protect the fourth interlayer dielectric layer 29 'underneath, so that the bit line structure is not exposed, and the undercut of the crown storage node structure is not caused The occurrence of the phenomenon. Please refer to FIG. 15 '. Next, a capacitor structure of a dynamic random access memory which is characterized by a coronal node structure will be formed. A capacitor dielectric layer 42 having two dielectric constants, such as ONO (fluorinated-silicon nitride-silicon oxide), is formed on the crown-shaped storage node structure 41b. The capacitor dielectric layer 42 is formed by first forming a silicon dioxide layer on the polycrystalline silicon crown-shaped storage node structure with a thickness between 10 and 50 Å, and then depositing a thickness between 10 and 60 Å. Then, a thermal oxidation step is performed, and a silicon oxide layer is further formed on the silicon layer, and its equivalent thickness is between 40 and 80A, as shown in Figure 15. Second, a low-pressure chemical vapor deposition method is used to form a polycrystalline silicon layer with a thickness between 1000 and 2000α. Immediately doped by adding arsenic or phosphine to the silicon-fired or silicon-fired environment during deposition. The lithography and reactive ion neodymium etching process is used to form the polycrystalline stone upper electrode plate 43 to complete the process of the dynamic random access memory capacitor structure, as shown in Figure 15. The photoresist was removed again by plasma oxygen ashing and wet cleaning. Although the present invention has been specifically disclosed and referenced to its preferred embodiment, the paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) paper size. ------ f Please read the back & gt (I will fill in this page again for matters of interest) Packing ----- I--Order- -----! ^ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs for consumer cooperation printing ^ 24324 A7 _B7_ V. Description of the invention (丨 f) Explanation 'However, it should be understood by those skilled in the art that various changes in form and detail can be made without departing from the spirit and scope of the present invention. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
5 I 本紙張尺度適用中國國家標準（CNS)A4規烙（210 x 297公釐）5 I This paper size applies to Chinese National Standard (CNS) A4 (210 x 297 mm)