TW424313B - Structure of semiconductor chip package - Google Patents

Abstract

A structure of semiconductor chip package mainly comprises a semiconductor chip loaded on a lead frame having a ground ring essentially separated from the bearing seat of the chip and in a flying off design. The lead frame comprises a plurality of lead wires surrounding the ground ring and a chip bearing seat designed in the ground ring. The semiconductor chip is mounted on the chip bearing seat, and electrically connected to a plurality of lead wires of the lead frame through a plurality of connection wires, and a predetermined region of the ground ring. The lead frame, the semiconductor chip and the plurality of connection wires are encapsulated by an encapsulant. Since the ground ring is essentially separated from the chip bearing seat and of a flying off design, when the semiconductor chip is fixed to the chip bearing seat of the lead frame by using a die attach, the die attach will not contaminate the predetermined region of the ground ring. Furthermore, the connection wires used for grounding, when performing wire bonding, has a larger processing window.

Description

[Field of the Invention] The present invention relates to a semiconductor wafer package structure and a manufacturing method thereof, and it is particularly related to a lead frame having a ground ring (grund) that is substantially separated from the wafer holder and is flying off. ring) to provide power and ground. [Prior Art] The Gadi diagram is a conventional semiconductor chip package structure, which includes a lead frame to carry a chip 10 ◦. The lead frame includes a plurality of leads having outer leads (portion) 106 and an inner leg (107). The wafer 100 is adhered and fixed to a wafer holder ⑴ by a die attach such as silver glue m, which is connected to the lead frame with a plurality of swept ribs (not shown). The outer legs 10 6 of the thread stand are electrically connected to an external circuit. The wafer i 〇 has a plurality of wafer pads which are electrically connected to the inner leg 107 of the wire selection frame and the predetermined area of the wafer socket 丨 j by using bonding wires 115 and 116? The wafer 100, the wafer holder 1 Π, the inner leg portion io 7 of the lead frame, and the plurality of connecting wires 1 15 and Π 6 are covered with a piece of gel 11 7. The sealing compound 7 is made of an insulating material such as epoxy resin. The second figure is a conventional non-lead semiconductor package structure, which generally includes a chip 210 that is fixed to a lead frame by a die attach 2 such as silver glue 2 1 2 2 〇. The chip 2} is electrically connected to a plurality of wires 23 of the lead frame and a predetermined area of the s-Xuan chip holder 2 2 0 by using the connecting wires 240 and 242. The wafer 2 10 and the lead frame are covered with a piece of gel 2 50, so that the lower surface of the lead frame is exposed to the sealant ’, so the heat generated by the semiconductor wafer during normal operation can be directly

P99-05 丨, ptc page 5 η correction a No. 88117 evil 0 V. Description of the invention (2) It is transmitted through the chip holder 220 of the lead frame of the Hai wire, so that the external lead-free half-body package structure can be improved. Of heat dissipation efficiency. : 1 2 The above-mentioned conventional package structure is used to connect the plurality of wires to the semiconductor wafer's wheel-in or output pad (receiving 〇 called

Pads), and the pre-set area of the chip holder is used to provide the voltage J, (s0urce v〇ltage) and the ground potential (grund). The voltage source and ground potential can be set at any place via the chip holder. The location provides a supply route that can shrink the voltage source and ground potential, thereby suppressing power supply noise and increasing the speed of the wafer. However, when a large-sized semiconductor wafer is mounted on the wafer holder of the lead frame, the i-crystal = Adhesive material easily spills around the wafer and contaminates the pre-set areas of the wafer holder for voltage, voltage source, and ground potential. Therefore, it is often necessary to use a time-consuming plasma before wire bonding. [Plasma clean] process to deal with the contaminated area on the wafer holder [Summary of the Invention] · f :: '. R The main purpose of the present invention is to provide a semiconductor wafer package structure which mainly includes a lead frame with a wafer carrier The base is roughly separated and has a high ground ring (ground ring), which is used to provide power and ground f. When a semiconductor wafer is fixed to it with a wafer adhesive substance When the lead frame aa chip holder is seated, 'the wafer adhesion material will not contaminate the ground ring.' With the secondary purpose of the present invention, a semiconductor chip package structure is provided, which mainly includes a lead frame with a high position (flying). ff) The grounding net; when the wire for grounding is wired (wire bonding), there is a working space of f, and the reliability of the wire for grounding (^ liability) is increased. In addition the flyin ^ off ground gauge

P99-05Lptc Page 6 Amendment No. 881 丨 7πη V. Description of the invention (3) Shorten the span of the connecting line (w 丨 re s p a η) for grounding and improve the problem of the strike line (w i r e s w e e ρ) generated during the win. The semiconductor chip package structure according to the present invention mainly includes a lead frame, a semiconductor wafer, and a colloid. The lead frame includes a plurality of wires, a wafer holder, and a ground ring. The ground ring is provided immediately adjacent to the periphery of the wafer holder and the plurality of wires surround the ground ring. The semiconductor wafer is fixed on the wafer holder. The semiconductor wafer has a plurality of wafer pads, which are electrically connected to a plurality of wires of the lead frame and a predetermined area of the ground ring through a plurality of connecting wires. The sealing compound covers the leadframe 'semiconductor chip and a plurality of connecting wires, so that at least a part of the plurality of wires of the leadframe is exposed to the sealing compound for electrical connection with the outside. Since the ground ring is substantially separated from the wafer holder, when the semiconductor wafer is fixed to the wafer holder of the lead frame with a wafer adhesive substance, the wafer adhesive substance does not contaminate the ground ring. Furthermore, the ground ring of the lead frame according to the present invention is elevated (f yi: 0 fo, so that it is higher than and parallel to the horizontal plane where the plurality of wires and the wafer holder t are located. Because the ground ring is higher than The chip holder can shorten the wire span for grounding, thereby improving the wire sweep problem caused by sealing. In addition, the grounding ring is elevated to make the car parent It is close to the horizontal plane where the semiconductor wafer is located, so when the connection wire for grounding is wired (wireb ο n ci, ing), it has a larger work iH (processing window) 'and increases the connection wire for grounding. Reliability. The present invention further provides a method for manufacturing a semiconductor chip package structure, which includes the following steps: (A) providing a lead frame including a plurality of wires,

P99.051.ptc Page 7

P99-051.ptc Page 8

Case No. 88117350 V. Description of the invention (5) The end of the ring 3 3 0 and the connecting bar 3 5 0 are punched and pressed to form a flying off region, thereby making the ground ring 33 3. Above and parallel to the horizontal plane where the plurality of wires and the crystal moon bearing are located (refer to the fifth figure). 0. According to the lead frame of the present invention, the inner end of the plurality of wires and a predetermined area for the ground ring to be grounded may be A conventional method is used to plate a layer of metal (such as gold or silver) with good bonding with the conventional bonding wire material. FIG. 6 illustrates a semiconductor wafer structure 500 according to a preferred embodiment of the present invention, which mainly includes a semiconductor wafer 51, which is adhered and fixed to a wafer by a die attach such as silver glue 520 A chip holder 320 of a lead frame 400. It can be understood that although the semiconductor worm chip package structure 500 uses the lead frame 400 as the preferred embodiment, it can also use the lead frame 30 () to carry the semiconductor wafer 510. The semiconductor wafer has a plurality of wafers, which are electrically connected to the rack 400 and the ground ring 3 30 via a plurality of connection wires such as gold wires 530 and 540. The gold wires 5 3 0 and 5 4 0 are respectively connected to the inner end of the wire 31 0 and a predetermined area of the ground-to-earth ring 3 3 0 to the corresponding wafer bonding pads using a conventional wire bonding technology. . The lead frame 400, the semi-conductor wafer 5 1 0, and the plurality of connecting wires 3 1 0 are covered with a piece of gel 5 50, so that the plurality of wires 31 of the lead frame 4 0 are at least partially exposed. The sealing colloid is used to electrically dope with the outside. The encapsulant 5 50 is formed on the wafer and the lead frame using a conventional encapsulation technique such as transfer molding (t r a n s f r r m 0 1 d i n g). The seventh figure reveals an outer-lead-free semiconductor package structure 6 0 0 ′ according to another preferred embodiment of the present invention, which mainly includes a semiconductor wafer 51 〇

Lion P99-051.ptc Page 9 Amendment Case No. 88117350 V. Description of the Invention (6) A die attach, such as silver glue 520, is fixed to a wafer holder 320 of a lead frame 400. It can be understood that although the semiconductor chip packaging structure 600 uses the lead frame 400 as a preferred embodiment, it can also use the lead frame 300 to carry the semiconductor wafer 510. The semiconductor wafer has a plurality of wafer pads, which are electrically connected to the lead frame 40 0 and the ground ring 330 by a plurality of connection wires such as gold wires 530 and 540. The outer-lead-free semiconductor package structure 600 is characterized in that the lead frame 400, the semiconductor wafer 51, and the plurality of connection lines 530 and 540 are covered with a single gel 56 to make the lead frame 400 The lower surface is exposed to the encapsulant 56 (). In addition, during the singulation process, the plurality of wires 31 are trimmed along the edge of the encapsulant 560 so that it is in contact with the encapsulant 560. The edges of the sealing compound are cut in line. According to the outer-lead semiconductor package structure 600 according to the present invention, during the molding process, 'because the ground ring 33 is slightly higher than the wafer holder 320, 'Therefore, it is possible to slow down the speed of molding low and make it difficult for plastics to form flashes under the wafer carrier. The outer-lead-free semiconductor package structure 600, which can Similar to other leadless devices, it is mounted on a substrate, such as a printed circuit board. The printed circuit board can be screen printed with solder paste to correspond to the semiconductor chip package structure 6 〇〇 of the bottom Conductor circular pattern (pa 11 er η). Then the package structure 600 is placed on the printed circuit board and re-soldered. It can be understood that the conductor 31 exposed at the bottom of the package structure 600 is also It can be printed with solder paste and then mounted on the substrate. Since the non-lead semiconductor package structure 6 0 0 is designed as a single-sided seal (sing 1 esidem ο 1 ding), the

P99-051, ptc Case No. 881Ι7πη Rev. 5 'Description of the Invention (7) The heat generated by the normal operation of the semiconductor wafer 5 1 0 can be directly transmitted through the wafer holder 3 2 0 of the lead frame 4 0 0, This can promote heat to be quickly dissipated from the chip, thereby improving the heat dissipation efficiency of the package structure. In the aforementioned package structure, the plurality of guides are used to connect to the input or output of the semiconductor chip. pad s) 'The preset area of the ground ring is used to provide a source voltage and a ground potential. Since the voltage source and the ground potential can be provided at any position via the ground ring, the supply route of the voltage source and the ground potential can be shortened, thereby suppressing noise and increasing the operating speed of the chip. And when a large-sized semiconductor wafer is mounted on a wafer holder of a lead frame using a wafer adhesive substance, 'because the ground ring for grounding is roughly separated from the wafer holder', the wafer adhesive substance will not contaminate the The grounding ring is used to ground a predetermined area. Therefore, before performing wiring (w i r e b ο n d i n g), no time-consuming plasma cleaning (P 1 a s m a c 1 e a η) process is required to process the ground ring for grounding. In addition, the H-ring connection of the lead frame according to the present invention is higher than the chip holder, so the wire span for connecting the ground can be shortened, thereby improving the wire resilience generated during sealing. sweep) problem. Furthermore, because the ground ring is placed southward to make it closer to the horizontal plane where the semiconductor wafer is located, the connection wire for grounding is advanced, and wire bonding (}) has a larger working space. window), and increase the reliability of the connection line for grounding (re 1 i ab U i ty). Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention, anyone familiar with this technology Without departing from the spirit of the invention and

Page 11 P99-05Lptc Amendment No. 88117350 5. Various changes and modifications can be made within the scope of the description of the invention (8). Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. .

i ιβι ill P99-05I.ptc Page 12 Case No. 881173 ^ Simple description of the revised drawing for the year and month [Illustration] Figure 1 Figure 2 Figure 3 Figure 4 Figure 4 Cross section of the conventional semiconductor chip package structure 圊A cross-sectional view of a conventional non-lead semiconductor package structure; a top view of a lead frame according to a preferred embodiment of the present invention; a top view of a lead frame according to another preferred embodiment of the present invention; FIG. 6 is an enlarged perspective view of a wafer holder and a ground ring of a guide frame; FIG. 6 is a cross-sectional view of a semiconductor wafer package structure according to a preferred embodiment of the present invention; and circle 7 is another preferred implementation according to the present invention Cross-sectional view of a handleless outer-lead semiconductor package structure. [Illustration of the drawing number 100 chip 106 outer leg 107 111 chip holder 114 silver glue 115 116 connecting wire 117 sealing gel 210 chip 212 silver glue 220 230 wire 240 gold wire 242 250 sealing gel 300 lead frame 310 wire 1J, '320 3 ^ 0 Ground ring 340 Sweeping rib 350 400 Lead frame 500 Semiconductor chip package structure j 510 520 Silver glue 530 Gold wire 540

P99-051.ptc Page 14

Claims (1)

6. Scope of patent application 1. A semiconductor wafer sealing structure including: a lead frame, which includes a plurality of wires, a wafer holder and a ground ring, the ground ring is adjacent to the periphery of the wafer holder; It is set apart from the wafer carrier ft and the plurality of wires are surrounding the ground ring, and the ground socket is south of the wafer socket;-…: a semiconductor wafer is fixed on the wafer socket, and the semiconductor wafer has A plurality of chip bonding pads; a plurality of connection wires electrically connecting the plurality of wires and pads, and the ground ring and the chip bonding pads; and a wire, ί?: 1f 5 Hai lead frame, semiconductor wafer, and a plurality of connection uses ^ The multiple wires of the toilet I are at least partially exposed to the sealed body for electrical connection with the outside. 2. According to the scope of application for patent No. 1 ^ ^ ^ ^. 1 + conductor chip package structure, in which part of the plurality of wires is extended outside the sealing compound. ^ 3. According to the first patent application scope Ig · '· The lead frame contains several support # rib # / guide f chip package structure * where α ^ ^ ^ ^ ^ m ribs are used to connect the ground ring and lead frame' and Several connecting bars are used to connect the ground ring and the chip holder. The semi-conductor wafer encapsulation structure surrounding item 1, wherein-a layer of metal, wherein the area of the metal-based conductor wafer is plated.糸 selected from a group of gold and silver $ 15 pages ^ W > I} No. 88117350 January ___ Sixth, the scope of the patent application will connect a plurality of connecting wires to the plurality of wires and the wafer pads' and the ground ring and the wafer pads; and the lead frame, semiconductors The chip and the plurality of connection lines are covered with a gel. , t ilk P99-051, p (c p.17