Γ 4 2 3 ο 6 Ο Α7 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（1 ) 發明背景 1. 發明領域 本發明係有關微電子裝置’尤係有關平面M〇SFET裝置 及該裝置之製造方法。 2. 背景技術 圖1所示之傳統MOSFET結構包含在一半導體基材1〇中 之n+或p-摻雜之深接面（12)及（14)，且該半導體基材具有 自源極區（24)及汲極區（26)延伸的淺延伸區（12A)及（14B) 。一閘極區包含在矽化物（18)中之一多晶矽閘電極（16)，且 石夕化物（1 8)係配置在基材（1〇)以及接面延伸區（12八）及 (12B)之上。介質間隔物（20)、（22)係配置在矽化物（18)及閘 極區（16)的每一側面上。圖i所示之傳統M〇SFET結構之 尺寸並不易於微縮。例如，當閘極尺寸小於〇.丨微米時， 即無法輕易地減少與閘極區（1 6)尺寸類似的間隔物（2〇)、 (22)之寬度，這是因爲閘極區（16)的寬度適用來使深接面不 會與淺延伸區（12A)及（12B)重疊。此外，閘極區（16)的寬度 也使閘極區（16)不會將矽化物（18)與源極區（24)及没極區 (26)橋接。也無法減少深接面（12)及（1幻之尺寸，這是因爲 該等尺寸決定了矽化物層（24)及（26)。有可能利用一較高的 閘極堆疊來避開橋接的問題，較高的閘極堆疊卻造成了間 極钱刻控制的困難，這是因爲在多晶矽之下的閘極氧化物 只包含了幾個單層的原子β此外，矽化物（18)/隔離區（1〇) 之邊界易於發生漏電流的情形。 -4- -----------I ^--------^---------^ 1 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中固國家標準（CNqA4描伙 钻 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（2 ) 發明概述 本發明提供了製造具有自行對準接點及金屬帶閘極的平 面MOSFET之結構及方法。本發明之M〇SFET由於有可能 取消矽化物及深接面，而而不太需要大型間隔物。也減少 了本發明的MOSFET之寄生電阻，這是因爲易於將金屬二 入閘極’且係將源極及汲極上的金屬接點置於儘量接近^ 道處。因爲在本發明的製造方法中並不需要一深接面，= 以節省了兩個植入掩蔽層，且亦無須後績的熱活化作 驟。 艾 若參照下文中之説明，並配合各圖$，將可易於 發明的其他及進-步之特徵、優點、及效益。我們當了解 ，前又中的概述及下文中的詳細説明係供舉例解説，並^ 對本發明加以限制。包含在本發明中且構成本發明一 的各附圖連同説明係用來以一般的方式說明本發明之原： 。而在整個揭示事項中，相同的代號代表相同的部分。 附圖簡述 圖1是習用技術所習知的-刪FET裝置之橫斷面圖。 面=2是根據本發明原理的一 M〇SFET裝置實抱例之橫斷 圖 3 、 4 、 5 、 6 、 7 、 8 、 9 、 Η) 、 η 、 12 、 13 、 14 : :5—、,16 : 17、18、19 '及20示出利用根據本發明 原理的一製造方法而製造一 M〇SFET之各步驟。 較佳實施例之詳細説明 請參閱圖2，圖示之本發明第一實施例具有一丰導體基 -5- 本紙張尺度 t ϋ ^--------^---------- (請先閱讀背面之注寺？事項再填寫本頁} 4230Γ 4 2 3 ο 6 Α7 Printed by B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (1) Background of the invention 1. Field of the invention The present invention relates to microelectronic devices, especially to planar MOSFET devices and Device manufacturing method. 2. Background Art The conventional MOSFET structure shown in FIG. 1 includes n + or p-doped deep junctions (12) and (14) in a semiconductor substrate 10, and the semiconductor substrate has a self-source region (24) and shallow extension regions (12A) and (14B) extending from the drain region (26). A gate region includes one of the polysilicon gate electrodes (16) in the silicide (18), and the lithium oxide (18) is arranged on the substrate (10) and the junction extension region (12) and (12B). ) Above. The dielectric spacers (20) and (22) are arranged on each side of the silicide (18) and the gate region (16). The size of the conventional MOSFET structure shown in Figure i is not easy to shrink. For example, when the gate size is less than 0.1 micron, the width of the spacers (20) and (22) similar to the size of the gate area (16) cannot be easily reduced, because the gate area (16 The width of) is suitable so that the deep junctions do not overlap the shallow extensions (12A) and (12B). In addition, the width of the gate region (16) also prevents the gate region (16) from bridging the silicide (18) with the source region (24) and the non-electrode region (26). It is also impossible to reduce the size of the deep junctions (12) and (1), because these sizes determine the silicide layers (24) and (26). It is possible to use a higher gate stack to avoid bridges The problem is that the higher gate stack has caused difficulty in controlling the electrode, because the gate oxide under polycrystalline silicon contains only a few single-layer atoms. In addition, silicide (18) / isolation The boundary of area (10) is prone to leakage current. -4- ----------- I ^ -------- ^ --------- ^ 1 (Please read the precautions on the back before filling this page) This paper size is applicable to the China National Standards (CNqA4, printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Intellectual Property Bureau, and printed by employees' consumer cooperatives. The structure and method of manufacturing a planar MOSFET with self-aligned contacts and metal strip gates are provided. The MOSFET of the present invention does not require large spacers because it is possible to eliminate silicide and deep junctions. It also reduces the number of spacers. The parasitic resistance of the MOSFET of the present invention is because it is easy to two metals into the gate 'and the metal on the source and the drain is connected. Place the dot as close as possible to the ^ track. Because in the manufacturing method of the present invention, there is no need for a deep interface, = to save two implant masking layers, and there is no need for thermal activation steps for subsequent performance. The following descriptions, combined with the drawings, will make it easy to invent other and further features, advantages, and benefits. We should understand that the overview in the previous section and the detailed description in the following are provided as examples, and ^ The present invention is limited. The drawings and descriptions included in the present invention and constituting the first of the present invention are used to explain the principle of the present invention in a general way: and throughout the disclosure, the same code represents the same part Brief Description of the Drawings Fig. 1 is a cross-sectional view of a conventional FET-deleted FET device. Surface = 2 is a cross-sectional view of a practical example of a MOSFET device according to the principles of the present invention. 3, 4, 5 , 6, 7, 8, 8, 9, Η), η, 12, 13, 14, 14:: 5, 16, 17, 18, 19 ', and 20 show that a M is manufactured using a manufacturing method according to the principles of the present invention. 〇SFET steps. For a detailed description of the preferred embodiment, please refer to Figure 2 The first embodiment of the present invention shown in the figure has a conductor base of -5- this paper size t ϋ -------- ^ ---------- (Please read the Note Temple on the back first ? Fill in this page again} 4230
五、發明說明（3 ) 材（30)、n +或p +摻雜接面（34)及（36)、自行對準金屬接點 (38)及（40)、以及一金屬帶閘極（32)。 請參閲圖3，圖中示出MOSFET裝置的製造方法之第一 步驟。利用Locos製程，或利用淺溝渠隔離區中之較厚氮 化物墊，而在半導體基材（3 0)中形成若干突出隔離結構（42) 。圖4是圖3所示結構之右側視圖。利用一額外的施加掩 蔽層步驟來開放一閘電極接點之更多面積。請注意，在圖4 中，該隔離結構之突出部分小於埋入部分。在淺溝渠隔離 區（Shallow Trench Isolation ;簡稱STI)氮化物移除之前， 可先執行該突出部分之移除，因而完好地保護了矽表面。 只要增加氮化矽的厚度，即可輕易地在標準平面淺溝渠隔 離（STI)製程中形成突出隔離結構（42)之高度。 請參閱圖5，在生長閘極氧化物（44)之後，沈積多晶矽層 (46)，並將多晶矽層（46)研磨及平面化到隔離結構（42)之高 度。可在此步驟中利用CMOS製程的所需雜質（例如 NMOSFET的磷及PMOSFET的硼）而掺雜多晶矽層（46)。 圖6是圖5之側視圖。在圖7中，利用光阻層（50)以及與 隔離材料（42)(例如氧化物）不同的硬掩蔽層材料（48)(例如 氮化物）執行閘層級的微影製程。然後執行離子植入，而形 成圖8所示之源極（52)及汲極（54)接面。圖8是圖7之側視 圖。在圖9中，沈積了圖示之間隔氧化物（56)。圖1 〇是圖9 之側視圖。然後以活性離子蝕刻製程蝕刻間隔氧化物（56) ，以便露出源極（52)及汲極（54)，並形成間隔物（58)，而得 到圖1 1及12所示之結構，其中圖1 2是圖11所示結構之側 -6- 各紙張又度適用中困國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --------訂·--------* 經濟部智慧財產局員工消費合作社印 A7V. Description of the invention (3) material (30), n + or p + doped junctions (34) and (36), self-aligned metal contacts (38) and (40), and a metal band gate ( 32). Referring to FIG. 3, a first step of a method of manufacturing a MOSFET device is shown. Using the Locos process, or using thicker nitride pads in the shallow trench isolation area, several protruding isolation structures (42) are formed in the semiconductor substrate (30). FIG. 4 is a right side view of the structure shown in FIG. 3. FIG. An additional masking step is used to open more area of a gate electrode contact. Please note that in FIG. 4, the protruding portion of the isolation structure is smaller than the buried portion. Before the shallow trench isolation region (Shallow Trench Isolation; STI for short) nitride is removed, the protruding portion may be removed first, thereby protecting the silicon surface intact. As long as the thickness of the silicon nitride is increased, the height of the protruding isolation structure (42) can be easily formed in a standard planar shallow trench isolation (STI) process. Referring to FIG. 5, after the gate oxide (44) is grown, a polycrystalline silicon layer (46) is deposited, and the polycrystalline silicon layer (46) is ground and planarized to a height of the isolation structure (42). In this step, the polycrystalline silicon layer (46) can be doped with the required impurities of the CMOS process (such as phosphorus of NMOSFET and boron of PMOSFET). FIG. 6 is a side view of FIG. 5. In FIG. 7, a gate-level lithography process is performed using a photoresist layer (50) and a hard masking layer material (48) (e.g., nitride) different from the isolation material (42) (e.g., oxide). Ion implantation is then performed to form the junction between the source (52) and the drain (54) as shown in FIG. Fig. 8 is a side view of Fig. 7. In Figure 9, a spacer oxide (56) is deposited as shown. FIG. 10 is a side view of FIG. 9. Then, the spacer oxide (56) is etched by an active ion etching process, so that the source electrode (52) and the drain electrode (54) are exposed, and a spacer (58) is formed to obtain the structure shown in Figs. 1 2 is the side of the structure shown in Figure 11-6- Each paper is also applicable to the National Standard for Difficulties (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) --- ----- Order · -------- * Employees' Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs printed A7
423L B7______ 五、發明說明（4 ) 視圖。 請參閱圖13及I4，沈積金屬（60) ’然後將金屬（6〇)研磨 及平面化到隔離結構（42)，以便形成自行對準接點。在圖 13及14中’可使用多個金屬層，以供擴散障壁之用。因爲 對多晶珍執行化學機械研磨（CMP)製程，而使得多晶沙層 (46)與隔離結構（42)有相同的高度，所以露出了多晶矽（46) 的上表面。圖14是圖13所示結構之側視圖。然後如圖j 5 及圖16的側視圖所示進行蚀刻，而完全或部分移除多晶砂 層（46)。圖1 5及16示出部分移除的情形。在圖1 7中，再 度沈積金屬（62)，並將金屬（62)平面化，而填滿多晶碎被移 除的空間’並完成閘極、源極、及汲極。使用一額外的研 磨步驟，而形成圖17及18所示之最後結構。 一替代之製程可進一步減少金屬研磨步驟。在圖9之後 ，並不執行圖1 1所示之間隔物蝕刻步驟，而是執行一氧化 物研磨步驟。所得到之結構係示於圖1 9。請注意，此時露 出了多晶矽區（46)。可在此步碟中部分移除多晶矽，而源 極及没極區則是受到氧化物的保護。 然後執行一各向異性蚀刻製程，以便露出源極及设極區 。現在因爲閘極、源極、及没極區全都露出了，所以可沈 積並研磨金屬，以便形成圖1 7所示之相同最後結構。 另一實施例係使用摻雜氧化物，例如圖9中之删推雜玻 璃及磷摻雜玻璃（BSG及PSG) ^然後使該裝置回火，以便 產生擴散接面。此種方式並不需要執行圖7及8所示之離 子植入製程。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------線' ' (請先閱讀背面之泫意事項再填寫本頁) 經濟部智慧財產局員工消貲合作社印製 A7 _Β7 五、發明說明（5 ) 玍此已說明ί 方法。此種MOSFET裝置具有並不需要大型間隔物的自朽 對準接點及金屬帶閘極。所述之MOSFET 1有妨批，冷， 電阻，且該麟訂之製造方法因而具有較::= = 層步驟。 我們當了解，前文中之説明只是用來解說本發明。在不 脱離本發明的範圍下，熟悉本門技術者 町有了想出各種替代刀 修改方式。因此’本發明將包含在最後的由 交扪申凊專利範圍户/ 述範圍内的所有此類替代、修改、及變彳匕。 ---I I I I--I —I— - I------訂 I I — I — 11 t ί (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱）423L B7______ 5. Description of the invention (4) View. Referring to FIGS. 13 and I4, the metal (60) 'is deposited and then the metal (60) is ground and planarized to the isolation structure (42) to form self-aligned contacts. In Figs. 13 and 14, multiple metal layers may be used for diffusion barriers. Because the CMP process is performed on polycrystalline silicon, the polycrystalline sand layer (46) and the isolation structure (42) have the same height, so the upper surface of the polycrystalline silicon (46) is exposed. FIG. 14 is a side view of the structure shown in FIG. 13. Etching is then performed as shown in the side views of Fig. 5 and Fig. 16, and the polycrystalline sand layer (46) is completely or partially removed. Figures 15 and 16 show the partially removed situation. In Fig. 17, the metal (62) is deposited again, and the metal (62) is planarized to fill the space where polycrystalline debris is removed 'and complete the gate, source, and drain. An additional grinding step is used to form the final structure shown in Figs. An alternative process can further reduce metal grinding steps. After FIG. 9, the spacer etching step shown in FIG. 11 is not performed, but a oxide polishing step is performed. The resulting structure is shown in FIG. Note that the polycrystalline silicon region (46) is exposed at this time. Polycrystalline silicon can be partially removed in this step, while the source and non-electrode regions are protected by oxide. Then an anisotropic etching process is performed to expose the source and electrode regions. Now that the gate, source, and non-electrode regions are all exposed, the metal can be deposited and ground to form the same final structure shown in FIG. 17. Another embodiment uses doped oxides, such as doped glass and phosphorous-doped glass (BSG and PSG) in FIG. 9 and then tempers the device to create a diffusion junction. This method does not need to perform the ion implantation process shown in Figs. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- Installation -------- Order -------- -Line '' (Please read the notice on the back before filling out this page) Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, A7 _Β7 V. Description of the invention (5) This method has been explained. Such MOSFET devices have self-degrading alignment contacts and metal strip gates that do not require large spacers. The MOSFET 1 may have batch, cold, and resistance, and the manufacturing method of the linth has the following steps :: == We should understand that the foregoing description is only used to illustrate the present invention. Without departing from the scope of the present invention, those skilled in the art have come up with various alternative knife modification methods. Therefore, the present invention will include all such substitutions, modifications, and alterations within the scope of the final patent application filed by the applicant. --- III I--I —I—-I ------ Order II — I — 11 t ί (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 This paper size applies to China National Standard (CNS) A4 (210 X 297 public love)