TW422947B - Microcomputer having reset control function - Google Patents

Microcomputer having reset control function Download PDF

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Publication number
TW422947B
TW422947B TW085113425A TW85113425A TW422947B TW 422947 B TW422947 B TW 422947B TW 085113425 A TW085113425 A TW 085113425A TW 85113425 A TW85113425 A TW 85113425A TW 422947 B TW422947 B TW 422947B
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Taiwan
Prior art keywords
reset
register
flag
signal
microcomputer
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TW085113425A
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Chinese (zh)
Inventor
Yuji Kitaguchi
Taiki Nishiuchi
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Mitsubishi Denki Engineering K
Mitsubishi Electric Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)

Abstract

A microcomputer having reset control function comprises: a central processing unit for executing collective processing; a peripheral unit for executing predetermined operations; a hardware-reset enabled peripheral register for setting the operation of the peripheral unit; a first flag for storing information on whether or not the reset operation of the central processing unit by an external reset signal is the first since the power is on; and a reset control unit for delivering a register reset signal for hardware resetting of the peripheral register when the external reset signal is inputted under the state where the information stored in the first flag represents the first reset operation, and inhibiting the output of the register reset signal when the external reset signal is inputted under the state where the information stored in the first flag represents that the reset operation is not the first reset operation, thereby performing the reset operation of the peripheral register.

Description

4229 47 A7 B7 經濟部中央標準局員工消費合作社印策 五、發明説明（1 ) 本發明係有關於用於例如電子機器之控制等的微電 腦，特別有關於微電腦的重置(reset)功能。 以往，微電腦等的半導體電路係爲了於電源切入後使 CPU及周邊機器正常地動作，而於電源切入後即施行重 置。 第27圖係顯-示此種習知微電腦之構造的方塊圖。在圖 中，10表示重置1C，而100表示單晶片微電腦。單晶片 微電腦100具有施行總括處理的CPU 110、儲存程式及資 料的記憶體120、周邊功能部130、周邊功能部用特殊功 能暫存器（以下稱SFR)部140、重置判定旗標150、指定記 憶體120等之位址的位址匯流排160以及用以將資料轉送 至各部的資料匯流排170。 記憶體120係具有RAM 121及ROM122。又周邊功能 部130係具有：將數位信號變換成類比信號而輸出的D_A 變換器131、輸入類比信號而轉換成數位信號的A-D變換 器132、串列地施行與外部機器之通信的串列1/0(以下稱 SI/0)133、若檢測CPU 110之失控而判定失控則重置cpu 110的監視(watchdog)計時器（以下稱WDT)134以及施行伴 隨控制等之計時動作的計時器135。又SFR部140係具有： D-A 用 SFR141、A-D 用 SFR142、SI/0 用 SFR143、WDT 用144 SFR以及計時器用SFR145。且施加電源電壓Vcc 於單晶片微電腦100。 其次，説明其動作。 若藉由重置1C而使電源電壓VCC由零上升至既定的 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2[0X297公釐） 22 9 47 Α7 Β7 經濟部中央標準局員工消費合作社印聚 五、發明説明（2 ) 電壓，則較此上升稍微延遲而使重置信號上升β藉由此延 遲而施行被供給重置信號之CPU 110及SFR部140的硬體 重置。亦即，每次電源切入都施行CPU 110及SFR部140 的重置。此後，藉由CPU 110的程式來施行CPu 11〇内之 暫存器之値及SFR部140之暫存器之値的初期設定的處 理。 因此’即使於電源未切斷，亦有藉由雜訊而使自重置 1C 10輸出的重置信號成爲「L」位準的場合β爲了考慮此 種事情而使CPU 110辨別電源切入（ON)時及其他場合，故 設有重置判定旗標150。 第28圖係顯示CPU 110之重置處理之動作的流程圖β 如第28圖所示，CPU 110係判定重置判定旗標150的値 (步驟ST2801)，而若爲「L」位準，亦即重置判定旗標150 不成立，則使重置判定旗標150成爲Γ H J位準（步驟 ST2802)，並設定CPU 110之暫存器的初期値（步驟 ST2803)。其後’設定SFR部140的初期値（步驟ST2804)。 另一方面’於步驟ST 2801，重置判定旗標150成立時， 亦即於「Η」時，判定電源未切入而進行至步驟ST2804， 進而設定SFR部140的初期値。 因此，於電源電壓VCC保持既定的電壓的場合，而重 置信號成爲「L」位準時，由於重置判定旗標15〇成立， 故未施行CPU110之暫存器的初期設定處理。然而，若SFR 部140被重置，則被硬體地設定成一定的値，故如第28圖 的流程圖所示，不論SFR部140的重置判定旗標150爲 C請先閲讀背面之注意事項再填寫本頁} -----------i(l ά------IT—-----i--r---- 本紙張尺度適用中國國家梯準{ CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印裝 A229 47 A7 --__ Β7 五、發明説明（3 ) 「H」或「L」’單晶片微電腦的程式必需藉由位址匯流 排160、資料匿流排來重新設定成必要之初期設定的 値’而相當費時，且中斷周邊功能部13〇的動作。所以， 於藉由雜訊等而對CPU11〇施行重置的場合，即使施行 CPU110未作資料之初期化的熱啓動(h〇t siart)，亦會造成 SFR部140被重置而必需施行SFR値的設定，進而周邊功 能部130不能夠連續動作的問題。 本發明之目的係爲了解決上述問題而提供一種電子裝 置，其於電源切入後雜訊被重疊於重置信號的場合，具有 能夠使周邊功能部繼續動作之微電腦等的重置功能。 依據申請專利範圍第1項所述的具有重置控制功能之 微電腦，由於重置控制部係若表示儲存於重置判定旗標之 資訊爲最初的重置動作，則於被輸入外部重置信號時送出 硬體地重置上述周邊功能暫存器部的暫存器重置信號，而 若表示儲存於重置判定旗標之資訊非爲最初的重置動作， 則於被輸入外部重置信號時不送出上述暫存器重置信號， 藉此以施行上述周邊功能暫存器部的重置控制，故即使因 雜訊等而產生重置信號，亦不能重置周邊功能暫存器部， 而具有周邊功能部於其後連續地繼續動作的效果。 依據申請#利範圍第2項所述的具有重置控制功能之 微電腦，由一邊功能部包括將頬比信號變換成數位信號的 A-D變換器，且周邊功能暫存器部包括上述a_d變換器之 動作設定用的暫存器，故即使因雜訊等而產生重置信號， 亦不能重置周邊功能暫存器部，而具有A_D變換器可於其 6 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公楚） .(請先閱讀背面之注意事項再填寫本頁) 袭--^--- 訂-- 422.9 47 A7 _____ B7 五、發明説明（4 ) 後連續地繼續動作的效果。 依據申請專利範圍第3項所述的具有重置控制功能之 微電腦，由於周邊功能部包括將數位信號變換成類比信號 的D-A變換器’且周邊功能暫存器部包括上述變換器 之動作設定用的暫存器，故即使因雜訊等而產生重置信 號，亦不能重置周邊功能暫存器部，而具有D A變換器可 於其後連續地繼續動作的效果。 依據申請專利範圍第4項所述的具有重置控制功能之 微電腦，由於周邊功能部包括串列地施行信號之輸出入控 制的串列輸出入裝置，且周邊功能暫存器部包括上述串列 輸出入裝置之動作設定用的暫存器，故即使因雜訊等而產 生重置乜號，亦不能重置周邊功能暫存器部，而具有串列 輸出入裝置可於其後連續地繼續動作的效果。 依據申請專利範圍第5項所述的具有重置控制功能之 微電腦，由於周邊功能部包括施行計時功能的計時器，且 周邊功能暫存器部包括上述計時器之動作設定用的暫存 器，故即使因雜訊等而產生重置信號，亦不能重置周邊功 能暫存器部，而具有計時器可於其後連續地繼續動作的效 果。 依據申請專利範圍第6項所述的具有重置控制功能之 微電腦’由於周邊功能部包括於監視中央處理部之失控而 判斷爲上逑中央處理部失控的場合輸出表示失控之信號的 監視計時器，且周邊功能暫存器部包括上述監視計時器之 動作設定用的暫存器，故即使因雜訊而產生重置信號，亦 (諳先閱讀背面之注意事項再填寫本頁) -訂 經濟部中央標準局員工消費合作社印製 422947 A7 _____ B7 五、發明説明（5 ^~ - 不能重置周邊功能暫存器部，而具有監視計時器可於其後 連續地繼續動作的效果。 依據申請專利範圍第7項所述的具有重置控制功能之 微電腦，由於在監视計時器輸出表示失控之信號的場合’ 重置控制部係不論儲存於重置判定旗標的資訊而送出暫存 器重置信號，以施行周邊功能暫存器部的重置控制，故具 有能夠施行更具穩定性的重置控制。 依據申請專利範圍第8項所述的具有重置控制功能之 微電腦，由於重置控制部係若於重置判定旗標儲存表示旗 標非依賴模式的資訊，則於外部重置信號被輸入時不論第 一旗標所儲存的資訊而送出暫存器重置信號至周邊功能暫 存器部，故藉由執行之程式等的性質來改變模式，而具有 能夠施行更有效率的重置處理。 經濟部中央椋準局貝工消費合作.杜印製 依據申請專利範圍第9項所述的具有重置控制功能之 微電腦，僅於輸入由將電源供給至中央處理器之第一電療 所產生的第一重置信號及由將電源供給至周邊功能部之第 二電源所產生的第二重置信號兩者的場合，將施行中央處 理部之重置的信號送出至中央處理部，故即使雜訊被重疊 於重置信號線的場合，中央處理部亦不易被重置，而具有 中央處理部穩定地動作的效果。 圖面簡單説明 第1圖係顯示本發明之實施的形態一之單晶片微電腦 之構造的方塊圖。 第2圖係顯示第1圖所示之重置控制電路之詳細構造 8 < CNS ) A4規格（2ί〇χ297公釐） 經濟部中央標準局員工消費合作杜印製 422947 A7 _________ B7 五、發明説明（~ ~ —- 的電路圖。 第3圖係顯示本發明之實施的形態一之CPU之重置處 理之動作的流程圖。 第4圖係顯示第2圖所示之重置控制電路之輸出入信 號之定時(timing)的時序圖。 第5圖係顯示本發明之實施的形態二之單晶片微電腦 之構造的方塊圖。 第6圖係顯示第5圖所示之重置控制電路之詳細構造 的電路圖。 l第7圖係顯示本發明之實施的形態二之Cpu之重置處 理之動作的流程圖。 第8圖係顯示於本發明之實施的形態二中電源處於切 入(ON)狀態時重置信號成爲「[」之場合之各部之信號之 定時的時序圖。 第9圖係顯示本發明之實施的形態三之單晶片微電腦 之構造的方塊圖。 第10圖係顯示第9圖所示之重置控制電路之構造的電 路圖。 第11圖係顯示本發明之實施的形態三之CPU之重置 時之動作的流程圖。 第12圖係顯示本發明之實施的形態三之各部之信號 之定時的時序圖。 第13圖係顯示本發明之實施的形態四之單晶片微電 腦之構造的方塊圖。 9 本紙張尺度適用中國國家橾準（CNS ) A4規格（2丨〇 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)4229 47 A7 B7 Imprint by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (1) The present invention relates to microcomputers used in, for example, the control of electronic equipment, and particularly to the reset function of the microcomputer. Conventionally, a semiconductor circuit such as a microcomputer has been reset so that the CPU and peripheral devices can operate normally after the power is switched on. Figure 27 is a block diagram showing the structure of such a conventional microcomputer. In the figure, 10 indicates resetting 1C, and 100 indicates a single-chip microcomputer. The single-chip microcomputer 100 includes a CPU 110 that performs overall processing, a memory 120 that stores programs and data, a peripheral function section 130, a special function register (hereinafter referred to as SFR) section 140 for the peripheral function section, a reset judgment flag 150, An address bus 160 that specifies an address of the memory 120 and the like, and a data bus 170 that is used to transfer data to the various units. The memory 120 includes a RAM 121 and a ROM 122. The peripheral function unit 130 includes a D_A converter 131 that converts a digital signal into an analog signal and outputs it, an AD converter 132 that inputs an analog signal and converts it into a digital signal, and a serial 1 that performs communication with external devices in series. / 0 (hereinafter referred to as SI / 0) 133, if the CPU 110 is detected to be out of control and determined to be out of control, the watchdog timer (hereinafter referred to as WDT) 134 of the CPU 110 is reset 134, and the timer 135 is used to perform timing operations such as control . The SFR unit 140 includes: SFR141 for D-A, SFR142 for A-D, SFR143 for SI / 0, 144 SFR for WDT, and SFR145 for timer. The power supply voltage Vcc is applied to the single-chip microcomputer 100. Next, the operation will be described. If the power supply voltage VCC is raised from zero to a predetermined value by resetting 1C (please read the precautions on the back before filling out this page) This paper size applies the Chinese National Standard (CNS) A4 specification (2 [0X297 mm) 22 9 47 Α7 Β7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China 5. Description of the invention (2) The voltage will be slightly delayed compared to this increase and the reset signal will be increased. And the hardware of the SFR section 140 is reset. That is, the CPU 110 and the SFR section 140 are reset each time the power is switched on. Thereafter, the processing of the initial setting of the register of the CPu 110 and the register of the SFR section 140 is performed by the program of the CPU 110. Therefore, 'even if the power is not cut off, there may be cases where the reset signal output from the self-reset 1C 10 is set to the "L" level by noise. In order to consider this, the CPU 110 recognizes that the power is switched on (ON ) And other occasions, a reset determination flag 150 is provided. FIG. 28 is a flowchart showing the operation of the reset processing of the CPU 110. As shown in FIG. 28, the CPU 110 determines the reset flag 150 (step ST2801), and if it is at the "L" level, That is, the reset determination flag 150 is not established, the reset determination flag 150 is set to the Γ HJ level (step ST2802), and the initial stage of the register of the CPU 110 is set (step ST2803). After that, the initial stage of the SFR unit 140 is set (step ST2804). On the other hand, at step ST 2801, when the reset determination flag 150 is established, that is, at "Η", it is determined that the power is not switched on and the process proceeds to step ST2804, and the initial stage of the SFR unit 140 is set. Therefore, when the power supply voltage VCC is maintained at a predetermined voltage and the reset signal reaches the "L" level, since the reset determination flag 15 is established, the initial setting processing of the register of the CPU 110 is not performed. However, if the SFR section 140 is reset, it is set to a fixed value by hardware. Therefore, as shown in the flowchart in FIG. 28, regardless of whether the reset determination flag 150 of the SFR section 140 is C, please read the Please fill in this page for matters needing attention} ----------- i (l ά ------ IT —----- i--r ---- Quasi {CNS) A4 specification (210X297 mm) printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A229 47 A7 --__ Β7 V. Description of the invention (3) "H" or "L" single chip microcomputer program must be borrowed It is time-consuming to reset the address bus 160 and the data hiding bus to the necessary initial settings, and the operation of the peripheral function unit 13 is interrupted. Therefore, in the case where the CPU 11 is reset by noise or the like, even if an initial warm start (HOT siart) where the CPU 110 is not initialized is performed, the SFR unit 140 is reset and SFR must be performed. The setting of 値 further causes the peripheral function unit 130 to fail to operate continuously. An object of the present invention is to provide an electronic device for solving the above-mentioned problems. When the noise is superimposed on the reset signal after the power is switched on, the electronic device has a reset function of a microcomputer or the like that enables the peripheral function section to continue to operate. According to the microcomputer with reset control function described in item 1 of the scope of patent application, since the reset control unit indicates that the information stored in the reset determination flag is the initial reset action, an external reset signal is input. A hardware reset signal for resetting the peripheral function register section is sent from time to time, and if the information stored in the reset judgment flag is not the initial reset action, an external reset signal is input The above-mentioned register reset signal is not sent from time to time in order to implement the reset control of the peripheral function register unit, so even if a reset signal is generated due to noise, etc., the peripheral function register unit cannot be reset. In addition, it has the effect that the peripheral function section continues to operate thereafter. According to the microcomputer with reset control function described in the application # 利 范围 2, one side of the function section includes an AD converter that converts the ratio signal to a digital signal, and the peripheral function register section includes the above-mentioned a_d converter. Register for action setting, so even if a reset signal is generated due to noise, etc., the peripheral function register section cannot be reset, and the A_D converter can be used on its 6 paper standards to apply Chinese National Standards (CNS) A4 specifications (210X297). (Please read the precautions on the back before filling out this page.)--^ --- Order-422.9 47 A7 _____ B7 V. Effect of continuous operation after the invention description (4) . According to the microcomputer with reset control function described in item 3 of the scope of patent application, since the peripheral function section includes a DA converter that converts digital signals into analog signals, and the peripheral function register section includes the above-mentioned converter for setting the operation Therefore, even if a reset signal is generated due to noise, the peripheral function register unit cannot be reset, and the DA converter can continue to operate continuously thereafter. According to the microcomputer with reset control function described in item 4 of the scope of patent application, since the peripheral function section includes a serial input / output device that performs the input / output control of signals in series, and the peripheral function register section includes the above serial Register for the operation setting of the input / output device, so even if the reset signal is generated due to noise, etc., the peripheral function register unit cannot be reset, and the serial input / output device can be continuously continued afterwards The effect of the action. According to the microcomputer with reset control function described in item 5 of the scope of the patent application, since the peripheral function section includes a timer that performs a timing function, and the peripheral function register section includes a register for setting the operation of the timer, Therefore, even if a reset signal is generated due to noise, the peripheral function register unit cannot be reset, and the timer can continue to operate continuously thereafter. According to the microcomputer with reset control function described in item 6 of the scope of the patent application, because the peripheral function unit is included in the monitoring of the central processing unit for out of control, it is judged that the central processing unit is out of control. A monitoring timer indicating a signal of out of control is output. And the peripheral function register section includes the register for setting the operation of the watchdog timer, so even if a reset signal is generated due to noise, (讯 Please read the precautions on the back before filling this page)-Order economy Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Education 422947 A7 _____ B7 V. Description of the invention (5 ^ ~-The peripheral function register unit cannot be reset, and the watchdog timer can continue to operate continuously thereafter. According to the application The microcomputer with reset control function described in item 7 of the patent scope, because the watchdog timer outputs a signal indicating that it is out of control, the reset control unit sends the register for reset regardless of the information stored in the reset judgment flag. Set the signal to perform the reset control of the peripheral function register section, so it has a more stable reset control. According to the patent application As for the microcomputer with reset control function described in the scope item 8, since the reset control section stores information indicating the flag-independent mode in the reset determination flag, it does not matter when the external reset signal is input. The information stored in the flag sends a register reset signal to the peripheral function register unit, so the mode is changed by the nature of the program executed, etc., and it can perform a more efficient reset process.椋 The quasi bureau shellfish consumer cooperation. Du printed the microcomputer with reset control function according to item 9 of the scope of the patent application, only the first input generated by the first electrotherapy that supplies power to the central processor When both the reset signal and the second reset signal generated by the second power supply that supplies power to the peripheral function unit, the reset signal from the central processing unit is sent to the central processing unit, so even if noise is overlapped When the signal line is reset, the central processing unit is not easily reset, but has the effect that the central processing unit operates stably. Brief Description of the Drawings The first figure is a diagram showing the implementation of the present invention. A block diagram of the structure of a single-chip microcomputer in state 1. Figure 2 shows the detailed structure of the reset control circuit shown in Figure 1. 8 < CNS) A4 specification (2ί297 × 297 mm) Employees of the Central Standards Bureau of the Ministry of Economic Affairs Consumption Cooperation Du printed 422947 A7 _________ B7 V. Circuit description of the invention (~ ~ ---. Figure 3 is a flowchart showing the operation of the reset process of the CPU of the first embodiment of the present invention. Figure 4 shows The timing chart of the timing of the input and output signals of the reset control circuit shown in Fig. 2. Fig. 5 is a block diagram showing the structure of the single-chip microcomputer of the second embodiment of the present invention. Fig. 6 shows The circuit diagram of the detailed structure of the reset control circuit shown in Fig. 5. Fig. 7 is a flowchart showing the operation of the reset processing of the CPU in the second form of the implementation of the present invention. Fig. 8 is a timing chart showing the timing of the signals of the respective units when the reset signal becomes "[" in the second embodiment of the present invention when the power supply is in the ON state. Fig. 9 is a block diagram showing the structure of a single-chip microcomputer according to a third embodiment of the present invention. Fig. 10 is a circuit diagram showing the configuration of the reset control circuit shown in Fig. 9. Fig. 11 is a flowchart showing the operation when the CPU of the third embodiment of the present invention is reset. Fig. 12 is a timing chart showing the timing of the signals of each part of the third embodiment of the present invention. Fig. 13 is a block diagram showing the structure of a single-chip microcomputer according to a fourth embodiment of the present invention. 9 This paper size is applicable to China National Standard (CNS) A4 (2 丨 〇 X 297 mm) (Please read the precautions on the back before filling this page)

422947 經濟部中央橾準局員工消費合作.杜印裝 A7 B7 五、發明説明（7) 第14圖係類示第13圖之重置控制電路之詳細構造的 電珞圖。 第15圏係類示本發明之實施的形態四之CPU之重置 處理之動作的流程圏。 第16圖係頬示第14圖所示之重置控制電路之輸出入 信號之定時的時序圖。 第17圖係顯示本發明之實施的形態五之構造的方塊 圖。 第18圖係顯示本發明之實施的形態五之CPU之重置 處理之動作的流程圖》 第19圖係顯示本發明之實施的形態六之單晶片微電 腦之構造的方塊圖。 第20圖係顯示本發明之實施的形態六之cPU之重置 處理之動作的流程圖。 第21圖係顯示本發明之實施的形態七之單晶片微電 腦之構造的方塊圖。 第22圖係顯示本發明之實施的形態七之cpu之重置 處理之動作的流程圖。 第23圖係顯示本發明之實施的形態八之單晶片微電 腦之構造的方塊圖。 第24圖係顯示第23圖所示之重置控制電路之詳細構 造的電路圖。 第25圖係顯示本發明之實施的形態八之cpu之重置 處理之動作的流程圖。 本紙張尺度適用中國國家標率（CNS ) A4規格（210x297公嫠） i ί 乜—广！ J—-i— 1 !_ I 訂.------β.----- '.(諳先閲讀背面之注意事項再填寫本頁) 4229 47 at ___B7_’____ 五、發明説明（9 ) SI/0 用 SFR243、WDT 用 244 SFR 以及計時器用 SFR245。 且施加電源電壓VCC於單晶片微電腦200。 且單晶片微電腦200具有重置控制電路（重置控制 部）280 。又來自重置IC20的重置信號係直接輸入至 CPU210及重置控制電路280。此外，重置判定旗標250 的旗標値被輸入至重置控制電路280。 第2圖係顯示第1圖之重置控制電路280之詳細構造 的電路圖。如第2圖所示，重置控制電路280係由反相器 281、282及反及閘283所構成。 其次，説明其動作。 於電流切入時，來自重置IC20的重置信號被輪入至 CPU210及重置控制電路280。CPU210被重置，而執行後 述的重置程式。電源切入時，重置判定旗標250爲「L」， 而由於重置信號爲「L」，故反及閘283的輸出成爲「L」。 因此’重置控制電路280輸出「L」位準的信號，SFR部 240被硬體地重置。 第3圖係顯示CPU210之重置處理之動作的流程圖。 如同-阖所示，首先，於重置判定旗標250的値爲「L」的 場合（步驟ST301)，判斷爲電源切入時的重置，而使重置 判定旗標25〇成爲「η」（步驟ST302)，進而施行CPU210 之暫存器的初期設定（步驟ST303)，接著施行SFR部240 之SFR值的初期設定（步驟ST3〇4)。另一方面，在步驟 ST301，若步驟ST250爲「Η」，則CPU210判斷爲熱啓 動’而不施行SFR部24〇及CPU210之暫存器等之値的初 12 本紙張尺度適用中酬( CNS〉( 210X 297公釐） Λ11»".-:".. ";®iai".···') .¾曼焉 - - 1 ί 111 In I - I— m 111--- -I— 1 ----.1_ I m , • * SOS (請先閲讀背面之注意事項再填寫本頁) Μ濟部中央摞準局員工消費合作社印装 ——1^----i__.-------------- 422947 經濟部中央橾隼局員工消費合作社印裝 A7 _______________B7 五、發明説明（10 ) 期設定動作，進而結束重置處理。 第4圖係顯示第2圖所示之重置控制電路28〇之輸出 入信號之定時的時序圖。在同圖中，表示輸入至重置控 制電路280的重置信號；（b)表示重置判定旗標25〇的値； (c)表示重置控制電路280的輸出信號。如同圖所示，若重 置判定旗標250被設定成「H」位準，則判斷爲電源切入 時，而即使重置信號成爲「L」位準，重置控制電路2⑽ 的輸出乜號亦爲「Hj位準。因此，SFR部240未被硬體 地重置。 且在電源切入時CPU210施行第3圖的步驟ST303之 前，重置控制電路280有必要將重置信號送至SFR24〇， 但疋重置控制電路280係以二個反相器及一個邏辑閘所構 成的小型硬體來作信號處理，故相對於cpu21〇施行步驟 ST303者，重置控制電路28〇之信號送出處理是相當早施 行。 如以上的説明，依據實施的形態一，於電源切入時以 外，即使重置彳&號成爲「L」位準，藉由重置控制電路280 亦不能重置SFR部240，故即使因雜訊而使重置信號成爲 「L」’亦可在未重置SFR部24〇的狀態下，而具有周邊 功能部23〇於其後連續地繼續動作的效果。 實施的形態二 第5圖係顯示本發明之實施的形態二之單晶片微電腦 之構造的方塊圖。與第1圖所示的部份相同者標上相同符 號，以省略重複的説明。在同圖中，300表示單晶片微電 本紙張尺度適用中國國家操準（CNS > A4規格（2丨〇χ297公釐） (請先閱请背面之注意事項再填寫本頁) ’等422947 Consumption cooperation among employees of the Central Bureau of Standards of the Ministry of Economic Affairs. Du Yinzhuang A7 B7 V. Description of the Invention (7) Figure 14 is an electric chart showing the detailed structure of the reset control circuit of Figure 13. The 15th series is a flowchart showing the operation of the reset processing of the CPU according to the fourth embodiment of the present invention. Fig. 16 is a timing chart showing the timing of the input and output signals of the reset control circuit shown in Fig. 14. Fig. 17 is a block diagram showing the structure of a fifth embodiment of the present invention. Fig. 18 is a flowchart showing the operation of the reset processing of the CPU according to the fifth embodiment of the present invention. Fig. 19 is a block diagram showing the structure of the single-chip microcomputer according to the sixth embodiment of the present invention. Fig. 20 is a flowchart showing the operation of the reset processing of the cPU according to the sixth embodiment of the present invention. Fig. 21 is a block diagram showing the structure of a single-chip microcomputer according to a seventh embodiment of the present invention. Fig. 22 is a flowchart showing the operation of resetting the CPU of the seventh embodiment according to the present invention. Fig. 23 is a block diagram showing the structure of a single-chip microcomputer according to a eighth embodiment of the present invention. Fig. 24 is a circuit diagram showing a detailed configuration of the reset control circuit shown in Fig. 23. Fig. 25 is a flowchart showing the operation of resetting the CPU of the eighth embodiment of the present invention. This paper size is applicable to China National Standards (CNS) A4 specifications (210x297 cm) i 广 —wide! J—-i— 1! _ I Order. ------ β .----- '. (谙 Read the precautions on the back before filling this page) 4229 47 at ___ B7 _'____ V. Description of the invention ( 9) SFR243 for SI / 0, 244 SFR for WDT, and SFR245 for timer. A single-chip microcomputer 200 is applied with a power supply voltage VCC. The single-chip microcomputer 200 includes a reset control circuit (reset control section) 280. The reset signal from the reset IC 20 is directly input to the CPU 210 and the reset control circuit 280. The flag 的 of the reset determination flag 250 is input to the reset control circuit 280. Fig. 2 is a circuit diagram showing a detailed structure of the reset control circuit 280 of Fig. 1. As shown in Fig. 2, the reset control circuit 280 is composed of inverters 281 and 282 and a reverse-gate 283. Next, the operation will be described. When the current is switched on, the reset signal from the reset IC 20 is rounded to the CPU 210 and the reset control circuit 280. The CPU 210 is reset, and a reset program described later is executed. When the power is switched on, the reset determination flag 250 is "L", and since the reset signal is "L", the output of the reverse gate 283 becomes "L". Therefore, the 'reset control circuit 280 outputs a signal at the "L" level, and the SFR section 240 is reset by hardware. FIG. 3 is a flowchart showing the operation of the reset processing of the CPU 210. As shown by-阖, first, when 値 of the reset determination flag 250 is "L" (step ST301), it is determined that the reset is performed when the power is switched on, and the reset determination flag 25 is set to "η". (Step ST302), the initial setting of the register of the CPU 210 is performed (step ST303), and then the initial setting of the SFR value of the SFR section 240 is performed (step ST304). On the other hand, in step ST301, if step ST250 is "Η", the CPU 210 determines that it is a hot start, and does not execute the first 12 paper standards of the SFR section 24o and the register of the CPU 210, etc. (CNS) 〉 (210X 297mm) Λ11 »" .-: " .. " ®iai ". ··· ') .¾Man 焉--1 ί 111 In I-I— m 111 ---- I— 1 ----. 1_ I m, • * SOS (Please read the notes on the back before filling in this page) Printed by the Consumers' Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs——1 ^ ---- i__. -------------- 422947 Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs A7 _______________B7 V. Description of the invention (10) Period setting action, and then the reset process is ended. Fig. 4 is a timing chart showing the timing of the input / output signals of the reset control circuit 280 shown in Fig. 2. In the same figure, a reset signal input to the reset control circuit 280 is shown; (b) a 値 of the reset determination flag 25; and (c) an output signal of the reset control circuit 280. As shown in the figure, if the reset determination flag 250 is set to the "H" level, it is determined that the power is switched on, and even if the reset signal becomes the "L" level, the output 乜 number of the reset control circuit 2⑽ is also "Hj level. Therefore, the SFR section 240 is not reset by hardware. And before the CPU 210 executes step ST303 in Fig. 3 when the power is switched on, it is necessary for the reset control circuit 280 to send a reset signal to SFR 24. However, the reset control circuit 280 uses small hardware composed of two inverters and a logic gate to perform signal processing. Therefore, the signal sending process of the reset control circuit 28 is performed with respect to the CPU 21 that performs step ST303. As described above, according to the above-mentioned implementation mode 1, except when the power is switched on, even if the reset 彳 & number becomes the "L" level, the SFR section 240 cannot be reset by the reset control circuit 280. Therefore, even if the reset signal becomes "L" 'due to noise, the peripheral function section 23 can continue to operate continuously after the SFR section 24 is not reset. Embodiment 2 FIG. 5 is a block diagram showing the structure of a single-chip microcomputer according to Embodiment 2 of the present invention. The same parts as those shown in Fig. 1 are marked with the same symbols to omit duplicate descriptions. In the figure, 300 indicates single chip microelectronics. The paper size is applicable to Chinese national standards (CNS > A4 specification (2 丨 〇χ297mm) (Please read the precautions on the back before filling this page) ’etc.

,1T -_ V ;422947 Α7 Β7 經濟部中央標隼局員工消費合作社印製 五、發明説明（11) 腦；310表示用以設定重置的模式的重置模式旗標（第二 旗標）；320表示依據由重置IC20輸出的重置信號、重置 判定旗標250的値及重置模式旗標310而將重置信號供給 至SFR部240的重置控制電路。 第6圖係顯示重置控制電路32〇之詳細之構造的電路 圖。在同圖中，321、322表示反相器；323表示或閘（0R gate) ’ 324 表不反及閉（NAND gate)。 其次説明其動作。 首先，使用者係藉由CPU210的程式來設定重置模式 旗標310的値。若選擇藉由未依賴於重置判定旗標250而 輸入的重置信號來重置SFR部240的旗標非依賴模式，則 將重置模式旗標310設定成Γ H」。另一方面，與上述實 施的形態一同樣地，若選擇依重置判定旗標25〇及重置信 號而重置SFR部240的旗標依賴模式，則使重置模式旗標 310成爲「LJ。如第6圖所示，若重置模式旗標31〇爲 「Η」’則或閘323的輸出持續成爲「η」，而由反及閘 324輪出與重置信號相同的信號，以當作sfR重置信號β 另一方面，若於重置模式旗標31〇設定「L」位準的信號， 則或閘323的輸出信號成爲與反相器321的輸出信號相 同，而施行與於實施的形態一所説明之動作相同的動作。 第7圖係顯示CPU210之重置處理之動作的流程圖。 首先，若施行重置，而在步驟ST701 ，重置判定旗標爲 「L」，（步驟ST701)則判斷爲電源切入時的重置，而使 重置判定旗標250成爲Γ η J (步驟ST702)，進而施行 (請先閲讀背面之注意事項再填寫本頁) 訂----1,--..------ 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公楚> 經濟部中央標準局員工消費合作杜印製 4229 47 at ___ B7 五、發明説明（12 ) CPU210之暫存器的初期設定（步驟ST7〇3)，接著施行SFR 部240之SFR値的初期設定（步驟ST704)。另一方面，若 在步驟ST701，重置判定旗標250爲「Η」，則參照重置 糢式旗標310(步驟ST705)，且於表示旗標依據模式的場 合’則進行至步驟ST7〇4，而於表示旗標非依賴模式的場 合’則依原樣結束重置處理。 亦即’ CPU210於電源切入時，施行CPU2 10之暫存 器及SFR部240之初期値的設定，以當作重置處理，而若 電源處於ON的狀態，則於爲通常模式時設定sfR部240 的初期値，而於爲旗標非依賴模式時依原樣結束重置處 理。 第8圖係顯示電源處於on狀態時重置信號成爲 「L」之場合之各部之信號之定時的時序圖。於同圖中， 0)表示輸入至重置控制電路32〇的重置信號；（…表示重置 判定旗標250的値；（c)表示重置模式旗標31〇的値；（d) 表示作爲重置控制電路320之輸出信號的SFR重置信號。 如同圖的時間T1所示，若「η」位準的信號儲存於重置 判定旗標，則即使重置信號成爲「L」，而重置判定旗標 250的値假使爲「H」，而重置信號亦爲「H」，亦不能 對SFR部240施行硬體的重置。另一方面，如時間丁2所 不’右重置模式旗標310爲「L」’亦即爲旗標非依賴模 式，則SFR重置信號係成爲與被輪入的重置信號相同的信 號，而著重置仏號成爲Γ L J，則硬體地重置MR部24〇。 如以上的説明，依據實施的形態二，設有重置模式旗 (請先間讀背面之注意事項再填寫本頁) '裝. 訂i 本紙張尺度適财國—g]家標準（CNS ) Α4·_ ( 2lQx2^^y- 經濟部中夬標準局員工消費合作社印製 4229 47 A7 ________B7____ 五、發明説明（13 ) 標310而藉由此旗標的値，來切換不依賴於重置判定旗標 250的値的旗標非依賴模式及依賴於重置判定旗標25〇的 旗標依賴模式，進而能夠施行SFr部24〇的重置。因此， 藉由執行之程式等的性質來改變模式，而具有能夠施行更 有效率之重置處理的效果。 實施的形態三 - 第9圖係顯示本發明之實施的形態三之單晶片微電腦 之構造的方塊圖。與第1圖所示之部份相同的部价標上相 同的符號，以省略重複的説明。且在此實施的形態三中， 將3伏特的VCC 3(第二電源）當作電源而供給至周邊功能 部230、SFR部240及重置IC20,且將5伏特的VCC5(第 一電源）當作電源而供給至CPU210。在第9圖中，21表示 重置1C，且被輸入VCC5。又重置IC20及重置IC21的輸 出信號係成爲相對於VCC5、VCC3的上升而重置SFR 部240、CPU 210者充份遲的上升。4〇〇表示此實施的形 態三的單晶片微電腦；410表示重置控制電路，其輸出藉 由自重置IC20所輸出的重置信號及自重置IC21所輸出的 重置信號而重置CPU210用的CPU重置信號。 第10圖係顯示第9圖所示之重置控制電路41〇之構造 的電路圖。如同圖所示，重置控制電路41〇係由或閘41】 所構成。重置IC20的輸出及重置IC21的輸出被輸入至此 或閘411，並將此等信號的邏辑和當作cpu重置信號而供 給至0?17210。又來自重置1〇20的重置信號亦供給至沾尺 部 240。 (請先閱讀背面之注意事項再填寫本頁) 裝, 1T -_ V; 422947 Α7 Β7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (11) Brain; 310 indicates the reset mode flag (second flag) used to set the reset mode ; 320 indicates that the reset signal is supplied to the reset control circuit of the SFR section 240 based on the reset signal output from the reset IC 20, the reset flag 250, and the reset mode flag 310. Fig. 6 is a circuit diagram showing a detailed structure of the reset control circuit 32o. In the same figure, 321 and 322 represent inverters; 323 represents OR gate ’324 means NAND gate. The operation will be described next. First, the user sets the reset mode flag 値 through a program of the CPU 210. If it is selected to reset the flag-independent mode of the SFR section 240 by a reset signal input that does not depend on the reset determination flag 250, the reset mode flag 310 is set to? H ''. On the other hand, as in the first embodiment, if the flag dependent mode of the SFR unit 240 is reset based on the reset determination flag 25 and the reset signal, the reset mode flag 310 is set to "LJ As shown in Figure 6, if the reset mode flag 31o is "Η", the output of OR gate 323 will continue to become "η", and the same signal as the reset signal will be generated by anti-and gate 324. As the sfR reset signal β On the other hand, if the signal of the "L" level is set at the reset mode flag 31, the output signal of the OR gate 323 becomes the same as the output signal of the inverter 321, and The operation described in the first embodiment is the same operation. FIG. 7 is a flowchart showing the operation of the reset processing of the CPU 210. First, if a reset is performed, and in step ST701, the reset determination flag is "L" (step ST701), it is determined that the reset is performed when the power is switched on, and the reset determination flag 250 is set to Γ η J (step ST702), and then implement (please read the precautions on the back before filling this page) Order ---- 1, --..------ This paper size applies to China National Standard (CNS) A4 specifications (2 丨0X297 Gongchu > Consumption Cooperation by Employees of the Central Standards Bureau of the Ministry of Economic Affairs 4229 47 at ___ B7 V. Description of the Invention (12) Initial setting of the register of the CPU210 (step ST7〇3), and then the SFR of the SFR section 240 Initial setting of 値 (step ST704). On the other hand, if the reset determination flag 250 is "Η" in step ST701, the reset mode flag 310 is referred to (step ST705), and In the case of 'the process proceeds to step ST704, and in the case of indicating the flag-independent mode', the reset processing is ended as it is. That is, when the CPU 210 is switched on, the register of the CPU 2 10 and the SFR section 240 are executed. The initial setting is treated as reset. If the power is on, the In the normal mode, the initial stage of the sfR section 240 is set, and the reset processing is ended as it is in the flag-independent mode. Figure 8 shows the signals of the sections when the reset signal becomes "L" when the power is on. Timing diagram of the timing. In the same figure, 0) represents the reset signal input to the reset control circuit 32〇; (... represents 値 of the reset determination flag 250; (c) represents the reset mode flag 31. (D) represents the SFR reset signal as the output signal of the reset control circuit 320. As shown at time T1 in the figure, if the signal of the "η" level is stored in the reset determination flag, even if reset The signal becomes "L", and if the reset determination flag 250 is set to "H", and the reset signal is also "H", it is not possible to perform a hardware reset on the SFR section 240. On the other hand, such as time Ding 2 said that the “right reset mode flag 310 is“ L ””, that is, the flag-independent mode, the SFR reset signal becomes the same signal as the reset signal being rotated, and the reset is performed. When the number becomes Γ LJ, the MR unit 24 is reset by hardware. As explained above, according to the implementation State two, with a reset mode flag (please read the precautions on the back before filling out this page) 'Package. Order i This paper size is suitable for financial countries — g] Home Standard (CNS) Α4 · _ (2lQx2 ^^ y -Printed by the Consumer Cooperatives of the China Standards Bureau of the Ministry of Economic Affairs 4229 47 A7 ________B7____ V. Description of the Invention (13) Mark 310 and use the flag of this flag to switch the flag of the flag not dependent on the reset judgment flag 250. The dependency mode and the flag dependency mode that depend on the reset determination flag 25 ° can further reset the SFr unit 240. Therefore, the mode is changed by the nature of the program to be executed, and the effect of performing more efficient reset processing is achieved. Embodiment 3-Fig. 9 is a block diagram showing the structure of a single-chip microcomputer according to Embodiment 3 of the present invention. The same symbols are assigned to the same parts as those shown in Fig. 1 to omit repeated descriptions. And in the third form of this implementation, a 3 volt VCC 3 (second power supply) is used as a power supply to the peripheral function section 230, the SFR section 240, and the reset IC 20, and a 5 volt VCC 5 (first power supply) It is supplied to the CPU 210 as power. In Figure 9, 21 indicates reset 1C and is input to VCC5. The output signals of reset IC20 and reset IC21 are set to rise sufficiently late relative to the rise of VCC5 and VCC3 and reset the SFR unit 240 and the CPU 210. 400 indicates a single-chip microcomputer of the third form of this implementation; 410 indicates a reset control circuit whose output resets the CPU 210 by a reset signal output by the self-reset IC20 and a reset signal output by the self-reset IC21. Used CPU reset signal. Fig. 10 is a circuit diagram showing the configuration of the reset control circuit 41o shown in Fig. 9. As shown in the figure, the reset control circuit 410 is composed of an OR gate 41]. The output of the reset IC20 and the output of the reset IC21 are input to the OR gate 411, and the logical sum of these signals is supplied as a CPU reset signal to 0-17172. The reset signal from the reset 1020 is also supplied to the staining section 240. (Please read the notes on the back before filling this page)

、1T 16 本纸張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）、 1T 16 This paper size is applicable to China National Standard (CNS) Α4 specification (210X297 mm)

五、發明説明（14 ) 其次，説明其動作。 經濟部中央標準局貝工消費合作社印製 首先，於電源切入時VCC 5及VCC 3同時上升。此時， 來自重置1C 20、重置1C 21的輸出係被輸入至重置控制電 路410，然後將此二信號的邏辑和當作cpu重置信號而供V. Description of the Invention (14) Next, the operation will be described. Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. First, VCC 5 and VCC 3 rose simultaneously when the power was switched on. At this time, the outputs from the reset 1C 20 and reset 1C 21 are input to the reset control circuit 410, and then the logical sum of these two signals is provided as a cpu reset signal.

給至CPU210。因此，於電源切入時CPU210被重置。CPU 210之被重置後的處理將於後詳述之。又自重置IC2〇所輸 出的重置信號亦供給至SFR部240，而被硬體地重置。 且於電源爲ON狀態時，由於以或閘411來取得邏辑 和’故即使雜訊等重疊於任一重置信號，而僅其中一信號 成爲「L」位準，亦不重置。 第11圖係顯示CPU 210之重置時之動作的流程圖。如 同圏所示，首先，若被重置，則於重置判定旗標25〇爲「L」 的場合（步驟ST 1101)，判斷成電源切入時的重置，而使重 置判定旗標25〇成爲「Η」（步驟ST 1102)，進而施行CPU 之暫存器的初期設定（步驟ST 1103)。接著施行SFR部 240之SFR値的初期設定（步驟ST 1104)。另一方面，在步 隸ST 11 〇1若重置判定旗標250爲「Η」，則進行至步驟 ST 1104，而設定SFR部240的初期値。 第12圖係顯示此實施的形態三之各部之信號之定時 的時序圖。在同圖中，（a)表示VCC 5 ; (b)表示VCC 3 : (c)表示來自重置IC 20的重置信號；（d)表示供給至CPU 210 的CPU重置信號：（e)表示重置判定旗標25〇的値。如同圖 所示，在時間T1，雖然VCC 3成爲Γ L J位準，但是VCC 5仍爲Γ Η」位準。因此，重置控制電路410未供給Γ L」 本紙張尺度適用中國國家樣率（CNS ) Α4規格（210Χ297公釐） (請先闖讀背面之注意事項再填寫本頁) Ί ,裝· 訂- 戀猶 4229 4 7 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（15 ) 位準的重置信號至CPU 210，而未重置CPU 210。另一方 面，在時間Τ2，由於VCC 5及VCC 3同時成爲「L」位 準，故重置控制電路410輸出「Ljii準的CPU重置信號。 此時，CPU210係參照重置判定旗標250 ,而依據是「η」 位準或是「LJ位準來施行第11圖所示的重置處理。 如以上的説明，依據實施的形態三，重置控制電路41〇 係藉由VCC 3所產生的重置信號及VCC 5所產生的重置信 號的運辑和而產生CPU重置信號，故即使雜訊重疊至重置 1C 20、21的輸出等，CPU210亦不易被重置，而具有CPU 210穩定地動作的效果。 實施的形態四 第13圖係顯示本發明之實施的形態四之單晶片微電 腦之構造的方塊圖。與第1圖所示的部份相同的部份標上 相同符號，以省略重複的説明。在第13圖中，500表示此 實施的形態四的單晶片微電腦；510表示重置控制電路， 其產生用以重置Si/Ο用SFR243的個別SFR重置信號。且 重置1C 20的輸出係供給至CPU210、重置控制電路510、 D-A 用 SFR241、A-D 用 SFR241、A-D 用 SFR242、WDT 用SFR 244及計時器用SFR 245。Si/Ο用SFR 243包括同 位(parity)、同步型、傳送緩衝暫存器、停止位元（st〇p bit) 之設定用的暫存器等。Give to CPU210. Therefore, the CPU 210 is reset when the power is switched on. The processing after the CPU 210 is reset will be described in detail later. The reset signal output from the reset IC20 is also supplied to the SFR section 240 and reset by hardware. And when the power supply is in the ON state, the OR gate 411 is used to obtain the logical sum. Therefore, even if noise or the like overlaps with any reset signal, only one of the signals becomes the "L" level and is not reset. FIG. 11 is a flowchart showing the operation when the CPU 210 is reset. As shown by 圏, first, if reset, when the reset determination flag 25 is "L" (step ST 1101), it is determined that the reset is performed when the power is turned on, and the reset determination flag 25 is reset. ○ becomes "Η" (step ST 1102), and the initial setting of the register of the CPU is performed (step ST 1103). Next, the initial setting of SFR (R) in the SFR section 240 is performed (step ST 1104). On the other hand, if the reset determination flag 250 is "Η" in step ST 11 〇1, the process proceeds to step ST 1104, and the initial stage of the SFR unit 240 is set. Fig. 12 is a timing chart showing the timing of the signals of each part of the third form of this implementation. In the same figure, (a) indicates VCC 5; (b) indicates VCC 3: (c) indicates a reset signal from the reset IC 20; (d) indicates a CPU reset signal supplied to the CPU 210: (e)値, which indicates that the judgment flag 25 is reset. As shown in the figure, at time T1, although VCC 3 is at the Γ L J level, VCC 5 is still at the Γ Η "level. Therefore, the reset control circuit 410 did not supply Γ L ”This paper size is applicable to the Chinese National Sample Rate (CNS) A4 specification (210 × 297 mm) (please read the precautions on the back before filling this page) Love Journey 4229 4 7 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. The description of the invention (15) reset signal to the CPU 210 without resetting the CPU 210. On the other hand, at time T2, since VCC 5 and VCC 3 are both at the "L" level, the reset control circuit 410 outputs a CPU reset signal of "Ljii level." At this time, the CPU 210 refers to the reset determination flag 250. According to the "n" level or the "LJ level", the reset processing shown in Fig. 11 is performed. As described above, according to the implementation form 3, the reset control circuit 41o is implemented by the VCC 3 The reset signal generated by the reset signal and the reset signal generated by VCC 5 generates the CPU reset signal, so even if the noise overlaps the output of reset 1C 20, 21, etc., the CPU 210 is not easy to reset, but has The effect of the stable operation of the CPU 210. The fourth embodiment is a block diagram showing the structure of the single-chip microcomputer according to the fourth embodiment of the present invention. The same parts as those shown in FIG. 1 are marked with the same Symbols to omit repetitive descriptions. In FIG. 13, 500 indicates the single-chip microcomputer of the fourth embodiment of this implementation; 510 indicates a reset control circuit that generates individual SFR reset signals for resetting SFR243 for Si / 0 The output of reset 1C 20 is supplied to CPU210, reset Control circuit 510, SFR241 for DA, SFR241 for AD, SFR242 for AD, SFR 244 for WDT, and SFR 245 for timer. SFR 243 for Si / 0 includes parity, synchronous, transfer buffer register, stop bit (Stoop bit) register and so on.

第14圖係顯示第13圖之重置控制電路510之詳細之 構造的電路圖。在第14圖中，511、512表示反相器；513 表示反及閘。來自重置判定旗標250的信號及來自重置1C 18 本紙張尺度適用中國國家標牟（CNS ) Μ规格（2!OX297公釐） )11^-----! 裝----.1 丨訂： C請先閲讀背面之注^^項再填寫本頁) U47 A7 _____B7_. _ "X、發明説明（16 ) 20的重置信號分別被輸入至反相器512、511。 其次，説明其動作。 於電源切入時，來自重置1C 20的重置信號被供給至 重置控制電路510、D-A用SFR 242、WDT用SFR 244 及計時器用SFR 245 ,而被硬體地重置。另一方面，若CPU 210被輸入來自重置1C 20的重置信號，則施行後述的動 作。又一方面，來自重置1C 20的重置信號被輸入至重置 控制電路510。電源切入時，重置判定旗標250爲「L」， 而重置信號爲「L」，故重置控制電珞510之反及閘513 的輸出成爲「L」。因此，重置控制電路510輸出「L」 位準的信號，而Si/Ο用SFR被硬體地重置。 第15圖係顯示CPU 210之重置處理之動作的流程圖。 如同圖所示，首先若重置判定旗標250的値爲「L」（步驟 ST 1501)，則判斷成電源切入時的重置，而使重置判定旗 標250成爲Γ Η」（步驟ST 1502)，進而施行CPU 210之暫 存器等的初期設定（步驟ST 1503)、Si/Ο用SFR 243之値 的初期設定（步驟ST 1504)及其他SFR的初期設定（步驟ST 15〇5)。另一方面，在步驟ST 15〇1，若重置判定旗標250 爲「Η」，則CPU 210判斷成熱啓動，並進行至步碌 1505，而不施行SI/O用SFR 243及CPU 210之暫存器等 之値的初期設定動作，進而設定其他SFR的初期値，然後 結束重置處理。 第16圖係顧示第14圖所示之重置控制電路510之輸 出入信號之定時的時序圖。在同圖中，（a)表示輪入至重置 19 ϋ尺國國家標準（CNS ) A4規格（Τϊ^χ297^釐) *-- _ (請先閲讀背面之注意事項再填寫本頁) L丨裝 經濟部中夬橾隼局員工消費合作社印製 422947 A7 ----- B7 五、發明説明（17 ) 控制電路510的重置信號；（b)表示重置判定旗標25〇的 値；（C)表示重置控制電路510所輪出的個別SFR重置信 號°如同圖所示，若重置判定旗標25〇被設定成「Η」位 準，則判斷成非電源切入時，而即使重置信號成爲「L」， 重置控制電路510的輸出信號亦仍爲「Η」位準，故SI/0 用SFR 243未被硬體地重置。 且於電源切入時CPU 210施行第15圖的步驟ST 1504 之前，重置控制電路510有必要將重置信號送至SI/〇用 SFR 243，但是重置控制電路510係以二個反相器及一個 邏辑閘所構成的小型硬體來作信處理，故相對於CPU 210 施行步驟ST 1504者，重置控制電路510之信號送出處理 是相當早施行》 如以上的説明，依據實施的形態四，於電源切入時以 外，即使重置信號成爲Γ L」位準，藉由重置控制電路510 亦不能重置Si/Ο用SFR243，故即使因雜訊等而使重置信 號成爲「L」，SI/O用SFR 243亦未被重置，而SI/0 233 不必要初期設定動作，進而具有能夠於其後連續地繼續動 作的效果。 實施的形態五 第17圖係顯示本發明之實施的形態五之單晶片微電 腦之構造的方塊圖。與第13圖所示部份相同的部份標上相 同的符號，以省略重複的説明。在第17圖與第13圖之不 同處係來自重置控制電路510的個別SFR重置信號不供給 至Si/Ο用SFR 243，而供給至計時器用SFR 245，且重置 20 本紙張尺度適用中國國家標準（CNS > Α4規格（2mx297公瘦） .:.5'^^;*'. .(請先閎讀背面之注意事項再填寫本買)Fig. 14 is a circuit diagram showing a detailed structure of the reset control circuit 510 of Fig. 13. In Figure 14, 511 and 512 represent inverters; 513 represents the inverse AND gate. The signal from the reset judgment flag 250 and the reset 1C 18 This paper size is applicable to China National Standards (CNS) M specifications (2! OX297 mm)) 11 ^ -----! Loading ----. 1 丨 Order: C Please read the note ^^ on the back before filling this page) U47 A7 _____B7_. _ &Quot; X, invention description (16) 20 The reset signals are input to the inverters 512, 511, respectively. Next, the operation will be described. When the power is switched on, the reset signal from reset 1C 20 is supplied to the reset control circuit 510, SFR 242 for D-A, SFR 244 for WDT, and SFR 245 for timer, and is reset by hardware. On the other hand, when a reset signal from the reset 1C 20 is input to the CPU 210, the operation described later is performed. In another aspect, a reset signal from the reset 1C 20 is input to the reset control circuit 510. When the power is switched on, the reset determination flag 250 is "L" and the reset signal is "L", so the output of the reset control circuit 510 and the output of the gate 513 become "L". Therefore, the reset control circuit 510 outputs a signal at the "L" level, and Si / 0 is reset by hardware using SFR. FIG. 15 is a flowchart showing the operation of the reset processing of the CPU 210. As shown in the figure, first, if 値 of the reset determination flag 250 is "L" (step ST 1501), it is determined that the reset when the power is switched on, and the reset determination flag 250 becomes Γ Η "(step ST 1502), and further perform the initial setting of the register of the CPU 210 (step ST 1503), the initial setting of the Si / O SFR 243 (step ST 1504), and the initial setting of other SFRs (step ST 1505) . On the other hand, in step ST 1501, if the reset determination flag 250 is "Η", the CPU 210 determines that it is a hot start, and proceeds to step 1505 without executing SI / O SFR 243 and CPU 210. The initial setting operation of a register such as a register, and then the initial registers of other SFRs are set, and then the reset processing is ended. Fig. 16 is a timing chart showing the timing of the input and output signals of the reset control circuit 510 shown in Fig. 14. In the same figure, (a) indicates the rotation to reset of the 19-inch national standard (CNS) A4 specification (Tϊ ^ χ297 ^ 297) *-_ (Please read the precautions on the back before filling this page) L丨 Printed by the Consumer Affairs Cooperative of the China Bureau of the Ministry of Economic Affairs, printed 422947 A7 ----- B7 V. Description of the invention (17) Reset signal of control circuit 510; (b) Representation of reset judgment flag 25 ; (C) represents the individual SFR reset signal that is reset by the reset control circuit 510. As shown in the figure, if the reset determination flag 25 is set to the "Η" level, when it is judged that the power is not switched on, And even if the reset signal becomes "L", the output signal of the reset control circuit 510 is still at the "Η" level, so the SFR 243 for SI / 0 is not reset by hardware. Before the CPU 210 executes step ST 1504 of FIG. 15 when the power is switched on, it is necessary for the reset control circuit 510 to send a reset signal to SI / 〇 SFR 243, but the reset control circuit 510 uses two inverters And the small hardware constituted by a logic gate is used for letter processing, so the signal sending process of the reset control circuit 510 is executed relatively early compared to the case where the CPU 210 performs step ST 1504. "As explained above, according to the implementation form 4. Except when the power is switched on, even if the reset signal becomes Γ L level, the S / 243 for Si / 0 cannot be reset by the reset control circuit 510, so even if the reset signal becomes “L” due to noise, etc. ", SI / O SFR 243 has not been reset, and SI / 0 233 does not require initial setting operation, and has the effect that it can continue to operate continuously thereafter. Embodiment 5 Fig. 17 is a block diagram showing the structure of a single-chip microcomputer according to Embodiment 5 of the present invention. The same parts as those shown in Fig. 13 are marked with the same symbols to omit repeated descriptions. The difference between Figure 17 and Figure 13 is that the individual SFR reset signal from the reset control circuit 510 is not supplied to SFR 243 for Si / 0, but to SFR 245 for timer, and reset 20. This paper size applies China National Standard (CNS > Α4 specification (2mx297 male thin).:. 5 '^^; *'.. (Please read the precautions on the back before filling in this purchase)

、1T 經濟部中央標準局員工消費合作社印製 422947 A7 B7 經濟部中央標準局貝Η消費合作社印策 五、發明説明（18 ) 1C 20所輸出的重置信號係供給至CPU 210、重置控制電 路 510、D-A 用 SFR241、A-D 用 SFR242、Si/Ο 用 SFR 243、WDT用SFR 244。且在第17圖中，600表示實施 的形態五的單晶片微電腦。 第18圖係顯示CPU 210之重置處理之動作的流程圖。 與第15圖相同的部份標上相同的符號，以省略重複説明。 第18圖與第15圖之不同處在於步騍ST 1801、步騍ST 1802。亦即，在步騍ST 1801，設定計時器用SFR 245的 初期値，且在步驟ST 1802，設定計時器用SFR 245以外 之SFR的初期値。 因此，在此實施的形態五中，於電源切入時以外，即 使重置信號成爲「L」位準，藉由重置控制電路510亦不 能重置計時器用SFR 245，故即使因雜訊等而使重置信號 成爲「L」，計時器用SFR 254亦不被重置，而計時器235 不必要初期設定動作，進而具有能夠於其後連續地繼續動 作的效果。 實施的形態六 第19圖係顯示本發明之實施的形態六之單晶片微電 腦之構造的方塊圖。與第13圖所示的部份相同的部份標上 相同的符號，以省略重複的説明。第19圖與第13圖之不 同處係來自重置控制電路510的個別SFR重置信號不供給 至Si/Ο用SFR 243，而供給至A-D用SFR 242，且重置ic 20所輸出的重置信號被供給至CPU 210、重置控制電路 510、b-A 用 SFR 241、Si/Ο 用 SFR 243、WDT 用 SFR 244 » ^^^1- ^^^1 kn^ nx «n I - - I n^i 、請先閱讀背面之注意事項再填寫本頁) ---訂------·ν-------i------ 本紙張尺度適用中國國家標牟（CNS ) Α4規格（210X297公楚） 經濟部中央標隼局員工消費合作社印製 4229 47 A? B7 五、發明説明（19 ) 及計時器用SFR245。又在第19圖中，700表示此實施的 形態六的單晶片微電腦。 第20圖係顯示CPU210之重置處理之動作的流程圖。 與第15圖相同的部份標上相同的符號，以省略重複的説 明。第20圖與第15圖之不同處在於步騍ST 2001、步驟 ST 2002。亦即，在步驟ST 2001，設定A-D用SFR 242 的初期値，而在步驟ST 2002，設定A-D用SFR 242以外 之SFR的初期値。 因此，在此實施的形態六中，於電源切入時以外，即 使重置信號成爲「LJ位準，藉由重置控制電路510而亦 不能重置A-D用SFR 242，故即使因雜訊等而使重置信號 成爲「L」，A-D用SFR 242亦不被重置，而A-D變換器 232亦不必要初期設定動作，進而具有能夠於其後連續地 繼續動作的效果。 實施的形態七 第21圖係顯示本發明之實施的形態七之單晶片微電 腦之構造的方塊圖。與第13圖所示的部份相同的部份標上 相同的符號，以省略重複的説明。第21圖第13圖之不同 處係來自重置控制電路510的個別SFR重置信號不供給至 SI/O用SFR 243，而供給至A-D用SFR 241，且重置1C 20 所輸出的重置信號係供給至CPU 210、重置控制電路510、 A-D 用 SFR242、SI/O 用 SFR243、WDT 用 SFR2 44 及計 時器用SFR245。又在第21圖中800表示此實施的形態七 的單晶片微電腦。 1;------Ί f------訂------方 (請先閲讀背面之注意事項再填寫本頁) 22 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 422947 經濟部中央橾率局員Η消費合作社印製 A7 —____B7 _. 五 '發明説明（20 ) 第22圖係顯示CPU210之重置處理之動作的流程圖。 與第15圖相同的部份標上相同的符號，以省略重複的説 明。第22圖與第15圖之不同處在於步躁st 2201、步隸 ST 2202。亦即’在步躁ST 2201，設定D-A用SFR 241 的初期値’且在步碌ST 2202，設定D-A用SFR 241以外 之SFR的初期値。 因此’在此實施的形態七中，於電源切入時以外，即 使重置1s號成爲「L」位準，藉由重置控制電路51〇亦不 能重置D-A用SFR 241，故即使因雜訊等而使重置信號成 爲「L J ’ D-A用SFR 241亦不被重置，而D-A變換器231 亦不必要初期設定動作，進而具有能夠於其後連續地繼續 動作的效果。 < 實施的形態八 第23圖係顯示本發明之實施的形態八之單晶片微電 腦之構造的方塊圖。與第1圖所示的部价相同的部份標上 相同的符號，以省略重複的説明。在第23圖中，900表示 此實施的形態八的單晶片微電腦；910表示重置控制電 路’其藉由重置1C 20所輪出的重置信號、WDT 234所輸 出之表示CPU 210失控的WDT中斷信號及重置判定旗標 250 ’而輸出WDT用SFR 244的個別重置信號。且重置IC 20的輸出係供給至CPU 210、重置控制電路910、D-A用 SFR241、A-D 用 SFR 242、Si/Ο 用 SFR243 及計時器用 SFR 245 。 第24圖係顯示第23圖之重置控制電路910之詳細構 23 本纸張尺度適用中國國家標準（CNS ) Α4規格（2Ι0Χ297公釐） 壤···'···"· (請先閲讀背面之注^一^項再填寫本頁) -m 裝---- ^ n H - - n I ^--- n n· ----- [.. 經濟部中央標準局員工消費合作社印裝 422947 A7 B7 — - ~ — I » - 五、發明説明（21 ) 造的電路圖。在第24圖中，911、912表示反相器；931 表示反及閘；914表示及閘（AND gate)。來自重置判定旗 標250的信號及來自重置1C 20的重置信號分別輸A至反 相器911、912。且及閛914輸出WDT用SFR244之硬體 之重置用的重置信號。 其次，説明其動作。 於電源切入時，藉由來自重置1C 20的輸出信號而重 置CPU 210、WDT用SFR 244以外的SFR。將於後詳述 CPU 210的重置處理。如實施的形態一中所説明者，重置 控制電路910之反及閘913的輸出成爲「LJ，不管WDT 中斷信號而及閑914均輸出「L」位準的信號。因此，「LJ 位準的信號供給至WDT用SFR 244，而被硬體地重置。 其後，在電源爲ON的狀態下，若WDT 234判斷CPU 210正常動作，則Γ Η」位準的信號被輸出至CPU 210及 重置控制電路910。於此場合，及閘914之連接至WDT 234 侧的輸入端子成爲「H」位準，而及閘914的輸出信號成 爲與反及閛913的輸出信號相同。另一方面，若WDT 234 檢測出CPU 210失控，則Γ L」位準的WDT中斷信號送 至CPU 210及重置控制電路910»若CPU 210接收此信號， 則停止動作。若Γ L」位準的WDT中斷信號被輸入至重 置控制電路910，則及閘914的輪出係不論輸入至其另一 輪入端子之信號的狀態而均成爲Γ L」位準。因此WDT 用SFR 244被硬體地重置。 第25圖係顯示CPU 210之重置處理之動作的流程圖。 本紙張尺度適用中國國家樣隼（CNS ) A4規格（210X297公楚） :.(請先閲讀背面之注意事項再填寫本頁) Ί— I—. —..——----i .裝：------tr:—一---Γ— A7 B71T printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 422947 A7 B7 printed by the Central Standards Bureau of the Ministry of Economic Affairs of the Beiya Consumer Cooperatives V. Description of the Invention (18) The reset signal output by 1C 20 is supplied to the CPU 210, reset control Circuits 510, SFR241 for DA, SFR242 for AD, SFR 243 for Si / O, and SFR 244 for WDT. In Fig. 17, reference numeral 600 indicates a single-chip microcomputer of the fifth embodiment. FIG. 18 is a flowchart showing the operation of the reset processing of the CPU 210. The same parts as those in FIG. 15 are marked with the same symbols to omit repeated description. The difference between FIG. 18 and FIG. 15 lies in steps ST 1801 and ST 1802. That is, in step ST1801, the initial stage of SFR 245 for timer is set, and in step ST1802, the initial stage of SFR other than SFR 245 for timer is set. Therefore, in the fifth form of this implementation, even when the power is switched on, even if the reset signal becomes the "L" level, the timer control S510 cannot be reset by the reset control circuit 510. By setting the reset signal to "L", the timer SFR 254 is not reset, and the timer 235 does not need to be initially set to operate, and has the effect that it can continue to operate continuously thereafter. Embodiment 6 FIG. 19 is a block diagram showing the structure of a single-chip microcomputer according to Embodiment 6 of the present invention. The same parts as those shown in Fig. 13 are marked with the same symbols to omit duplicate descriptions. The difference between FIG. 19 and FIG. 13 is that the individual SFR reset signal from the reset control circuit 510 is not supplied to SFR 243 for Si / 0, but is supplied to SFR 242 for AD, and the weight output from reset ic 20 is reset. Set signal is supplied to CPU 210, reset control circuit 510, SFR 241 for bA, SFR 243 for Si / O, SFR 244 for WDT »^^^ 1- ^^^ 1 kn ^ nx« n I--I n ^ i, please read the notes on the back before filling this page) --- Order ------ · ν ------- i ------ This paper size is applicable to Chinese national standards ( CNS) Α4 specification (210X297). Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 4229 47 A? B7 5. Description of the invention (19) and SFR245 for timers. In Fig. 19, 700 indicates a single-chip microcomputer of the sixth embodiment. FIG. 20 is a flowchart showing the operation of the reset processing of the CPU 210. The same parts as those in Fig. 15 are marked with the same symbols to omit duplicate explanations. The difference between Fig. 20 and Fig. 15 lies in steps ST 2001 and ST 2002. That is, in step ST2001, the initial stage of SFR 242 for A-D is set, and in step ST2002, the initial stage of SFR other than SFR 242 for A-D is set. Therefore, in the form 6 of this implementation, even when the power is switched on, even if the reset signal is at the "LJ level", the SFR 242 for AD cannot be reset by resetting the control circuit 510. By setting the reset signal to "L", the SFR 242 for AD is not reset, and the AD converter 232 does not need to be initially set to operate, and has the effect of being able to continue the operation continuously thereafter. Embodiment 7 FIG. 21 is a block diagram showing the structure of a single-chip microcomputer according to Embodiment 7 of the present invention. The same parts as those shown in Fig. 13 are marked with the same symbols to omit duplicate descriptions. The difference between FIG. 21 and FIG. 13 is that the individual SFR reset signal from the reset control circuit 510 is not supplied to SFR 243 for SI / O, but is supplied to SFR 241 for AD, and the reset output is reset by 1C 20 The signals are supplied to the CPU 210, the reset control circuit 510, SFR242 for AD, SFR243 for SI / O, SFR2 44 for WDT, and SFR245 for timer. In Fig. 21, 800 indicates a single-chip microcomputer according to the seventh embodiment of the present invention. 1; ------ Ί f ------ order ------ party (please read the notes on the back before filling out this page) 22 This paper size applies to China National Standard (CNS) A4 specifications (210X297mm) 422947 Printed by the Central Government Bureau of the Ministry of Economic Affairs and Consumer Cooperatives A7 —____ B7 _. Five 'Description of Invention (20) Figure 22 is a flowchart showing the operation of the reset processing of CPU210. The same parts as those in Fig. 15 are marked with the same symbols to omit duplicate explanations. The difference between Fig. 22 and Fig. 15 lies in the step st 2201 and the step ST 2202. That is, "the initial stage of SFR 241 for D-A is set in step ST 2201" and the initial stage of SFR other than SFR 241 for D-A is set in step ST 2202. Therefore, in the form 7 of this implementation, even when the power is switched on, even if the 1s number is reset to the "L" level, the SFR 241 for DA cannot be reset by resetting the control circuit 51. As a result, the reset signal becomes "LJ 'DA SFR 241 is not reset, and the DA converter 231 does not need to be set initially, and has the effect of being able to continue the operation continuously thereafter. ≪ Implementation form FIG. 23 is a block diagram showing the structure of a single-chip microcomputer according to the eighth embodiment of the present invention. The same parts as those shown in FIG. 1 are marked with the same symbols to omit repeated descriptions. In the figure 23, 900 indicates the single-chip microcomputer of the eighth form of this implementation; 910 indicates the reset control circuit, which resets the reset signal rotated by 1C 20 and WDT 234 indicates that the WDT interrupt that the CPU 210 is out of control Signal and reset judgment flag 250 'to output individual reset signals for WDT SFR 244. The output of reset IC 20 is supplied to CPU 210, reset control circuit 910, SFR 241 for DA, SFR 242 for AD, Si / Ο SFR243 and Timer SFR 245. Figure 24 shows the detailed structure of the reset control circuit 910 shown in Figure 23. The paper size applies to the Chinese National Standard (CNS) A4 specification (2Ι0 × 297 mm). ··· '·· " · ( Please read the notes on the back ^ a ^ before you fill out this page) -m equipment ---- ^ n H--n I ^ --- nn · ----- [.. Staff Consumption of the Central Standards Bureau of the Ministry of Economic Affairs Cooperative printed 422947 A7 B7 —-~ — I »-V. Circuit diagram of invention (21). In Figure 24, 911 and 912 represent inverters; 931 represents reverse gate; 914 represents AND gate (AND gate). The signal from the reset judgment flag 250 and the reset signal from the reset 1C 20 are input to the inverters 911 and 912, respectively, and the 914 outputs the reset weight of the hardware of SFR244 for WDT. When the power is switched on, the CPU 210 and the SFR other than the WDT SFR 244 are reset by the output signal from the reset 1C 20. The reset processing of the CPU 210 will be described in detail later. As explained in the first aspect of the implementation, the output of the inverse of the reset control circuit 910 and the gate 913 becomes "LJ," regardless of the WDT interrupt signal, and the idle 914 outputs "L". Level signal. Therefore, the "LJ level signal is supplied to the WDT SFR 244 and is reset by hardware. After that, when the power is ON, if WDT 234 determines that the CPU 210 is operating normally, Γ Η" level The signals are output to the CPU 210 and the reset control circuit 910. In this case, the input terminal connected to the WDT 234 side of the AND gate 914 becomes the "H" level, and the output signal of the AND gate 914 becomes the same as the output signal of the inverse 閛 913. On the other hand, if the WDT 234 detects that the CPU 210 is out of control, a WDT interrupt signal at the Γ L ″ level is sent to the CPU 210 and the reset control circuit 910 »If the CPU 210 receives this signal, it stops the operation. If a WDT interrupt signal at the Γ L ″ level is input to the reset control circuit 910, the wheel output of the AND gate 914 becomes the Γ L ″ level regardless of the state of the signal input to another of its round-in terminals. Therefore, the WDT is reset by hardware with SFR 244. FIG. 25 is a flowchart showing the operation of the reset processing of the CPU 210. This paper size is applicable to China National Sample (CNS) A4 specification (210X297). (Please read the precautions on the back before filling this page) Ί— I—. —..——---- i. ： ------ tr: — 一 --- Γ— A7 B7

A2294T 五、發明説明（22 ) 與第15圖相同的部份標上相同的符號，以省略重複的説 明。第25圖與第15圖之不同處在於步驟ST 25〇ι、步碌 ST 2502。亦即，在步驟ST 2501，設定WDT用SFR 244 的初期値’而在步驟ST 2502，設定WDT用SFR 244以外 之SFR的初期値。 第26圖係顯示第24圖所示之重置控制電路91〇之輪 出入電路之定時的時序圖。在同圖中’（a)表示被輸入至重 置控制電路910的重置信號；（b)表示重置判定旗標的値； (c)表示WDT 234所輸出的WDT中斷信號：（d)表示作爲重 置控制電路910之輸出信號的WDT用SFR重置信號。在 如第26圖所示之時序圖的時間T1 ，若重置信號成爲 「L」，則於重置判定旗標250爲「Η」位準且WDT中 斷信號爲「Η」時，WDT用SFR重置信號成爲Γ η」。 另一方面，在時間Τ2,若WDT中斷信號成爲「L」，亦 即於WDT 234檢測出CPU210失控時，WDT用SFR重置 信號成爲「L」，而施行WDT 234之硬體的重置。 且在上述的説明中，雖然重置控制電路910的輸出信 號僅供給至WDT用SFR 244，但是對於其他SFR亦可代 替相同來自重置1C 20的重置信號而供給之。 如以上説明，依據實施的形態八，藉由WDT 234的監 視，而於CPU 210失控時強制地施行特定之SFR的重置， 因此具有能夠施行具穩定性之重置控制的效果。 且在上述之實施的形態一至八中，亦可以將重置1C之 至少一者設於單晶片微電腦的内部。 25 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 X 297公釐} (請先閲讀背面之注意事項再填寫本頁) 裝-------訂-- 經濟部中央標準局員工消費合作社印製 4229 47 A7 B7 五、發明説明（23 )又本發明可利用於例如電手機器之控制等所使用的微 電腦。 :.·:.;:{#·:先掀讀背面之注意事項再填窟本頁.) :裝- -39 經濟部中央標率局貝工消費合作社印裝 26 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐）A2294T V. Description of the invention (22) The same parts as in Figure 15 are marked with the same symbols to omit repetitive explanations. The difference between FIG. 25 and FIG. 15 lies in step ST 250 and step ST 2502. That is, in step ST2501, the initial stage of SFR 244 for WDT is set, and in step ST2502, the initial stage of SFRs other than SFR 244 for WDT is set. Fig. 26 is a timing chart showing the timing of the wheel access circuit of the reset control circuit 91o shown in Fig. 24. In the figure, '(a) represents the reset signal input to the reset control circuit 910; (b) represents 値 of the reset judgment flag; (c) represents the WDT interrupt signal output by the WDT 234: (d) represents The WDT SFR reset signal is an output signal of the reset control circuit 910. At time T1 of the timing chart shown in FIG. 26, if the reset signal becomes "L", when the reset determination flag 250 is "Η" level and the WDT interrupt signal is "Η", the WDT uses SFR The reset signal becomes Γ η ″. On the other hand, at time T2, if the WDT interrupt signal becomes "L", that is, when WDT 234 detects that the CPU 210 is out of control, the WDT SFR reset signal becomes "L", and the hardware reset of WDT 234 is performed. In the above description, although the output signal of the reset control circuit 910 is only supplied to the WDT SFR 244, other SFRs may be supplied instead of the same reset signal from the reset 1C 20. As described above, according to the implementation of the eighth form, by monitoring the WDT 234, a specific SFR reset is forcibly executed when the CPU 210 is out of control, so it has the effect of being able to implement a stable reset control. And in the implementation forms 1 to 8 described above, at least one of the reset 1Cs may also be set inside the single-chip microcomputer. 25 This paper size applies to China National Standard (CNS) A4 (2 丨 0 X 297 mm) (Please read the precautions on the back before filling this page) Loading ----- Order-Central Standard of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives 4229 47 A7 B7 V. Invention Description (23) The invention can also be used in microcomputers such as the control of mobile phones.: ..:.; :: {# ·: First read the back Note for refilling this page.): Packing--39 Printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 26 The paper size applies to the Chinese National Standard (CNS) Α4 specification (210 × 297 mm)

Claims (1)

ABOD 42294T 六、申請專利範圍 1. 一種具有重置控制功能之微電脂，藉由外部所輸人 的重置信號而施行重置動作，且上述微電腦包括： 中央處理部，施行上述微電腦的總括處理； 周邊功能部，用以施行既定的動作.； 周邊功能暫存器部，可硬體地重置，而用以設定上述 周邊功能部的動作； 第一旗標，儲存依據上述外部重置信號之輸入所造成 之上述中央處理部的重置動作是否爲自上述微電腦之電源 切入時最初之重置動作的資訊；以及 重置控制部係若表示儲存於掌置判定旗標之資訊爲最 初的重置動作，則於被輸入外部重置信號時送出硬韙地重 置上述周邊功能暫存器部的暫存器重置信號，而若表示儲 存於重置判定旗標之資訊非爲最初的重置動作，則於被輸 入外部重置信號時不送出上述暫存器重置信號，藉此以施 行上述周邊功能暫存器部的重置控制。 2. 如申請專利範圍第1項所述的具有重置控制功能之 微電腦’其中周邊功能部包括將類比信號變換成數位信號 的A-D變換器，且周邊功能暫存器部包括上述a_d變換器 之動作設定用的暫存器。 3. 如申請專利範圍第1項所述的具有重置控制功能之 微電腦’其中周邊功能部包括將數位信號變換成類比/信號 的D-A變換器，且周邊功能暫存器部包括上述D-A變換器 之動作設定用的暫存器。 4. 如申請專利範圍第1項所述的具有重置控制功能之 本紙張从適财闕 III·— — — — — 卜裝 ili (請先聞讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印11 ----線-I----Γ-IU —---- 蛵濟部中央標準局員工消費合作社印製 4229 47 as -------------- 六、申請專$範園 微電腦’其中周邊功能部包括串列地施行信號之輪出入控 制的串列輪出入裝置，且周邊功能暫存器部包括上述串列 輪出入裝置之動作設定用的暫存器。 5. 如申請專利範圍第1項所述的具有重置控制功能之 微電腦’其中周邊功能部包括施行計時功能的計時器，且 周邊功能暫存器部包括上逑計時器之動作設定用的暫存 器° 6. 如申請專利範圍第1項所述的具有重置控制功能之 微電腦’其中周邊功能部包括於監視中央處理部之失控而 判斷爲上述中央處理部失控的場合輸出表示失控之信號的 監視計時器*且周邊功能暫存器部包括上述監視計時器之 動作設定用的暫存器。 7 如申請專利範圍第6項所述的具有重置控制功能之 微電脂，其中於監視計時器輸出表示失控之信號的場合， 重置控制部係不論儲存於第一旗標的資訊而送出暫存器重 置信號，以施行周邊功能暫存器部的重置控制。 8,如申請專利範圍第1項所述的具有重置控制功能之 微電腦，其中更包括第二旗標，且上述第二旗標係儲存有 依賴於第一旗標而施行周邊功能暫存器部之重置的旗標依 賴模式或不依賴於上述第一旗標而施行上述周邊功能暫存 器部之重置的旗標非依賴模式的資訊，又重置控制部係若 上述第二旗標儲存表示旗標非依賴模式的資訊，則於外部 重置信號被輸入時不論上述第一旗標所儲存的資訊而送出 暫存器重置信號至上述周邊功能暫存器部。 本纸張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先聞讀背面之.注項再填寫本頁) -裝---------訂--1. 線-----t---- _1 I -. J--.!x----- 4229 47 A8 B8 _ a__ 六、申請專利範圍 9.一種具有重置控制功能之微電瑙，被供給第一電躁 及第二電源，而上述微電腦包括： 中央處理部，施行上述微電腦的總括處理，且受上述 第一電源所驅動； 周邊功能部，施行既定的動作，且受上述第二電源所 驅動：以及 重置控制部，僅於輸入由上述第一電源所產生的第一 重置信號及由上述第二電源所產生的第二重置信號兩者的 場合，將施行上述中央處理部之重置的信號送出至上逑中 央處理部，以施行上述中央處理部的重置控制。 4 -I: ^^^1 —- - - I. ίΛ» I I i^n c請先閲讀背面之注意事項再填寫本頁} --—訂--- 經濟部中央樣準局員工消費合作社印製 線一---I----Γ---ru---- 本紙張尺度適用巾關家標準（CNS) A4· ( 21Qx297,>jft }ABOD 42294T VI. Application for patent scope 1. A micro-electric grease with reset control function, which performs reset action by reset signal input from outside, and the above microcomputer includes: a central processing unit that executes the above-mentioned microcomputer summary Processing; Peripheral function section for performing predetermined actions .; Peripheral function register section, which can be reset in hardware, and is used to set the actions of the peripheral function section; First flag, stored according to the above external reset Whether the reset action of the central processing unit caused by the input of the signal is the information of the initial reset action when the power of the microcomputer is switched on; and if the reset control unit indicates that the information stored in the judgment flag is the initial Reset action, when the external reset signal is input, the register reset signal of the above-mentioned peripheral function register is sent to reset the register. If the information indicating that the flag is stored in the reset judgment flag is not the initial one, Reset operation, when the external reset signal is input, the register reset signal is not sent, so as to perform the reset of the peripheral function register unit System. 2. The microcomputer with reset control function described in item 1 of the scope of the patent application, wherein the peripheral function section includes an AD converter that converts analog signals into digital signals, and the peripheral function register section includes the above-mentioned a_d converter. Register for action setting. 3. The microcomputer with reset control function described in item 1 of the scope of patent application, wherein the peripheral function section includes a DA converter that converts digital signals into analog / signal, and the peripheral function register section includes the DA converter described above. Register for operation setting. 4. The paper with reset control function as described in item 1 of the scope of patent application is from Shicai 阙 III. — — — — — Bu Zili (please read the precautions on the back before filling this page) Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Justice 11 ---- line-I ---- Γ-IU ------ Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4229 47 as -------- ------ VI. Apply for a special Fanyuan Microcomputer, where the peripheral function section includes a tandem wheel input device that performs wheel input / output control in series, and the peripheral function register section includes the tandem wheel input device. Register for operation setting. 5. The microcomputer with a reset control function as described in item 1 of the scope of the patent application, wherein the peripheral function section includes a timer that performs a timing function, and the peripheral function register section includes a temporary setting for the operation of the timer. 6. The microcomputer with reset control function as described in item 1 of the scope of the patent application, where the peripheral function section includes monitoring the central processing section for out of control and judges that the central processing section is out of control, and outputs a signal indicating out of control. The watchdog timer * includes a register for setting the operation of the watchdog timer. 7 The micro-electric grease with reset control function as described in item 6 of the scope of patent application, where the watchdog timer outputs a signal indicating runaway, the reset control unit sends a temporary message regardless of the information stored in the first flag. Register reset signal to perform reset control of the peripheral function register section. 8. The microcomputer with reset control function described in item 1 of the scope of patent application, which further includes a second flag, and the second flag stores a temporary register that performs peripheral functions depending on the first flag. The reset flag dependent mode of the ministry or the non-dependent mode of the reset flag of the peripheral function register that implements the peripheral function register that does not depend on the first flag, and resets the control unit if the second flag The flag stores information indicating the flag-independent mode, and when an external reset signal is input, a register reset signal is sent to the peripheral function register unit regardless of the information stored in the first flag. This paper size is applicable to Chinese National Standard (CNS) Α4 specification (210X297 mm) (Please read the back. Note before filling out this page) -Install --------- Order--1. Line ----- t ---- _1 I-. J-.! x ----- 4229 47 A8 B8 _ a__ VI. Scope of patent application 9. A microelectric agate with reset control function is The first microcomputer and the second power source are supplied, and the microcomputer includes: a central processing unit that performs the overall processing of the microcomputer and is driven by the first power source; a peripheral function unit that performs a predetermined action and receives the second power source Driven: and the reset control unit will execute the central processing unit only when both the first reset signal generated by the first power source and the second reset signal generated by the second power source are input. The reset signal is sent to the central processing unit of the upper loop to perform the reset control of the central processing unit. 4 -I: ^^^ 1 —---I. ίΛ »II i ^ nc Please read the notes on the back before filling out this page} --- Order --- Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs Line 1 --- I ---- Γ --- ru ---- This paper size is applicable to the family standard (CNS) A4 · (21Qx297, > jft}
TW085113425A 1996-09-20 1996-11-04 Microcomputer having reset control function TW422947B (en)

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