JP3480721B2 - Power on / off sequence controller - Google Patents
Power on / off sequence controllerInfo
- Publication number
- JP3480721B2 JP3480721B2 JP2001046768A JP2001046768A JP3480721B2 JP 3480721 B2 JP3480721 B2 JP 3480721B2 JP 2001046768 A JP2001046768 A JP 2001046768A JP 2001046768 A JP2001046768 A JP 2001046768A JP 3480721 B2 JP3480721 B2 JP 3480721B2
- Authority
- JP
- Japan
- Prior art keywords
- sequence
- control signal
- output
- interval time
- types
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Power Sources (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は電源オン／オフシー
ケンス制御装置に関し、特に、電源のオン／オフを順序
付けて行う電源オン／オフシーケンス制御装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply on / off sequence control device, and more particularly to a power supply on / off sequence control device for sequentially turning on / off a power supply.
【０００２】[0002]
【従来の技術】この種の従来例について図面を参照して
説明する。2. Description of the Related Art A conventional example of this type will be described with reference to the drawings.
【０００３】図５は従来の電源オン／オフシーケンス制
御装置の一例を示すブロック図である。FIG. 5 is a block diagram showing an example of a conventional power on / off sequence control device.
【０００４】図５において、この従来例のパソコンシス
テム用電源装置１０１は、実開平５−２３２３２号公報
の開示内容を示し、複数のコンセント１０８は、ＣＰＵ
１０４とディスプレイ１０５，プリンタ１０６及びハー
ドディスク１０７の周辺機器との電源プラグが差し込ま
れる。選択スイッチ１０２は各コンセント１０８に電源
供給する設定をＣＰＵと周辺機器とに対応して行う。タ
イマー回路１０９はマスタスイッチ１０３により電源の
投入又は切断が行われたとき予め設定された時間間隔と
順序とに従ってコンセント１０８に電源の投入又は切断
を行う。In FIG. 5, a power supply device 101 for a personal computer system of this conventional example shows the disclosed contents of Japanese Utility Model Laid-Open No. 5-23232, and a plurality of outlets 108 are CPUs.
The power plugs of 104, the display 105, the printer 106, and the peripheral devices of the hard disk 107 are inserted. The selection switch 102 sets power supply to each outlet 108 corresponding to the CPU and peripheral devices. The timer circuit 109 turns on or off the power of the outlet 108 according to a preset time interval and order when the power is turned on or off by the master switch 103.
【０００５】[0005]
【発明が解決しようとする課題】この従来例において
は、タイマー回路がマスタスイッチにより手動で電源の
投入又は切断が行われたとき、予め設定された時間間隔
と順序とによってコンセントに電源の投入又は切断を行
う構成になっているので、外部からの制御信号によっ
て、電源をオンする順序またはオフする順序を任意に変
更することができず、また、その時間間隔も変更するこ
とができないという問題点がある。In this conventional example, when the timer circuit is manually turned on or off by the master switch, the outlet is turned on or off according to a preset time interval and order. Since it is configured to disconnect, it is not possible to arbitrarily change the power-on sequence or the power-off sequence by an external control signal, and the time interval cannot be changed. There is.
【０００６】（発明の目的）本発明の目的は、電圧レベ
ルの異なる複数の電源をオンする順序またはオフする順
序シーケンスを外部からの制御信号によって任意に変更
が可能であり、更にその順序シーケンス内の時間間隔を
変更することができる電源オン／オフシーケンス制御装
置を提供することにある。(Object of the Invention) It is an object of the present invention that the order of turning on or turning off a plurality of power supplies having different voltage levels can be arbitrarily changed by a control signal from the outside, and further within the order sequence. It is an object of the present invention to provide a power-on / off sequence control device capable of changing the time interval of.
【０００７】[0007]
【課題を解決するための手段】本発明の電源オン／オフ
シーケンス制御装置は、複数種類の入力電圧を出力電圧
として出力させるのに前記複数の数から考えられる複数
個の順序シーケンスを予め記憶する第１の記憶手段と、
前記順序シーケンス内の各出力電圧間の間隔時間のデー
タを複数種類予め記憶する第２の記憶手段と、前記複数
種類の入力電圧を前記出力電圧として出力（オン）又は
出力断（オフ）する場合に、外部から第１の制御信号を
受信する前記第１の記憶手段から前記第１の制御信号の
内容に対応する順序シーケンスを選出し、前記外部から
第２の制御信号を受信すると前記第２の記憶手段から前
記第２の制御信号に対応する間隔時間のデータを選出
し、前記複数種類の入力電圧を前記選出した順序シーケ
ンスで且つ前記選出した間隔時間で出力（オン）又は出
力断（オフ）させる出力制御手段とを有し、また、前記
第１及び第２の記憶手段及び出力制御手段を含む機能手
段並びに前記複数種類の入力電圧及び出力電圧，前記第
１の制御信号，前記順序シーケンス決定信号，前記間隔
時間制御信号及び第２の制御信号を含む信号を接続する
複数の端子が一チップのＬＳＩとして構成されている。The power supply on / off sequence control device of the present invention stores in advance a plurality of sequential sequences that can be considered from the plurality of numbers to output a plurality of types of input voltages as output voltages. A first storage means,
Second storage means for pre-storing a plurality of types of interval time data between the output voltages in the sequence sequence, and a case of outputting (on) or disconnecting (off) the plurality of types of input voltages as the output voltages In addition, an order sequence corresponding to the contents of the first control signal is selected from the first storage means that receives a first control signal from the outside, and the second sequence is received when the second control signal is received from the outside. Data of the interval time corresponding to the second control signal is selected from the storage means, and the plurality of types of input voltages are output (on) or output off (off) in the selected sequence sequence and at the selected interval time. ) Output control means, and the functional means including the first and second storage means and the output control means, the plurality of types of input voltage and output voltage, the first control signal, the Introduction sequence decision signal, a plurality of terminals for connecting the signal including the interval time control signal and the second control signal is configured as a chip LSI of.
【０００８】本発明の電源オン／オフシーケンス制御装
置は、複数種類の入力電圧を出力電圧として出力させる
前記複数の数から考えられる複数個の順序シーケンスを
予め記憶としていて外部からの第１の制御信号及び順序
シーケンス決定信号の受信によって前記複数種類の入力
電圧の出力時（オン時）及び出力断時（オフ時）の動作
シーケンスを前記記憶の複数個の順序シーケンスから選
出してシーケンス出力信号を出力するシーケンス回路
と、前記順序シーケンス内の各出力電圧間の間隔時間デ
ータを予め複数種類記憶し、前記外部からの間隔時間制
御信号及び第２の制御信号を受信すると前記シーケンス
回路からの前記シーケンス出力信号を前記間隔時間制御
信号の内容によって前記記憶の複数種類の間隔時間デー
タから選出した前記間隔時間に従って順次ゲート制御信
号として出力するディレイ回路と、このディレイ回路か
らの前記ゲート制御信号によって順次開閉されて前記複
数種類の入力電圧を前記シーケンス回路で決定された順
序で前記出力電圧として出力させる複数のゲート回路と
を有し、また、前記シーケンス回路，前記ディレイ回路
及び前記複数のゲート回路並びに前記複数種類の入力電
圧及び出力電圧，前記第１の制御信号，前記順序シーケ
ンス決定信号，前記間隔時間制御信号及び第２の制御信
号を含む信号を接続する複数の端子が一チップのＬＳＩ
として構成されている。The power-on / off sequence control device of the present invention has a plurality of sequential sequences, which can be considered from the above-mentioned number of output voltages of a plurality of kinds of input voltages, stored in advance and has a first external control. By receiving the signal and the sequence sequence determination signal, the operation sequence at the time of output (on) and output interruption (off) of the plurality of types of input voltages is selected from the plurality of sequence sequences stored in the memory, and a sequence output signal is obtained. A sequence circuit for outputting and a plurality of types of interval time data between output voltages in the sequence sequence are stored in advance, and when the interval time control signal and the second control signal from the outside are received, the sequence from the sequence circuit is received. The output signal is selected from a plurality of types of interval time data stored in the memory according to the content of the interval time control signal. A delay circuit that sequentially outputs as a gate control signal according to an interval, and a plurality of types of input voltages that are sequentially opened and closed by the gate control signal from the delay circuit and output as the output voltage in the order determined by the sequence circuit. A plurality of gate circuits, the sequence circuit, the delay circuit, the plurality of gate circuits, the plurality of types of input voltage and output voltage, the first control signal, the sequence determination signal, and the interval. An LSI in which a plurality of terminals for connecting signals including a time control signal and a second control signal are one chip
Is configured as.
【０００９】本発明の電源オン／オフシーケンス制御装
置は、複数種類の入力電圧を出力電圧として出力させる
のに前記複数の数から考えられる順序シーケンスを予め
記憶する第１の記憶部と前記順序シーケンス内の各出力
電圧間の間隔時間のデータを複数種類予め記憶する第２
の記憶部とを含むメモリと、前記間隔時間の時間を発生
するタイマと、外部からの第１の制御信号及び順序シー
ケンス決定信号の受信によって前記複数種類の入力電圧
の出力時（オン時）及び出力断時（オフ時）の前記順序
シーケンス決定信号の内容に対応する順序シーケンスを
前記メモリ内の前記第１の記憶部から選出し、前記外部
からの間隔時間制御信号及び第２の制御信号を受信する
と前記間隔時間制御信号の内容に対応する間隔時間デー
タを前記メモリ内の前記第２の記憶部から選出し、前記
選出した順序シーケンス及び間隔時間データを基にし前
記タイマから発生する間隔時間に従って順次にゲート制
御信号を出力するＣＰＵと、前記ゲート制御信号によっ
て前記複数種類の入力電圧のそれぞれが入力されていて
前記ゲート制御信号によって開閉され前記複数の種類の
出力電圧として出力（オン）及び出力断（オフ）させる
複数のゲート回路とを有し、また、前記メモリ，前記タ
イマ，前記ＣＰＵ及び前記複数のゲート回路を含む回路
並びに前記複数種類の入力電圧及び出力電圧，前記第１
の制御信号，前記順序シーケンス決定信号，前記間隔時
間制御信号及び第２の制御信号を含む信号を接続する複
数の端子が一チップのＬＳＩとに構成されている。The power-on / off sequence control device of the present invention includes a first storage section for storing in advance a sequence sequence considered from the plurality of numbers for outputting a plurality of types of input voltages as output voltages, and the sequence sequence. A plurality of types of data of the interval time between the output voltages in
A memory including a storage unit, a timer that generates the interval time, and a plurality of types of input voltages that are output (on) when receiving a first control signal and an order sequence determination signal from the outside. An order sequence corresponding to the contents of the order sequence determination signal when the output is cut off (off) is selected from the first storage unit in the memory, and the interval time control signal and the second control signal from the outside are selected. Upon reception, interval time data corresponding to the content of the interval time control signal is selected from the second storage unit in the memory, and based on the selected sequence sequence and interval time data, according to the interval time generated by the timer. A CPU for sequentially outputting a gate control signal and the gate control signal to which each of the plurality of types of input voltages is input by the gate control signal. A circuit that includes a plurality of gate circuits that are opened and closed by the above to output (on) and output (off) the plurality of types of output voltages, and that includes the memory, the timer, the CPU, and the plurality of gate circuits. And the plurality of types of input voltage and output voltage, the first
Of the control signal, the sequence determination signal, the interval time control signal and the second control signal are connected to a single chip LSI.
【００１０】[0010]
【発明の実施の形態】次に、本発明について図面を参照
して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【００１１】図１は本発明の第１の実施の形態の電源シ
ーケンサ１は、一チップのＬＳＩ内に構成され、端子
（以下Ｔ）１−１，１−２，１−３のそれぞれには、入
力電圧Ｖｉａ，Ｖｉｂ，Ｖｉｃが接続され、Ｔ１−４，
１−５にはそれぞれ入力電圧Ｖｉａ，Ｖｉｂ，Ｖｉｃを
出力させる場合の間隔時間を制御する間隔時間制御信号
Ｔ０，Ｔ１が接続され、Ｔ１−６には内部のディレイ回
路９に対するプログラミング制御信号が接続され、Ｔ１
−７，Ｔ１−８には内部のシーケンス回路８に対して入
力電圧Ｖｉａ，Ｖｉｂ，Ｖｉｃのオン，オフの順序を予
め設定された最大８種類の順序に設定するシーケンサ制
御信号，動作シーケンス信号が接続され、Ｔ１−９，Ｔ
１−１０，Ｔ１−１１には入力電圧のシーケンス制御さ
れた出力電圧Ｖｏａ，Ｖｏｂ，Ｖｏｃが出力される。FIG. 1 shows a power supply sequencer 1 according to a first embodiment of the present invention, which is configured in a one-chip LSI and has terminals (hereinafter T) 1-1, 1-2, 1-3 respectively. , Input voltages Via, Vib, Vic are connected, and T1-4,
Interval time control signals T0 and T1 for controlling the interval time when outputting the input voltages Via, Vib, and Vic are connected to 1-5, and a programming control signal for the internal delay circuit 9 is connected to T1-6. And T1
In -7 and T1-8, there are a sequencer control signal and an operation sequence signal for setting the ON / OFF order of the input voltages Via, Vib, and Vic to the internal sequence circuit 8 in a preset maximum of eight kinds of order. Connected, T1-9, T
Output voltages Voa, Vob, and Voc, which are sequence-controlled input voltages, are output to 1-10 and T1-11.
【００１２】電源シーケンサ１の内部には、Ｔ１−７及
びＴ１−８からのシーケンサ制御信号ＯＥ及び動作シー
ケンス信号Ａ［２：０］の受信によって入力電圧Ｖｉ
ａ，Ｖｉｂ，Ｖｉｃのオン時（出力時）及びオフ時（出
力断）の動作シーケンスを予め記憶している複数の動作
シーケンスの中から一つを決定して出力信号Ｓａ，Ｓ
ｂ，Ｓｃを出力するシーケンス回路８と、出力Ｓａ，Ｓ
ｂ，Ｓｃ及びＴ１−４〜Ｔ１−５からの間隔時間制御信
号Ｔ０，Ｔ１，Ｔ１−６からのプログラミング制御信号
ＷＥを受信して動作シーケンスの間隔時間を決定してゲ
ート制御信号Ｃｓａ，Ｃｓｂ，Ｃｓｃをシーケンス回路
８で決定した順序で出力するディレイ回路９と、Ｔ１−
１，Ｔ１−２，Ｔ１−３からの入力電圧Ｖｉａ，Ｖｉ
ｂ，Ｖｉｃをディレイ回路９からのゲート制御信号Ｃｓ
ａ，Ｃｓｂ，Ｃｓｃによって出力順序及び相互の時間間
隔が制御されて、Ｔ１−９，Ｔ１−１０，Ｔ１−１１へ
出力電圧Ｖｏａ，Ｖｏｂ，Ｖｏｃとして出力させるゲー
ト回路１１−１，１１−２，１１−３とを有している。In the power supply sequencer 1, the input voltage Vi is received by receiving the sequencer control signal OE and the operation sequence signal A [2: 0] from T1-7 and T1-8.
The output signals Sa, S are determined by deciding one of a plurality of operation sequences in which a, vib, and Vic are turned on (outputting) and off (outputting off) in advance.
sequence circuit 8 for outputting b, Sc and outputs Sa, S
b, Sc and the programming control signal WE from the interval time control signals T0, T1, T1-6 from T1-4 to T1-5 to determine the interval time of the operation sequence to determine the gate control signals Csa, Csb, A delay circuit 9 for outputting Csc in the order determined by the sequence circuit 8;
1, input voltages Via, Vi from T1-2 and T1-3
b and Vic are gate control signals Cs from the delay circuit 9
The output order and mutual time intervals are controlled by a, Csb, and Csc, and the gate circuits 11-1 and 11-2, which output the output voltages Voa, Vob, and Voc to T1-9, T1-10, and T1-11, respectively. 11-3.
【００１３】図２は本第１の実施の形態の電源シーケン
スにおけるシーケンス回路の入力制御信号による入力電
圧に対する予め設定された出力電圧の動作シーケンス及
び間隔時間の設定情報を示す図で、（ａ）はＯＮ時，Ｏ
ＦＦ時の入力電圧に対する出力電圧の動作シーケンスの
一例を示す図、（ｂ）は間隔時間の設定情報の一例を示
す図である。FIG. 2 is a diagram showing a preset operation sequence of the output voltage with respect to the input voltage by the input control signal of the sequence circuit in the power supply sequence of the first embodiment and setting information of the interval time. Is ON when ON
FIG. 6 is a diagram showing an example of an operation sequence of the output voltage with respect to the input voltage at the time of FF, and FIG. 6B is a diagram showing an example of setting information of the interval time.
【００１４】図２において、本第１の実施の形態の電源
シーケンサ１においては、例えば、Ｔ１−８の動作シー
ケンス信号Ａ［２：０］として“００１”が入力され、
シーケンサ信号ＯＥとしてＴ１−７に“０”信号の入力
されたとすると、入力電圧Ｖｉａ，Ｖｉｂ，Ｖｉｃを出
力させるＯＮ時には出力電圧としてＶｏａ→Ｖｏｃ→Ｖ
ｏｂの順に出力させ、ＯＦＦ時には同様な信号の入力さ
れると、シーケンス回路８によってＶｏｂ→Ｖｏｃ→Ｖ
ｏａの順に出力電圧が停止させることをしめしている。In FIG. 2, in the power supply sequencer 1 of the first embodiment, for example, "001" is input as the operation sequence signal A [2: 0] of T1-8,
Assuming that a "0" signal is input to T1-7 as the sequencer signal OE, the output voltage is Voa → Voc → V at the ON time when the input voltages Via, Vib, Vic are output.
When the same signal is input at the time of OFF, the sequence circuit 8 outputs Vob → Voc → V.
The output voltage is stopped in the order of oa.
【００１５】また、ＯＮ時及びＯＦＦ時の各出力電圧の
間隔は、例えばＴ１−４，１−５に間隔時間制御信号Ｔ
０，Ｔ１としてそれぞれに“０”，“１”が入力される
と、シーケンス回路８で決定された順序の各順序間の間
隔時間は１０ｎ秒であることが決定される。The intervals between the output voltages at ON and OFF are, for example, T1-4 and 1-5 at the interval time control signal T.
When "0" and "1" are input as 0 and T1, respectively, it is determined that the interval time between the sequences determined by the sequence circuit 8 is 10 ns.
【００１６】即ち、上記の例においては、ＯＮ時には最
初Ｖｏａを出力し、次に１０ｎ秒後にＶｏｃ、そのまた
１０秒ｎ後にＶｏｂを出力させるべく、ディレイ回路９
がゲート回路１１−１〜１１−３にゲート制御信号Ｃｓ
ａ，Ｃｓｂ，Ｃｓｃを出力する。That is, in the above example, the delay circuit 9 outputs Voa first when ON, then Voc after 10 n seconds, and Vob after 10 seconds n.
Is applied to the gate circuits 11-1 to 11-3 by the gate control signal Cs.
It outputs a, Csb, and Csc.
【００１７】次に、本第１の実施の形態の電源シーケン
サ１の動作について図１，図２を参照して説明する。Next, the operation of the power supply sequencer 1 according to the first embodiment will be described with reference to FIGS.
【００１８】本第１の実施の形態の電源シーケンサ１に
おいては、シーケンス回路８は、予め図２の（ａ）に示
す動作シーケンスがプログラミングされている。外部か
らの信号、シーケンサ制御信号（ＯＥ）及び動作シーケ
ンス信号（Ａ［２：０］）の値によって、シーケンス回
路８はシーケンス回路出力信号（Ｓａ，Ｓｂ，Ｓｃ）
を、それぞれ任意の時間間隔で出力する。ここでは例と
して１ｎ秒。図２の（ｂ）の通り１ｎ秒は次段のディレ
イ回路９の最小電源投入間隔時間である。つまり、動作
シーケンス信号（Ａ［２：０］）が０で且つシーケンサ
制御信号（ＯＥ）が０の場合、Ｓａ→（１ｎ秒間隔）→
Ｓｂ→（１ｎ秒間隔）→Ｓｃとなる。ディレイ回路９で
は、前段のシーケンス回路８からの出力信号である、シ
ーケンス回路出力信号（Ｓａ，Ｓｂ，Ｓｃ）の時間間隔
を、更に図２の（ｂ）に示す通り、間隔時間制御信号
（Ｔ０，Ｔ１）の値によって予め決められた時間間隔で
ゲート制御信号（ＣＳａ，ＣＳｂ，ＣＳｃ）をそれぞれ
出力する。ディレイ回路９のプログラミングは、ディレ
イ回路プログラミング制御信号（ＷＥ）をイネーブルに
して、任意の値を間隔時間制御信号（Ｔ０，Ｔ１）で書
き込むことが可能である。ディレイ回路９より出力され
たゲート制御信号（ＣＳａ，ＣＳｂ，ＣＳｃ）は、それ
ぞれのゲート回路１１−１〜１１−３へ繁がり、入力電
圧２（Ｖｉａ，ｖｉｂ，Ｖｉｃ）を、それぞれ間隔時間
制御信号（Ｔ０，Ｔ１）の間隔時間による順序で出力電
圧（Ｖｏａ，Ｖｏｂ，Ｖｏｃ）として出力する。In the power supply sequencer 1 of the first embodiment, the sequence circuit 8 is programmed in advance with the operation sequence shown in FIG. The sequence circuit 8 outputs the sequence circuit output signals (Sa, Sb, Sc) according to the values of the signal from the outside, the sequencer control signal (OE), and the operation sequence signal (A [2: 0]).
Are output at arbitrary time intervals. Here, as an example, 1 n seconds. As shown in FIG. 2B, 1 ns is the minimum power-on interval time of the delay circuit 9 in the next stage. That is, when the operation sequence signal (A [2: 0]) is 0 and the sequencer control signal (OE) is 0, Sa → (1 n second interval) →
Sb → (1n second interval) → Sc. In the delay circuit 9, the time interval of the sequence circuit output signals (Sa, Sb, Sc), which is the output signal from the sequence circuit 8 of the preceding stage, is further changed to the interval time control signal (T0 as shown in FIG. , T1) to output the gate control signals (CSa, CSb, CSc) at predetermined time intervals. For programming the delay circuit 9, it is possible to enable the delay circuit programming control signal (WE) and write an arbitrary value with the interval time control signal (T0, T1). The gate control signals (CSa, CSb, CSc) output from the delay circuit 9 propagate to the respective gate circuits 11-1 to 11-3 to control the input voltage 2 (Via, vib, Vic) by the interval time. The signals (T0, T1) are output as output voltages (Voa, Vob, Voc) in the order according to the interval time.
【００１９】電源ＯＦＦ時も同様に、動作シーケンス信
号（Ａ［２：０］）が０で且つシーケンサ制御信号（Ｏ
Ｅ）が０の場合、シーケンス回路８からＳｃ→（１ｎ秒
間隔）→Ｓｂ→（１ｎ秒間隔）→Ｓａの順に出力信号が
出力され、ディレイ回路９からは間隔時間制御信号（Ｔ
０，Ｔ１）の値によって、ＯＮの場合と同様に、ゲート
信号（ＣＳａ，ＣＳｂ，ＣＳｃ）をそれぞれ出力する。Similarly, when the power is off, the operation sequence signal (A [2: 0]) is 0 and the sequencer control signal (O
When E) is 0, the sequence circuit 8 outputs an output signal in the order of Sc → (1n second interval) → Sb → (1n second interval) → Sa, and the delay circuit 9 outputs the interval time control signal (T).
0, T1), the gate signals (CSa, CSb, CSc) are respectively output as in the case of ON.
【００２０】図３は本発明の第２の実施の形態の電源シ
ーケンサを示すブロック図である。FIG. 3 is a block diagram showing a power sequencer according to the second embodiment of the present invention.
【００２１】図３においては、本第２の実施の形態の電
源シーケンサ１Ａは、図１に示す電源シーケンサ１と異
なり、シーケンス回路８及びディレイ回路９の独立した
２回路の代りに、ＣＰＵ１０によってこの２回路と同等
な制御を行う。In FIG. 3, the power sequencer 1A of the second embodiment is different from the power sequencer 1 shown in FIG. 1 in that instead of the two independent circuits of the sequence circuit 8 and the delay circuit 9, it is replaced by the CPU 10. Performs control equivalent to two circuits.
【００２２】即ち、電源シーケンサ１Ａは、電源シーケ
ンサ１と、同様に端子（Ｔ）１１−１〜１−１１を有
し、また、同じ番号のＴには同じ入出力電圧及び同じ信
号が接続され、間隔時間制御信号Ｔ０，Ｔ１，プログラ
ミング制御信号ＷＥ，シーケンサ制御信号ＯＥ及び動作
シーケンス信号Ａ［２：０］にインタフェースしてゲー
ト信号ＣＳａ，ＣＳｂ，ＣＳｃを出力するＩ／Ｏ回路１
０ａと、図２の（ａ）及び（ｂ）に対応するデータを格
納しているメモリ１０ｂと、間隔時間の基となるデータ
を出力するタイマ１０ｃと、Ｉ／Ｏ回路１０ａからの入
力信号によって、メモリ１０ｂ，タイマ１０ｃを制御し
てＩ／Ｏ回路１０ａからゲート制御信号ＣＳａ，ＣＳ
ｂ，ＣＳｃを出力するＣＰＵ１０とを有し、他は電源シ
ーケンサ１と同様な構成を有している。That is, the power supply sequencer 1A has terminals (T) 11-1 to 1-11 similarly to the power supply sequencer 1, and the same input / output voltage and the same signal are connected to Ts having the same number. , I / O circuit 1 for interfacing with the interval time control signals T0, T1, programming control signal WE, sequencer control signal OE and operation sequence signal A [2: 0] to output gate signals CSa, CSb, CSc
0a, a memory 10b that stores data corresponding to (a) and (b) of FIG. 2, a timer 10c that outputs data that is the basis of the interval time, and an input signal from the I / O circuit 10a. , The memory 10b, the timer 10c to control the gate control signals CSa, CS from the I / O circuit 10a.
It has a CPU 10 that outputs b and CSc, and otherwise has the same configuration as the power sequencer 1.
【００２３】本第２の実施の形態の電源シーケンサ１Ａ
の動作は、電源シーケンサ１のシーケンス回路８及びデ
ィレイ回路９の代りにＣＰＵ１０がメモリ１０ｂ，タイ
マ１０ｃを制御して電源シーケンサ１の場合と同様にゲ
ート制御信号ＣＳａ，ＣＳｂ，ＣＳｃをＩ／Ｏ回路１０
ａから出力しており、詳細な動作説明を省略する。Power supply sequencer 1A of the second embodiment
In the operation of, the CPU 10 controls the memory 10b and the timer 10c in place of the sequence circuit 8 and the delay circuit 9 of the power sequencer 1 and outputs the gate control signals CSa, CSb, CSc to the I / O circuit as in the case of the power sequencer 1. 10
Since it is output from a, detailed description of the operation is omitted.
【００２４】図４は本発明の第３の実施の形態の電源シ
ーケンサを示すブロック図である。FIG. 4 is a block diagram showing a power supply sequencer according to the third embodiment of the present invention.
【００２５】図４において、本第３の実施の形態の電源
シーケンサ１ａは、図１に示す第１の実施の形態の電源
シーケンサ１に対して、入力電圧が３以上の場合に拡張
した場合の構成となっており、シーケンス回路８ａ、デ
ィレイ回路９ａおよびゲート回路１１ａ−１〜１１ａ−
ｎはそれぞれシーケンス回路８，ディレイ回路９および
ゲート回路１１−１〜１１−３に対応するものである。In FIG. 4, the power supply sequencer 1a of the third embodiment is the same as the power supply sequencer 1 of the first embodiment shown in FIG. 1 when the input voltage is extended to 3 or more. The sequence circuit 8a, the delay circuit 9a, and the gate circuits 11a-1 to 11a- are configured.
n corresponds to the sequence circuit 8, the delay circuit 9 and the gate circuits 11-1 to 11-3, respectively.
【００２６】また、シーケンス回路８ａには入力電圧Ｖ
ｉａ〜Ｖｉｎに対応して、最大ｎ階乗（ｎ！）の種類の
動作シーケンスが格納されてあり、ディレイ回路９ａで
は間隔時間制御信号Ｔ０〜Ｔｍに対応して最大２m 個の
間隔時間を発生することができる。The input voltage V is applied to the sequence circuit 8a.
The maximum n factorial (n!) types of operation sequences are stored corresponding to ia to Vin, and the delay circuit 9a stores a maximum of 2 m interval times corresponding to the interval time control signals T0 to Tm. Can occur.
【００２７】従って、本第３の実施の形態の電源シーケ
ンサ１ａの入力電圧Ｖｉａ〜Ｖｉｎに対する出力電圧Ｖ
ｏａ〜ＶｏｎのＯＮ時、ＯＦＦ時の動作シーケンス及び
そのシーケンス内の間隔時間は、それぞれ、外部から入
力される動作シーケンス信号Ａ［ｋ：０］及び間隔時間
制御信号Ｔ０〜Ｔｍの二値符号データによって決定され
る。Therefore, the output voltage V with respect to the input voltages Via to Vin of the power supply sequencer 1a of the third embodiment.
The operation sequence when the oa to Von are ON and OFF and the interval time in the sequence are the binary coded data of the operation sequence signal A [k: 0] and the interval time control signals T0 to Tm, which are input from the outside, respectively. Determined by
【００２８】尚、入力電圧の個数をｎとした場合、ｎ！
≦２k の関係によってｋのビット数が決められる。When the number of input voltages is n, n!
The number of bits of k is determined by the relationship of ≦ 2 k .
【００２９】本第３の実施の形態の電源シーケンサ１ａ
の動作については、図１に示す第１の実施の形態の動作
シーケンス１とほぼ同等なので詳細な動作説明を省略す
る。Power supply sequencer 1a of the third embodiment
1 is almost the same as the operation sequence 1 of the first embodiment shown in FIG.
【００３０】[0030]
【発明の効果】以上説明したように本発明は、複数種類
の入力電圧を出力電圧として出力させるのに複数の数か
ら考えられる複数個の順序シーケンスを予め記憶する第
１の記憶手段と、順序シーケンス内の各出力電圧間の間
隔時間のデータを複数種類予め記憶する第２の記憶手段
と、複数種類の入力電圧を前記出力電圧として出力（オ
ン）又は出力断（オフ）する場合に、外部から第１の制
御信号を受信すると第１の記憶手段から第１の制御信号
の内容に対応する順序シーケンスを選出し、外部から第
２の制御信号を受信すると第２の記憶手段から第２の制
御信号に対応する間隔時間のデータを選出し、複数種類
の入力電圧を選出した順序シーケンスで且つ選出した間
隔時間で出力（オン）又は出力断（オフ）させる出力制
御手段とを備えることにより、電圧レベルの異なる複数
の入力電圧を出力（オン）するまたは出力断（オフ）す
る順序シーケンスを外部からの信号によって任意に変更
することができ、更にその順序シーケンス内の間隔時間
も任意に変更することができるので、複数の電圧を使用
する装置に適した電圧の入力及び切断の順序シーケンス
を提供することができる効果がある。As described above, according to the present invention, the first storage means for storing in advance a plurality of sequence sequences that can be considered from a plurality of numbers for outputting a plurality of types of input voltages as output voltages, A second storage unit that stores in advance a plurality of types of data of the interval time between the output voltages in the sequence, and an external device that outputs (ON) or disconnects (OFF) the plurality of types of input voltages as the output voltages. When the first control signal is received from the first storage means, an order sequence corresponding to the contents of the first control signal is selected from the first storage means, and when the second control signal is received from the outside, the second storage means outputs the second sequence from the second storage means. And output control means for selecting data of the interval time corresponding to the control signal and outputting (turning on) or disconnecting (turning off) the output at a selected sequence time in a selected sequence of a plurality of types of input voltages. Allows the sequence sequence of outputting (turning on) or disconnecting (turning off) a plurality of input voltages having different voltage levels to be arbitrarily changed by a signal from the outside, and the interval time in the sequence sequence is also arbitrary. Therefore, it is possible to provide an order sequence of voltage input and disconnection suitable for a device using a plurality of voltages.
【００３１】また、一チップのＬＳＩ化にすることによ
り、使用する装置に大きな場所をとらずに組込ませるこ
とができる効果がある。Further, by forming a one-chip LSI, there is an effect that it can be incorporated in a device to be used without taking up a large space.
【図１】本発明の第１の実施の形態の電源シーケンサを
示すブロック図である。FIG. 1 is a block diagram showing a power supply sequencer according to a first embodiment of this invention.
【図２】本第１の実施の形態の電源シーケンサにおける
シーケンス回路の入力制御信号による入力電圧に対する
予め設定された出力電圧の動作シーケンス及び間隔時間
の設定情報を示す図で、（ａ）はＯＮ時のＯＦＦ時の入
力電圧に対する出力電圧の動作シーケンスの一例を示す
図、（ｂ）は間隔時間の設定情報の一例を示す図であ
る。FIG. 2 is a diagram showing an operation sequence of an output voltage set in advance for an input voltage according to an input control signal of a sequence circuit in the power supply sequencer of the first embodiment and setting information of an interval time, in which (a) is ON. Is a diagram showing an example of an operation sequence of the output voltage with respect to the input voltage at the time of OFF, and (b) is a diagram showing an example of setting information of the interval time.
【図３】本発明の第２の実施の形態の電源シーケンサを
示すブロック図である。FIG. 3 is a block diagram showing a power supply sequencer according to a second embodiment of this invention.
【図４】本発明の第３の実施の形態の電源シーケンサを
示す図である。FIG. 4 is a diagram showing a power sequencer according to a third embodiment of the present invention.
【図５】従来の電源オン／オフシーケンス制御装置の一
例を示すブロック図である。FIG. 5 is a block diagram showing an example of a conventional power on / off sequence control device.
１，１Ａ，１ａ 電源シーケンサ
１−１〜１−１１，１ａ−１〜１ａ−ｎ，１ａ−２１〜
１ａ−２ｍ，１ａ−３１，１ａ−４１，１ａ−５１，１
ａ−６１〜１ａ−６ｎ 端子（Ｔ）
８，８ａ シーケンス回路
９，９ａ ディレイ回路
１０ ＣＰＵ
１０ａ Ｉ／Ｏ回路
１０ｂ メモリ
１０ｃ タイマ
１１−１，１１−２，１１−３ ゲート回路
１１ａ−１，〜１１ａ−ｎ ゲート回路
Ａ［２：０］，Ａ［ｋ：０］ 動作シーケンス信号
ＯＥ シーケンサ制御信号
Ｔ０，Ｔ１，〜Ｔｍ 間隔時間制御信号1, 1A, 1a Power sequencer 1-1 to 1-11, 1a-1 to 1a-n, 1a-21 to
1a-2m, 1a-31, 1a-41, 1a-51, 1
a-61 to 1a-6n Terminal (T) 8, 8a Sequence circuit 9, 9a Delay circuit 10 CPU 10a I / O circuit 10b Memory 10c Timer 11-1, 11-2, 11-3 Gate circuit 11a-1, ... 11a-n gate circuits A [2: 0], A [k: 0] operation sequence signal OE sequencer control signals T0, T1, to Tm interval time control signal
Claims (6)
力させるのに前記複数の数から考えられる複数個の順序
シーケンスを予め記憶する第１の記憶手段と、前記順序
シーケンス内の各出力電圧間の間隔時間のデータを複数
種類予め記憶する第２の記憶手段と、前記複数種類の入
力電圧を前記出力電圧として出力（オン）又は出力断
（オフ）する場合に、外部から第１の制御信号を受信す
ると前記第１の記憶手段から前記第１の制御信号の内容
に対応する順序シーケンスを選出し、前記外部から第２
の制御信号を受信すると前記第２の記憶手段から前記第
２の制御信号に対応する間隔時間のデータを選出し、前
記複数種類の入力電圧を前記選出した順序シーケンスで
且つ前記選出した間隔時間で出力（オン）又は出力断
（オフ）させる出力制御手段とを備えることを特徴とす
る電源オン／オフシーケンス制御装置。1. A first storage means for pre-storing a plurality of sequence sequences considered from the plurality of numbers for outputting a plurality of kinds of input voltages as output voltages, and between each output voltage in the sequence sequence. Second storage means for preliminarily storing a plurality of types of interval time data, and a first control signal from the outside when outputting (on) or disconnecting (off) the plurality of types of input voltages as the output voltages. Is received, an order sequence corresponding to the contents of the first control signal is selected from the first storage means, and a second sequence is selected from the outside.
When the control signal is received, the data of the interval time corresponding to the second control signal is selected from the second storage means, and the plurality of kinds of input voltages are selected in the selected sequence and at the selected interval time. A power supply on / off sequence control device, comprising: an output control means for outputting (on) or cutting off (off) the output.
御手段を含む機能手段並びに前記複数種類の入力電圧及
び出力電圧，前記第１の制御信号，前記順序シーケンス
決定信号，前記間隔時間制御信号及び第２の制御信号を
含む信号を接続する複数の端子が一チップのＬＳＩとし
て構成されていることを特徴とする請求項１記載の電源
オン／オフシーケンス制御装置。2. A functional means including the first and second storage means and an output control means, the plurality of types of input voltage and output voltage, the first control signal, the order sequence determination signal, and the interval time control. 2. The power-on / off sequence control device according to claim 1, wherein the plurality of terminals for connecting the signal and the signal including the second control signal are configured as a one-chip LSI.
力させる前記複数の数から考えられる複数個の順序シー
ケンスを予め記憶としていて外部からの第１の制御信号
及び順序シーケンス決定信号の受信によって前記複数種
類の入力電圧の出力時（オン時）及び出力断時（オフ
時）の動作シーケンスを前記記憶の複数個の順序シーケ
ンスから選出してシーケンス出力信号を出力するシーケ
ンス回路と、前記順序シーケンス内の各出力電圧間の間
隔時間データを予め複数種類記憶し、前記外部からの間
隔時間制御信号及び第２の制御信号を受信すると前記シ
ーケンス回路からの前記シーケンス出力信号を前記間隔
時間制御信号の内容によって前記記憶の複数種類の間隔
時間データから選出した前記間隔時間に従って順次ゲー
ト制御信号として出力するディレイ回路と、このディレ
イ回路からの前記ゲート制御信号によって順次開閉され
て前記複数種類の入力電圧を前記シーケンス回路で決定
された順序で前記出力電圧として出力させる複数のゲー
ト回路とを有することを特徴とする電源オン／オフシー
ケンス制御装置。3. A plurality of sequence sequences considered from the plurality of numbers for outputting a plurality of types of input voltages as output voltages are stored in advance, and the first sequence control signal and the sequence sequence determination signal are received from the outside to obtain the sequence sequence. A sequence circuit for selecting an operation sequence when a plurality of kinds of input voltages are output (on) and an output disconnection (off) from the plurality of sequence sequences stored in the memory, and outputting a sequence output signal; A plurality of types of interval time data between the respective output voltages are stored in advance, and when the interval time control signal and the second control signal from the outside are received, the sequence output signal from the sequence circuit is converted into the content of the interval time control signal. According to the interval time selected from a plurality of types of interval time data stored by the And a plurality of gate circuits that are sequentially opened and closed by the gate control signal from the delay circuit to output the plurality of types of input voltages as the output voltages in the order determined by the sequence circuit. Characteristic power on / off sequence control device.
及び前記複数のゲート回路並びに前記複数種類の入力電
圧及び出力電圧，前記第１の制御信号，前記順序シーケ
ンス決定信号，前記間隔時間制御信号及び第２の制御信
号を含む信号を接続する複数の端子が一チップのＬＳＩ
として構成されていることを特徴とする請求項３記載の
電源オン／オフシーケンス制御装置。4. The sequence circuit, the delay circuit, the plurality of gate circuits, the plurality of types of input voltage and output voltage, the first control signal, the sequence determination signal, the interval time control signal, and the second. LSI with multiple terminals for connecting signals including control signals
The power-on / off sequence control device according to claim 3, wherein the power-on / off sequence control device is configured as follows.
力させるのに前記複数の数から考えられる順序シーケン
スを予め記憶する第１の記憶部と前記順序シーケンス内
の各出力電圧間の間隔時間のデータを複数種類予め記憶
する第２の記憶部とを含むメモリと、前記間隔時間の時
間を発生するタイマと、外部からの第１の制御信号及び
順序シーケンス決定信号の受信によって前記複数種類の
入力電圧の出力時（オン時）及び出力断時（オフ時）の
前記順序シーケンス決定信号の内容に対応する順序シー
ケンスを前記メモリ内の前記第１の記憶部から選出し、
前記外部からの間隔時間制御信号及び第２の制御信号を
受信すると前記間隔時間制御信号の内容に対応する間隔
時間データを前記メモリ内の前記第２の記憶部から選出
し、前記選出した順序シーケンス及び間隔時間データを
基にし前記タイマから発生する間隔時間に従って順次に
ゲート制御信号を出力するＣＰＵと、前記ゲート制御信
号によって前記複数種類の入力電圧のそれぞれが入力さ
れていて前記ゲート制御信号によって開閉されて前記複
数の種類の出力電圧として出力（オン）及び出力断（オ
フ）させる複数のゲート回路とを有することを特徴とす
る電源オン／オフシーケンス制御装置。5. A first storage unit that stores in advance a sequence sequence that can be considered from the plurality of numbers for outputting a plurality of types of input voltages as output voltages, and an interval time between each output voltage in the sequence sequence. A memory including a second storage unit that stores a plurality of types of data in advance, a timer that generates the time of the interval time, and a plurality of types of input by receiving a first control signal and an order sequence determination signal from the outside. An order sequence corresponding to the contents of the order sequence determination signal at the time of voltage output (on) and output off (off) is selected from the first storage section in the memory;
When receiving the interval time control signal and the second control signal from the outside, interval time data corresponding to the content of the interval time control signal is selected from the second storage unit in the memory, and the selected sequence sequence. And a CPU that sequentially outputs a gate control signal according to the interval time generated from the timer based on the interval time data, and each of the plurality of types of input voltages is input by the gate control signal, and is opened / closed by the gate control signal. And a plurality of gate circuits for outputting (on) and cutting off (off) the plurality of types of output voltages.
び前記複数のゲート回路を含む回路並びに前記複数種類
の入力電圧及び出力電圧，前記第１の制御信号，前記順
序シーケンス決定信号，前記間隔時間制御信号及び第２
の制御信号を含む信号を接続する複数の端子が一チップ
のＬＳＩとに構成されていることを特徴とする請求項５
記載の電源オン／オフシーケンス制御装置。6. A circuit including the memory, the timer, the CPU, and the plurality of gate circuits, the plurality of types of input voltage and output voltage, the first control signal, the sequence determination signal, and the interval time control. Signal and second
6. A plurality of terminals for connecting signals including the control signal according to claim 1 are configured in one-chip LSI.
The power on / off sequence control device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001046768A JP3480721B2 (en) | 2001-02-22 | 2001-02-22 | Power on / off sequence controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001046768A JP3480721B2 (en) | 2001-02-22 | 2001-02-22 | Power on / off sequence controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002251230A JP2002251230A (en) | 2002-09-06 |
| JP3480721B2 true JP3480721B2 (en) | 2003-12-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001046768A Expired - Fee Related JP3480721B2 (en) | 2001-02-22 | 2001-02-22 | Power on / off sequence controller |
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| Country | Link |
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| JP (1) | JP3480721B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10725516B2 (en) | 2017-08-28 | 2020-07-28 | Samsung Electronics Co., Ltd. | Semiconductor device and power off method of a semiconductor device |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4038134B2 (en) | 2003-02-05 | 2008-01-23 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Power supply control apparatus and information processing apparatus |
| JP2006107127A (en) * | 2004-10-05 | 2006-04-20 | Nec Electronics Corp | Semiconductor integrated circuit device |
| JP4581933B2 (en) * | 2005-09-14 | 2010-11-17 | 日本電気株式会社 | Power supply system, portable device, and power-on sequence control method used therefor |
| JP5043356B2 (en) * | 2006-03-31 | 2012-10-10 | 三菱電機株式会社 | Programmable controller activation method and programmable controller |
| JP5876277B2 (en) * | 2011-11-21 | 2016-03-02 | ローム株式会社 | Power control device |
| JP6189340B2 (en) * | 2012-02-24 | 2017-08-30 | クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ | Method and apparatus for load switch controller |
| JP5867173B2 (en) * | 2012-03-05 | 2016-02-24 | 株式会社リコー | Power activation control device |
| JP6365475B2 (en) * | 2015-09-15 | 2018-08-01 | 京セラドキュメントソリューションズ株式会社 | Power supply control circuit and image forming apparatus |
| JP6917819B2 (en) * | 2017-07-28 | 2021-08-11 | ローム株式会社 | Sequence controller and electronics |
| CN116643140A (en) * | 2022-02-15 | 2023-08-25 | 华为技术有限公司 | Integrated circuit and testing method thereof |
-
2001
- 2001-02-22 JP JP2001046768A patent/JP3480721B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10725516B2 (en) | 2017-08-28 | 2020-07-28 | Samsung Electronics Co., Ltd. | Semiconductor device and power off method of a semiconductor device |
| US11379028B2 (en) | 2017-08-28 | 2022-07-05 | Samsung Electronics Co., Ltd. | Semiconductor device and power off method of a semiconductor device |
| US11709537B2 (en) | 2017-08-28 | 2023-07-25 | Samsung Electronics Co., Ltd. | Semiconductor device and power off method of a semiconductor device |
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| Publication number | Publication date |
|---|---|
| JP2002251230A (en) | 2002-09-06 |
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