TW420862B - Manufacturing method for static random access memory - Google Patents

Abstract

A manufacturing method for static random access memory (SRAM) which can reduce the size of SRAM cells composed of CMOS transistors. The method includes the following steps: (i) firstly, defining active region to form p-well and n-well regions, using the implantation process to adjust the threshold voltage of NMOS and PMOS, growing the gate oxide, depositing un-doped polysilicon, and defining the position of buried contact connecting the pull up transistor and pull down transistor; (ii) depositing the un-doped polysilicon or amorphous silicon as the gate material, defining the position of gates, and defining the connecting line between the drain of pull up transistor and the source of pull down transistor; (iii) then, conducting n-type light drain doping and p-type light drain doping, forming the spacer, using the mask photolithography and implantation to conduct n+ doping and p+ doping respectively so as to form the source/drain and gate regions of NMOS and PMOS respectively, burying the implantation of contacts, then forming the titanium silicon as the gate and source/drain, depositing an oxide layer as the spacer and forming the contact holes; (iv) forming a metal layer defined to be as the power line and the connecting line between the polysilicon of pull up transistor and pull down transistor gates and the drain of pull up transistor and the source of pull down transistor, the ground line of the drain of pull down transistor, the tape and plug for the word lines; (v) then, forming an oxide layer again as the isolation layer and forming the contact holes; and (vi) forming another metal layer and defining the bit lines.

Description

42086 2 ^ Copy 5. Description of the invention (1) The present invention relates to a semiconductor memory device, and more particularly to a static random access memory and a manufacturing method thereof, wherein each memory cell uses four buried contact windows and Double gate. Static random access memory is the fastest processing memory of all semiconductor memories. It mainly stores data in the conductive state of the memory cells. In the conventional art, there are several different designs of static random access memory (hereinafter referred to as SRAM). For example, 6 NM0S transistors can be used to form a SRAM circuit; or polycrystalline silicon can be used as a load and composed of 4 transistors. SRAM circuit; and SRAM circuit with CMOS design.

Please refer to Figure 1 'The conventional SRAM memory cell system designed with CMOS includes two PM0S and four NM0S, of which two pm0S 1 0 and 12 are SRAM pull-up transistors' NM0S 18 and 20 are Pass gate transistors for SRAM. NMOS 14, 16 are pull-down transistors for SRAM. Among them, the gates of pm0s 10, 12 and NM0S 14, 16 are shared respectively, the sources of 10, 12 are commonly connected to the power source Vcc 'and the non-poles of NM0S 14, 16 are commonly grounded. Although 'the SR and circuits constructed by the above several different methods have no difference in operation', when the SRAM circuit is in standby mode, the power consumed by the SRAM circuit composed of CMOS transistors will be higher than the above The other two ways are different ... the circuit is low. Therefore, as far as practical applications are concerned, it is natural that the SRAM circuit is composed of CMOS transistors to meet the eight requirements. However, using this method to design and construct the SRAM circuit has the disadvantage of a large memory cell size, which has a negative impact on improving the circuit accumulation degree.

Page 5 4 2 0862 ^ V. Description of the invention (2) In view of this, in order to overcome the shortcomings of the conventional technology, the main purpose of the present invention is to propose a static random access memory and a manufacturing method thereof, which can reduce The size of the SRAM memory cell composed of CMOS transistors. In order to achieve the above-mentioned object, the present invention proposes a new SRAM layout, and uses a process of four buried contact windows and a double-gate process to make SRAM memory cells. Next, the embodiments of the present invention will be described with reference to the drawings to more clearly explain the architecture, steps, and advantages of the present invention. Among them: FIG. 1 is a circuit diagram showing an SRAM composed of a * CM0S transistor in the conventional art. Figures 2a to 2f are layout diagrams illustrating the method for manufacturing the static random access memory of the present invention. Description of reference numerals Pull-up transistors 10, 12 'Pull-down transistors 14, 16, Transmission gate transistors 18, 20, Active area 100, Buried contact window 丨 丨 仏 ~ 丨〗 0d, Gate material 120 'Gate 122a ~ 122f, contact holes 130a, 130b, 132a ~ 132d, 134a, 134b, 136a, 136b, 150a, 150b, power line 1 4 0' connection line 1 2 4, 1 4 2 ' The pole ground line 144 'word line connection line 146, plug 148, bit line 160. Description of the embodiment 凊 Refer to FIG. 2a to FIG. 2f. The method for manufacturing the static random access memory of the present invention includes the following steps: (i) First, define an active area "100, and form a P-well area and an η-well. The region 'simultaneously uses the implantation step to adjust the threshold voltages of NMOs and PMOS' and grows a gate oxide with a thickness of about 40 to 15 angstroms.

Layer, depositing about 500-1500 angstroms of undoped polycrystalline silicon, and defining the position of the buried contact window 丨 丨 仏 ~ 丨 ^ / to connect the pull-up transistor to the pull-down transistor, as shown in Figure 2a ; (Ii) Please refer to FIG. 2b, and then sink approximately 500 to 150 angstroms of undoped polycrystalline or amorphous stone as the gate material 120, and define gates I22a to 122i (I 丨 i) a Refer to Figure 2c 'and then do n-type light-drain doping and? Then, a spacer layer with a thickness of about 600 to 2500 angstroms is formed, and then a mask layer using a photolithography technique and an implantation technique is used to perform n + doping and p + doping, respectively, so as to form a source and a PMOS / The area of the drain and gate electrodes and the buried contact window are implanted, and then a titanium metal oxide compound is formed as the gate and source electrodes; and the electrode, and then an oxide layer is deposited as an isolation layer to form a contact hole 13〇a , I30b, 132a ~ 132d, 134a, 134b, 136a, 136b; (iv) Please refer to Figure 2d to form a metal layer 'and define it to obtain the power line. 40. As a pull-up transistor and a pull-down transistor The polycrystalline chip of the gate and the connection line 142 of the pull-up transistor and the source of the pull-down transistor, the > of the pull-down transistor and the ground line 144 of the electrode, and the strapping 146 of the character line Plug 148, (v) please refer to FIG. 2e ', then form a wide oxide again as an isolation layer, and form contact holes 150a, 150b; (vi) refer to FIG. 2f, and then form a metal layer and define Out bit line 160. The N-type light-drain doping is implanted with phosphorus or arsenic at an energy of 5 Kev ~ 60KeV and a concentration of 1E13 ~ 3E14 / cm2. The P-type light-drain doping is implanted with boron or boron at an energy of 2 KeV ~ 60KeV and a concentration of 1E13 ~ 3E14 / cm2.

420862

The N + doping is implanted with arsenic at an energy of 10 KeV ~ 60Key and a concentration of 2E5 ~ 6EI5 / cm2. The above ρ + doping is implanted with boron or boron fluoride at a concentration of 2E15 ~ 6E15 / cm2. The gate and source / drain formation methods described above utilize two rapid temperature annealing (RTA) steps to form titanium or cobalt. In other words, the first rapid heating annealing step is used first to process the formed metal at a temperature of 600 to 700 ° C, and then the unreacted metal is selectively removed, and then the second rapid heating annealing step is used at a temperature of 800 ~ 900 ° C processed metal. The above step of forming a dielectric layer as an isolation layer is the deposition of borophosphotetraoxyethyl silicon (BPTEOS), which includes a 2K angstrom plasma-promoted tetraoxyethyl silicon (PETEOS) and a 3 ~ 12K angstrom borophosphotetraoxysilane. Ethyl silicon, then fill BPTEOS at 750 ~ 900 ° C.

Page 8

Claims (1)

6. Scope of Patent Application1. A method for manufacturing static random access memory 'includes the following steps: / (0) First, define the active area to form the p-well area and the η 丼 area, and use the implantation steps to adjust the NMOS and The threshold voltage of PMOS, and the growth of the interlayer oxide layer 'deposits undoped polycrystalline silicon, and defines the location of the buried contact window used to connect the pull-up transistor and the pull-down transistor; (ii) then deposit the gate material' And define the position of the gate, and also define the connection line between the drain of the pull-up transistor and the source of the pull-down transistor, (iii) then perform n-type light-drain doping and p-type light-drain doping, Next, a spacer layer is formed, and η + doping and P + doping are performed by using photolithography technology and implantation technology, respectively, to form regions of source / drain and gate of 405 and pM0s, respectively, and The implantation of the contact window is buried, and then a gate and a source / drain are formed, then a dielectric layer is deposited as an isolation layer, and then a contact hole is formed; (iv) a metal layer is formed and defined to obtain a power line, As pull-up electric aa body and pull-down electric The connection line of the polygate of the body gate and the drain of the pull-up transistor and the source of the pull-down transistor, the ground line of the drain of the pull-down transistor, the connection line of the character line, and the plug; (\ 〇 Then, a dielectric layer is formed again as an isolation layer and a contact is formed; and (VI) Then a metal layer is formed and a bit line is defined. 2 'The manufacturing method according to item 1 of the scope of patent application, wherein the above The gate oxide layer in step (i) has a thickness of about 40 to 150 angstroms. 3_ As in the manufacturing method of the first item of the patent application scope, wherein the above step 4 2 086 2 ”, 6. Application scope of patents The interphase electrode material is undoped polycrystalline or non -... The concentration of the above steps is as in the method for making item i of the application scope, which is ―IQ type light-drain doping. Based on the energy of 5 Kev ~ 60KeV, 1E13 ~ 3E14 / cm2, implanted with phosphorus or Kund 5. The production method of item 1 in the scope of the patent of β, wherein the above-mentioned p-type immersion doping system in step 1) above Boron or boron fluoride was implanted at an energy of 2 KeV ~ 60KeV and a concentration of 1E13-3E14 / cm2. 6. The manufacturing method according to item 1 of the scope of patent application, wherein the gate and source / drain electrodes in the above step (1 1 1) may be metal silicides of titanium or cobalt. 7. According to the manufacturing method of item 1 of the scope of patent application, in the step (iii), the N + doping is implanted with sand at an energy of 10 KeV ~ 60KeV and a concentration of 2 £ 15 ~ 6E1 5 / cm2. 8. According to the manufacturing method of item 1 of the scope of patent application, in the above step (i i i), the P + doping is implanted with boron or boron fluoride with an energy of 2KeV ~ 60KeV and a concentration of 2E15 ~ 6E15 / cm2 '. 9. The manufacturing method of item 1 in the scope of the patent application, wherein the step of forming the dielectric layer as the isolation layer is to deposit boron phosphorus tetraoxoethylsilicon, which includes 1 ~ 2K angstroms of electropolymerization to promote tetraoxoethyl breakdown. And 3 ~ 12K angstrom boron scale tetraoxyethyl silicon, and then 750 ~ 900 t: filled with boron phosphorus tetraoxyethyl silicon. 10 · The manufacturing method according to item 1 of the scope of patent application, wherein the gate and source / drain formation methods described above are formed by using two rapid temperature annealing steps.