TW420854B - Method for improving the bonding property between the gold (Au) connection wire and the copper (Cu) bonding-pad - Google Patents

Method for improving the bonding property between the gold (Au) connection wire and the copper (Cu) bonding-pad Download PDF

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Publication number
TW420854B
TW420854B TW088114826A TW88114826A TW420854B TW 420854 B TW420854 B TW 420854B TW 088114826 A TW088114826 A TW 088114826A TW 88114826 A TW88114826 A TW 88114826A TW 420854 B TW420854 B TW 420854B
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layer
copper
aluminum
bonding
pad
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TW088114826A
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Chinese (zh)
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Shiun-Ming Jang
Meng-Sung Liang
Jen-Hua Yu
Jung-Shi Liou
Jen-Bei Lai
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Taiwan Semiconductor Mfg
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Because the resistance of copper is relatively low, it is widely used in the ultra large integrated circuit of the sub-quarter micrometer. However, it is well known that copper is easily eroded in the air. In addition, the reaction property between the Au bonding ball and the Cu bonding pad is very poor. An inert layer of dense aluminum oxide with about 3 to 4 mini-micrometer thickness is formed for aluminum (Al) in air and is used to protect the Al layer below the aluminum oxide from being further oxidized. The reaction property between Au and Al is very good. One of the main purposes of this invention is to add a layer of Al or AlCu alloy to the Cu bonding pad in order to enhance the bonding property between the Cu bonding pad and the Au bonding wire. With this method, the Al or AlCu used as the bonding and protection layer is formed on the Cu bonding pad so as to make the Au bonding wire effectively bond with the Cu bonding pad.

Description

^ A7 - A 7 --- B7 五、發明説明(1 ) f 愛_明範圍 本發明係關於一種改良積體電路製造封裝中接合性的方 法,更確切地說’是關於積體電路封,裝中金質接線與铜質 焊接墊間接合性的改良方法。 , I明背景 在過去的二十年間’積體電路製程技術突飛猛進,目前 已堂堂進入次四分之一微米世代。而對於電子元件要求其 體積更小’更經濟及功能更強大等需求,更加快了積體電 路尺寸縮小之速度。在尋找符合此先進世代的金屬化材料 的努力中’铜是目前研究最多可用來取代鋁的材料。銅較 鋁具更低的電阻率及較高的原子量。然而,不像銘在空氣 中會自然地形成一緻密的氧化層以對抗腐蝕,金屬銅就無 此鈍化保護層’因此就要比鋁更易受到侵蝕。由於銅的氧 化電位不低,基體原則上不易發生電化腐蝕;可是,由氧 化銅的量在空氣中會隨時間而增加可知,其所生成的氧化 铜層不具保護性。也就因為此不具保護功能的氧化層,鋼 比銘易受到化學物質的侵犯。特別是於晶片的金屬化製程 以及與金質接線接合時’由於會與空氣接觸,銅的氧化問 題更需受到重視。此外’氧化銅是影響銅焊接整與金質接 線間接合品質的主要因素之一。 另一方面’除了 一些金線結合時的控制變數(像是接合溫 度、荷載、及超音波振盪振幅)之外,建立—高品質、可 靠之接合線主要問題是金質接線與焊接墊之間的接合性。 銅質金屬鑲嵌法是製造多層内連接的良方且已在業界廣為 _______- 4 ~_ $張尺度適用中國國家標準(Ins ) Μ規格(210X297公釐)„ (請先閱讀背面之注意事項再填蹲本頁) 丁 、-fl 線 經濟部智慈財產局員工消費合作社印製 A7 B7 五、發明説明( 然而’因為銅質焊接㈣封錄線時常使用的金質 間的接合性(反應性)不良,此不反的接合面將會導致 可罪度的問題。 ,因此,如何改進金質接線與銅焊接墊間之接合性,—直 為業界所努力而未能有效突破之問題。 發呵概述 由於awak:u合金早已證實與金f焊接線的相容性佳, 本發明的主要目的之一為於鋼質焊接墊上加上一層Μ或 AJCU合金,以增加銅焊接墊與金焊接線的焊接性。在本發 明中’當作接著劑層之AUA1Cu係沈積於鋼悍接塾上,以 使金焊接線可有效地與銅焊接塾相接合。而具銅接合替之 晶片與金焊接線之間的接合便可得到大幅改善。 本發明之—實施例中$包括纟該純化保護層&面引入粗 糙的表面,製造出些微的高低起伏,藉以提升封裝接合化 合物與純化保護層間的黏著性。而在與接合樹脂接合的製 程中,其熱膨脹係數(CTE)的重要性將可降低。 經濟部智慧財產局員工消費合作社印製 故本發明的目的之—為提供一種於銅焊接墊上形成一銘 層或紹銅層’其角色為防止下層鋼烊接塾氧化以及作為與 金質接線之接著劑,以改善金質接線與銅質焊接墊之結合 性;本發明之另一目的為提升封裝接合化合物與鈍化保護 層間的黏著性;本發明之又一目的為減少製程步騾,降低 製造的複雜度及成本。 根據本發明之—種用於半導體製程中之改良金質接線與 銅質焊接墊之間接合性的方法,包括形成-銅質焊接墊於 本紙Λ尺度適用中國國参標準(CNS ) Λ4規格(210X297公楚) 經濟部智慧財產局員工消費合作社印製 ^ 2 0 3 5 d J ^ A7 B7 五、發明説明(3 ) t 毛頂層金屬層之上;化學機械研磨該銅質焊接蟄;回蝕該 詞質焊接塾;沈積一障壁層於該铜質焊接墊上;以及沈積 鋁或鋁銅層於該障壁層上,以使該銅質焊接整被鋁鋼層 .覆蓋。 根據本發明之另一種用於半導體製程中之改進金質接線 與鋼質焊接墊之間接合性的方法,包括蝕刻一鈍化保護 層’使其下頂層金屬層之銅焊接墊曝露出來;沈積一鎢障 壁層於該销焊接整上;以及沈積一銘或銘銅層於該鶴障壁 層之上。 根據本發明之又一種用於半導體製程中之改良金質接線 與銅質焊接整之間接合性的方法,包括形成一銅質焊接蟄 於頂層金屬之上;沈積一鈍化保護層於該頂層金屬層之銅 質焊接墊上;蝕刻該鈍化保護層,使其下之鋼質焊接墊經 由接觸窗曝露出來;全面(地毯式)沈積一鋁層於該鈍化保 遵層表面上’以及以化學機械式研磨該铭層,以除去該純 化保護層之上的鋁層而只留下接觸窗中銅質焊接墊上之鋁 層。 經由以下的對應圖示與發明詳述’本發明的其他特徵及 優點將會更加地明顯。 圖式之簡單說明 圖1至圖7表示一根據本發明之方法步驟’用來於一積體 電路之銅質焊接整上形成一層鋁質或鋁鋼金屬層。 圖8至圖10表示根據本發明之另一方法步驟,用來於一 積體電路之銅質焊接墊上選擇性沈積一鋁質或鋁銅金屬 _______ — 6 _ 本紙張尺度適用中國國豕標率(CNS ) Λ4規格(210X297公楚) ..<ΐτ------鱗,~ (請先閱讀背面之注意事項再填寫本頁) 2 〇s5 4 A7 五、發明説明(4 ) 層。 圖j 1至圖13表示根據本發明之又一方法步驟,用來於一 積體電路之銅質焊接墊上以及其接觸窗孔的侧壁表面上, 形成一銘質或銘銷金屬層。 經濟部智慧財產局員工消費合作社印製 10 積體電路 12 介電層 14 非導電性障壁層 16 障壁層 18 通道孔 22 銅焊接墊 42 障壁層 52 金屬層 72 鈍化保護層 74 接觸窗 80 積體電路 82 銅質焊接墊 84 鈍化保護層 85 第一障壁層 86 非導電層 88 接觸窗 92 第二障壁層 102 金屬層 110 積體電路 112 銅焊接墊 (請先閲讀背面之注意事項再填窝本頁) 本紙張尺度適用中國國家標隼(CNS ) A4規格(210X297公釐) 420854^ A7-A 7 --- B7 V. Description of the invention (1) f Love_Ming Scope The present invention relates to a method for improving the bonding in integrated circuit manufacturing packages, more specifically, 'integrated circuit sealing, Improved method for bonding between gold wiring and copper soldering pads. I. Background In the past two decades, the integrated circuit process technology has made rapid progress, and has now entered the second quarter micron generation. The demand for electronic components to be smaller, more economical, and more powerful has accelerated the size reduction of integrated circuits. In an effort to find a metallization material that fits this advanced generation, copper is the most researched material that can be used to replace aluminum. Copper has lower resistivity and higher atomic weight than aluminum. However, unlike Ming naturally forming a dense oxide layer in the air to resist corrosion, metallic copper does not have this passivation protective layer 'and is therefore more susceptible to corrosion than aluminum. Since the oxidation potential of copper is not low, the substrate is not prone to galvanic corrosion in principle; however, it can be seen from the increase in the amount of copper oxide in the air over time that the resulting copper oxide layer is not protective. Because of this non-protective oxide layer, steel biming is vulnerable to chemical intrusion. Especially in the metallization process of the wafer and the bonding with the gold wire, the copper oxidation problem needs to be paid more attention due to the contact with the air. In addition, 'copper oxide is one of the main factors affecting the quality of joints between copper brazing and gold wires. On the other hand, in addition to some control variables (such as bonding temperature, load, and ultrasonic oscillation amplitude) during the bonding of gold wires, the main problem of establishing high-quality and reliable bonding wires is between the gold wiring and the solder pads. Of jointability. The copper metal inlay method is a good recipe for manufacturing multilayer internal connections and has been widely used in the industry. _______- 4 ~ _ $ The scale applies the Chinese National Standard (Ins) M specifications (210X297 mm) „(Please read the note on the back first Matters need to be refilled on this page) D, -fl Printed by the Consumers Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (however 'because of copper welding, the joints between the gold and the seal line are often used ( Poor reactivity), this irreversible joint surface will lead to the problem of guilt. Therefore, how to improve the joint between the gold wiring and the copper soldering pads is a problem that has not been effectively overcome by the industry's efforts. Faha Overview Since awak: u alloy has long been proven to be compatible with gold f welding wire, one of the main purposes of the present invention is to add a layer of M or AJCU alloy to the steel welding pad to increase the copper welding pad and gold. Weldability of the welding wire. In the present invention, AUA1Cu, which is used as an adhesive layer, is deposited on the steel joint so that the gold welding wire can be effectively joined with the copper welding joint. The copper bonding is used instead of the wafer and Bonding between gold welding wires The invention is greatly improved. In the embodiment of the present invention, the purification protection layer & surface is introduced into a rough surface to create a slight fluctuation, thereby improving the adhesion between the packaging bonding compound and the purification protection layer. In the process of resin bonding, the importance of the coefficient of thermal expansion (CTE) will be reduced. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics. Therefore, the purpose of the present invention is to provide a coating or copper on a copper pad. The role of the layer is to prevent the oxidation of the lower steel joints and to act as an adhesive to the gold wiring to improve the bonding between the gold wiring and the copper soldering pad. Another object of the present invention is to improve the packaging bonding compound and passivation protection. Adhesion between layers; Another object of the present invention is to reduce process steps, reduce manufacturing complexity and cost. According to the present invention, an improved bonding between a gold wire and a copper pad used in a semiconductor process Method, including forming-copper solder pad on paper Λ scale applicable to Chinese National Ginseng Standard (CNS) Λ4 specification (210X297) Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau ^ 2 0 3 5 d J ^ A7 B7 V. Description of the invention (3) t Above the top metal layer of wool; chemical mechanical grinding of the copper welding 蛰; etchback of the word welding 塾Depositing a barrier layer on the copper bonding pad; and depositing an aluminum or aluminum-copper layer on the barrier layer, so that the copper welding is entirely covered by an aluminum steel layer. Another method according to the present invention is used in a semiconductor process. A method for improving the bondability between a gold wire and a steel soldering pad includes etching a passivation protective layer to expose the copper soldering pad of the lower top metal layer; depositing a tungsten barrier layer on the pin weld; and A copper or copper layer is deposited on the crane barrier layer. According to another method of the present invention, a method for improving the bonding between a gold wire and a copper solder joint in a semiconductor process includes forming a copper solder joint. On the top metal; deposit a passivation protection layer on the copper solder pad of the top metal layer; etch the passivation protection layer so that the underlying steel solder pad is exposed through the contact window; An aluminum layer is on the surface of the passivation compliance layer and the coating is chemically and mechanically ground to remove the aluminum layer above the purified protective layer and leave only the aluminum layer on the copper bonding pad in the contact window. Other features and advantages of the present invention will become more apparent through the following corresponding drawings and detailed description of the invention. Brief Description of the Drawings Figures 1 to 7 show a method step according to the present invention for forming a metal layer of aluminum or aluminum-steel on the copper soldering of an integrated circuit. 8 to 10 show another method step for selectively depositing an aluminum or aluminum-copper metal on a copper pad of an integrated circuit according to the present invention. _______ — 6 _ This paper size is applicable to the Chinese national standard. Rate (CNS) Λ4 specification (210X297) .. < ΐτ ------ scale, ~ (Please read the notes on the back before filling this page) 2 〇s5 4 A7 V. Description of the invention (4) Floor. Figures 1 to 13 show steps of a method according to the present invention for forming an intaglio or pin metal layer on a copper soldering pad of an integrated circuit and on the side wall surface of its contact window hole. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 10 Integrated circuit 12 Dielectric layer 14 Non-conductive barrier layer 16 Barrier layer 18 Channel hole 22 Copper soldering pad 42 Barrier layer 52 Metal layer 72 Passivation protective layer 74 Contact window 80 Circuit 82 Copper soldering pad 84 Passivation protective layer 85 First barrier layer 86 Non-conductive layer 88 Contact window 92 Second barrier layer 102 Metal layer 110 Integrated circuit 112 Copper soldering pad (Please read the precautions on the back before filling the book Page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 420854

114 第一障壁層 116 非導電層 117 第二障壁層 118 接觸窗 132 鋁層 119 接觸窗 (請先閱讀背面之注意事項再填寫本頁) 較佳實施例詳诚 實例一 此實施例是於銅烊接塾上製造一銘質或紹鋼金屬層,以 利於隨後與金質連接線建立有效的接合。 : ,t D 〜疋以銅 的金屬鑲嵌法於金屬頂層結構上產生。 圖1是積體電路1〇的部份剖面圖。如圖i中所示’—障辟 層16形成於一非導電性障壁層14與介電層ι2之項層表= 上,其t障壁層16亦覆蓋通道孔18側壁表面。 接下來,在圖2中沈積銅來填滿通道孔18,以形成鋼焊 接墊22。然後,以銅的化學機械式研磨法(CMp)來去除於 非導電性障壁層14頂層表面上之銅及障壁層]6。 經濟部智慧財產局員工消費合作社印製 通道孔18中的銅焊接墊22接著以乾式或濕式法回蝕 back)。這導致銅焊接墊22的高度變得比四周介電層為低, 如圖3中所示。 之後,在圖4令’此銅焊接墊22的頂層表面以CVD法沈積 —障壁層42 ’像是氮化鈦(TiN)層,其不僅用於防止銅的擴 散’更作用有如同時對銅及鋁金屬的黏著層(a glue layer)。 在圖5中,以PVD法在障壁層42表面上沈積一鋁或鋁銅金 一 8 — 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X297公嫠) 經濟部智慧財產局員工涓費合作社印製 A7 —---------B7 ____ 五、發明説明(6 ) 属層52,其中尚包括有該銅焊接墊22上方區域。 圖6所不為實行鋁或鋁銅的CMP ’用來去除在非導電層i4 上之鋁(或鋁銅)與障壁層42,並將其表面平坦化。 在CMP平坦化之後,—鈍化保護層乃,如圖7中所示,沈 %於非導廷層14之上此純化保護層π最後被触刻,使得 ’、下的銅知接塾22經由接觸窗(c〇ntact win(j〇w) 曝露出來。 I後可再加上一研磨步驟,以刻意地在該鈍化保護層表 面引入像是刮痕之粗糙表面(未在圖中示出),製造出些微 的南低起伏,藉以提升接合化合物與鈍化保護層間的黏著 性。 在此實施例中,該鋁或鋁銅層之沈積可為自行校正式沈 積。 實例二 此實施例是用以於銅焊接墊上選擇性地沈積—鋁質或鋁 銅金屬層,而此銅層是以銅的金屬鑲嵌法於金屬頂層結構 上產生,用以後續晶片之封裝。藉由此選擇性地成長鋁或 銘銅層作為接著層’铜質焊接墊與金焊接球之間的接合性 便可得到改良= 圖8是積體電路80的一個部份剖面圖。在圖8中,一銅質 焊接墊82是以金屬鑲嵌法在一第一障壁層85上形成。此 外’一位於非導電層86上方之她化保護層被回蚀,使其 F方之銅質焊接墊82得以經由接觸窗88曝露出來。藉由原 位之氫/氮(或氨)氣體或電漿可將回蝕時於焊接墊表面上 所生成之薄鋼氧化層還原。 _ - 9 - 本紙張尺度適用中國國家禕率(CNS ) Λ4規格UlOXM7公楚) (请先閱讀背面之注意事項再填寫本頁} 訂 “ d u 8 b 4 -呦 A7 ___B7 五、發明説明(7 ) ♦ 在圖9中,一鶴質第二障壁層92 ί Μ户,丨1 > 丨平土臂w (/子反小於2〇毫微米)以 CVD法選擇性地沈積在該铜焊接墊82上, 丄丄以便隨後可選擇 性沈積Α丨或AlCu。 在此步驟之後,如圖10中所示,一鋁或鋁鋼層〗〇2 (厚度 約150至200毫微米)係選擇性地以CVD法原位(m_situ)或異位 (ex-S1tu)沈積在該鎢質第二障壁層92。因此,—位於銅焊接 塾82上之同時俱備有保護及接著功能的肖或叙銅層得:形 成。如此的接著層改良了金質焊接球與銅烊接墊之間的接 合性。而選擇性沈積紹或鋁銅層的好處在於簡化了後續 CMP等步驟。 之後可再加上一研磨步驟,以刻意地在該鈍化保護層表 面引入像是刮痕之粗糙表面(未在圖中示出),製造出些微 的高低起伏,藉以提升接合化合物與鈍化保護層間的黏著 性。 實例三 此優先實施例是用以於銅焊接墊上沈積一自行校正之銘 貝或鋁銅金屬層,而此銅層是以銅的金屬鑲嵌法於金屬頂 層結構上產生,用於後續晶片之封裝。 圖11為一積體電路110之部份剖面圖,其中描述—鈍化保 漠層118被回蚀經由接觸窗119曝露出其下的銅焊接| 112。 在圖η中’一銅焊接墊m在第一障壁層U4上以金屬鑲嵌 法製成,接著在烊接餐1丨2上沈積—第二障壁層117。此 外’於非導電層丨16上之鈍化保護層118被回蝕,使得銅焊 接墊112經由接觸窗119曝露出來。 _____._____一 10 - 本纸張尺度適$中國國家標準(CMS ) A4規格(2】G X 297公釐)" " {請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智E財產局員工消f合作社印製 A7 B7 五 發明説明( 接下來’沈積—地毯式(blanket)鋁層於鈍化保護層U8之 上,如圖12中所示。於圖13中,以銘的CMp除去該純化保 護層118上的紹金屬’而只留下鋼焊接塾ιΐ2上方以及接觸 ®侧壁表面上的鋁層132。因此製程無需光微影與蝕刻的 步驟,此自行校正製程要比習知方法省錢經濟。 在銘的CMP程序[可再加上一研磨步驟,以刻意地在 邊鈍化保護層表面引入像是刮痕之粗糙表面(未在圖中示 出),製造出些微的高低起伏,藉以提升接合化合物與鈍 化保護層間的黏著性。 本發明之技術内及特點已藉由實施例說明如上。然而’ 熟悉本項技術之士可基於本發明之揭示而作出各種不背離 本發明精神之修改及變更;因此本發明之保護範圍應不限 於已揭示之實施例,而應包含該等修改及變 I Λ-- (請先閲讀背面之注意事項再填寫本頁) 訂 1. ! 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用十国國家標準(CNS ) Λ4規格(210Χ 297公釐)114 First barrier layer 116 Non-conductive layer 117 Second barrier layer 118 Contact window 132 Aluminum layer 119 Contact window (please read the precautions on the back first and then fill out this page) The preferred embodiment is detailed and honest Example 1 This embodiment is based on copper A metal or Shao steel metal layer is manufactured on the joint to facilitate the subsequent effective connection with the gold connection line. :, T D ~ 疋 is generated on the top metal structure by the metal inlay method of copper. FIG. 1 is a partial cross-sectional view of the integrated circuit 10. As shown in FIG. I ', the barrier layer 16 is formed on the surface of a non-conductive barrier layer 14 and a dielectric layer ι2, and the barrier layer 16 also covers the sidewall surface of the channel hole 18. Next, copper is deposited in FIG. 2 to fill the via holes 18 to form a steel pad 22. Then, the chemical mechanical polishing method (CMp) of copper was used to remove the copper and the barrier layer on the top surface of the non-conductive barrier layer 14] 6. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the copper pads 22 in the channel holes 18 are then etched back by dry or wet method). This causes the height of the copper bonding pad 22 to be lower than the surrounding dielectric layer, as shown in FIG. 3. Then, in FIG. 4, the top surface of the copper bonding pad 22 is deposited by a CVD method—the barrier layer 42 is like a titanium nitride (TiN) layer, which is not only used to prevent the diffusion of copper, but also acts as both copper and copper. A glue layer of aluminum. In Figure 5, PVD method is used to deposit aluminum or aluminum copper gold on the surface of the barrier layer 42. This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 gong). The staff of the Intellectual Property Bureau of the Ministry of Economic Affairs pays a fee for cooperatives. Print A7 —--------- B7 ____ 5. Description of the invention (6) The metal layer 52 also includes the area above the copper soldering pad 22. FIG. 6 does not implement CMP of aluminum or aluminum-copper to remove aluminum (or aluminum-copper) and the barrier layer 42 on the non-conductive layer i4 and planarize the surface thereof. After the CMP is flattened, the passivation protective layer is, as shown in FIG. 7, the pure protective layer π deposited on the non-conductive layer 14 is finally etched, so that the lower copper connection 22 passes through The contact window (c〇ntact win (j〇w) is exposed. A grinding step can be added after I to deliberately introduce a rough surface like scratches on the surface of the passivation protective layer (not shown in the figure) In order to improve the adhesion between the bonding compound and the passivation protective layer, a slight south low fluctuation is produced. In this embodiment, the deposition of the aluminum or aluminum-copper layer can be self-correcting. Example 2 This embodiment is used to Selective deposition on copper bonding pads—aluminum or aluminum-copper metal layer, and this copper layer is produced on the top metal structure by the copper metal damascene method, which is used for subsequent chip packaging. By this, aluminum is selectively grown. Or the copper layer as the bonding layer can improve the joint between the copper solder pad and the gold solder ball. Figure 8 is a partial cross-sectional view of the integrated circuit 80. In Figure 8, a copper solder pad 82 is formed by a metal damascene method on a first barrier layer 85 In addition, a protective layer above the non-conductive layer 86 is etched back, so that the F-side copper solder pad 82 can be exposed through the contact window 88. With in-situ hydrogen / nitrogen (or ammonia) gas Or plasma can reduce the thin steel oxide layer formed on the surface of the solder pad during etchback. _-9-This paper size is applicable to China National Standard (CNS) Λ4 size UlOXM7 male Chu (Please read the note on the back first) Please fill in this page again for the item} Order "du 8 b 4-呦 A7 ___B7 V. Description of the invention (7) ♦ In Figure 9, the second barrier layer 92 of a crane mass, 丨 M > 丨 Flat soil arm w (/ Sub-micron is less than 20 nm) is selectively deposited on the copper bonding pad 82 by CVD method, so that A 丨 or AlCu can be subsequently selectively deposited. After this step, as shown in FIG. 10, An aluminum or aluminum steel layer (the thickness of about 150 to 200 nanometers) is selectively deposited on the tungsten second barrier layer 92 in situ (m_situ) or ex-situ (ex-S1tu) by CVD. Therefore, , —The copper or copper layer on the brazed joint 82 with protection and bonding function at the same time is formed. Such bonding layer improvement The bonding between gold solder balls and copper pads. The advantage of selective deposition of aluminum or copper layers is that it simplifies subsequent CMP and other steps. A polishing step can be added afterwards to deliberately protect the passivation. A rough surface (not shown in the figure) is introduced into the surface of the layer to create slight fluctuations, thereby improving the adhesion between the bonding compound and the passivation protective layer. Example 3 This preferred embodiment is used for copper welding. A self-calibrated Mingbei or aluminum-copper metal layer is deposited on the pad, and the copper layer is produced on the top layer of the metal by the copper metal damascene method for subsequent chip packaging. Figure 11 is a part of a integrated circuit 110 Sectional view, described—the passivation layer 118 is etched back to expose the braze underneath via the contact window 119 | 112. In FIG. Η, a copper bonding pad m is made by the metal damascene method on the first barrier layer U4, and then deposited on the barrier layer 1-2-the second barrier layer 117. In addition, the passivation protection layer 118 on the non-conductive layer 16 is etched back, so that the copper bonding pad 112 is exposed through the contact window 119. _____._____ 10-This paper is suitable for Chinese National Standards (CMS) A4 specifications (2) GX 297 mm) " " {Please read the notes on the back before filling this page) Order the Ministry of Economic Affairs E property bureau staff printed A7 B7 five cooperative instructions (the next 'deposition-blanket aluminum layer on the passivation protective layer U8, as shown in Figure 12. In Figure 13, with the inscription The CMp removes the metal from the purified protective layer 118, leaving only the aluminum layer 132 above the steel welding pad 2 and the contact surface of the side wall. Therefore, the process of photolithography and etching is not required. The conventional method saves money and economy. In the CMP process of Ming [a grinding step can be added to deliberately introduce a rough surface (not shown in the figure) such as a scratch on the surface of the passivation protective layer to make a little The fluctuations in height can improve the adhesion between the bonding compound and the passivation protective layer. The technology and features of the present invention have been described above by way of examples. However, those skilled in the art can make various departures based on the disclosure of the present invention. This invention God's modifications and changes; therefore, the scope of protection of the present invention should not be limited to the disclosed embodiments, but should include such modifications and changes I Λ-(Please read the precautions on the back before filling this page) Order 1.! Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size is applicable to the ten national standards (CNS) Λ4 specification (210 × 297 mm)

Claims (1)

42^85 4 ^ as B8 C8 ^7----^____ 六、申請專利範圍 l —種用於半導體製程中之改良金質接線與銅質焊接墊之 間接合性的方法,包括 形成一鋼質焊接墊於於頂層金屬層之上; 化學機械研磨該鋼質烊接塾; 回蝕該鋼質焊接塾; 沈積一障壁層於該銅質焊接墊上;以及 沈積一鋁或鋁銅層於該障壁層上,以使該銅質焊接墊被 鋁銅層覆蓋。 2.如申請專利範圍第丨項之方法,其中該障壁層之材料係 為氮化飲D &如申請專利範圍第2項之方法,其中該氮化鈦障壁層係 以物理氣相沈積法沈積。 4. 如申請專利範園第2項之方法,其中該氮化鈦障壁層的 厚度小於20毫微米。 5. 如申請專利範圍第!項之方法,其中該沈積一銘或銘鋼 層·^步驟係為自行校正式沈積—鋁或鋁銅層於該障壁層 上。 6. 如申請專利範圍第1項之方法,其中更包括: 經濟部中央標準局貝工消費合作社印策 Hu .¾-* (請先閱讀背面之注意事項再填寫本頁〕 以化學機械式研磨該鋁或鋁銅層; 沈積一純化保積層於該頂層金屬上:以及 粗糙化該鈍化保護層表面。 7. —種用於半導體製程中之改進金質接線與鋼質焊接墊之 間接合性的方法,包括 蝕刻一鈍化保護層,使其下頂層金屬層之銅焊接墊曝露 出來; -12 - 本紙張尺度適用中國國家標率(CNS > A4現格(210x297公董)42 ^ 85 4 ^ as B8 C8 ^ 7 ---- ^ ____ 6. Scope of Patent Application l-A method for improving the bonding between a gold wire and a copper pad in a semiconductor process, including forming a steel A quality welding pad is on the top metal layer; chemically grind the steel welding pad; etch back the steel welding pad; deposit a barrier layer on the copper welding pad; and deposit an aluminum or aluminum copper layer on the The barrier layer, so that the copper bonding pad is covered with an aluminum copper layer. 2. The method according to the scope of the patent application, wherein the material of the barrier layer is a nitrided beverage D & The method according to the scope of the patent application, wherein the titanium nitride barrier layer is a physical vapor deposition method Deposition. 4. The method of claim 2 in the patent application park, wherein the thickness of the titanium nitride barrier layer is less than 20 nm. 5. Such as the scope of patent application! The method of claim 1, wherein the step of depositing a Ming or Ming steel layer is a self-correcting deposition-an aluminum or aluminum copper layer on the barrier layer. 6. For the method of applying for the first item of the patent scope, which further includes: Printing policy Hu .¾- * of the Central Bureau of Standards of the Ministry of Economic Affairs, Shellfish Consumer Cooperative (Please read the precautions on the back before filling this page) Chemical mechanical polishing The aluminum or aluminum-copper layer; depositing a purified retention layer on the top metal; and roughening the surface of the passivation protective layer. 7. An improved bonding between a gold wire and a steel pad used in a semiconductor process Method, including etching a passivation protective layer to expose the copper bonding pads of the lower top metal layer; -12-This paper size is applicable to China's national standard (CNS > A4 standard (210x297) 經濟部中失橾準局員工消費合作社印裝 六、申請專利範圍 沈積一鎢障壁層於該銅焊接墊上;以及 沈積一鋁或鋁銅層於該鎢障壁層之上D 8.如申請專利範圍第7項之方法,其中該鶴障壁層係為選 擇性地沈積於該銅質焊接墊上。 9'如申請專利範圍第7或8項之方法,其中該鶴障壁層係 以化學氣相沈積法沈積。 1(1.如申請專利範圍第7項之方法,其中該鶴障壁層的厚度 小於20毫微米。 11. 如申請專利範圍第7項之方法,其中該沈積一鋁或鋁銅 層之步驟係為選擇性地沈積一銘或銘銅層於該障壁層 上- 12. 如申請專利範園第7項之改良方法,其中更包括粗糙化 諸純化保護層表面之步驟。 13. —種用於半導體製程中之改良金質接線與銅質焊接墊之 間接合性的方法,包括 形成一铜質焊接墊於頂層金屬之上; 沈積一鈍化保護層於該頂層金屬層之銅質焊接誓上; 蝕刻該鈍化保護層,使其下之銅質焊接墊經由接觸窗曝 露出來; 全面(地毯式)沈積一鋁層於該鈍化保護層表面上;以及 以化學機械式研磨該鋁層,以除去該鈍化保護層之上的 銘層而只留下該接觸窗中銅質焊接墊上之鋁層。 14. 如申請專利範園第n項之方法,其中更包括粗糙化該鈍 化保護層表面之步驟。 __ - i3 - 本紙張尺度適用中國國家橾隼(CNS ) Α4ίΛ^Τ?ϊ〇^297^ϊ1---- n m »ί --- - - - - m I. f n —^n - - - i ^—* 03 、-e (請先間讀背面之注意事項再填寫本頁)Printed by the Consumers' Cooperative of the Ministry of Economic Affairs, the Consumer Cooperatives 6. Depositing a tungsten barrier layer on the copper welding pad in the scope of patent application; and depositing an aluminum or aluminum copper layer on the tungsten barrier layer D 8. If the scope of patent application The method of item 7, wherein the crane barrier layer is selectively deposited on the copper bonding pad. 9 'The method of claim 7 or 8, wherein the crane barrier layer is deposited by a chemical vapor deposition method. 1 (1. The method according to item 7 of the patent application, wherein the thickness of the crane barrier layer is less than 20 nm. 11. The method according to item 7 of the patent application, wherein the step of depositing an aluminum or aluminum copper layer is In order to selectively deposit an inscription or inscription copper layer on the barrier layer-12. The improved method of item 7 of the patent application park, which further includes a step of roughening the surface of the purified protective layer. 13.-A method for A method for improving the bondability between a gold wiring and a copper bonding pad in a semiconductor manufacturing process includes forming a copper bonding pad on a top metal; depositing a passivation protective layer on the copper bonding oath of the top metal layer; Etching the passivation protective layer, exposing the copper solder pads through the contact window; depositing a full (carpet) aluminum layer on the surface of the passivation protective layer; and chemically and mechanically grinding the aluminum layer to remove the The passivation layer above the passivation protective layer leaves only the aluminum layer on the copper bonding pad in the contact window. 14. The method of claim n of the patent application park, which further includes a step of roughening the surface of the passivation protective layer.__-i3-This paper size applies to China National Standards (CNS) Α4ίΛ ^ Τ? ϊ〇 ^ 297 ^ ϊ1 ---- nm »ί -------m I. fn — ^ n---i ^ — * 03 、 -e (Please read the precautions on the back before filling in this page)
TW088114826A 1999-08-30 1999-08-30 Method for improving the bonding property between the gold (Au) connection wire and the copper (Cu) bonding-pad TW420854B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8034711B2 (en) 2004-03-08 2011-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structure and fabrication thereof

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Publication number Priority date Publication date Assignee Title
US8034711B2 (en) 2004-03-08 2011-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structure and fabrication thereof

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