TW420827B - Fabrication process of SOI substrate - Google Patents

Abstract

A fabrication process of SOI substrate efficiently removes a non-porous Si region on a porous Si region, and solves the problem that a glass substarte is inevitably etched and the problem that a relatively thick porous Si region is necessary. The fabrication process of SOI substrate comprises a step of making a surface layer of a single-crystal Si substrate porous to form a porous single-crystal Si region 101 on a first non-porous single-crystal Si region 100, a step of forming a second non-porous single-crystal Si region 102 over a surface of the porous single-crystal Si region, a step of bonding a support substrate 110 through an insulating region 103 to a surface of the second non-porous single-crystal Si region, a step of removing the first non-porous single-crystal Si region 100, and a step of removing the porous single-crystal Si region 101, wherein the step of removing the first non-porous single-crystal Si region 100 comprises a step of performing dry etching in which an etch rate of non-porous single-crystal Si region 100 is greater than that of porous single-crystal Si region 101.

Description

4 2 Ο 8 2 趸 85115259 Patent Application ^ Chinese Manual Revised Page Minfeng θ November 2007 7 '7 J' '---, «·»------ ---. · I · Five, DESCRIPTION OF THE INVENTION (1) Background of the Invention Field of the Invention The present invention relates to a S 0 I substrate process with excellent film thickness uniformity and excellent film vacancy (or void) suppression, especially for high-functionality and high-performance electronic devices, integrated circuits, etc. ( S 0 I substrate process on a transparent insulating substrate such as glass or a silicon substrate with an oxide film on it (S 0 I substrate process) · Forming a single crystal silicon semiconductor layer on an insulating hip is called silicon on an insulator (S 0 I) technology, because this substrate has many advantages that cannot be achieved with a silicon substrate used to make general silicon integrated circuits, so many studies have been conducted. [SOS and SIMOX] A traditional SOI technology is the so-called SOS (silicon On sapphire), the technology of heteroepitaxial growth of silicon layer on sapphire crystal, but the quality of heteroepitaxial growth of silicon crystal is poor. S IMOX (separated by implanted oxygen) is actually used as the S 0 I formation technology. Many oxygen ions are implanted into the silicon and then annealed to form the Si 02 layer, and the implanted oxygen is buried from the surface of the silicon to Location of about 0.2 / zm. However, many oxygen ion implantation and annealing require a lot of time, which is not conducive to productivity and cost. Ion implantation causes many crystal defects in the S 0 I silicon layer. Reduction of oxygen ions Implantation is difficult to maintain the film quality of the oxide layer, and it is also difficult to change the thickness of the implanted Si 02 film layer. [Join S 0 I] The paper size of 遢 川 '!, Leisure W 孓 (?: Decision -(cn.s): > 彳:. 'a

-15 !: Please # 而 之; 1: & event blood * 7 too S ^ nil, 1 ^, m ^ i order ---- --- the central government of the Ministry of Economic Affairs to express and eliminate the cooperation of Du Yin Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs r. Η P ~ 厶 2 〇 8 2 · (a7 _______B7 V. Description of the Invention (2) In the recently reported operation of SOI formation, the quality of * bonded SOI * · is particularly good. Two of the wafers (at least one with an insulating film formed by oxidation, etc.) are mirror bonded and annealed to enhance the coupling of the adhesive interface. The substrate is then polished or etched from either side, leaving a silicon sheet of any thickness on the insulating film. Crystalline film β This technology focuses on the steps of modifying the silicon substrate into a thin film. • In particular, 'usually a silicon substrate that is about several hundred μm thick must be uniformly polished or etched to a thickness of several 4 m or even 1 μm or less. Its controllability and Uniformity is difficult. There are two ways to modify silicon into a thin film. One is the method of polishing only by polishing (BPSOI: Bonding and Polishing SOI), and the other is on the remaining film (actually when the single crystal substrate is manufactured) Under the thin film) method for providing an etch stop layer and performing second-level substrate etching and etch stop layer etching (BES 0 I: Bonding and Etching Back SOI) »Since BESOI, the silicon active layer is often epitaxially grown on a pre-formed etch stop layer, BES 0 I is beneficial to ensure uniform film thickness. However, the etch stop layer often contains high Concentration of impurities, resulting in lattice distortion, leading to the transmission of lattice defects to the epitaxial layer. It is also possible that impurities diffuse during the oxidation of the epitaxial layer or during the annealing after bonding, thereby changing the etching characteristics. In these joints S 0 I, if the If the bonding surface is contaminated or uneven due to poor flatness of the bonding surface, many spaces called t-voids appear at the bonding interface. The above-mentioned BESO I is disadvantageous in many cases. The reason is as follows. The etch stop is usually grown by heteroepitaxial growth of CVD. Or epitaxial growth doped with high concentration of impurities. In the case of C VD, especially in the case of heteroepitaxial growth, the flatness achieved is often worse than the flat surface obtained by polishing. * The etch stop is sometimes formed by ion implantation , But the flatness is also degraded in this case. (谙 Please read the notes on the back before filling in this page) The paper size of the booklet applies the Chinese national standard (CNS > A4 size (210 X 297 mm) -5- ^ 320827 Printed by Zhengong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _ B7 _ V. Description of the Invention (3) [New BES Ο I Technology] Achieve good joint surface flatness, such as the uniform film thickness of the active layer of BES Ο I, high An example of the technology of feed-back selectivity in traditional BES 0 I is the technology of anodizing and epitaxially growing a silicon active layer to make the surface of the silicon substrate porous (Japanese Patent Application Laid-Open No. 5-21338). ^ In this case, the porous layer Corresponds to the etch stop layer of BES 0 I. However, compared to single-crystal silicon, porous silicon with a hydrofluoric acid etchant has a high etching rate, so high selective etching characteristics are more important than the stop layer. Because this technology is not a CVD, but a porous Si layer formed by anodizing a flat Si substrate, the flatness of the epitaxial growth active layer is better than that of the BESOI formed by CVD or the like. The epitaxial layer grown on this surface has the property of achieving crystallinity almost equal to that of an epitaxial layer grown on a non-porous single crystal substrate. A single crystal thin film equivalent to an epitaxial layer can be used as an active layer on a single crystal silicon substrate with high reliability, thereby providing a S 0 I substrate with excellent crystallinity and excellent film thickness uniformity. K. Sakaguchi et al. Reported that the surface of the single crystal silicon substrate was anodized to make it porous and epitaxially grown. The substrate was connected to a silicon substrate with an oxidized surface. The non-porous single crystal silicon substrate was ground by a grinder to expose a porous layer. The HF / H20 2 mixture solution was used to selectively etch the porous layer, so that the thickness of the SO I silicon layer film on a 5-inch wafer was 507nm ± l 5nm (± 3%) or 96. 8nm ± 4. 5nm (± 4. Ί %) ° When etching with a / F / H2O2 mixture solution, even in this case, the etching rate of the porous silicon layer is 5 times that of the non-porous silicon layer. Therefore, the porous silicon layer serves as an etching stopper in BESOI. _The standard of single crystal silicon substrate or transparent silicon dioxide paper with thermally oxidized surface is applicable to China National Sample (CNS) A4 * i grid {210 × 297 mm) (Please read the precautions on the back before filling this page ) Central Government Bureau of Standards, Ministry of Economic Affairs, Buyer and Consumer Cooperation Du Yin ^ 420827 A7 __B7 V. Description of the Invention (4) Method for connecting a glass substrate to an epitaxial silicon film grown on this porous silicon * It is also possible to interconnect two substrates S i 〇2 surface. The interface state of the interface between the epitaxial silicon film as the active layer and S i 0 2 (the thermal oxide film of the epitaxial layer) is sufficiently low. The thickness of the S i layer can be arbitrarily controlled. Therefore, the substrate can be made by making full use of the characteristics of S 0 I. Plasma treatment then activates the Si 02 surface of the bonding interface, so the bonding strength can be completely increased and voids can be suppressed. The above-mentioned new BESO I technology can obtain a high-quality SO I substrate. With the highly selective etching of the porous silicon layer, the film thickness distribution preserves the flatness and film thickness distribution during epitaxial growth. However, the new B E S ◦ I technology mentioned above has the following problems in removing non-porous single crystal silicon regions. 1. Problems caused by using wet-type hydrofluoric acid-based etchant This technology involves poor controllability of liquid exchange and liquid concentration management in many substrate treatments, and thus has poor productivity. Hydrofluoric acid-based etchant etches si 02 layer and si 02 glass substrate with its large etch rate. In detail, if a transparent Si 02 glass substrate is connected, the back of the glass substrate is also etched, which destroys the transparency of the transparent substrate. * If Exposing the porous silicon part with a wet etchant such as hydrofluoric acid / nitrate-based etchant or an alkaline solution (as a method to remove non-porous single-crystal silicon regions) | Regardless of the etchant, low density .. Porous The silicon layer has a higher etch rate than non-porous silicon *. Therefore, before removing all non-porous silicon parts, the exposed part of the porous silicon is etched quickly *. Therefore, the residual film thickness of the porous silicon varies greatly, more than a few Am. When the thickness of the porous silicon film is less than a few / zm, the etching further reaches the bottom epitaxial silicon layer under the porous silicon, which destroys the film thickness of the final S 0 I layer (please read the precautions on the back before filling this page)-booklet Paper size General China National Standards (CNS) A4: It grid (210X297 mm) Consumption cooperation between employees of the China Economic Development Bureau, Ministry of Economic Affairs, printed 420827 A7 ___B7 V. Description of the invention (5) Uniformity > Therefore, porous silicon The layer thickness must be more than 10, and the porous silicon layer cannot be thinner than it. 2. Regarding the thickness of the porous silicon layer film, if a grinder is used as a method to remove non-porous single-crystal silicon regions, a thickness of not less than 10 μm is required as the grinding margin of the grinder (at the bottom of the porous silicon) Layer stops grinding) and damage the layer, so the porous silicon layer cannot be thinner than it. Therefore, it takes a lot of time to form and etch porous silicon. SUMMARY OF THE INVENTION Therefore, the object of the present invention is to solve all the problems. (Ufi uses wet hydrofluoric acid-based etchant that removes porous single-crystal silicon regions to reduce productivity and transparent substrate transparency (Such as the problem of thermal annealing, and the problem that the polishing machine cannot be used to trim the porous silicon layer, which requires a lot of time to form and etch the porous silicon). In order to achieve the above objective, the present inventors endeavored to achieve the following invention β. That is, the S 0 I substrate process of the present invention includes the following steps: making the surface layer of the single crystal silicon substrate porous, and forming a porous single crystal on the first non-porous single crystal silicon region. Crystalline silicon region; forming a second non-porous single crystal silicon region on the surface of the porous single crystal silicon region; preparing at least one surface layer as a support substrate for the insulating region; connecting the insulating region to the surface of the second non-porous single crystal silicon region: removing The first non-porous single-crystal silicon region; removing the porous single-crystal silicon region; wherein the step of removing the cold non-porous single-crystal silicon region includes a step of performing dry etching, wherein the etching rate of the non-porous single-crystal silicon region is greater than Porous single crystal sand. This paper size applies the national standard of China (CNS > Α4 size UiOX297 mm) (Please read the precautions on the back before filling this KK)

1T " -8-42082 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) The step of removing the first non-porous single-crystal silicon region is preferably preceded by the step of dry etching The machine partially grinds the step of the zone. Dry etching is best to make the release of electrical or optical energy into activated ion species, which accelerates in a direction perpendicular to the substrate surface. The reaction occurs on the substrate surface. It is best to set the parallel plate electrode on the substrate and observe the change in self-bias voltage between the parallel plate electrode and the substrate, and determine the etching termination point where the porous single crystal silicon region is exposed on the entire surface by dry etching. The step of removing the porous single crystal silicon region can be performed by wet etching of the porous single crystal silicon region more than wet etching of the non-porous single crystal silicon region or more than dry etching of the non-porous single crystal silicon region. The etching rate of the porous single crystal silicon region is greater than that of the non-porous single crystal silicon region. The dry etching is preferably such that an activated group derived from the decomposition of at least electrical or optical energy enters the pores of the porous region, and the region is etched from the inside. The step of forming a second non-porous single crystal silicon region on the surface of the porous single crystal silicon region is preferably a step of epitaxially growing the second non-porous single crystal silicon region on the surface of the porous single crystal silicon region. This step may be a step of performing annealing to close the pores on the surface of the porous single crystal silicon region. Furthermore, the supporting substrate may be a Si wafer, a Si wafer having an insulating surface, or an insulating substrate such as silica glass. If the supporting substrate is a Si wafer, the surface of the second non-porous single crystal silicon region is insulated. The inventors have found that under certain conditions dry etching, the etching rate of porous silicon is several times slower than that of non-porous silicon. The present invention uses dry etching to remove the non-multi-jL capped crystal region. The etching mechanism of non-porous silicon is greater than that of porous silicon. The mechanism is not fully understood, but it can be under the seat. For selective etching of non-porous silicon regions, the surface etch rate is equal to the entry rate of Hua Ning. The rate • For example, using an anisotropic reaction ion in the direction of the electric field (read the precautions on the back before filling this page) '-β This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 420827 Printed by the Ministry of Economic Affairs + Central Standards Bureau Shellfish Consumer Cooperative A7 —_____ B7_ V. Description of the invention (7) Sub-etching mode, such as RIE (Reactive Ion Etching), surface etching can go further. In addition, because the surface of porous silicon is oxidized or its concentration is low, the DC electric field direction component of porous silicon in ion etching mode is different from that of non-porous silicon, so the etching rate of porous silicon decreases. In order to promote surface etching in this ion etching mode, in addition to appropriately selecting the pressure, power, and etching gas in the RF plasma discharge to increase the self-bias voltage • The method of applying a DC bias voltage from the outside is also effective * 100 to several hundred V The application makes the etching rate of porous silicon approximately several to several tens times slower than that of non-porous silicon. When the non-porous wafer portion is removed after bonding, the bottom porous silicon is partially exposed due to the wafer thickness distribution and the etched thickness distribution. However, since the etching rate of this portion is low, the residual thickness distribution of the porous silicon is relaxed, thereby improving uniformity. Since the etching rate selectivity and the uniformity of the coplanar distribution of the etching rate are sufficiently high, when the non-porous silicon-based bottom is etched and the porous silicon portion is exposed on the entire surface, the time control is sufficient to determine the end point of the etching. But productivity-conscious devices can monitor self-bias to determine the end point. That is, since the self-bias voltage drops when the porous silicon is exposed, the end point can be determined with certainty. Since the present invention involves removing non-porous single crystal silicon regions with a conventional wet hydrofluoric acid-based etchant or a base etchant, it solves the difficult control of poor productivity and thick liquid concentration management caused by liquid replacement after many substrate treatments. Problems * In addition, etching of transparent Si 02 glass substrates with hydrofluoric acid-based etchant does not occur during dry etching (solving the problem of transparency degradation of transparent substrates) β If grinding by a grinder or etching with hydrofluoric acid-based etchant , It is difficult to stop the etching in the porous silicon portion> The thickness of the porous silicon film is as thick as 1 Ο ΐ ΐ m or more to maintain the margin. However, the non-porous silicon wafer portion has an etching rate greater than that of the selective etching of the porous silicon layer. The thickness of the porous silicon film can be as thin as 5 to 10. This paper size is applicable to Chinese national standards ^ CNS} A4 size (210X 297 mm) (Please read the precautions on the back before filling this page)

-10-^ ZϋδZ (Α2〇82 ^ Printed by the Ministry of Economic Affairs, Central Fengfeng Bureau, Department of Consumer and Consumer Cooperation, Du Yin A7, B7, V. Description of Invention (8) # m. Anodizing time for forming porous silicon and etching time for etching porous silicon Both have been reduced to the previous half, thus improving productivity * Brief description of the drawings Figures 1A, 1B, 1C, ID, 1E are cross-sectional views explaining the steps of the embodiment of the present invention and the first and second examples: Figures 2A, 2B, 2C, 2D, 2E, 2F are cross-sectional views explaining the steps of the third example of the present invention; FIGS. 3A, 3B ′ 3C, 3D, 3E, 3F are cross-sectional views explaining the steps of the fourth example of the present invention; FIGS. 4A, 4B 4C, 4C, 4D, 4E, and 4F are cross-sectional views explaining the steps of the fifth example of the present invention; Figs. 5A and 5B are cross-sectional views of a device for making a silicon substrate porous. The preferred embodiment is explained in detail with reference to Figs. 1A to 1E. An embodiment of the present invention. (Figure 1 A) A single-crystal silicon substrate 100 is anodized to form porous silicon 1 ◦ 1 »The thickness of the porous layer at this time may be between several Mm and several tens of pm" Refer to Figure 5 A and 5 B Explains the method of forming porous silicon. First, a p-type single crystal silicon substrate 500 is made into a substrate. N-type is not impossible, but it is limited to a low-resistance substrate, or Anodization must be performed in a state where the surface of the substrate is irradiated with light to promote the generation of holes. The substrate 5 0. 0 is set in the device as shown in Figure 5 A »That is, the surface side is in contact with the hydrofluoric acid-based solution 5 0 4 and the negative electrode 5 0 6 is set on the solution side, and the other side of the substrate is in contact with the positive gold electrode 5 0 5. As shown in Figure 5 B, the positive side (please read the precautions on the back before filling this page) This paper size applies to China National Standards (CNS) A4 grid (2 丨 0X297 mm) -11-420827 A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (9.) 505 < Also via solution 504 > Set at a potential ° In any case The formation of the porous layer starts from the negative side of the hydrofluoric acid-based solution. The hydrofluoric acid-based solution 50 is usually hydrofluoric acid (49% HF). When the hydrofluoric acid solution is diluted with pure water (H20), Etching starts at a certain concentration. In some cases, bubbles occur on the surface of the substrate from anodizing, so alcohol is added as a surfactant to effectively remove bubbles. The available alcohols are methanol, ethanol, propanol, isopropyl Alcohol, etc. Use a stirrer instead of a surfactant and stir the solution for anodization The negative electrode 506 is made of a material that is not corroded by a hydrofluoric acid solution, such as gold (Au), platinum (Pt), etc. The material of the positive electrode 505 may be selected from commonly used metal materials, but because of the hydrofluoric acid-based solution 5 0 4 reaches the positive electrode 5 5 after the anodization of the entire substrate 5 0 5 is completed, so the surface of the positive electrode 5 5 5 is best coated with a hydrofluoric acid resistant solution. The anodizing current value can be selected in the hundreds. The range of the maximum value of mA / cm 2 to the minimum value greater than zero is determined to be within a range that allows good quality epitaxial growth on the surface of porous silicon. Generally, as the current value increases, the anodization rate increases and the density of the porous silicon layer decreases. That is, the volume occupied by the pores increases. This changes the epitaxial growth conditions. (Figure 1B) Non-porous single crystal silicon layer 1 0 2 Epitaxial growth on the above porous layer 1 0 1 Epitaxial growth consists of general thermal CVD, low pressure CVD, plasma CVD, molecular beam Epitaxial, sputtering, etc. are performed. It can be determined that the film thickness of the growth layer is the same as the design value of the S 01 layer, but the film thickness is preferably not more than 2 μm. The reason is as follows "If a single crystal Si film with a thickness of 2em or more exists on an insulating substrate containing Si 02 on the car, the Chinese National Standard (CNS) A4 specification (2 丨0X297 mm) (Please read the precautions on the back before filling this page) -12-2082 Printed by A7 B7 Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of the invention (10) Because of the poor expansion coefficient, great stress It occurs at the bonding interface during annealing, causing the silicon film to collapse, the substrate to bend, and the interface to peel off. Since the stress is relatively small and the film thickness is not greater than 2, film collapse, peeling, and bending cannot occur in this case. The film thickness is not greater than 0.5 vm. This is because when the film thickness is not less than 0.5, although the peeling and collapse do not occur during the annealing in the subsequent process, the slip line may occur on the crystal. The pores * on the surface of the porous silicon layer 101 can be closed by annealing to form a porous single crystal Si layer 102. (FIG. 1C) Surface oxidation of the epitaxial layer 102 (103). If the epitaxial layer is directly connected to the support substrate in the next step, impurities tend to accumulate on the bonding interface, and the uncoupled bonds (dangling bonds) of atoms in the interface increase, which is a factor that makes the characteristics of the thin film device unfavorable. The sufficient thickness of the oxide film can be determined within a range that is not affected by the contamination taken from the atmosphere into the bonding interface. (Fig. 1D) The above-mentioned substrate 100 and a supporting substrate 110 having an epitaxial surface were prepared. Specific examples of supporting substrate 1.10 include surface-oxidized silicon substrate, silica glass, crystallized glass, S i 0 2 deposited on any substrate, and the like. When the two surfaces to be bonded are both S0 02, these two substrates or one of them is exposed to the plasma to activate the surface s i 02. The gas used at this time is preferably oxygen, but in addition * the available gases are air (mixture of oxygen and nitrogen), nitrogen, hydrogen, inert gas such as argon or helium, molecular gas such as ammonia, and the like. When the surface composed of Si is connected to the surface composed of Si 〇2, the above treatment is not required * (Please read the precautions on the back before filling this page)

* tT · " This paper size applies to China National Standard (CNS) A4 (210X297 mm) -13-Printed by the Consumers' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 420827 A7 __B7 V. Description of the invention (11) Clean up in the above steps The prepared two substrates were connected to each other thereafter. The preferred cleaning method is to rinse with pure water only. Examples of other solutions that can be used include a solution of hydrogen peroxide diluted with pure water and a solution of hydrochloric acid or sulfuric acid diluted with sufficiently pure water. Pressing the entire substrate surface after joining has the effect of increasing the strength of the joint. The bonded substrate is then annealed. The annealing temperature is preferably as high as possible | but too high a temperature causes the structure of the porous layer 101 to change or impurities contained in the substrate to diffuse into the epitaxial layer. Therefore, temperature and time must be selected. In detail, the preferred temperature is not more than 1 200 ° C. Furthermore, some substrates are not resistant to annealing at high temperatures. For example, if the supporting substrate 1 10 is silica glass, the difference in thermal expansion coefficient between silicon and silicon dioxide must be maintained at a temperature not greater than about 200 ° C. Temperature annealing. The temperature at which * the bonded substrate is peeled or damaged due to stress. But as long as the interface can withstand the grinding of silicon 100 and the stress in the next step of etching, annealing is sufficient. Therefore, the activated surface conditions are optimized and can be processed even at a temperature not higher than 200 ° C. ('Figure 1E) Next, the silicon-based bottom 100 and the porous part 10 1 are selectively removed, leaving Lei晶 层 102。 Crystal layer 102. First, the non-porous silicon-based bottom 100 is ground by a surface grinder and the like, and thereafter is etched by RI Ε, or the entire silicon-based bottom 100 is removed by RI Ε without polishing. When the Si base portion 100 is removed by the abrasive portion, the Si base portion on the porous silicon region 10 1 is preferably left in a thickness range of 2 to 3 00. A thickness range of 5 to 100 μm is better. As for non-porous silicon-based bottom etching, the focus of the present invention is that the surface etching rate is equal to or greater than the penetration rate of the substrate or the like. Therefore, the use of reactive ion etching mode (such as RIE) with anisotropy in the direction of the electric field can further touch the paper size. Applicable to the Chinese national standard < CNS) A4 size (210X297 mm) (Please read the precautions on the back first) (Fill in this page again) -14-Printed by 420827 A7 _B7_ Cooperative of the Central Government Bureau of the Ministry of Economic Affairs V. Description of Invention (12) Engraved surface. Furthermore, because the surface of porous silicon is oxidized or its density is small, the DC electric field distribution in the ion etching mode changes between non-porous and porous silicon, so the etching rate of porous silicon decreases. In order to promote the surface etching in this ion etching mode, the pressure, work, rate, and etching gas in the RF plasma discharge must be appropriately selected. Reactive ion etching is performed so that an etching gas such as H2 gas, C F4 or S F6 containing F atoms is mixed with a carrier gas such as 02 or 1 ^ 2 gas, or a mood such as He or Ar, and is RF or microwaved. The plasma generated by the power may be decomposed by light energy, and the activated ions reach the surface of the etched substrate when it is accelerated in the direction of the electric field, so the surface is etched. When setting the discharge conditions, it is important to set the discharge pressure low enough to ensure a long average free path for the gas molecules to achieve free energy. "A greater RF power increases the DC bias component between the electrodes to promote ion etching. Decomposition reaction, so the base etching mode is also mixed. Therefore, attention must be paid to this situation. In addition to increasing the self-biased house by RF power, the method of applying DC bias from the outside is also effective. Applying 100 to several hundred V improves the etching rate of non-porous silicon, and even several hundred Am etching is completed in a few hours. The etching rate of the porous silicon at this time is several to several tens times slower. Therefore, when the non-porous wafers are removed after bonding, the bottom porous silicon is partially exposed due to the wafer thickness distribution and the etching thickness distribution. However, since the etching rate of this portion is slow, the thickness distribution of the remaining porous silicon is widened, thereby improving uniformity. The use of magnetron plasma or E C R plasma is also effective to promote ion etching. As described above, when the porous portion 101 is exposed after etching the non-porous silicon-based bottom portion 10 ζ), the etching stops once. Due to the sufficient selectivity of the etching rate, this paper size is applicable to China National Standard (CNS) Α4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page) Order -15-420827 Central Ministry of Economic Affairs Printed bag A7 of quasi-office consumer and consumer cooperatives _____ B7 V. Invention description (13) Because of the sufficient coplanar distribution uniformity of etching rate, time control can determine the saturation end point *, but monitoring self-bias can also be determined. That is, when the porous silicon is exposed, since the self-bias voltage drops, the end point can be determined with certainty. Next, the bottom porous region 1 01 is removed by wet etching. The hydrofluoric acid is removed with a general contact agent of si or a selective etchant of porous silicon, and the non-porous region is exposed. Specific examples of the selective etchant include hydrofluoric acid, a mixture of hydrofluoric acid with at least one of an alcohol and hydrogen peroxide, buffered hydrofluoric acid, and a mixture of buffered hydrofluoric acid with at least one of an alcohol and hydrogen peroxide. The general etchant of Si can also selectively etch only porous silicon due to its large surface area. Since a low-concentration hydrofluoric acid etchant can be used for wet etching of the porous region 101, the phenomenon of dissolving Si02 is apparent. Dry etching can also remove the bottom porous part 1 0 1 »In porous silicon, there are tens to hundreds of angstroms of holes from the surface to the inside. The holes penetrate into the holes and the base of the etching is attached to the hole wall to start etching from the side wall and attached to Thin pillars with columnar structure, so the porous silicon part is finally split and removed. On the other hand, non-porous silicon has no pores, so only the surface is etched. For example, suppose that the substrate involved in the etching penetrates into the pores with a depth of tens of tens of angstroms on the non-porous surface and attaches to the hole of the porous silicon. Split, so tens of jtzm etching of porous silicon is performed. The important point is that the rate of penetration of the substrate involved in the etching and attaching to the pores of the porous silicon is sufficiently higher than the surface etching rate "So> The point of the present invention is that the etching to remove the porous silicon is in a chemical-based etching mode, wherein Diffusion to etch, etching is performed isotropically. Due to the anisotropic reactive ion etching (such as general RIE) in the direction of the electric field, the surface is etched beyond the surface. This paper size applies the Chinese standard (CNS) A4 size (210X297 mm) (Please read the precautions on the back first) (Fill in this page again.) -16-420827 B7 Imprint of the Consumer Cooperatives of the Central Prototype Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (14) Therefore, it is not used as the etching β here, but the appropriate conditions such as gas flow rate pressure are selected. * The RIE etching device can also achieve the saturation here. The discharge conditions must be set to keep the discharge pressure high and the average whiteness of the gas molecules to be short. The secondary reaction of ions can be promoted to keep the substrate white bias low without activating ions. The surface etching method is effective by applying a DC bias reversely from the outside to the white bias or by positioning the etching base on the anode side of the electrode. However, it is difficult to completely suppress the ions from reaching the best base. The zone is distinguished from the etching and provides a process for transporting the substrate therebetween. «Etching gas such as Krypton 2 gas or C F4 or SF β of F atom mixed with carrier gas such as 0 2 or N 2 gas. Electricity formed by RF or microwave The secondary reaction of the slurry or the base gas with the carrier gas Γ3 & etc. occurs in the gas phase of the transportation process to obtain a more stable and long-lived etching base. 0 This is because the etching gas reaches the non-etching substrate 9 or when the substrate is in When heating or vibration during etching, it promotes the isotropic diffusion of the group to a more stable position and thus promotes the penetration of pores in porous silicon. Therefore, the etching rate of porous silicon is 105 to 106 times that of non-porous silicon. ] () 2 is non-porous, so its etching rate is less than that of porous silicon. Etching is almost non-occurring. Therefore, the Jiajing layer 1 0 2 is a thin film with uniform film thickness achieved during the growth of Jiajing. 〇 Furthermore, the following steps may be added in some cases. (1) The inner wall of the pores of the porous layer is oxidized (pre-oxidized). The thickness of the wall between adjacent pores of the porous silicon layer is very small η m to several tens m. 〇For example, when the epitaxial Si layer is formed or when annealing is performed after joining) Sometimes the pore walls are made to adhere to each other at the high temperature of the porous layer. ♦ The pore walls become larger and thicker to apply the Chinese paper standard to the Chinese standard. (CNS) A4 specification (2 丨 0X297) 嫠 -17-Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed 42082 A7 ____B7 V. Description of the invention (15) Closed, thus reducing the etching rate. If a thin oxide film is formed on the pore wall after the porous layer is formed, it prevents the pore wall from becoming larger and thicker. However, since the non-porous single crystal Si layer must be epitaxially grown on the porous layer, it is necessary to oxidize only the inner wall surface of the pores to leave single crystallinity in the pore walls of the porous layer. The formed oxide film preferably has a film thickness of several A to several tens A. An oxide film of this film thickness is formed by annealing in an oxygen environment at a temperature ranging from 200 ° C to 700 ° C (preferably at a temperature ranging from 250 ° C to 500 ° C) * (2 ) Hydrogen baking treatment EP 5 5 3 8 5 2A2 shows that annealing under a hydrogen environment can remove the fine unevenness on the Si surface to obtain an extremely smooth Si surface. Baking under a hydrogen environment can also be used in the present invention. For example, before the porous silicon layer is formed into an epitaxial Si layer, hydrogen baking may be performed. Hydrogen baking may be performed on the S 0 I substrate obtained after the porous silicon layer is removed by etching. During the formation of the epitaxial Si layer, the hydrogen baking process causes the phenomenon that the outermost surface is blocked by the migration of the Si atoms constituting the porous silicon surface. When the epitaxial Si layer is formed along the outermost surface of the barrier hole, an epitaxial Si layer with fewer crystal defects is obtained. On the other hand, the hydrogen baking performed after the porous silicon layer is etched has the effect of flattening the surface of the epitaxial Si that is thickened by the etching, and helps to take boron from the air into the clean room and thermally diffuse the porous silicon layer to the epitaxial The boron in the Si layer diffuses out to the bonding interface to drive out the boron. By performing this step, a S 0 I substrate with a good film thickness distribution or a transparent insulating substrate forming a single silicon crystal can be obtained. In the possible modification of the above S 0 I substrate process, the surface of the epitaxially grown non-porous single crystal silicon region 1 02 is connected to an Si wafer with an oxide film (please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) -18-

42082T A7! ------ -B7_ V. Description of the invention (16) 1 1 0 ′ does not form an oxide film 103 on the surface of the region 102. In another possible modification, an oxide film is formed on the surface of the non-porous single crystal silicon region 10 2 and is connected to the Si wafer 1 1 0 without an oxide film. (Please read the precautions on the back before filling this page) Example [Example 1] The first example of the present invention will be described in detail with reference to Figures 1A to 1E and Figures 5A and 5B. (Figure 1A) Prepare about 300 #m thick 6 Inch p-type (100) single crystal silicon substrate (0.1 to 0.2Qcm), set in a device such as circle 5 A, and anodizing only changes the surface of the silicon substrate 100 to porous silicon 101. The solution 504 at this time was a 49% HF solution, and the current density was 10 OmA / cm2. The formation rate of the porous layer at this time was 5 Am / min, and the porous layer was 10 μrn thick after two minutes. (Fig. 1 B) The single-crystal silicon layer 102 was epitaxially grown by CVD on the porous silicon 100 with a thickness of 0.3. The deposition conditions are as follows. Printed by Shelley Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs Gas used: SiH4 / H2 Gas flow rate: 0.62 / 140 (i? / Min)

Temperature: 7 5 0 ° C Pressure: 8 ◦ T 〇rr Growth rate: 0.1 ISem / min (Fig. 1 C) The substrate prepared by the above method was treated in a steam environment at 900 ℃ to obtain 0.2 0 μm oxide film 1 0 3 »f-circle 1 D) Clean substrate with oxide film 1 0 0 and pre-made paper 伕 standard common Chinese national standard (CNS > A4 size (210X297 mm) -19- 420827 A7 B7 V. Description of the invention (17) _ Support substrate (bare silicon wafer without silicon dioxide film) 1 1 0, then spin-dry, and then interconnect with each other. In this case, the original adhesive strength is due to the si surface and The surface of S i 〇2 is high, but after bonding, it is annealed at 1150 ° C for five minutes to further improve the adhesive strength. (Fig. 1E) After annealing, the non-porous single crystal substrate 100 is on the parallel plate. The plasma etching system selectively etches to expose the porous silicon 1 0 1 = At this time, the thickness of the bonded wafer is changed, and the thickness of the porous silicon layer is changed during anodization. Therefore, the maximum value of the bottom of the non-porous single crystal substrate 1 0 0 The thickness varies by about 300 ± 5 / zm. The etching conditions at this time are as follows.

Frequency: 13.56MHz Power: 1 k W SF6 gas flow rate: 1 〇◦◦ sc oxygen flow rate: 300 sccm pressure: 2 0 P a substrate bias: 500V processing time: 63 minutes non-porous silicon under the above conditions The etching rate is η «and the porous silicon is 1 wm / mi η. If the bottom of the non-porous single crystal substrate 1 0 0 is about 2 9 5 in the worst case, overetch for three minutes; if it is 3 0 5

Mm, over-etch for one minute. At this time, the etching thickness of the porous silicon 101 is 4 // m and 2 Am, respectively. Therefore, in the worst case, the etching of the porous silicon 101 can be stopped at 10 μm. At this time, the end point is not determined, but the porous silicon layer of the six substrates * all substrates provided in the etching system is exposed on the entire surface at a set processing time, and the common wafer surface of the residual thickness is distributed on the paper standard. Chinese national standards apply (CNS) A4 specification (2 丨 0X297 mm) (Please read the precautions on the back before filling out this page) Order-Gas __ Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economy-20-Staff of the Central Bureau of Standards of the Ministry of Economy Printed by a consumer cooperative 420827 A7 _________B7 V. Description of the invention (18) within 10% * Then the substrate is etched with a conventional hf / h20 2 solution, and the porous sand is removed by wet etching. 11 Result 'with a silicon dioxide film of 0-2 / im The excellent ultra-thin single-crystal silicon film with a film thickness distribution of about 80 nm ± 5 ′ 4 nm above forms an S 0 I substrate. [Example 2] Example 2 had the same steps as in Example 1 before the step of removing the non-porous single crystal silicon region 100 (Figs. 1A to 1E). This substrate was then set in a microwave-excited chemical dry etching system to selectively etch only the porous portion 101. This system is divided into an area where plasma is generated by microwave power and an area where etching is performed, so that ion species do not reach the unetched substrate. The etching conditions at this time are as follows. Microwave frequency: 1GHz Microwave power: 100W SFe gas flow rate: 100 sccm ◦ 2 flow rate: 500 sccm N 2 flow rate: SOCsccm pressure: 1 0 0 P a Processing time: 30 minutes non-porous under the above conditions The silicon etching rate is as high as about 5 X 1 0_4 iim / mi η «But because the etching first entered the holes of the porous silicon ', the surface engraving was not seen. The porous silicon layer suddenly began to split about 20 minutes after the etching started (please read the precautions on the back before filling in this page) The paper size is free to use the national standard (CNS) Α4 specification (2 丨 0X297 mm) -21-420827 A7 B7 printed by Shellfish Consumer Cooperation of the Central Bureau of Standards and Quarantine of the Ministry of Economic Affairs 5. Description of the invention (19) 1 bell > After 30 minutes from the start, the residual thickness change of α porous silicon i 1 is at most The bad case is about 6 to 8 β ΤΠ 〇 Suppose the i I overetching of the bottom Jiajing single-crystal silicon layer 1 2 is about 10 minutes in 30 minutes. Then the overetching of the single crystal silicon 1 I is not more than 5 0 A does not affect the uniformity achieved during epitaxial growth. Please note 1 Method 1 Monitoring the fluorescence of the etched surface »The end point of the etching can be determined but the back is read during the etching! With 0 6 β m two There is about 1 8 0 η m on the silicon oxide film. Matters 1 and 1 1 soil 5 4 (± 3%). Excellent ultra-thin single-crystal silicon film with film thickness distribution to obtain f 1 S 0 I substrate 〇 page 'W 1 1 IC Example 3 1 1 1 f Refer to ISJ Figures 2 A to 2 F for a detailed description of the third example of the present invention (Figure 2 A) Preparation of 3 0 0 β m thickness 0 • 0 1 Ω • C m 6 inches of resistance i coefficient P-type (1 0 0) silicon substrate 2 0 0 only 1 0 β m 1 I The surface layer becomes porous silicon in the same manner as in the first example 2 0 1 g! | (Γ ^ Ι Figure 2 B) Shape / text on the obtained porous surface in the same way | into 0-1 5 β thick Jiajing layer 2 0 2 9 1 1 I (ΓΒ | 1 Fig. 2 C) The substrate prepared by the method at 1 0 0 0 ° c steam Oxidation 1 1 I 0 1 β m (2 0 3) 9 L 1 (Figure 2 D) Surface of the above substrate and prefabricated 6-inch synthetic silicon dioxide substrate 2 1 0 Plasma treated substrate with oxide film 2 0 3 1 1 2 0 0 and prefabricated support substrate (synthetic silicon dioxide substrate) 2 1 0 Set 1 | The surface of each substrate of the parallel plate plasma processing system is charged with oxygen The pulp is activated. I The 9 conditions are as follows: 0 1 1 I This paper size is applicable to the Chinese National Standard (CNS) A4 (2 丨 OX 297 mm) -22-420827 A7 B7 Central Standard of the Ministry of Economic Affairs—Industrial and Consumer Cooperatives Printed 5. Description of the invention (20) ί RF frequency 1 3 5 6 Μ Z 1 1 RF power 4 0 0 W 1 1 Oxygen flow rate 3 0 SCC m 1 1 Pressure: 2 0 P a Please read 1 first Time 1 1 minute read back 1 Special control of no bias between the plasma and the substrate is only made by the plasma! I mean 1 I white bias-treated surface Matter I again 1 I (Figure 2 Ε) silicon substrate 2 0 0 and silicon dioxide substrate 2 1 0 immersion and filling% 1 of this pure water for five minutes and then spin-drying the surfaces and then connect to each other 0 then I page 1 I at 3 0 0 ° C annealing for ten hours 〇 t [I (Figure 2 F) First, I 1 was etched by RIE under the same conditions as in Example 1 1 2 etched 2 9 0 β m thick silicon-based bottom 2 0 0 〇 porous silicon layer After the 2 0 1 surface is exposed, the porous layer is selectively etched by wet etching in the same manner as in Example 1 1 2 0 1 0 At this time, the silicon dioxide substrate is not etched at all 2 1 0 0 The method can determine the end point of etching but the etching time is controlled by 1 I. It is sufficient due to the great selectivity. The result is 9 8 2 η m ± 3 4 1 1 1 η m on the silicon dioxide substrate (soil 3 • 5%) Film thickness distribution of silicon single crystal thin film obtained S 0 I [1 Base 0: 丨 · 1 t- ί C Example 4) i 1 1 Refer to ΓΗ * 1 Figure 3 A to 3 F Detailed description of the fourth example of the present invention 0 1 I (Figure 3 A) Preparation 3 0 0 β m thickness 0 0 1 Ω • C m electrical 1 I resistance system at 5 o'clock P-type (1 0 0) silicon substrate 3 0 0 only from the surface 5 1! 1 This paper size applies to China National Standards (CNS) A4 Grid (210X297 mm) -23-42082: / Printed by A7, Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 87___ V. Description of the invention (21) The porous layer 301 is formed thick. (Fig. 3B) In the same manner as in the first example, a 0.15 / im-thick epitaxial wafer 3 0 2 »(Fig. 3C) was prepared on the porous surface of the substrate in the same manner as in Example 1. The environment was treated at 900 ° C to obtain an oxide film of 0.054 m. (Figure 3D) The substrate 300 with an oxide film and the prefabricated support substrate (silicon wafer) 3 with a silicon dioxide film 3.2 are set in a parallel plate plasma processing system. The surface of each substrate is similar. Example 3 was activated under oxygen plasma conditions. (Fig. 3E) The two substrates thus surface-treated are immersed in pure water for five minutes, spin-dried, and the treated surfaces are connected to each other. Thereafter, it was annealed at 400 ° C for six hours. (Fig. 3F) After annealing | Similar to the above, in a parallel plate plasma etching system, the side of the silicon substrate 300 is selectively etched under the following conditions, thereby exposing the porous silicon 3 ◦ 1. RF frequency: 13. 56MHz RF power: 1 k W 匸 卩 4 gas flow rate: 800 sccm Ar gas flow rate: 200 sc cm pressure: 5 P a substrate bias: 500V processing time: 9 9 minutes to 102 minutes Η。 The etching rate of non-porous silicon under the above conditions is 3.1 μm / mi r}, and the porous silicon is 0. η. Similar to Example 1, (Please read the precautions on the back before filling in this page) This paper size applies the Chinese National Standard (CNS) Α4 specification (210 × 297 mm) -24 — printed by the Shell Industry Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs 420827 A7 __ B7 V. Description of the invention (22) The worst case of 3 0 0 at the bottom of the non-porous single crystal substrate has a change of 3 0 to 3 0 5 // m, for example, in the case of etching at 1000 minutes, the porous Silicon is over-etched for 1.6 to 4.8 minutes. At this time, the etching thickness of the porous silicon 301 is 0. 69 # ιη and 2. l // m. Even in the worst case, the etching of the porous silicon 301 can be stopped, leaving 2.9 to 4.3. // m thick. Monitor the self-bias to determine the end point. When the self-bias is 900V to 700V, stop the discharge as the end point of porous silicon etching. For the six substrates provided in the etching system, the porous silicon of all the substrates is exposed on the entire surface. The co-wafer surface of the residual thickness is distributed within 10%. Then the substrate is set in a microwave-excited chemical dry etching system, only selective. Etched porous part 3 0 1. The etching conditions at this time were almost the same as those in Example 1, but the substrate was heated and ultrasonically vibrated. Microwave frequency: 1 G Η z Microwave power: 1 0 0 W 5-3 Gas flow rate: 100 seem 〇a flow rate: 500 sc cm N2 flow rate: 500s ccm pressure: 1 0 0 P a substrate temperature: 3 0 0 ° C Ultrasonic: 1 kW ♦ Processing time: 10 minutes Under the above conditions, the non-porous silicon etch rate also reaches 5 χ 1 0— / min. The effect of substrate heating and ultrasonic vibration first promotes diffusion to porous silicon (please read the precautions on the back before filling this page)

， 1T This paper size is applicable to China National Standards (CNS) Α4 standard (2 丨 0 × 297 mm) -25-420827 Printed by Shellfish Consumer Cooperatives of China Standard Sample Bureau of Ministry of Economic Affairs A7 _____B7_ V. Description of Invention (23) The pores of the pores also promote physical splitting, and almost all bottom epitaxial layers are exposed after 7 to 8 minutes, and the porous part is completely etched after 10 minutes. Even if the bottom epitaxial single crystal silicon layer 3 is over-etched for 10 minutes, the over-etched thickness is not more than 50 A, which does not affect the uniformity achieved during epitaxial growth. Using the method of monitoring the fluorescence of the etched surface, the endpoint of the etch can be determined. But the control of the etch time is sufficient because of the great selectivity. As a result, there is about 100. 8nm ± 3. 4 (± 3.4%) Excellent ultra-thin single-crystal silicon film with film thickness distribution to obtain SO I substrate. [Example 5] A fifth example of the present invention will be described in detail with reference to FIGS. 4A to 4F * (FIG. 4A). A 5 inch ρ-type (1 0 0) silicon substrate 400 with a resistivity of 01 Ω · cm has a porous layer 4 0 1 only 5 μm thick on the surface. (Fig. 4B) In the same manner as in the first example, a 0.15 # 111 thick crystal layer 4 02 was formed on the porous surface of the obtained substrate. (FIG. 4C) The substrate prepared by the above method was processed in a steam environment at 900 ° C to obtain a 0.05 μm oxide film 403. (Fig. 4D) The substrate 400 with an oxide film and the prefabricated support substrate with a silicon dioxide film 0.2 thick ('silicon wafer) 4 1 0 are set on a parallel plate plasma processing system, and the surface of each substrate Activated under oxygen plasma conditions similar to Example 3. (Figure 4 E) The two substrates treated in this way are immersed in pure water for five minutes. This paper size applies to Chinese national standards (CNS M4 specifications (210X297 mm). (Please read the precautions on the back before filling out this page).) ^ I -26-Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 420827 a7 B7__ V. Description of the invention (24) Rotary drying, and then the surfaces after treatment are connected to each other. After that, it will be annealed for 6 hours at 40 °. ( (Fig. 4F) After annealing, similar to the above-mentioned, the side of the silicon substrate 400 is selectively etched in the parallel plate plasma etching apparatus under the conditions of Example 3, thereby exposing porous silicon 41. Non-porous silicon under this condition The etching rate is 3.1 μm / min, while the porous silicon is 0.43 / zm / min. Similar to Example 1, the worst case of a non-porous single crystal substrate at the bottom of 4 0 has a change of 300 to 30 5em, such as' In the case of etching for 100 minutes, the porous silicon is over-etched for 1.6 to 4.8 minutes. At this time, similar to Example 3, even in the worst case, the etching of porous silicon 4 0 1 can be stopped, leaving The next 2. 9 to 4.3 / ζπι * monitor the self-bias to determine the end point. 'When the self-bias is 9 0V to 7 0V', stop Electricity is used as the end point of porous silicon etching. 'This substrate is set on a photo-excited Η 2 base generation system' and only selectively etches the porous part 4 0 1. Since the area where ^^ 2 is generated is separated from the etched area, the plasma is not used for In the case of light excitation, the ion species does not reach the substrate. The etching conditions at this time are as follows: Excitation light source: low-pressure mercury lamp (253. 7 e V) H2 gas flow rate: 100 sc cm pressure: 1 0 P a substrate temperature: 300 ° C Ultrasonic: 1 kW Processing time: 30 minutes Non-porous in this optically decomposed Η 2 base etch under the above conditions (please read the precautions on the back before filling this page) Applicable to National Standards (CNS) Α4 specifications (210 × 297 mm) -27-420827 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy ¾ 5. Description of the invention (25) The silicon etching rate is also about 2 X 1 0 1i η. The effect of substrate heating and ultrasonic vibration first promotes the diffusion into the pores of porous silicon, and because the pore wall etching also promotes physical splitting, almost all bottom epitaxial layers are exposed after the beginning of 20 minutes. The holes are completely etched after 30 minutes Even if the bottom epitaxial single silicon The layer 4 was over-etched for 10 minutes, and the over-etched thickness was not greater than 50 Α, which did not affect the uniformity achieved during epitaxial growth. The end point of the etch can also be determined by monitoring the fluorescence of the etched surface, but the control of the etch time It is extremely selective and sufficient. As a result, S 0 is obtained with a thin film having a thickness of approximately 99.8 nm ± 3.6 (± 3. 6%) on a 0.25em silicon dioxide film with a thin film thickness distribution. I 基。 I base. [Example 6] A sixth example of the present invention will be described in detail with reference to Figs. 1A to 1E and Figs. 5A and 5B. (FIG. 1A) A 600 # ιη thick 6 o'clock p-type (100) single crystal silicon substrate (0.1 to 0.2 Ω · (: ιη)) was prepared, and the device β in FIG. 5A was then anodized, and only silicon was used. The 10 # m surface of the substrate 100 becomes porous silicon 101. At this time, the solution 504 is a 49% HF solution, and the current density is 100 mA / cm2. Furthermore, the porous layer formation rate at this time is 5um / mi η. After 1 minute, a porous layer 1 was obtained. It was from m thick. (Fig. 1 B) The single crystal silicon layer 1 〇2 was grown on the porous silicon 1 0 1 by CVD. The deposition conditions were the same as in the first example. This paper The scale applies to China's national kneading rate {CNS) Α4 specification (210X297 mm) (read first and read the notes on the back before filling this page) l · Order! -28-Printed by 420827 A7 B7, Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy _ V. Description of the invention (26). (Figure 1 C) The substrate produced by the above method is processed in a steam environment at 900 ° C. An oxide film 103 of 0.20 # m was obtained. (Fig. 1D) Clean the substrate with oxide film 100 and the prefabricated support substrate (bare silicon wafer without silicon dioxide film) 1 10, then spin dry, and then connect to each other. In this case, although the adhesive strength was originally high due to the bonding between the Si surface and the Si 102 surface, after bonding, it was annealed at 1 1 50 ° C for five minutes to further improve the adhesive strength. (Figure 1 E) After annealing, the side of the silicon substrate 100 was ground by a grinder for about 5 50 # m. Furthermore, similar to the above example, the bottom of the non-porous single crystal base of about 40 # m was in a parallel plate plasma etching system. Selective etching to expose the porous silicon 1 0 1 »At this time, there is a change in thickness of the bonded wafer, a change in the polishing thickness of the grinder device, and a change in the thickness of the porous silicon during anodization. Therefore, the maximum thickness change of the non-porous single crystal substrate bottom 100 is about 40 ± 5 # m »The etching conditions are as follows. RF frequency: 13.56MHz

R F power: 1 k W Taiwan 卩 gas flow rate: 100 sccm oxygen flow rate: 300 sc cm pressure: 2 ◦ P a

Substrate bias: 500V Processing time: 11 minutes Under the above conditions, the etching rate of non-porous silicon is 5 μm / m i n, and porous sand is 1 Mm / m i η. If the bottom of the non-porous single crystal substrate is about 10 Q in the worst case, about 3 5 am, then over-etch for 4 minutes. "If not many paper sizes apply the Chinese National Standard (CNS) A4 size (210X297 mm) (Please read the back Note for refilling this page) Order-29 420827 A7 ____B7_ V. Description of the invention (27) The bottom of the single crystal base with a thickness of 100 Å is 4 5 / xm, then over-etch for 2 minutes. At this time, the etching thickness of the porous silicon 101 is 4 / im and 2 respectively, and even at worst, the etching can be stopped within 10 mm of the porous silicon 101. At this time, no special judgment is made on the end point, but all six substrates' porous silicon provided in the etching system are exposed on the entire surface within a set processing time. The co-wafer plane of the residual thickness of porous silicon is distributed within ± 10%. This substrate was then wet-etched with a conventional HF / H20 2 solution to remove the porous part. As a result, the thickness was about 108 nm ± 3.2 nm (± 3%) on a 0.2 # m silicon dioxide film. Excellent ultra-thin monocrystalline silicon film with S 0 I substrate (please read the precautions on the back before filling this page). I · Printed by the Central Standards Bureau of the Ministry of Economy Half (CNS) A4 size (210x297 mm) -30-

Claims (1)

420827 B & CS • Patent Application No. 85115259 Chinese Patent Application Amendment November 1987 1. A SOI substrate process including the following steps: Making a part of the single crystal silicon substrate porous To form a porous single-crystal silicon region on the first non-porous single-crystal silicon region: forming a second non-porous single-crystal silicon region on the surface of the porous single-crystal silicon region: attach the single-crystal silicon substrate to a supporting substrate in order to obtain A multilayer structure, wherein the second non-porous single crystal silicon region is built into the multilayer structure; removing the first non-porous single crystal silicon region; removing the porous single crystal silicon region: wherein the step of removing the first non-porous single crystal silicon region includes The dry etching step is performed, in which the non-porous single-crystal silicon region has a higher etch rate than the porous single-crystal silicon region J— i Ί. III mounting ti (please read the precautions on the back first iv page) J—Order the central standard of the Ministry of Economic Affairs Printing by the Office of the Consumer Cooperative 2 Removed the part 3 Dry etching in the vertical 4 Etching on the substrate self-biased. For example, a non-porous single crystal grinding application for a patent is applied. If applied, the electricity is applied to the substrate. Provides changes on the surface. * A patented parallel plate with a non-multiple patented or light surface can be used to determine the SOI substrate process of multi-range item 1. The silicon area step is packaged with monocrystalline silicon before the dry etching step. Steps in the zone · Fan 1's SO 1 substrate process, in which the activated ion species are formed freely, and the direction of the activated ion species is accelerated | The reaction occurs on the substrate surface. The so I substrate process of the third item, in which the single crystal silicon region of the electrode and the hole between the parallel plate electrode and the substrate is exposed on the entire surface by dry etching. The iron scale of the paper is used (CNS) A4J ^ l grid (210X297mm) 420827 Β8 C8 D8 Ministry of Economic Affairs, printed by the Central Government Bureau of Industrial and Commercial Cooperatives, patent application scope 5. For the SOI substrate process of the first scope of the patent application, the step of removing the porous single crystal silicon area The eyelashes are implemented by wet etching, in which the etching rate of the porous single crystal sand region is greater than that of the non-porous single crystal silicon region. 6. For example, the SOI substrate process of claim 1 in which the step of removing the porous single crystal silicon region is performed by dry etching * where the etching rate of the porous single crystal fragment region is greater than that of the non-porous single crystal silicon region * 7. The SOI substrate process of item 6 of the patent. The porous single-crystal silicon region has a higher etching rate than the non-porous single-crystal silicon region. The dry etching allows the activation group that leads from the decomposition of at least electrical or optical energy to enter the pores of the porous region and etches from the inside. Porous region 8. The process of removing the first non-porous single-crystal silicon region as described in the patent application for the first SOI substrate process includes: grinding the first non-porous single-crystal silicon region, and then performing activation Ion etching. 9. According to the SOI substrate process of claim 1, the step of removing the first non-porous single crystal silicon region includes: grinding the first non-porous single crystal silicon region * and then performing activated ion etching: where The step of removing the polycrystalline silicon region includes: performing wet etching, the non-porous single crystal silicon region has a lower etching rate than the porous single crystal silicon region; or performing radiation etching, the non-porous single crystal silicon region also has an etching rate lower than that of the porous single crystal silicon region. Crystal silicon area β This paper is applicable in the national standard (CNS) A4 grid (2 丨 0 > &297;#) 丨 M: ————— 装 — (Please read the precautions on the back first ^ f this page)