TW420827B - Fabrication process of SOI substrate - Google Patents

Fabrication process of SOI substrate Download PDF

Info

Publication number
TW420827B
TW420827B TW085115259A TW85115259A TW420827B TW 420827 B TW420827 B TW 420827B TW 085115259 A TW085115259 A TW 085115259A TW 85115259 A TW85115259 A TW 85115259A TW 420827 B TW420827 B TW 420827B
Authority
TW
Taiwan
Prior art keywords
porous
crystal silicon
etching
porous single
substrate
Prior art date
Application number
TW085115259A
Other languages
Chinese (zh)
Inventor
Tadashi Atoji
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP32510596A external-priority patent/JP3250721B2/en
Application filed by Canon Kk filed Critical Canon Kk
Application granted granted Critical
Publication of TW420827B publication Critical patent/TW420827B/en

Links

Landscapes

  • Weting (AREA)

Abstract

A fabrication process of SOI substrate efficiently removes a non-porous Si region on a porous Si region, and solves the problem that a glass substarte is inevitably etched and the problem that a relatively thick porous Si region is necessary. The fabrication process of SOI substrate comprises a step of making a surface layer of a single-crystal Si substrate porous to form a porous single-crystal Si region 101 on a first non-porous single-crystal Si region 100, a step of forming a second non-porous single-crystal Si region 102 over a surface of the porous single-crystal Si region, a step of bonding a support substrate 110 through an insulating region 103 to a surface of the second non-porous single-crystal Si region, a step of removing the first non-porous single-crystal Si region 100, and a step of removing the porous single-crystal Si region 101, wherein the step of removing the first non-porous single-crystal Si region 100 comprises a step of performing dry etching in which an etch rate of non-porous single-crystal Si region 100 is greater than that of porous single-crystal Si region 101.

Description

4 2 Ο 8 2趸85115259號專利申請案 ^ 中文說明書修正頁 民風θ7年11月呈 Η 7 J ' ' -—、里« ·»—— - ---- ---. · I · 五、發明説明(1 ) 發明背景 發明領域 本發明關於膜厚度均勻性和膜空位(或空隙)抑制優 良的S 0 I基底製程,尤指用於高功能性和高性能電子裝 置、積髅電路等(在玻璃之類的透明絕緣基底上或其上有 氧化物膜的矽基底上製造於單晶半導體層)的S 0 I基底 製程· 在絕緣髖上形成單晶矽半導體層稱爲矽在絕緣體上( S 0 I )科技,因爲此基底有許多用於製造一般矽積體電 路之塊矽基底不能達成的許多優點,故進行許多研究》 〔SOS 和 SIMOX〕 一傳統SOI科技是所謂的SOS (矽在藍寶石上) ,是在藍寶石晶體上異磊晶生長矽層科技,但異磊晶生長 矽晶體的品質差。S IMOX (由植入的氧分離)實際上 做爲S 0 I形成科技,將許多氧離子植入矽,其後退火, 藉以形成S i 02層,而植入的氧埋在從矽表面至約 0. 2 /zm的位置。但許多氧離子植入和退火需要許多時 間,不利於生產力和成本,離子植入在S 0 I矽層造成許 多晶體缺陷。氧離子的減少植入難以保持氧化物層的膜品 質,也難也改變植入S i 02膜層厚度· 〔接合S 0 I〕 本纸張尺度遢川‘!,闲W孓(?:决-(cn.s ) :>彳:. ' 一4 2 Ο 8 2 趸 85115259 Patent Application ^ Chinese Manual Revised Page Minfeng θ November 2007 7 '7 J' '---, «·»------ ---. · I · Five, DESCRIPTION OF THE INVENTION (1) Background of the Invention Field of the Invention The present invention relates to a S 0 I substrate process with excellent film thickness uniformity and excellent film vacancy (or void) suppression, especially for high-functionality and high-performance electronic devices, integrated circuits, etc. ( S 0 I substrate process on a transparent insulating substrate such as glass or a silicon substrate with an oxide film on it (S 0 I substrate process) · Forming a single crystal silicon semiconductor layer on an insulating hip is called silicon on an insulator (S 0 I) technology, because this substrate has many advantages that cannot be achieved with a silicon substrate used to make general silicon integrated circuits, so many studies have been conducted. [SOS and SIMOX] A traditional SOI technology is the so-called SOS (silicon On sapphire), the technology of heteroepitaxial growth of silicon layer on sapphire crystal, but the quality of heteroepitaxial growth of silicon crystal is poor. S IMOX (separated by implanted oxygen) is actually used as the S 0 I formation technology. Many oxygen ions are implanted into the silicon and then annealed to form the Si 02 layer, and the implanted oxygen is buried from the surface of the silicon to Location of about 0.2 / zm. However, many oxygen ion implantation and annealing require a lot of time, which is not conducive to productivity and cost. Ion implantation causes many crystal defects in the S 0 I silicon layer. Reduction of oxygen ions Implantation is difficult to maintain the film quality of the oxide layer, and it is also difficult to change the thickness of the implanted Si 02 film layer. [Join S 0 I] The paper size of 遢 川 '!, Leisure W 孓 (?: Decision -(cn.s): > 彳:. 'a

-15!:请#而之;1:&事項血*7太 S ^ nil、1^, m^i 訂-------線 經浐部中央抒穿而ί消资合作杜印緊 經濟部中央標準局貝工消費合作社印裝 r. η P 〜 厶 2 Ο 8 2· ( a7 _______B7 五、發明説明(2 ) 近來報導的SOI形成術中,*接合SOI*·的品質 特別優良。其中二晶圓(至少一個有氧化等所形成的絕緣 膜)的鏡面接合,退火以加強黏著介面的耦合,其後基底 從任一側拋光或蝕刻,在絕緣膜上留下任意厚度的矽單晶 薄膜β此科技的重點是將矽基底修成薄膜的步驟•詳言之 ’通常約數百y m厚的矽基底須均勻抛光或蝕刻至幾4 m 或甚至1 ym以下的厚度,其控制性和均勻性很難。將矽 修成薄膜有二方式。其一是只由拋光進行修磨的方法( BPSOI :接合和拋光SOI),另一是在留下的薄膜 上(實際上在單晶基底製造時的薄膜下)提供蝕刻止層並 進行二級之基底蝕刻和蝕刻止層蝕刻的方法(B E S 0 I :接合和蝕回SOI) »由於BESOI中,矽活性層常 在預先形成的蝕刻止層上磊晶生長,故此B E S 0 I有利 確保膜厚度均勻。但由於蝕刻止層常含高濃度雜質,故造 成晶格畸變,導致晶格缺陷傳到磊晶層。也可能雜質在磊 晶層氧化時或接合後的退火時擴散,而改變蝕刻特性。 這些接合S 0 I中,若在接合表面有污染或因接合表 面不良平坦度而不平,則稱爲t空隙〃的許多空間出現在 接合介面。上述BESO I在許多情形不利。理由如下。 蝕刻止層通常由C V D的異磊晶生長或摻雜高濃度雜質的 磊晶生長形成。在C VD的情形,特別在異磊晶生長的情 形,達成的平坦度常比拋光所得的平坦表面差*蝕刻止層 有時由離子植入形成,但平坦度在此情形也退化。 (諳先閱讀背面之注意事項再填寫本頁) 訂 線 本紙張尺度適用中國國家標隼(CNS > A4規格(210 X 297公釐) -5 - ^320827 經濟部中央標準局貞工消费合作社印製 A7 _ B7 _五、發明説明(3 ) 〔新B E S Ο I科技〕 達成良好接合表面平坦度、如B E S Ο I之活性層均 勻膜厚度、高於傳統B E S Ο I幾位數之饋回選擇性之科 技的例子是陽極化並磊晶生長矽活性層而使矽基底表面多 孔的科技(日本特開5-21338) ^在此情形,多孔 層對應於B E S Ο I的蝕刻止層。但由於相較於單晶矽, 具有氫氟酸蝕刻劑之多孔矽的蝕刻率很高,故高選擇性蝕 刻特性比蝕刻止層重要。由於此科技並非由CVD而是由 平..坦單晶矽基底表面陽極化形成多孔矽層,故磊晶生長活 性層的平坦度優於蝕刻止層由CVD等形成的BESOI 。生長在此表面上的磊晶層有達成幾乎等於生長在非多孔 單晶基底上之磊晶層之晶性的性質。可在單晶矽基底上以 高可靠度使用相當於磊晶層的單晶薄膜做爲活性層,因而 提供優良晶性和優良膜'厚度均勻性的S 0 I基底。 K.Sakaguchi等人報導使單晶矽基底表面陽極化以令 其多孔並進行磊晶生長所得的基底接到有氧化表面的矽基 底,非多孔單晶矽基底部由研磨機研磨而露出多孔層,以 HF/H20 2混合物溶液選擇性蝕刻多孔層,因此對5吋 晶圓達成SO I矽層膜厚度分布507nm±l 5nm ( ±3%)或 96. 8nm±4. 5nm(±4. Ί % ) ° 以Η F/H2〇2混合物溶液蝕刻時,连此情形,多孔矽層 的蝕刻率爲非多孔矽層的5倍•因此,多孔矽層在 BESOI做爲蝕刻止層。 _了將具有熱氧化表面的單晶矽基底或透明二氧化矽 本紙張尺度適用中國國家樣隼(CNS ) A4*i格{ 210Χ297公釐) (請先聞讀背面之注意事項再填寫本頁) 經濟部中央標隼局買工消費合作杜印^ 420827 A7 __B7五、發明説明(4 ) 玻璃基底接到生長在此多孔矽上之磊晶矽膜方法*也可互 接二基底的S i 〇2表面。做爲活性層的磊晶矽膜與 S i 0 2 (磊晶層的熱氧化膜)之間之介面的介面狀態杏 度夠低•可任意控制S i 層厚度。因此,充分利用 S 0 I特性可製成基底。然後電漿處理激活接合介面的 S i 02表面,因此接合強度可完全提高,可抑制空隙發 生。 上述新BESO I科技可得高品質SO I基底,藉由 多孔矽層的高選擇性蝕刻,膜厚度分布保存磊晶生長時的 平坦度和膜厚度分布。但上述新B E S ◦ I科技在除去非 多孔單晶矽區中有以下問題。 1 .使用濕型氫氟酸基蝕刻劑所引發的問題 此科技涉及許多基底處理時的液體交換及液體濃度管 理的困難控制性,因此生產力很差。 氫氟酸基蝕刻劑藉其大的蝕刻率蝕刻s i 02層和 s i 02玻璃基底》詳言之,若接到透明S i 02玻璃基底 ,則也蝕刻玻璃基底背面,破壞透明基底透明性* 若以諸如氫氟酸/硝酸基蝕刻劑或鹼性溶液的濕型蝕 刻劑(做爲除去非多孔單晶矽區的方法)露出多孔矽部| 則不論使用什刻劑,低密..度多孔矽層的蝕刻率大於非 多孔矽*因此,除去所有非多孔矽部前,在多孔矽露出的 部分蝕刻較快*因而多孔矽的殘餘膜厚度變化很大,幾 Am以上。當多孔矽膜厚度爲幾/zm以下時,蝕刻進一步 到達多孔矽下的底磊晶矽層,破壞最終S 0 I層的膜厚度 (請先閱讀背面之注意事項再填寫本頁) -訂 本紙張尺度通用中國國家摞準(CNS ) A4:it格(210X297公釐) 經濟部中夬榡隼局員工消費合作杜印製 420827 A7 ___B7 五、發明説明(5 ) 均勻·>因此,多孔矽層厚度須爲1 〇 以上,多孔矽層 不能比它薄。 2.關於多孔矽層膜厚度的問題 若使用研磨機的研磨做爲除去非多孔單晶矽區的方法 ’則需不小於1 0 μ πι的厚度做爲研磨機的研磨邊際(在 底多孔矽層停止研磨)和損壞層,因此,多孔矽層不能比 它薄。 因此,形成和蝕刻多孔矽需要許多時間》 發明概要 因此,本發明的目標是實現解決所有問題(边Ufi使用 除去多孔單晶矽區的濕型氫氟酸基蝕刻劑之生產力降低和 透明基底透明性退火的問題,和因研磨機不能用於修整多 孔矽層而需許多時間以形成及蝕刻多孔矽的問題)的 s 0 I基底製程。 爲達成上述目標,本發明人盡力達成以下發明β亦即 ,本發明的S 0 I基底製程包括下列步驟:使單晶矽基底 表面層多孔,在第一非多孔單晶矽區上形成多孔單晶矽區 ;在多孔單晶矽區表面上形成第二非多孔單晶矽區;製備 至少一表面層爲絕緣區的支持基底;將絕緣區接到第二非 多孔單晶矽區表面:除去第一非多孔單晶矽區;除去多孔 單晶矽區;其中除.去__寒一非多孔單晶矽區的步驟包括進行 乾蝕刻的步驟,其中非多孔單晶矽區的蝕刻率大於多孔單 晶砂辱。 本紙張尺度適用肀國國家標準(CNS > Α4規格UiOX297公釐) (請先閲讀背面之注意事項再填寫本Κ)-15 !: Please # 而 之; 1: & event blood * 7 too S ^ nil, 1 ^, m ^ i order ---- --- the central government of the Ministry of Economic Affairs to express and eliminate the cooperation of Du Yin Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs r. Η P ~ 厶 2 〇 8 2 · (a7 _______B7 V. Description of the Invention (2) In the recently reported operation of SOI formation, the quality of * bonded SOI * · is particularly good. Two of the wafers (at least one with an insulating film formed by oxidation, etc.) are mirror bonded and annealed to enhance the coupling of the adhesive interface. The substrate is then polished or etched from either side, leaving a silicon sheet of any thickness on the insulating film. Crystalline film β This technology focuses on the steps of modifying the silicon substrate into a thin film. • In particular, 'usually a silicon substrate that is about several hundred μm thick must be uniformly polished or etched to a thickness of several 4 m or even 1 μm or less. Its controllability and Uniformity is difficult. There are two ways to modify silicon into a thin film. One is the method of polishing only by polishing (BPSOI: Bonding and Polishing SOI), and the other is on the remaining film (actually when the single crystal substrate is manufactured) Under the thin film) method for providing an etch stop layer and performing second-level substrate etching and etch stop layer etching (BES 0 I: Bonding and Etching Back SOI) »Since BESOI, the silicon active layer is often epitaxially grown on a pre-formed etch stop layer, BES 0 I is beneficial to ensure uniform film thickness. However, the etch stop layer often contains high Concentration of impurities, resulting in lattice distortion, leading to the transmission of lattice defects to the epitaxial layer. It is also possible that impurities diffuse during the oxidation of the epitaxial layer or during the annealing after bonding, thereby changing the etching characteristics. In these joints S 0 I, if the If the bonding surface is contaminated or uneven due to poor flatness of the bonding surface, many spaces called t-voids appear at the bonding interface. The above-mentioned BESO I is disadvantageous in many cases. The reason is as follows. The etch stop is usually grown by heteroepitaxial growth of CVD. Or epitaxial growth doped with high concentration of impurities. In the case of C VD, especially in the case of heteroepitaxial growth, the flatness achieved is often worse than the flat surface obtained by polishing. * The etch stop is sometimes formed by ion implantation , But the flatness is also degraded in this case. (谙 Please read the notes on the back before filling in this page) The paper size of the booklet applies the Chinese national standard (CNS > A4 size (210 X 297 mm) -5- ^ 320827 Printed by Zhengong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _ B7 _ V. Description of the Invention (3) [New BES Ο I Technology] Achieve good joint surface flatness, such as the uniform film thickness of the active layer of BES Ο I, high An example of the technology of feed-back selectivity in traditional BES 0 I is the technology of anodizing and epitaxially growing a silicon active layer to make the surface of the silicon substrate porous (Japanese Patent Application Laid-Open No. 5-21338). ^ In this case, the porous layer Corresponds to the etch stop layer of BES 0 I. However, compared to single-crystal silicon, porous silicon with a hydrofluoric acid etchant has a high etching rate, so high selective etching characteristics are more important than the stop layer. Because this technology is not a CVD, but a porous Si layer formed by anodizing a flat Si substrate, the flatness of the epitaxial growth active layer is better than that of the BESOI formed by CVD or the like. The epitaxial layer grown on this surface has the property of achieving crystallinity almost equal to that of an epitaxial layer grown on a non-porous single crystal substrate. A single crystal thin film equivalent to an epitaxial layer can be used as an active layer on a single crystal silicon substrate with high reliability, thereby providing a S 0 I substrate with excellent crystallinity and excellent film thickness uniformity. K. Sakaguchi et al. Reported that the surface of the single crystal silicon substrate was anodized to make it porous and epitaxially grown. The substrate was connected to a silicon substrate with an oxidized surface. The non-porous single crystal silicon substrate was ground by a grinder to expose a porous layer. The HF / H20 2 mixture solution was used to selectively etch the porous layer, so that the thickness of the SO I silicon layer film on a 5-inch wafer was 507nm ± l 5nm (± 3%) or 96. 8nm ± 4. 5nm (± 4. Ί %) ° When etching with a / F / H2O2 mixture solution, even in this case, the etching rate of the porous silicon layer is 5 times that of the non-porous silicon layer. Therefore, the porous silicon layer serves as an etching stopper in BESOI. _The standard of single crystal silicon substrate or transparent silicon dioxide paper with thermally oxidized surface is applicable to China National Sample (CNS) A4 * i grid {210 × 297 mm) (Please read the precautions on the back before filling this page ) Central Government Bureau of Standards, Ministry of Economic Affairs, Buyer and Consumer Cooperation Du Yin ^ 420827 A7 __B7 V. Description of the Invention (4) Method for connecting a glass substrate to an epitaxial silicon film grown on this porous silicon * It is also possible to interconnect two substrates S i 〇2 surface. The interface state of the interface between the epitaxial silicon film as the active layer and S i 0 2 (the thermal oxide film of the epitaxial layer) is sufficiently low. The thickness of the S i layer can be arbitrarily controlled. Therefore, the substrate can be made by making full use of the characteristics of S 0 I. Plasma treatment then activates the Si 02 surface of the bonding interface, so the bonding strength can be completely increased and voids can be suppressed. The above-mentioned new BESO I technology can obtain a high-quality SO I substrate. With the highly selective etching of the porous silicon layer, the film thickness distribution preserves the flatness and film thickness distribution during epitaxial growth. However, the new B E S ◦ I technology mentioned above has the following problems in removing non-porous single crystal silicon regions. 1. Problems caused by using wet-type hydrofluoric acid-based etchant This technology involves poor controllability of liquid exchange and liquid concentration management in many substrate treatments, and thus has poor productivity. Hydrofluoric acid-based etchant etches si 02 layer and si 02 glass substrate with its large etch rate. In detail, if a transparent Si 02 glass substrate is connected, the back of the glass substrate is also etched, which destroys the transparency of the transparent substrate. * If Exposing the porous silicon part with a wet etchant such as hydrofluoric acid / nitrate-based etchant or an alkaline solution (as a method to remove non-porous single-crystal silicon regions) | Regardless of the etchant, low density .. Porous The silicon layer has a higher etch rate than non-porous silicon *. Therefore, before removing all non-porous silicon parts, the exposed part of the porous silicon is etched quickly *. Therefore, the residual film thickness of the porous silicon varies greatly, more than a few Am. When the thickness of the porous silicon film is less than a few / zm, the etching further reaches the bottom epitaxial silicon layer under the porous silicon, which destroys the film thickness of the final S 0 I layer (please read the precautions on the back before filling this page)-booklet Paper size General China National Standards (CNS) A4: It grid (210X297 mm) Consumption cooperation between employees of the China Economic Development Bureau, Ministry of Economic Affairs, printed 420827 A7 ___B7 V. Description of the invention (5) Uniformity > Therefore, porous silicon The layer thickness must be more than 10, and the porous silicon layer cannot be thinner than it. 2. Regarding the thickness of the porous silicon layer film, if a grinder is used as a method to remove non-porous single-crystal silicon regions, a thickness of not less than 10 μm is required as the grinding margin of the grinder (at the bottom of the porous silicon) Layer stops grinding) and damage the layer, so the porous silicon layer cannot be thinner than it. Therefore, it takes a lot of time to form and etch porous silicon. SUMMARY OF THE INVENTION Therefore, the object of the present invention is to solve all the problems. (Ufi uses wet hydrofluoric acid-based etchant that removes porous single-crystal silicon regions to reduce productivity and transparent substrate transparency (Such as the problem of thermal annealing, and the problem that the polishing machine cannot be used to trim the porous silicon layer, which requires a lot of time to form and etch the porous silicon). In order to achieve the above objective, the present inventors endeavored to achieve the following invention β. That is, the S 0 I substrate process of the present invention includes the following steps: making the surface layer of the single crystal silicon substrate porous, and forming a porous single crystal on the first non-porous single crystal silicon region. Crystalline silicon region; forming a second non-porous single crystal silicon region on the surface of the porous single crystal silicon region; preparing at least one surface layer as a support substrate for the insulating region; connecting the insulating region to the surface of the second non-porous single crystal silicon region: removing The first non-porous single-crystal silicon region; removing the porous single-crystal silicon region; wherein the step of removing the cold non-porous single-crystal silicon region includes a step of performing dry etching, wherein the etching rate of the non-porous single-crystal silicon region is greater than Porous single crystal sand. This paper size applies the national standard of China (CNS > Α4 size UiOX297 mm) (Please read the precautions on the back before filling this KK)

,1T " -8 - 42082 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明(6 ) 除去第一非多孔單晶矽區的步驟在進行乾蝕刻的步驟 前最好有由研磨機部分研磨該區的步驟。乾蝕刻最好使得 電或光能的游離製成活化離子種,活化離子種在垂直於基 底表面的方向加速*反應發生在基底表面。最好在基底上 設定平行板電極並觀察平行板電極與基底之間的自偏壓改 變,判定多孔單晶矽區由乾蝕刻在整個表面露出的蝕刻終 點。 除去多孔單晶矽區的步驟可由多孔單晶矽區的蝕刻率 大於非多孔單晶矽區的濕蝕刻或多_孔單晶矽區的蝕刻率大 於非多孔單晶矽區的乾蝕刻進行。多孔單晶矽區蝕刻率大 於非多孔單晶矽區的乾蝕刻最好使得導自至少電或光能之 分解的活化基進入多孔區的孔,從內部蝕刻該區。 在多孔單晶矽區表面上形成第二非多孔單晶矽區的步 驟最好是在多孔單晶矽區表面上磊晶生長第二非多孔單晶 矽區的步驟。該步驟可爲進行退火以封閉多孔單晶矽區表 面之孔的步驟。再者,支持基底可爲S i晶圓、有絕緣表 面的S i晶圓、或諸如二氧化矽玻璃的絕緣基底。若支持 基底爲S i晶圓,則使第二非多孔單晶矽區表面絕緣。 本發明人發現在某些條件下乾蝕刻,多孔矽的蝕刻率 比非多孔矽慢幾倍以上。本發明使用除去非多jL蓋晶_ .區之 ·· ·- , 條件的乾蝕刻。非多孔矽之蝕刻率大於多孔矽的蝕刻機構 未完全瞭解,但可鼠^座下。 對於非多孔矽區的選擇性蝕刻,表面蝕刻率等於高於 華,之寧的進入.率•例如,在電場方向使用異向性的反應離 (旖先閱讀背面之注意事項再填寫本頁) '-β 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ 297公釐) 420827 經濟部+央標準局貝工消费合作社印製 A7 —_____B7_五、發明説明(7 ) 子蝕刻模式,例如R I E (反應離子蝕刻),表面蝕刻可 更前進。此外,因多孔矽表面氧化或其濃度低,故離子蝕 刻模式之多孔矽的D C電場方向分量異於非多孔矽,因此 多孔矽蝕刻率下降。爲在此離子蝕刻模式促進表面蝕刻, 除了在RF電漿放電適當選擇壓力、功率、蝕刻氣體等而 增加自偏壓•從外部施加D C偏壓的方法也有效* 1 〇 〇 至數百V的施加使多孔矽的蝕刻率比非多孔矽約慢幾至幾 十倍。在接合後除去非多孔晶圓部時,因晶圓厚度分布和 蝕刻厚度分布而導致部分露出底多孔矽,但因該部分的蝕 刻率低,故多孔矽的殘餘厚度分布鬆弛,因此增進均勻。 由於蝕刻率選擇性和蝕刻率共面分布均勻性夠高,故 當非多孔矽基底部蝕刻而在整個表面露出多孔矽部時,時 間控制足以判定蝕刻終點。但考慮生產力的裝置可監控自 偏壓以判定終點。亦即,因自偏壓在多孔矽露出時下降, 故可確實判定終點。 由於本發明涉及以傳統濕型氫氟酸基蝕刻劑或鹼基蝕 刻劑去非多孔單晶矽區,故解決許多基底處理後之液體更 換所造成之極差生產力和液體濃度厚管理之困難控制性的 問題*此外,以氫氟酸基蝕刻劑蝕刻透明S i 02玻璃基 底不發生在乾蝕刻(解決透明基底的透明性退化問題)β 若由研磨機研磨或以氫氟酸基蝕刻劑蝕刻,則在多孔 矽部難以停止蝕刻 > 多孔矽膜厚度厚達1 Ο ίΐ m以上以保 持邊際•但非多孔矽晶圓部之蝕刻率大於多孔矽層的選擇 性蝕刻不需保持邊際,因而多孔矽膜厚度可薄到5至1 0 本紙張尺度適用中國國家標準^ CNS } A4規格(210X 297公釐) (請先閱讀背面之注意事項再填寫本頁)1T " -8-42082 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) The step of removing the first non-porous single-crystal silicon region is preferably preceded by the step of dry etching The machine partially grinds the step of the zone. Dry etching is best to make the release of electrical or optical energy into activated ion species, which accelerates in a direction perpendicular to the substrate surface. The reaction occurs on the substrate surface. It is best to set the parallel plate electrode on the substrate and observe the change in self-bias voltage between the parallel plate electrode and the substrate, and determine the etching termination point where the porous single crystal silicon region is exposed on the entire surface by dry etching. The step of removing the porous single crystal silicon region can be performed by wet etching of the porous single crystal silicon region more than wet etching of the non-porous single crystal silicon region or more than dry etching of the non-porous single crystal silicon region. The etching rate of the porous single crystal silicon region is greater than that of the non-porous single crystal silicon region. The dry etching is preferably such that an activated group derived from the decomposition of at least electrical or optical energy enters the pores of the porous region, and the region is etched from the inside. The step of forming a second non-porous single crystal silicon region on the surface of the porous single crystal silicon region is preferably a step of epitaxially growing the second non-porous single crystal silicon region on the surface of the porous single crystal silicon region. This step may be a step of performing annealing to close the pores on the surface of the porous single crystal silicon region. Furthermore, the supporting substrate may be a Si wafer, a Si wafer having an insulating surface, or an insulating substrate such as silica glass. If the supporting substrate is a Si wafer, the surface of the second non-porous single crystal silicon region is insulated. The inventors have found that under certain conditions dry etching, the etching rate of porous silicon is several times slower than that of non-porous silicon. The present invention uses dry etching to remove the non-multi-jL capped crystal region. The etching mechanism of non-porous silicon is greater than that of porous silicon. The mechanism is not fully understood, but it can be under the seat. For selective etching of non-porous silicon regions, the surface etch rate is equal to the entry rate of Hua Ning. The rate • For example, using an anisotropic reaction ion in the direction of the electric field (read the precautions on the back before filling this page) '-β This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 420827 Printed by the Ministry of Economic Affairs + Central Standards Bureau Shellfish Consumer Cooperative A7 —_____ B7_ V. Description of the invention (7) Sub-etching mode, such as RIE (Reactive Ion Etching), surface etching can go further. In addition, because the surface of porous silicon is oxidized or its concentration is low, the DC electric field direction component of porous silicon in ion etching mode is different from that of non-porous silicon, so the etching rate of porous silicon decreases. In order to promote surface etching in this ion etching mode, in addition to appropriately selecting the pressure, power, and etching gas in the RF plasma discharge to increase the self-bias voltage • The method of applying a DC bias voltage from the outside is also effective * 100 to several hundred V The application makes the etching rate of porous silicon approximately several to several tens times slower than that of non-porous silicon. When the non-porous wafer portion is removed after bonding, the bottom porous silicon is partially exposed due to the wafer thickness distribution and the etched thickness distribution. However, since the etching rate of this portion is low, the residual thickness distribution of the porous silicon is relaxed, thereby improving uniformity. Since the etching rate selectivity and the uniformity of the coplanar distribution of the etching rate are sufficiently high, when the non-porous silicon-based bottom is etched and the porous silicon portion is exposed on the entire surface, the time control is sufficient to determine the end point of the etching. But productivity-conscious devices can monitor self-bias to determine the end point. That is, since the self-bias voltage drops when the porous silicon is exposed, the end point can be determined with certainty. Since the present invention involves removing non-porous single crystal silicon regions with a conventional wet hydrofluoric acid-based etchant or a base etchant, it solves the difficult control of poor productivity and thick liquid concentration management caused by liquid replacement after many substrate treatments. Problems * In addition, etching of transparent Si 02 glass substrates with hydrofluoric acid-based etchant does not occur during dry etching (solving the problem of transparency degradation of transparent substrates) β If grinding by a grinder or etching with hydrofluoric acid-based etchant , It is difficult to stop the etching in the porous silicon portion> The thickness of the porous silicon film is as thick as 1 Ο ΐ ΐ m or more to maintain the margin. However, the non-porous silicon wafer portion has an etching rate greater than that of the selective etching of the porous silicon layer. The thickness of the porous silicon film can be as thin as 5 to 10. This paper size is applicable to Chinese national standards ^ CNS} A4 size (210X 297 mm) (Please read the precautions on the back before filling this page)

-10 - ^ΖϋδΖ(Α2〇82^ 經濟部中央橾丰局負工消費合作杜印製 Α7 Β7五、發明説明(8 ) # m。將形成多孔矽的陽極化時間和蝕刻多孔矽的蝕刻時 間都降到先前的一半,因此增進生產力* 圖式簡述 圖1A、1B、1C、ID、1E是解釋本發明之實 施例和第一和第二例之步驟的剖面圖: 圖2A、2B、2 C、2D、2E、2F是解釋本發 明第三例之步驟的剖面圖; 圖3A、3B ' 3C,3D、3E、3F是解釋本發 明第四例之步驟的剖面圖; 圖4A、4B、4C、4D、4E、4F是解釋本發 明第五例之步驟的剖面圖; 圖5 A和5 B是使矽基底多孔之裝置的剖面圖。 較佳實施例詳述 參照圖1A至1E解釋本發明的實施例。 (圖1 A)單晶矽基底1 0 0陽極化而形成多孔矽 1◦1»此時的多孔層厚度可在幾Mm與幾十pm之間》 參照圖5 A和5 B解釋形成多孔矽的方法。首先,p型單 晶矽基底5 0 0做成基底。N型不是不可能,但限於低電 阻基底,或須在以光照射基底表面而促進電洞產生的狀態 進行陽極化。基底5 0. 0設在裝置如圖5 A »亦即,表面 一側接觸氫氟酸基溶液5 0 4,負極5 0 6設在溶液側, 基底另一側接觸正金靥極5 0 5。如圖5 B,正極側 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標率(CNS ) A4说格(2丨0X297公釐) -11 - 420827 A7 B7 經濟部中央橾準局員工消費合作社印裝 五、發明説明(9 .) 505<也經由溶液504>設在一電位° 在任一情形,多孔層形成從接觸氫氟酸基溶液的負極 側開始0氫氟酸基溶液5 0 4通常是氫氟酸(4 9%HF )。當氫氟酸溶液以純水(H20)稀釋時,蝕刻從某濃 度開始。在某些情形,氣泡在陽極化從基底5 0 0的表面 發生,因此加入醇做爲表面活化劑,有效除去氣泡β可用 的醇爲甲醇、乙醇、丙醇、異丙醇等。使用攪拌器取代表 面活化劑,攪動溶液可進行陽極化。 負極5 0 6由不被氫氟酸溶液腐蝕的材料製成,例如 金(Au)、鉑(Pt)等。正極505的材料可選自通 常使用的金屬材料,但因氫氟酸基溶液5 0 4在整個基底 5 0 0的陽極化完成後到達正極5 0 5,故正極5 0 5的 表面最好塗上抗氫氟酸溶液的金靥膜。陽極化電流值可選 在幾百mA / c m 2之最大值至大於零之最小值的範圍 此值判定在容許多孔矽表面上之良好品質磊晶生長的範圍 內。通常隨著電流值增加,陽極化速率增加而多孔矽層密 度減小。亦即,孔所佔的體積增加。這改變磊晶生長條件 〇 (圖1 Β)非多孔單晶矽層1 〇 2在上述多孔層 1 0 1上磊晶生長•磊晶生長由一般熱CVD、低壓 CVD、電漿CVD、分子束磊晶、濺射等進行。可判定 生長層的膜厚度與S 01層設計值相同,但膜厚度最好不 大於2ym。理由如下》若2em厚以上的單晶S i膜存 在於车要含有S i 02的絕緣基底上,則因二材料的熱膨 本紙伕尺度逋用中國國家梯準(CNS ) A4規格(2丨0X297公釐) (請先閲讀背面之注意事項再填寫本頁) -12 - 2082 了 A7 B7 經濟部中央標隼局員工消費合作社印製 五、發明説明(10 ) 脹係數差之故,大應力在退火時發生在接合介面,造成矽 膜崩潰、基底彎曲、介面剝落等。由於應力相當小而膜厚 度不大於2 ,故膜崩潰、剝落、彎曲等不可能發生在 此情形。膜厚度不大於0. 5vm更好。這是因爲膜厚度 不小於0· 5時,雖在隨後過程的退火不發生剝落、 崩潰等,但滑移線可能發生在晶體上。 由退火封閉多孔矽層1 0 1之表面的孔*可形成多孔 單晶S i層1 0 2。 (圖1C)磊晶層102的表面氧化(103)。若 磊晶層在下一步驟直接接到支持基底,則雜質容易聚在接 合介面,在介面之原子的未耦合鍵(懸掛鍵)增加,是令 薄膜裝置特性不稞的因素。 氧化物膜的充分厚度可判定在不受從大氣取入接合介 面之污染影響的範圍內。 (圖1D)製備具有磊晶表面的上述基底1〇〇和支 持基底1 1 0。支持基底1.1 0的特例包含表面氧化的矽 基底、二氧化矽玻璃、結晶玻璃、沈積在任意基底上的 S i 0 2等。 要接合的二表面都是S ί 〇2時,這二基底或其中一 個暴露於電漿而激活表面的s i 〇2。此時所用的氣,體最 好是氧,但此外*可用的氣體爲空氣(氧與氮的混合物) 、氮、氫,諸如氬或氦的情惰氣、氨之類的分子氣體等。 當S i組成的表面接到S i 〇2組成的表面時,不需 上述處理* (請先閱讀背面之注意事項再填寫本頁)-10-^ ZϋδZ (Α2〇82 ^ Printed by the Ministry of Economic Affairs, Central Fengfeng Bureau, Department of Consumer and Consumer Cooperation, Du Yin A7, B7, V. Description of Invention (8) # m. Anodizing time for forming porous silicon and etching time for etching porous silicon Both have been reduced to the previous half, thus improving productivity * Brief description of the drawings Figures 1A, 1B, 1C, ID, 1E are cross-sectional views explaining the steps of the embodiment of the present invention and the first and second examples: Figures 2A, 2B, 2C, 2D, 2E, 2F are cross-sectional views explaining the steps of the third example of the present invention; FIGS. 3A, 3B ′ 3C, 3D, 3E, 3F are cross-sectional views explaining the steps of the fourth example of the present invention; FIGS. 4A, 4B 4C, 4C, 4D, 4E, and 4F are cross-sectional views explaining the steps of the fifth example of the present invention; Figs. 5A and 5B are cross-sectional views of a device for making a silicon substrate porous. The preferred embodiment is explained in detail with reference to Figs. 1A to 1E. An embodiment of the present invention. (Figure 1 A) A single-crystal silicon substrate 100 is anodized to form porous silicon 1 ◦ 1 »The thickness of the porous layer at this time may be between several Mm and several tens of pm" Refer to Figure 5 A and 5 B Explains the method of forming porous silicon. First, a p-type single crystal silicon substrate 500 is made into a substrate. N-type is not impossible, but it is limited to a low-resistance substrate, or Anodization must be performed in a state where the surface of the substrate is irradiated with light to promote the generation of holes. The substrate 5 0. 0 is set in the device as shown in Figure 5 A »That is, the surface side is in contact with the hydrofluoric acid-based solution 5 0 4 and the negative electrode 5 0 6 is set on the solution side, and the other side of the substrate is in contact with the positive gold electrode 5 0 5. As shown in Figure 5 B, the positive side (please read the precautions on the back before filling this page) This paper size applies to China National Standards (CNS) A4 grid (2 丨 0X297 mm) -11-420827 A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (9.) 505 < Also via solution 504 > Set at a potential ° In any case The formation of the porous layer starts from the negative side of the hydrofluoric acid-based solution. The hydrofluoric acid-based solution 50 is usually hydrofluoric acid (49% HF). When the hydrofluoric acid solution is diluted with pure water (H20), Etching starts at a certain concentration. In some cases, bubbles occur on the surface of the substrate from anodizing, so alcohol is added as a surfactant to effectively remove bubbles. The available alcohols are methanol, ethanol, propanol, isopropyl Alcohol, etc. Use a stirrer instead of a surfactant and stir the solution for anodization The negative electrode 506 is made of a material that is not corroded by a hydrofluoric acid solution, such as gold (Au), platinum (Pt), etc. The material of the positive electrode 505 may be selected from commonly used metal materials, but because of the hydrofluoric acid-based solution 5 0 4 reaches the positive electrode 5 5 after the anodization of the entire substrate 5 0 5 is completed, so the surface of the positive electrode 5 5 5 is best coated with a hydrofluoric acid resistant solution. The anodizing current value can be selected in the hundreds. The range of the maximum value of mA / cm 2 to the minimum value greater than zero is determined to be within a range that allows good quality epitaxial growth on the surface of porous silicon. Generally, as the current value increases, the anodization rate increases and the density of the porous silicon layer decreases. That is, the volume occupied by the pores increases. This changes the epitaxial growth conditions. (Figure 1B) Non-porous single crystal silicon layer 1 0 2 Epitaxial growth on the above porous layer 1 0 1 Epitaxial growth consists of general thermal CVD, low pressure CVD, plasma CVD, molecular beam Epitaxial, sputtering, etc. are performed. It can be determined that the film thickness of the growth layer is the same as the design value of the S 01 layer, but the film thickness is preferably not more than 2 μm. The reason is as follows "If a single crystal Si film with a thickness of 2em or more exists on an insulating substrate containing Si 02 on the car, the Chinese National Standard (CNS) A4 specification (2 丨0X297 mm) (Please read the precautions on the back before filling this page) -12-2082 Printed by A7 B7 Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of the invention (10) Because of the poor expansion coefficient, great stress It occurs at the bonding interface during annealing, causing the silicon film to collapse, the substrate to bend, and the interface to peel off. Since the stress is relatively small and the film thickness is not greater than 2, film collapse, peeling, and bending cannot occur in this case. The film thickness is not greater than 0.5 vm. This is because when the film thickness is not less than 0.5, although the peeling and collapse do not occur during the annealing in the subsequent process, the slip line may occur on the crystal. The pores * on the surface of the porous silicon layer 101 can be closed by annealing to form a porous single crystal Si layer 102. (FIG. 1C) Surface oxidation of the epitaxial layer 102 (103). If the epitaxial layer is directly connected to the support substrate in the next step, impurities tend to accumulate on the bonding interface, and the uncoupled bonds (dangling bonds) of atoms in the interface increase, which is a factor that makes the characteristics of the thin film device unfavorable. The sufficient thickness of the oxide film can be determined within a range that is not affected by the contamination taken from the atmosphere into the bonding interface. (Fig. 1D) The above-mentioned substrate 100 and a supporting substrate 110 having an epitaxial surface were prepared. Specific examples of supporting substrate 1.10 include surface-oxidized silicon substrate, silica glass, crystallized glass, S i 0 2 deposited on any substrate, and the like. When the two surfaces to be bonded are both S0 02, these two substrates or one of them is exposed to the plasma to activate the surface s i 02. The gas used at this time is preferably oxygen, but in addition * the available gases are air (mixture of oxygen and nitrogen), nitrogen, hydrogen, inert gas such as argon or helium, molecular gas such as ammonia, and the like. When the surface composed of Si is connected to the surface composed of Si 〇2, the above treatment is not required * (Please read the precautions on the back before filling this page)

*tT ·" 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) -13 - 經濟部中央橾準局員工消費合作社印製 420827 A7 __B7五、發明説明(11 ) 清理在上述步驟製備的二基底,其後互接。較佳清潔 法是只以純水沖洗,可用的其它溶液例子包含以純水稀釋 的過氧化氫溶液和以充分純水稀釋的氫氯酸或硫酸溶液。 接合後加壓整個基底表面有提高接面強度的效果。 然後接合的基底退火。退火溫度最好儘量高|但太高 溫造成多孔層101的結構改變或包含在基底的雜質擴散 到磊晶層。因此,須選擇溫度和時間。詳言之,較佳溫度 不大於1 200 °C。再者,一些基底在高溫不耐退火*例 如,若支持基底1 1 0爲二氧化矽玻璃,則因矽與二氧化 矽的熱膨脹係數差之故,須在不大於約2 0 0°C的溫度退 火。在其上的溫度*接合的基底因應力而剝落或損壞•但 只要介面可忍耐矽1 0 0的研磨和下一步驟之蝕刻時的應 力,則退火便足夠。因此,使活化的表面條件最佳化,即 使在不大於200 °C的溫度也可處理· ' (圖1 E )接著,選擇性除去矽基底部1 0 0和多孔 部10 1 ,留下磊晶層102。 首先,非多孔矽基底部1 0 0由表面研磨機等部分研 磨,其後由RI Ε蝕刻,或整個矽基底部1 00由RI Ε 除去而不研磨。當S i基底部1 0 0由研磨部分除去時’ 多孔矽區1 0 1上的S i基底部最好留下2至3 00 厚度範圍| 5至ΙΟΟμιη厚度範圍更好。 至於非多孔矽基底部蝕刻,本發明的重點是表面蝕刻 率等於或大於基之類的侵入率。因此,使用在電場方向有 異向性的反應離子蝕刻模式(例如RIE),可進一步触 本紙張尺度適用中國國家揉隼< CNS ) Α4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) -14 - 經濟部中央橾隼局貞工消f合作社印製 420827 A7 _B7_五、發明説明(12 ) 刻表面。再者,因多孔矽表面氧化或因其密度小,故離子 蝕刻模式的D C電場分布在非多孔與多孔矽之間變化,因 此多孔矽蝕刻率下降。 爲促進此離子蝕刻模式的表面蝕刻,在RF電漿放電 須適當選擇壓力、功、率、蝕刻氣體等。進行反應離子蝕刻 ,使得諸如H2氣體、含F原子之C F4或S F6的蝕刻氣 體混以諸如〇2或1^2氣體的載體氣體或諸如H e或A r的 情氣,被R F或微波功率所得的電漿或被光能分解,活化 離子在電場方向加速時到達蝕刻的基底表面,因此蝕刻表 面。 設定放電條件時,設定放電壓力低到確保氣體分子的 長平均自由路徑以達成游離能量很重要》較大R F功率增 加電極間的D C偏壓分量以促進離子蝕刻,但另一方面, 也促進基分解反應,因而基蝕刻模式也混合。因此,須注 意該情形。除了由RF功率增加自偏屋,從外部施加D C 偏壓的方法也有效。施加1 0 0至數百V提高非多孔矽蝕 刻率,甚至數百Am的蝕刻在數小時內完成。此時的多孔 矽蝕刻率慢了約幾至幾十倍。因此,接合後除去非多孔晶 圓部時,底多孔矽因晶圓厚度分布和蝕刻厚度分布而部分 露出,但因該部的蝕刻率慢,故殘餘多孔矽的厚度分布放 寬,因此增進均勻。利用磁控管的電漿或E C R電漿也有 效促進離子蝕刻。 如上述,當多孔部1 0 1在蝕刻非多孔矽基底部 1 Ο ζ)後露出時,蝕刻一度停止。因蝕刻率的充分選擇性 本纸張尺度適用中國國家梯準(CNS ) Α4規格(210Χ 297公釐) (請先聞讀背面之注意事項再填寫本頁) 訂 -15 - 420827 經濟部中央樣準局負工消资合作社印袋 A7 _____B7五、發明説明(13 ) 和蝕刻率的充分共面分布均勻性之故,時間控制可判定飽 刻終點*但監控自偏壓也可判定。亦即,當多孔矽露出時 ,因自偏壓下降,故可確實判定終點· 接著,濕蝕刻除去底多孔區1 0 1。以s i的一般触 刻劑或多孔矽的選擇性蝕刻劑除去氫氟酸,露出非多孔區 1 0 2。選擇性蝕刻劑的特例包含氫氟酸、氫氟酸與醇和 過氧化氫至少一種的混合物、緩衝氫氟酸、緩衝氫氟酸與 醇和過氧化氫至少一種的混合物。S i的一般蝕刻劑因多 孔矽的大表面積也可選擇性只蝕刻多孔矽。 由於低濃度氫氟酸蝕刻劑可用於多孔區101的濕蝕 刻,故溶解S i 〇2的現象顯明。 乾蝕刻也可除去底多孔部1 0 1 »多孔矽中,從表面 到內部有數十至數百埃的孔,侵入孔且有關蝕刻的基附在 孔壁以開始從側壁蝕刻,並附在柱形結構的薄柱,因此多 孔矽部最後分裂而除去》另一方面,非多孔矽沒有孔,因 此,只蝕刻表面。例如,假設涉及蝕刻的基在非多孔表面 的數十埃蝕刻中侵入到數十jum深度並附在多孔矽的孔, 則孔壁也蝕刻與表面相同的童,因而基侵入孔之部分的柱 分裂,因此進行多孔矽的數十jtzm蝕刻。 重點是涉及蝕刻之基侵入並附在多孔矽之孔的速率充 分大於表面蝕刻率《所以 > 本發明的要點是除去多孔矽的 蝕刻在化學基蝕刻模式,其中只由涉及蝕刻到孔之基的擴 散來蝕刻,蝕刻同向性進行。由於在電場方向有異向性的 反應離子蝕刻(例如一般R I E )進行超過表面的蝕刻, 本紙張尺度適用中國闺家標準(CNS ) A4規格(210X297公釐) (請先W讀背面之注意事項再填寫本頁) -16 - 420827 B7 經濟部中央樣準局員工消費合作社印策 五、發明説明(14 ) 故 不 做 爲 此 處 的 蝕 刻 β 但 選 擇 氣 體 流 率 壓 力 等 的 適 當 條 件 * 即 使 在 R I E 蝕 刻 裝 置 也 可 實 現 此 處 的 飽 刻 〇 須 設 定 放 電 條 件 以 保持放 電 壓 力 高 而 令 氣 體 分 子 的 平 均 白 由 路 徑 短 > 藉 以 促 進 離 子 的 二 次 反 應 保 持 基 底 白 偏 壓 低 而 不 發 生 活 化 離 子 的 表面 蝕 刻 利 用 從 外 部 在 白 偏 壓 反 向 施 加 D C 偏 壓 的 方 法 或 在 電 極 的 陽 極 側 定 位 蝕 刻 基 底 的 方 法 也 有 效 » 但難 以 兀 全 抑 制 離 子 到 達 最 好 基 產 生 區 與 蝕 刻 區 分 開 並 提 供 在 其 間 輸 送 基 的 處 理 « 諸 如 Η 2氣體的蝕刻氣體或F原子的C F4 或 S F β混 以 諸 如 0 2或Ν 2 氣 體 的 載 體 氣 體 由 R F 或 微 波 所形 成 的 電 漿 或 由 光 能 分 解 成 基 與 載 體 氣 體 Γ3& 等 的 二 次 反 應 發 生 在 輸 送 過 程 的 氣 相 藉 以 得 到 更 穩 定 和 長 壽 的 蝕 刻 基 0 這 是 因 爲 蝕 刻 氣 體 到 達 非 蝕 刻 基 底 9 再 者 當 基 底 在 蝕 刻 中 加 熱 或 振 動 時 促 進 基 同 向 性 擴 散 到 較 穩 定 位 置 因 而 促 進 侵 入 多 孔 矽 的 孔 因 此 多 孔 矽 蝕 刻 率 此 非 多 孔 矽 大 1 0 5 至 1 0 6倍 >此時 由於底磊晶部] ( )2爲非多孔 故其 蝕 刻 率 比 多 孔 矽 蝕 刻率小 五 至 J\ 位 蝕 刻 幾 乎 不 發 生 因 此 嘉 晶 層 1 0 2 成 爲 保 存 嘉 晶 生 長 時所 達 成 之 膜 厚 度 均 勻 的 薄 膜 〇 再 者 下 列 步 驟 在 某 些 情 形 可 加 入 上 述 步 驟 ύ ( 1 ) 多 孔 層 之 孔 的 內 壁 氧 化 ( 預 氧 化 ) 多 孔 矽 層 之 相 鄰 孔 間 的 壁 厚 度 很 小 幾 η m 至 幾 十 η m 〇 例 如 在 磊 晶 S i 層 形 成 時 或在 接 合 後 的 退 火 時 ) 有 時 使 孔 壁 在 多 孔 層 的 高 溫 處 中 互 黏 ♦ 孔 壁 變 大 且 粗 以 將 孔 本紙伕尺度適用中國國家標率(CNS ) A4規格(2丨0X297公嫠) -17 - 經濟部中央標準局貝工消費合作社印裝 42082 了 A7 ____B7五、發明説明(15 ) 閉合,因此減低蝕刻率。若在多孔層形成後,薄氧化物膜 形成於孔壁上•則防止孔壁變大且粗。但由於非多孔單晶 s i層須在多孔層上磊晶生長,故須只氧化孔內壁表面, 以在多孔層的孔壁內留下單晶性。所形成的氧化物膜最好 有幾A至幾十A膜厚度。在氧環境於2 0 0°C至7 0 0°C 範圍的溫度(最好於2 5 0 °C至5 0 0 °C範圍的溫度)之 退火形成此膜厚度的氧化物膜* (2 )氫烘焙處理 EP 5 5 3 8 5 2A2顯示在氫環境下的退火可除去 S i表面的細微凹凸,以得到極平滑S i表面》在氫環境 下的烘焙也可用於本發明。例如,在多孔矽層形成磊晶 S i層形成前,可進行氫烘焙》氫烘焙可在多孔矽層蝕刻 除去後所得的S 0 I基底上進行。在磊晶S i層形成前進 行氫烘焙處理造成最外表面被構成多孔矽表面之.S i原子 的遷移阻隔的現象。當磊晶S i層隨著阻隔孔最外表面形 成時,得到較少晶體缺陷的磊晶S i層。另一方面,在多 孔矽層蝕刻後進行的氫烘焙具有弄平由蝕刻變粗之磊晶S i表面的作用,和幫助從空氣取入清潔室的硼和從多孔矽 層熱擴散到磊晶S i層的硼向外擴散到接合介面的作用, 以驅出此硼。 執行此步驟可得到良好膜厚度分布的S 0 I基底或形 成單一矽晶體的透明絕緣基底。 上述S 0 I基底製程的可能修改中,磊晶生長之非多 孔單晶矽區1 〇 2的表面接到有氧化物膜的S i晶圓 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4現格(210X297公釐) -18 -* tT · " This paper size applies to China National Standard (CNS) A4 (210X297 mm) -13-Printed by the Consumers' Cooperative of the Central Government Bureau of the Ministry of Economic Affairs 420827 A7 __B7 V. Description of the invention (11) Clean up in the above steps The prepared two substrates were connected to each other thereafter. The preferred cleaning method is to rinse with pure water only. Examples of other solutions that can be used include a solution of hydrogen peroxide diluted with pure water and a solution of hydrochloric acid or sulfuric acid diluted with sufficiently pure water. Pressing the entire substrate surface after joining has the effect of increasing the strength of the joint. The bonded substrate is then annealed. The annealing temperature is preferably as high as possible | but too high a temperature causes the structure of the porous layer 101 to change or impurities contained in the substrate to diffuse into the epitaxial layer. Therefore, temperature and time must be selected. In detail, the preferred temperature is not more than 1 200 ° C. Furthermore, some substrates are not resistant to annealing at high temperatures. For example, if the supporting substrate 1 10 is silica glass, the difference in thermal expansion coefficient between silicon and silicon dioxide must be maintained at a temperature not greater than about 200 ° C. Temperature annealing. The temperature at which * the bonded substrate is peeled or damaged due to stress. But as long as the interface can withstand the grinding of silicon 100 and the stress in the next step of etching, annealing is sufficient. Therefore, the activated surface conditions are optimized and can be processed even at a temperature not higher than 200 ° C. ('Figure 1E) Next, the silicon-based bottom 100 and the porous part 10 1 are selectively removed, leaving Lei晶 层 102。 Crystal layer 102. First, the non-porous silicon-based bottom 100 is ground by a surface grinder and the like, and thereafter is etched by RI Ε, or the entire silicon-based bottom 100 is removed by RI Ε without polishing. When the Si base portion 100 is removed by the abrasive portion, the Si base portion on the porous silicon region 10 1 is preferably left in a thickness range of 2 to 3 00. A thickness range of 5 to 100 μm is better. As for non-porous silicon-based bottom etching, the focus of the present invention is that the surface etching rate is equal to or greater than the penetration rate of the substrate or the like. Therefore, the use of reactive ion etching mode (such as RIE) with anisotropy in the direction of the electric field can further touch the paper size. Applicable to the Chinese national standard < CNS) A4 size (210X297 mm) (Please read the precautions on the back first) (Fill in this page again) -14-Printed by 420827 A7 _B7_ Cooperative of the Central Government Bureau of the Ministry of Economic Affairs V. Description of Invention (12) Engraved surface. Furthermore, because the surface of porous silicon is oxidized or its density is small, the DC electric field distribution in the ion etching mode changes between non-porous and porous silicon, so the etching rate of porous silicon decreases. In order to promote the surface etching in this ion etching mode, the pressure, work, rate, and etching gas in the RF plasma discharge must be appropriately selected. Reactive ion etching is performed so that an etching gas such as H2 gas, C F4 or S F6 containing F atoms is mixed with a carrier gas such as 02 or 1 ^ 2 gas, or a mood such as He or Ar, and is RF or microwaved. The plasma generated by the power may be decomposed by light energy, and the activated ions reach the surface of the etched substrate when it is accelerated in the direction of the electric field, so the surface is etched. When setting the discharge conditions, it is important to set the discharge pressure low enough to ensure a long average free path for the gas molecules to achieve free energy. "A greater RF power increases the DC bias component between the electrodes to promote ion etching. Decomposition reaction, so the base etching mode is also mixed. Therefore, attention must be paid to this situation. In addition to increasing the self-biased house by RF power, the method of applying DC bias from the outside is also effective. Applying 100 to several hundred V improves the etching rate of non-porous silicon, and even several hundred Am etching is completed in a few hours. The etching rate of the porous silicon at this time is several to several tens times slower. Therefore, when the non-porous wafers are removed after bonding, the bottom porous silicon is partially exposed due to the wafer thickness distribution and the etching thickness distribution. However, since the etching rate of this portion is slow, the thickness distribution of the remaining porous silicon is widened, thereby improving uniformity. The use of magnetron plasma or E C R plasma is also effective to promote ion etching. As described above, when the porous portion 101 is exposed after etching the non-porous silicon-based bottom portion 10 ζ), the etching stops once. Due to the sufficient selectivity of the etching rate, this paper size is applicable to China National Standard (CNS) Α4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page) Order -15-420827 Central Ministry of Economic Affairs Printed bag A7 of quasi-office consumer and consumer cooperatives _____ B7 V. Invention description (13) Because of the sufficient coplanar distribution uniformity of etching rate, time control can determine the saturation end point *, but monitoring self-bias can also be determined. That is, when the porous silicon is exposed, since the self-bias voltage drops, the end point can be determined with certainty. Next, the bottom porous region 1 01 is removed by wet etching. The hydrofluoric acid is removed with a general contact agent of si or a selective etchant of porous silicon, and the non-porous region is exposed. Specific examples of the selective etchant include hydrofluoric acid, a mixture of hydrofluoric acid with at least one of an alcohol and hydrogen peroxide, buffered hydrofluoric acid, and a mixture of buffered hydrofluoric acid with at least one of an alcohol and hydrogen peroxide. The general etchant of Si can also selectively etch only porous silicon due to its large surface area. Since a low-concentration hydrofluoric acid etchant can be used for wet etching of the porous region 101, the phenomenon of dissolving Si02 is apparent. Dry etching can also remove the bottom porous part 1 0 1 »In porous silicon, there are tens to hundreds of angstroms of holes from the surface to the inside. The holes penetrate into the holes and the base of the etching is attached to the hole wall to start etching from the side wall and attached to Thin pillars with columnar structure, so the porous silicon part is finally split and removed. On the other hand, non-porous silicon has no pores, so only the surface is etched. For example, suppose that the substrate involved in the etching penetrates into the pores with a depth of tens of tens of angstroms on the non-porous surface and attaches to the hole of the porous silicon. Split, so tens of jtzm etching of porous silicon is performed. The important point is that the rate of penetration of the substrate involved in the etching and attaching to the pores of the porous silicon is sufficiently higher than the surface etching rate "So> The point of the present invention is that the etching to remove the porous silicon is in a chemical-based etching mode, wherein Diffusion to etch, etching is performed isotropically. Due to the anisotropic reactive ion etching (such as general RIE) in the direction of the electric field, the surface is etched beyond the surface. This paper size applies the Chinese standard (CNS) A4 size (210X297 mm) (Please read the precautions on the back first) (Fill in this page again.) -16-420827 B7 Imprint of the Consumer Cooperatives of the Central Prototype Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (14) Therefore, it is not used as the etching β here, but the appropriate conditions such as gas flow rate pressure are selected. * The RIE etching device can also achieve the saturation here. The discharge conditions must be set to keep the discharge pressure high and the average whiteness of the gas molecules to be short. The secondary reaction of ions can be promoted to keep the substrate white bias low without activating ions. The surface etching method is effective by applying a DC bias reversely from the outside to the white bias or by positioning the etching base on the anode side of the electrode. However, it is difficult to completely suppress the ions from reaching the best base. The zone is distinguished from the etching and provides a process for transporting the substrate therebetween. «Etching gas such as Krypton 2 gas or C F4 or SF β of F atom mixed with carrier gas such as 0 2 or N 2 gas. Electricity formed by RF or microwave The secondary reaction of the slurry or the base gas with the carrier gas Γ3 & etc. occurs in the gas phase of the transportation process to obtain a more stable and long-lived etching base. 0 This is because the etching gas reaches the non-etching substrate 9 or when the substrate is in When heating or vibration during etching, it promotes the isotropic diffusion of the group to a more stable position and thus promotes the penetration of pores in porous silicon. Therefore, the etching rate of porous silicon is 105 to 106 times that of non-porous silicon. ] () 2 is non-porous, so its etching rate is less than that of porous silicon. Etching is almost non-occurring. Therefore, the Jiajing layer 1 0 2 is a thin film with uniform film thickness achieved during the growth of Jiajing. 〇 Furthermore, the following steps may be added in some cases. (1) The inner wall of the pores of the porous layer is oxidized (pre-oxidized). The thickness of the wall between adjacent pores of the porous silicon layer is very small η m to several tens m. 〇For example, when the epitaxial Si layer is formed or when annealing is performed after joining) Sometimes the pore walls are made to adhere to each other at the high temperature of the porous layer. ♦ The pore walls become larger and thicker to apply the Chinese paper standard to the Chinese standard. (CNS) A4 specification (2 丨 0X297) 嫠 -17-Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed 42082 A7 ____B7 V. Description of the invention (15) Closed, thus reducing the etching rate. If a thin oxide film is formed on the pore wall after the porous layer is formed, it prevents the pore wall from becoming larger and thicker. However, since the non-porous single crystal Si layer must be epitaxially grown on the porous layer, it is necessary to oxidize only the inner wall surface of the pores to leave single crystallinity in the pore walls of the porous layer. The formed oxide film preferably has a film thickness of several A to several tens A. An oxide film of this film thickness is formed by annealing in an oxygen environment at a temperature ranging from 200 ° C to 700 ° C (preferably at a temperature ranging from 250 ° C to 500 ° C) * (2 ) Hydrogen baking treatment EP 5 5 3 8 5 2A2 shows that annealing under a hydrogen environment can remove the fine unevenness on the Si surface to obtain an extremely smooth Si surface. Baking under a hydrogen environment can also be used in the present invention. For example, before the porous silicon layer is formed into an epitaxial Si layer, hydrogen baking may be performed. Hydrogen baking may be performed on the S 0 I substrate obtained after the porous silicon layer is removed by etching. During the formation of the epitaxial Si layer, the hydrogen baking process causes the phenomenon that the outermost surface is blocked by the migration of the Si atoms constituting the porous silicon surface. When the epitaxial Si layer is formed along the outermost surface of the barrier hole, an epitaxial Si layer with fewer crystal defects is obtained. On the other hand, the hydrogen baking performed after the porous silicon layer is etched has the effect of flattening the surface of the epitaxial Si that is thickened by the etching, and helps to take boron from the air into the clean room and thermally diffuse the porous silicon layer to the epitaxial The boron in the Si layer diffuses out to the bonding interface to drive out the boron. By performing this step, a S 0 I substrate with a good film thickness distribution or a transparent insulating substrate forming a single silicon crystal can be obtained. In the possible modification of the above S 0 I substrate process, the surface of the epitaxially grown non-porous single crystal silicon region 1 02 is connected to an Si wafer with an oxide film (please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) -18-

42082T A7 !------ -B7_ 五、發明説明(16 ) 1 1 0 ’不在區域1 〇 2的表面上形成氧化物膜1 〇 3。 另一可能修改中,氧化物膜形成於非多孔單晶矽區1 〇 2 的表面上,接到S i晶圓1 1 〇而無氧化物膜。 (請先閱讀背面之注意事項再填寫本頁) 實例 〔例1〕 參照圖1A至1 E及圖5A和5B詳述本發明第一例 〇 (圖1 A)製備約300#m厚的6吋p型(1 00 )單晶矽基底(0. 1至〇. 2Qcm),設在裝置如圓 5 A,進行陽極化只將矽基底1 〇 〇的1 〇 表面變成 多孔矽101。此時的溶液504爲49%HF溶液,電 流密度爲10 OmA/cm2。此時的多孔層形成率爲5 Am/min,二分鐘後得到多孔層lOyrn厚。 (圖1 B)單晶矽層1 〇 2由CVD在多孔矽1 0 1 上磊晶生長0. 3厚。沈積條件如下。 經濟部t央標準局貝工消費合作社印製 使用的氣體:SiH4/H2 氣體流率:0. 62/140 (i?/min)42082T A7! ------ -B7_ V. Description of the invention (16) 1 1 0 ′ does not form an oxide film 103 on the surface of the region 102. In another possible modification, an oxide film is formed on the surface of the non-porous single crystal silicon region 10 2 and is connected to the Si wafer 1 1 0 without an oxide film. (Please read the precautions on the back before filling this page) Example [Example 1] The first example of the present invention will be described in detail with reference to Figures 1A to 1E and Figures 5A and 5B. (Figure 1A) Prepare about 300 #m thick 6 Inch p-type (100) single crystal silicon substrate (0.1 to 0.2Qcm), set in a device such as circle 5 A, and anodizing only changes the surface of the silicon substrate 100 to porous silicon 101. The solution 504 at this time was a 49% HF solution, and the current density was 10 OmA / cm2. The formation rate of the porous layer at this time was 5 Am / min, and the porous layer was 10 μrn thick after two minutes. (Fig. 1 B) The single-crystal silicon layer 102 was epitaxially grown by CVD on the porous silicon 100 with a thickness of 0.3. The deposition conditions are as follows. Printed by Shelley Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs Gas used: SiH4 / H2 Gas flow rate: 0.62 / 140 (i? / Min)

溫度:7 5 0 °C 壓力:8 ◦ T 〇 r r 生長率:〇. ISem/min (圖1 C )上法所製備的基底在蒸汽環境於9 0 〇°c 條件下處理,得到0 . 2 0 μ m的氧化物膜1 0 3 » f圓1 D)清潔具有氧化物膜的基底1 0 0和預製的 本紙伕尺度通用中國國家標準(CNS > A4規格(210X297公釐) -19 - 420827 A7 B7 五、發明説明(17 )_ 支持基底(沒有二氧化矽膜的裸矽晶圓)1 1 0,再旋轉 乾燥,其後互接》在此情形,原來黏著強度雖因s i表面 與S i 〇2表面的接合而高,但接合後,在1 1 5 0°C退 火五分鐘,藉以進一步提高黏著強度。 (圖1 E )退火後,非多孔單晶基底1 〇 〇在平行板 電漿蝕刻系統選擇性蝕刻,藉以露出多孔矽1 0 1 =此時 接合的晶圓有厚度變化,多孔矽層也有陽極化時造成的厚 度變化,因此非多孔單晶基底部1 0 0的最大厚度變化約 3 0 0± 5 /zm。此時的蝕刻條件如下。Temperature: 7 5 0 ° C Pressure: 8 ◦ T 〇rr Growth rate: 0.1 ISem / min (Fig. 1 C) The substrate prepared by the above method was treated in a steam environment at 900 ℃ to obtain 0.2 0 μm oxide film 1 0 3 »f-circle 1 D) Clean substrate with oxide film 1 0 0 and pre-made paper 伕 standard common Chinese national standard (CNS > A4 size (210X297 mm) -19- 420827 A7 B7 V. Description of the invention (17) _ Support substrate (bare silicon wafer without silicon dioxide film) 1 1 0, then spin-dry, and then interconnect with each other. In this case, the original adhesive strength is due to the si surface and The surface of S i 〇2 is high, but after bonding, it is annealed at 1150 ° C for five minutes to further improve the adhesive strength. (Fig. 1E) After annealing, the non-porous single crystal substrate 100 is on the parallel plate. The plasma etching system selectively etches to expose the porous silicon 1 0 1 = At this time, the thickness of the bonded wafer is changed, and the thickness of the porous silicon layer is changed during anodization. Therefore, the maximum value of the bottom of the non-porous single crystal substrate 1 0 0 The thickness varies by about 300 ± 5 / zm. The etching conditions at this time are as follows.

頻率:13. 56MHz 功率:1 k W SF6氣體流率:1 〇〇◦ s c cm 氧流率:300sccm 壓力:2 0 P a 基底偏壓:500V 處理時間:63分鐘 在上述條件下的非多孔矽蝕刻率爲η « 而多孔矽爲1 wm/m i η。若非多孔單晶基底部1 0 0 在最壞情形約2 9 5 ,則過蝕刻三分鐘;若爲3 0 5Frequency: 13.56MHz Power: 1 k W SF6 gas flow rate: 1 〇◦◦ sc oxygen flow rate: 300 sccm pressure: 2 0 P a substrate bias: 500V processing time: 63 minutes non-porous silicon under the above conditions The etching rate is η «and the porous silicon is 1 wm / mi η. If the bottom of the non-porous single crystal substrate 1 0 0 is about 2 9 5 in the worst case, overetch for three minutes; if it is 3 0 5

Mm,則過蝕刻一分鐘。此時之底多孔矽1 〇 1的蝕刻厚 度分別是4 //m和2 Am,因此,在最壞情形可在1 0 y m的多孔矽1 0 1停止蝕刻。此時,不判定終點,但對 設在蝕刻系統的六基底*所有基底的多孔矽層在設定的處 理時間於整個表面露出,殘餘厚度的共晶圓面分布在士 本紙張尺度適用中國國家標準(CNS )A4規格(2丨0X297公釐) (請先閲讀背面之注意事項再填寫本頁) 訂 -气__ 經濟部中央搮準局员工消費合作社印裝 -20 - 經濟部中央標準局員工消費合作社印裝 420827 A7 _________B7五、發明説明(18 ) 1 0 % 內 * 然後以傳統hf/h20 2溶液蝕刻此基底,由濕蝕刻 除去多孔砂11 結果’以0 - 2/im二氧化矽膜上之約I8 0nm± 5 ' 4 n m膜厚度分布的優良超薄單晶矽膜形成S Ο I基 底。 〔例2〕 例2在除去非多孔單晶矽區1 〇 〇的步驟前具有與例 1相同的步驟(圖1A至1E)。 然後此基底設在微波激勵的化學乾蝕刻系統,只選擇 性蝕刻多孔部1 〇 1。此系統分成由微波功率產生電漿的 區域和進行蝕刻的區域,因此離子種不到達未蝕刻基底。 此時的蝕刻條件如下。 微波頻率:1GHz 微波功率:100W SFe氣體流率:1 〇〇 s c cm ◦ 2流率:500sccm N 2流率:SOOsccm壓力:1 0 0 P a 處理時間:3 0分鐘 在上述條件下的非多孔矽蝕刻率高達約5 X 1 0_4 iim/m i η «但由於蝕刻先進入多孔矽的孔’故未看到 表面師刻。多孔矽層在蝕刻開始後突然開始分裂約2 〇分 (請先閏讀背面之注意事項再填寫本頁) 本紙張尺度逍用令國國家椹率(CNS ) Α4規格(2丨0X297公釐) -21 - 420827 經 濟 部 中 央 橾 準 局 貝 工 消 費 合 作 杜 印 製 A7 B7 五、發明説明( 19 ) 1 鐘 > 在 開 始 3 0 分 鐘 後 完 全 飽 刻 α 多 孔 矽 的 殘 餘 厚 度 變 化 i 1 在 最 壞 情 形 約 6 至 8 β ΤΠ 〇 假 設 底 嘉 晶 單 晶 矽 層 1 0 2 的 i I 過 蝕 刻 在 3 0 分 鐘 的 蝕 刻 約 爲 1 0 分 鐘 » 則 單 晶 矽 的 過 蝕 1 I 刻 不 大 於 5 0 A 不 影 響 磊 晶 生 長 時 達 成 的 均 勻 性 利 用 請 1 聞 1 監 控 蝕 刻 表 面 之 螢 光 的 方 法 » 可 判 定 蝕 刻 終 點 但 蝕 刻 時 讀 背 ! 面 間 控制 因 極 大 選 擇 性而 足 夠 〇 之 注 音 I I 結 果 以 在 0 6 β m 二 氧 化矽 膜 上 有 約 1 8 0 η m 事 項 1 再 1 1 土 5 4 ( 士 3 % ) 膜 厚 度 分 布 的 優 良 超 薄 單 晶 矽 膜 得 到 f 1 本 S 0 I 基 底 〇 頁 'W 1 1 I C 例 3 1 1 1 f 參 照 ISJ 圖 2 A 至 2 F 詳 述 本發 明 第 三 例 ΰ 訂 ( 圖 2 A ) 製 備 3 0 0 β m 厚 之 0 • 0 1 Ω • C m 電 阻 i 係 數 的 6 吋 P 型 ( 1 0 0 ) 矽 基 底 2 0 0 只 有 1 0 β m 1 I 表 面 層 以 第 一 例 的 相 同 方 式 變 成 多 孔 矽 2 0 1 g ! | ( Γ^Ι 圖 2 B ) 以 第 * 例 的 相 同 方 式 在 所 得 多 孔 表 面 上 形 /文 | 成 0 - 1 5 β 厚 嘉 晶 層 2 0 2 9 1 1 I ( ΓΒ|1 圖 2 C ) 上 法 所 製 的 基 底 在 1 0 0 0 °c 蒸 汽 氧 化 1 1 I 0 1 β m ( 2 0 3 ) 9 L 1 ( 圖 2 D ) 上 述 基 底 和 預 製 之 6 吋 合 成 二 氧 化 矽 基 底 2 1 0 的 表 面 被 電 漿 處 理 其 中 有 氧 化 物 膜 2 0 3 的 基 底 1 1 2 0 0 和 預 製 的 支 持 基 底 ( 合成 二 氧 化 矽 基 底 ) 2 1 0 設 1 | 在 平 行 板 電 漿 處 理 系 統 各 基 底 表 面 由 氧 電 漿 進 行活 化 處 I 理 9 導 理 條 件 如 下 0 1 1 I 本紙張尺度適用中國國家標準(CNS ) A4規格(2丨OX 297公釐) -22 - 420827 A7 B7 經濟部中央標準扃—工消費合作社印裝 五、發明説明(20 ) ί R F 頻 率 1 3 5 6 Μ Η Z 1 1 R F 功 率 4 0 0 W 1 1 氧 流率 3 0 S C C m 1 1 壓 力 : 2 0 P a 請 先 1 閱 ί 處 理 時 間 1 1 分 鐘 讀 背 1 面 在 電 漿 與 基 底 之 間 不 進 行 偏 壓 的 特 別 控 制 只 由 電 漿 之 注 ! I 意 1 I 的 白 偏 壓 處 理 表 面 事 項 I 再 1 I ( 圖 2 Ε ) 矽 基 底 2 0 0 和 二 氧 化 矽 基 底 2 1 0 浸 入 填 % 1 本 純 水 五 分 鐘 其 後 旋 轉 乾 燥 處 理 的 表 面 再 互 接 0 隨 後 I 頁 1 I 在 3 0 0 °C 退 火 十 小 時 〇 t [ I ( 圖 2 F ) 首 先 在 與 例 1 相 同 的 條 件 下 由 R I E 蝕 I 1 1 刻 2 9 0 β m 厚 的 矽 基 底 部 2 0 0 〇 多 孔 矽 層 2 0 1 露 出 訂 表 面 後 再 以 例 1 的 相 同 方 式 由 濕 蝕 刻 選 擇 性 蝕 刻 多 孔 層 1 2 0 1 0 此 時 完 全 不 蝕 刻 二 氧 化矽 基 底 2 1 0 0 利 用 監 1 1 控 蝕 刻 表 面 之 螢 光 的 方 法 可 判 定 蝕 刻 終 點 但蝕刻 時 間 控 1 I 制 因 極 大 選 擇 性 而 足 夠 〇 1 結 果 以 在 二 氧 化 矽 基 底 上 有 9 8 2 η m 士 3 4 1 1 1 η m ( 土 3 • 5 % ) 膜 厚 度 分 布 的 矽 單 晶 薄 膜 得 到 S 0 I [ 1 基 底 0 :丨· 1 t- ί C 例 4 ) i 1 1 參 照 ΓΗ*1 圖 3 A 至 3 F 詳 述 本 發 明 第 四 例 0 1 I ( 圖 3 A ) 製 備 3 0 0 β m 厚 之 0 0 1 Ω • C m 電 1 I 阻 係 m 的 5 时 P 型 ( 1 0 0 ) 矽 基 底 3 0 0 只 從 表 面 5 1 ! 1 本紙張尺度適用中國國家梯準(CNS ) A4说格(210X297公釐) -23 - 42082:/ 經濟部中央標準局貝工消費合作社印製 A7 87___ 五、發明説明(21 ) 厚形成多孔層301。 (圖3 B )以第1例的相同方式在如此得到之基底的 多孔表面上形成0 . 1 5 /im厚的磊晶餍3 0 2 » (圖3 C )上法所製的基底在蒸汽環境於9 0 0 °C條 件下處理,藉以得到0 . 0 5 4 m的氧化物膜。 (圖3D)有氧化物膜的基底3 0 0和預製之具有二 氧化矽膜0 . 2 厚的支持基底(矽晶圓)3 1 0設在 平行板電漿處理系統,各基底表面在類似例3的氧電漿條 件下活化。 (圖3 E )如此表面處理的二基底浸入純水五分鐘, 旋轉乾燥,處理的表面再互接。其後,在4 0 0 °C退火六 小時。 (圖3 F )退火後|類似上述,在平行板電漿蝕刻系 統於下述條件下選擇性蝕刻矽基底3 0 0之側,藉以露出 多孔矽3 ◦ 1 。 RF頻率:13. 56MHz R F功率:1 k W 匸卩4氣體流率:800sccm Ar氣體流率:200 s c cm 壓力:5 P a 基底偏壓:500V 處理時間:9 9分鐘至1 0 2分鐘 在上述條件下之非多孔矽的蝕刻率爲3. 1 μ m / mi r},而多孔矽爲0. η。類似例1 , (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ 297公釐) -24 — 經濟部中央樣準局貝工消費合作社印裝 420827 A7 __ B7五、發明説明(22 ) 在非多孔單晶基底部3 0 0的最壞情形有3 0 0至3 0 5 //m變化,例如,在1 〇 0分鐘蝕刻的情形,多孔矽過触 刻1. 6至4. 8分鐘。此時之底多孔矽301的蝕刻厚 度分別是0. 69#ιη和2. l//m,即使在最壞情形, 也可停止之多孔矽301的蝕刻,留下2. 9至 4. 3//m厚。監控自偏壓判定此終點,當自偏壓爲 9 0 0V至7 0 0V時,停止放電做爲多孔矽蝕刻終點。 對於設在蝕刻系統的六基底,所有基底的多孔矽在整個表 面露出*殘餘厚度的共晶圓面分布在士 1 0%內》 然後此基底設在微波激勵的化學乾蝕刻系統,只選擇 性蝕刻多孔部3 0 1。此時的蝕刻條件幾乎與例1相同, 但基底加熱且被超音波振動。 微波頻率:1 G Η z 微波功率:1 0 0 W 5?3氣體流率:100 seem 〇a流率:500 sc cm N2 流率:500s ccm 壓力:1 0 0 P a 基底溫度:3 0 0 °C 超音波:1 k W ♦ 處理時間:1 0分鐘 在上述條件下的非多孔矽蝕刻率也達5 χ 1 0— /min。 基底之加熱和超音波振動的效果先促進擴散到多孔矽 (請先閲讀背面之注意事項再填寫本頁)Mm, over-etch for one minute. At this time, the etching thickness of the porous silicon 101 is 4 // m and 2 Am, respectively. Therefore, in the worst case, the etching of the porous silicon 101 can be stopped at 10 μm. At this time, the end point is not determined, but the porous silicon layer of the six substrates * all substrates provided in the etching system is exposed on the entire surface at a set processing time, and the common wafer surface of the residual thickness is distributed on the paper standard. Chinese national standards apply (CNS) A4 specification (2 丨 0X297 mm) (Please read the precautions on the back before filling out this page) Order-Gas __ Printed by the Consumer Cooperatives of the Central Procurement Bureau of the Ministry of Economy-20-Staff of the Central Bureau of Standards of the Ministry of Economy Printed by a consumer cooperative 420827 A7 _________B7 V. Description of the invention (18) within 10% * Then the substrate is etched with a conventional hf / h20 2 solution, and the porous sand is removed by wet etching. 11 Result 'with a silicon dioxide film of 0-2 / im The excellent ultra-thin single-crystal silicon film with a film thickness distribution of about 80 nm ± 5 ′ 4 nm above forms an S 0 I substrate. [Example 2] Example 2 had the same steps as in Example 1 before the step of removing the non-porous single crystal silicon region 100 (Figs. 1A to 1E). This substrate was then set in a microwave-excited chemical dry etching system to selectively etch only the porous portion 101. This system is divided into an area where plasma is generated by microwave power and an area where etching is performed, so that ion species do not reach the unetched substrate. The etching conditions at this time are as follows. Microwave frequency: 1GHz Microwave power: 100W SFe gas flow rate: 100 sccm ◦ 2 flow rate: 500 sccm N 2 flow rate: SOCsccm pressure: 1 0 0 P a Processing time: 30 minutes non-porous under the above conditions The silicon etching rate is as high as about 5 X 1 0_4 iim / mi η «But because the etching first entered the holes of the porous silicon ', the surface engraving was not seen. The porous silicon layer suddenly began to split about 20 minutes after the etching started (please read the precautions on the back before filling in this page) The paper size is free to use the national standard (CNS) Α4 specification (2 丨 0X297 mm) -21-420827 A7 B7 printed by Shellfish Consumer Cooperation of the Central Bureau of Standards and Quarantine of the Ministry of Economic Affairs 5. Description of the invention (19) 1 bell > After 30 minutes from the start, the residual thickness change of α porous silicon i 1 is at most The bad case is about 6 to 8 β ΤΠ 〇 Suppose the i I overetching of the bottom Jiajing single-crystal silicon layer 1 2 is about 10 minutes in 30 minutes. Then the overetching of the single crystal silicon 1 I is not more than 5 0 A does not affect the uniformity achieved during epitaxial growth. Please note 1 Method 1 Monitoring the fluorescence of the etched surface »The end point of the etching can be determined but the back is read during the etching! With 0 6 β m two There is about 1 8 0 η m on the silicon oxide film. Matters 1 and 1 1 soil 5 4 (± 3%). Excellent ultra-thin single-crystal silicon film with film thickness distribution to obtain f 1 S 0 I substrate 〇 page 'W 1 1 IC Example 3 1 1 1 f Refer to ISJ Figures 2 A to 2 F for a detailed description of the third example of the present invention (Figure 2 A) Preparation of 3 0 0 β m thickness 0 • 0 1 Ω • C m 6 inches of resistance i coefficient P-type (1 0 0) silicon substrate 2 0 0 only 1 0 β m 1 I The surface layer becomes porous silicon in the same manner as in the first example 2 0 1 g! | (Γ ^ Ι Figure 2 B) Shape / text on the obtained porous surface in the same way | into 0-1 5 β thick Jiajing layer 2 0 2 9 1 1 I (ΓΒ | 1 Fig. 2 C) The substrate prepared by the method at 1 0 0 0 ° c steam Oxidation 1 1 I 0 1 β m (2 0 3) 9 L 1 (Figure 2 D) Surface of the above substrate and prefabricated 6-inch synthetic silicon dioxide substrate 2 1 0 Plasma treated substrate with oxide film 2 0 3 1 1 2 0 0 and prefabricated support substrate (synthetic silicon dioxide substrate) 2 1 0 Set 1 | The surface of each substrate of the parallel plate plasma processing system is charged with oxygen The pulp is activated. I The 9 conditions are as follows: 0 1 1 I This paper size is applicable to the Chinese National Standard (CNS) A4 (2 丨 OX 297 mm) -22-420827 A7 B7 Central Standard of the Ministry of Economic Affairs—Industrial and Consumer Cooperatives Printed 5. Description of the invention (20) ί RF frequency 1 3 5 6 Μ Z 1 1 RF power 4 0 0 W 1 1 Oxygen flow rate 3 0 SCC m 1 1 Pressure: 2 0 P a Please read 1 first Time 1 1 minute read back 1 Special control of no bias between the plasma and the substrate is only made by the plasma! I mean 1 I white bias-treated surface Matter I again 1 I (Figure 2 Ε) silicon substrate 2 0 0 and silicon dioxide substrate 2 1 0 immersion and filling% 1 of this pure water for five minutes and then spin-drying the surfaces and then connect to each other 0 then I page 1 I at 3 0 0 ° C annealing for ten hours 〇 t [I (Figure 2 F) First, I 1 was etched by RIE under the same conditions as in Example 1 1 2 etched 2 9 0 β m thick silicon-based bottom 2 0 0 〇 porous silicon layer After the 2 0 1 surface is exposed, the porous layer is selectively etched by wet etching in the same manner as in Example 1 1 2 0 1 0 At this time, the silicon dioxide substrate is not etched at all 2 1 0 0 The method can determine the end point of etching but the etching time is controlled by 1 I. It is sufficient due to the great selectivity. The result is 9 8 2 η m ± 3 4 1 1 1 η m on the silicon dioxide substrate (soil 3 • 5%) Film thickness distribution of silicon single crystal thin film obtained S 0 I [1 Base 0: 丨 · 1 t- ί C Example 4) i 1 1 Refer to ΓΗ * 1 Figure 3 A to 3 F Detailed description of the fourth example of the present invention 0 1 I (Figure 3 A) Preparation 3 0 0 β m thickness 0 0 1 Ω • C m electrical 1 I resistance system at 5 o'clock P-type (1 0 0) silicon substrate 3 0 0 only from the surface 5 1! 1 This paper size applies to China National Standards (CNS) A4 Grid (210X297 mm) -23-42082: / Printed by A7, Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 87___ V. Description of the invention (21) The porous layer 301 is formed thick. (Fig. 3B) In the same manner as in the first example, a 0.15 / im-thick epitaxial wafer 3 0 2 »(Fig. 3C) was prepared on the porous surface of the substrate in the same manner as in Example 1. The environment was treated at 900 ° C to obtain an oxide film of 0.054 m. (Figure 3D) The substrate 300 with an oxide film and the prefabricated support substrate (silicon wafer) 3 with a silicon dioxide film 3.2 are set in a parallel plate plasma processing system. The surface of each substrate is similar. Example 3 was activated under oxygen plasma conditions. (Fig. 3E) The two substrates thus surface-treated are immersed in pure water for five minutes, spin-dried, and the treated surfaces are connected to each other. Thereafter, it was annealed at 400 ° C for six hours. (Fig. 3F) After annealing | Similar to the above, in a parallel plate plasma etching system, the side of the silicon substrate 300 is selectively etched under the following conditions, thereby exposing the porous silicon 3 ◦ 1. RF frequency: 13. 56MHz RF power: 1 k W 匸 卩 4 gas flow rate: 800 sccm Ar gas flow rate: 200 sc cm pressure: 5 P a substrate bias: 500V processing time: 9 9 minutes to 102 minutes Η。 The etching rate of non-porous silicon under the above conditions is 3.1 μm / mi r}, and the porous silicon is 0. η. Similar to Example 1, (Please read the precautions on the back before filling in this page) This paper size applies the Chinese National Standard (CNS) Α4 specification (210 × 297 mm) -24 — printed by the Shell Industry Consumer Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs 420827 A7 __ B7 V. Description of the invention (22) The worst case of 3 0 0 at the bottom of the non-porous single crystal substrate has a change of 3 0 to 3 0 5 // m, for example, in the case of etching at 1000 minutes, the porous Silicon is over-etched for 1.6 to 4.8 minutes. At this time, the etching thickness of the porous silicon 301 is 0. 69 # ιη and 2. l // m. Even in the worst case, the etching of the porous silicon 301 can be stopped, leaving 2.9 to 4.3. // m thick. Monitor the self-bias to determine the end point. When the self-bias is 900V to 700V, stop the discharge as the end point of porous silicon etching. For the six substrates provided in the etching system, the porous silicon of all the substrates is exposed on the entire surface. The co-wafer surface of the residual thickness is distributed within 10%. Then the substrate is set in a microwave-excited chemical dry etching system, only selective. Etched porous part 3 0 1. The etching conditions at this time were almost the same as those in Example 1, but the substrate was heated and ultrasonically vibrated. Microwave frequency: 1 G Η z Microwave power: 1 0 0 W 5-3 Gas flow rate: 100 seem 〇a flow rate: 500 sc cm N2 flow rate: 500s ccm pressure: 1 0 0 P a substrate temperature: 3 0 0 ° C Ultrasonic: 1 kW ♦ Processing time: 10 minutes Under the above conditions, the non-porous silicon etch rate also reaches 5 χ 1 0— / min. The effect of substrate heating and ultrasonic vibration first promotes diffusion to porous silicon (please read the precautions on the back before filling this page)

,1T 本紙張尺度適用中國國家捸準(CNS ) Α4说格(2丨0Χ 297公釐) -25 - 420827 經濟部中夬樣準局貝工消費合作社印製 A7 _____B7_ 五、發明説明(23 ) 的孔•因孔壁蝕刻也促進物理分裂,在開始7至8分鐘後 露出幾乎所有底磊晶層,1 0分鐘後完全蝕刻多孔部。即 使底磊晶單晶矽層3 0 2過蝕刻1 0分鐘,過蝕刻厚度也 不大於5 0A,不影響磊晶生長時達成的均勻性。利用監 控蝕刻表面之螢光的方法可判定蝕刻終點•但蝕刻時間控 制因極大選擇性而足夠》 結果,以在0. 25^m二氧化矽膜上有約 100. 8nm±3. 4 (±3. 4%)膜厚度分布的優 良超薄單晶矽膜得到SO I基底》 〔例5〕 參照圖4A至4 F詳述本發明第五例* (圖4A)製備300iim厚之具有0. 01Ω· cm電阻係數的5吋ρ型(1 0 0)矽基底400,只在 表面5 #πι厚形成多孔層4 0 1。 (圖4 Β )以第一例的相同方式在所得基底的多孔表 面上形成0.15#111厚的晶晶層4 0 2。 (圖4 C )上法所製的基底在蒸汽環境於9 0 0 °C條 件下處理,得到0. 05μιη的氧化物膜403。 (圖4 D )有氧化物膜的基底4 0 0和預製之具有二 氧化矽膜0 . 2 厚的支持基底(’矽晶圓)4 1 0設在 平行板電漿處理系統,各基底表面在類似例3的氧電漿條 件下活化。 (圖4 E )如此表面處理的二基底浸入純水五分鐘· 本紙張尺度適用中國國家標準(CNS M4规格(210X297公釐) (請先聞讀背面之注意事項再填寫本頁) 訂 ^I . -26 - 經濟部中央標準局員工消費合作社印製 420827 a7 B7__五、發明説明(24 ) 再旋轉乾燥,其後處理的表面互接。其後’在4 〇。^退 火六小時。 (圖4 F )退火後,類似上述’在平行板電漿蝕刻裝 置於例3的條件下選擇性蝕刻矽基底4 0 0之側,藉以露 出多孔矽4 0 1。在此條件下之非多孔矽的蝕刻率爲 3. Ιμιη/min,而多孔矽爲 0. 43/zm/min 。類似例1 ,在非多孔單晶基底部4 0 0的最壞情形有 3 00至30 5em變化,例如’在1 〇〇分鐘蝕刻的情 形,多孔矽過蝕刻1. 6至4. 8分鐘。此時’類似例3 ,即使在最壞情形,也可停止5 jum之多孔矽4 0 1的蝕 刻,留下2. 9至4. 3/ζπι*監控自偏壓判定此終點’ 當自偏壓爲9 0 0V至7 0 0V時’停止放電做爲多孔矽 蝕刻終點。' 此基底設在光激勵的Η 2基產生系統’只選擇性蝕刻 多孔部4 0 1。由於產生^^2的區域與蝕刻的區域分開, 且電漿不用於光激勵的情形,故離子種不到達基底。此時 的蝕刻條件如下》 激勵光源:低壓汞燈(253. 7 e V ) H2氣體流率:100 sc cm 壓力:1 0 P a 基底溫度:300 °C 超音波:1 k W 處理時間:30分鐘 在上述條件下之此光學分解的Η 2基蝕刻中,非多孔 (請先聞讀背面之注意事項再填寫本頁) 訂 吹! 本紙張尺度適用t國國家標準(CNS ) Α4規格(210Χ297公釐) -27 - 420827 A7 B7 經濟部中央標準局員工消費合作社印¾ 五、發明説明(25 ) 矽蝕刻率也約達2 X 1 0 一i η。 基底之加熱和超音波振動的效果先促進擴散到多孔矽 的孔,因孔壁蝕刻也促進物理分裂,在開始2 0分鐘後露 出幾乎所有底磊晶層’ 3 0分鐘後完全蝕刻多孔部。即使 底磊晶單矽層4 0 2過蝕刻1 0分鐘,過蝕刻厚度也不大 於5 ΟΑ,不影響磊晶生長時達成的均勻性。利用監控蝕 刻表面之螢光的方法也可判定蝕刻終點,但蝕刻時間控制 因極大磬擇性而足夠。 結果,以在0. 25em二氧化矽膜上有約99. 8 nm±3. 6 (±3. 6%)膜厚度分布的優良起薄單晶 矽膜得到S 0 I基底。 .〔例 6〕 參照圖1 A至1 E和圖5 A及圖5 B詳述本發明第六 例。 (圖1A)製備600#ιη厚的6时p型(100) 單晶矽基底(0. 1至0. 2Ω·(:ιη),設在圖5Α的 裝置β然後進行陽極化,只將矽基底100的1〇#m表 面變成多孔矽101。此時的溶液504爲49%HF溶 液,電流密度爲1 0 OmA/cm2»再者,此時的多孔 層形成率爲5um/m i η ,二分鐘後得到多孔層1 ◦ 从m厚。 (圖1 B)單晶矽層1 〇 2由CVD在多孔矽1 0 1 上磊辱生長0 3 Ομπι厚《沈積條件與第一例相同。 本紙張尺度適用中國國家揉率{ CNS ) Α4規格(210X297公釐) (讀先W讀背面之注意事項再填寫本頁) l·訂 竦! -28 - 經濟部中央標準局貝工消費合作社印製 420827 A7 B7 _ 五、發明説明(26 ). (圖1 C )上法所製的基底於蒸汽環境在9 0 〇°C條 件下處理,得到0. 20#m的氧化物膜103。 (圖1 D)清潔具有氧化物膜的基底1 〇 〇和預製的 支持基底(沒有二氧化矽膜的裸矽晶圓)1 1 0,再旋轉 乾燥,其後互接。在此情形,原來黏著強度雖因S i表面 與S i02表面之間的接合而高,但接合後,在1 1 50 °C退火五分鐘,藉以進一步提高黏著強度。 (圖1 E )退火後,矽基底1 0 0之側被研磨機研磨 約5 50#m 〇再者,類似上例,殘餘約40#m非多孔 單晶基底部在平行板電漿蝕刻系統選擇性蝕刻,藉以露出 多孔矽1 0 1 »此時接合的晶圓有厚度變化,也有研磨機 裝置的研磨厚度變化,再者,有陽極化時的多孔矽厚度變 化。因此|非多孔單晶基底部1 0 0的最大厚度變化約 4 0 ± 5 # m »蝕刻條件如下。 RF頻率:13. 56MHz, 1T This paper size is applicable to China National Standards (CNS) Α4 standard (2 丨 0 × 297 mm) -25-420827 Printed by Shellfish Consumer Cooperatives of China Standard Sample Bureau of Ministry of Economic Affairs A7 _____B7_ V. Description of Invention (23) The pores of the pores also promote physical splitting, and almost all bottom epitaxial layers are exposed after 7 to 8 minutes, and the porous part is completely etched after 10 minutes. Even if the bottom epitaxial single crystal silicon layer 3 is over-etched for 10 minutes, the over-etched thickness is not more than 50 A, which does not affect the uniformity achieved during epitaxial growth. Using the method of monitoring the fluorescence of the etched surface, the endpoint of the etch can be determined. But the control of the etch time is sufficient because of the great selectivity. As a result, there is about 100. 8nm ± 3. 4 (± 3.4%) Excellent ultra-thin single-crystal silicon film with film thickness distribution to obtain SO I substrate. [Example 5] A fifth example of the present invention will be described in detail with reference to FIGS. 4A to 4F * (FIG. 4A). A 5 inch ρ-type (1 0 0) silicon substrate 400 with a resistivity of 01 Ω · cm has a porous layer 4 0 1 only 5 μm thick on the surface. (Fig. 4B) In the same manner as in the first example, a 0.15 # 111 thick crystal layer 4 02 was formed on the porous surface of the obtained substrate. (FIG. 4C) The substrate prepared by the above method was processed in a steam environment at 900 ° C to obtain a 0.05 μm oxide film 403. (Fig. 4D) The substrate 400 with an oxide film and the prefabricated support substrate with a silicon dioxide film 0.2 thick ('silicon wafer) 4 1 0 are set on a parallel plate plasma processing system, and the surface of each substrate Activated under oxygen plasma conditions similar to Example 3. (Figure 4 E) The two substrates treated in this way are immersed in pure water for five minutes. This paper size applies to Chinese national standards (CNS M4 specifications (210X297 mm). (Please read the precautions on the back before filling out this page).) ^ I -26-Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 420827 a7 B7__ V. Description of the invention (24) Rotary drying, and then the surfaces after treatment are connected to each other. After that, it will be annealed for 6 hours at 40 °. ( (Fig. 4F) After annealing, similar to the above-mentioned, the side of the silicon substrate 400 is selectively etched in the parallel plate plasma etching apparatus under the conditions of Example 3, thereby exposing porous silicon 41. Non-porous silicon under this condition The etching rate is 3.1 μm / min, while the porous silicon is 0.43 / zm / min. Similar to Example 1, the worst case of a non-porous single crystal substrate at the bottom of 4 0 has a change of 300 to 30 5em, such as' In the case of etching for 100 minutes, the porous silicon is over-etched for 1.6 to 4.8 minutes. At this time, similar to Example 3, even in the worst case, the etching of porous silicon 4 0 1 can be stopped, leaving The next 2. 9 to 4.3 / ζπι * monitor the self-bias to determine the end point. 'When the self-bias is 9 0V to 7 0V', stop Electricity is used as the end point of porous silicon etching. 'This substrate is set on a photo-excited Η 2 base generation system' and only selectively etches the porous part 4 0 1. Since the area where ^^ 2 is generated is separated from the etched area, the plasma is not used for In the case of light excitation, the ion species does not reach the substrate. The etching conditions at this time are as follows: Excitation light source: low-pressure mercury lamp (253. 7 e V) H2 gas flow rate: 100 sc cm pressure: 1 0 P a substrate temperature: 300 ° C Ultrasonic: 1 kW Processing time: 30 minutes Non-porous in this optically decomposed Η 2 base etch under the above conditions (please read the precautions on the back before filling this page) Applicable to National Standards (CNS) Α4 specifications (210 × 297 mm) -27-420827 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy ¾ 5. Description of the invention (25) The silicon etching rate is also about 2 X 1 0 1i η. The effect of substrate heating and ultrasonic vibration first promotes the diffusion into the pores of porous silicon, and because the pore wall etching also promotes physical splitting, almost all bottom epitaxial layers are exposed after the beginning of 20 minutes. The holes are completely etched after 30 minutes Even if the bottom epitaxial single silicon The layer 4 was over-etched for 10 minutes, and the over-etched thickness was not greater than 50 Α, which did not affect the uniformity achieved during epitaxial growth. The end point of the etch can also be determined by monitoring the fluorescence of the etched surface, but the control of the etch time It is extremely selective and sufficient. As a result, S 0 is obtained with a thin film having a thickness of approximately 99.8 nm ± 3.6 (± 3. 6%) on a 0.25em silicon dioxide film with a thin film thickness distribution. I 基。 I base. [Example 6] A sixth example of the present invention will be described in detail with reference to Figs. 1A to 1E and Figs. 5A and 5B. (FIG. 1A) A 600 # ιη thick 6 o'clock p-type (100) single crystal silicon substrate (0.1 to 0.2 Ω · (: ιη)) was prepared, and the device β in FIG. 5A was then anodized, and only silicon was used. The 10 # m surface of the substrate 100 becomes porous silicon 101. At this time, the solution 504 is a 49% HF solution, and the current density is 100 mA / cm2. Furthermore, the porous layer formation rate at this time is 5um / mi η. After 1 minute, a porous layer 1 was obtained. It was from m thick. (Fig. 1 B) The single crystal silicon layer 1 〇2 was grown on the porous silicon 1 0 1 by CVD. The deposition conditions were the same as in the first example. This paper The scale applies to China's national kneading rate {CNS) Α4 specification (210X297 mm) (read first and read the notes on the back before filling this page) l · Order! -28-Printed by 420827 A7 B7, Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy _ V. Description of the invention (26). (Figure 1 C) The substrate produced by the above method is processed in a steam environment at 900 ° C. An oxide film 103 of 0.20 # m was obtained. (Fig. 1D) Clean the substrate with oxide film 100 and the prefabricated support substrate (bare silicon wafer without silicon dioxide film) 1 10, then spin dry, and then connect to each other. In this case, although the adhesive strength was originally high due to the bonding between the Si surface and the Si 102 surface, after bonding, it was annealed at 1 1 50 ° C for five minutes to further improve the adhesive strength. (Figure 1 E) After annealing, the side of the silicon substrate 100 was ground by a grinder for about 5 50 # m. Furthermore, similar to the above example, the bottom of the non-porous single crystal base of about 40 # m was in a parallel plate plasma etching system. Selective etching to expose the porous silicon 1 0 1 »At this time, there is a change in thickness of the bonded wafer, a change in the polishing thickness of the grinder device, and a change in the thickness of the porous silicon during anodization. Therefore, the maximum thickness change of the non-porous single crystal substrate bottom 100 is about 40 ± 5 # m »The etching conditions are as follows. RF frequency: 13.56MHz

R F功率:1 k W 台卩^氣體流率:lOOOsccm 氧流率:300 sc cm 壓力:2 ◦ P aR F power: 1 k W Taiwan 卩 gas flow rate: 100 sccm oxygen flow rate: 300 sc cm pressure: 2 ◦ P a

基底偏壓:500V 處理時間:1 1分鐘 在上述條件下之非多孔矽的蝕刻率爲5 ym/m i n ,而多孔砂爲1 Mm/m i η。若非多孔單晶基底部 1 0 Q在最壞情形約3 5 am,則過蝕刻4分鐘"若非多 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂 -29 420827 A7 ____B7_ 五、發明説明(27 ) 孔單晶基底部1 0 〇厚達4 5 /xm,則過蝕刻2分鐘。此 時之底多孔矽1 〇 1的蝕刻厚度分別是4/im和2 , 即使最壞’也可在1 〇 Mm多孔矽1 Ο 1內停止蝕刻。此 時對終點不做特殊判定,但對設在蝕刻系統的所有六個基 底’多孔矽在設定的處理時間內於整個表面露出。多孔矽 殘餘厚度的共晶圓面分布在±10%內。 此基底再以傳統HF/H20 2溶液進行濕蝕刻,藉以 除去多孔部》 結果,以在0. 2#m二氧化矽膜上之約l〇8nm ± 3 . 2 nm (±3%)膜厚度分布的優良超薄單晶矽膜 得到S 0 I基底》 (請先閲讀背面之注意事項再填寫本頁) 卜訂 I · 經濟部中央標準局貝工消费合作社印製 本紙張尺度適用中國國家橾半(CNS ) A4規格(210x297公釐) -30 -Substrate bias: 500V Processing time: 11 minutes Under the above conditions, the etching rate of non-porous silicon is 5 μm / m i n, and porous sand is 1 Mm / m i η. If the bottom of the non-porous single crystal substrate is about 10 Q in the worst case, about 3 5 am, then over-etch for 4 minutes. "If not many paper sizes apply the Chinese National Standard (CNS) A4 size (210X297 mm) (Please read the back Note for refilling this page) Order-29 420827 A7 ____B7_ V. Description of the invention (27) The bottom of the single crystal base with a thickness of 100 Å is 4 5 / xm, then over-etch for 2 minutes. At this time, the etching thickness of the porous silicon 101 is 4 / im and 2 respectively, and even at worst, the etching can be stopped within 10 mm of the porous silicon 101. At this time, no special judgment is made on the end point, but all six substrates' porous silicon provided in the etching system are exposed on the entire surface within a set processing time. The co-wafer plane of the residual thickness of porous silicon is distributed within ± 10%. This substrate was then wet-etched with a conventional HF / H20 2 solution to remove the porous part. As a result, the thickness was about 108 nm ± 3.2 nm (± 3%) on a 0.2 # m silicon dioxide film. Excellent ultra-thin monocrystalline silicon film with S 0 I substrate (please read the precautions on the back before filling this page). I · Printed by the Central Standards Bureau of the Ministry of Economy Half (CNS) A4 size (210x297 mm) -30-

Claims (1)

420827 B& CS •、申請專利範圍 第85115259號專利申請案 中文申請專利範圍修正本 民國87年11月修 1.一種SOI基底製程,包括下列步驟: 使一部份的單晶矽基底做成多孔,以在第一非多孔單 晶矽區上形成多孔單晶矽區: 在多孔單晶矽區表面上形成第二非多孔單晶矽區: 將單晶矽基底接至支持基底上,以便獲得多層結構, 其中該第二非多孔單晶矽區係內置於多層結構中; 除去第一非多孔單晶矽區; 除去多孔單晶矽區: 其中除去第一非多孔單晶矽區的步驟包括進行乾蝕刻 的步驟,其中非多孔單晶矽區的蝕刻率大於多孔單晶矽區 J— i Ί. I I I 裝 t i (請先閎讀背面之注意事項iv本頁) J—訂 經濟部中央標準局負工消费合作社印裝 2 除去第 括部分 3 乾蝕刻 在垂直 4 在基底 自偏壓 出的蝕 .如申請專利 一非多孔單晶 研磨第 .如申 使得電 於基底 .如申 上提供 改變* 刻終黏 一非多 請專利 或光能 表面的 請專利 平行板 判定多 範圍第1項的SO I基底製程,其中 矽區的步驟在進行乾蝕刻的步驟前包 孔單晶矽區的步驟· 範圔第1項的SO 1基底製程,其中 的游離形成活化離子種,活化離子種 方向加速|反應發生在基底表面。 範圍第3項的so I基底製程,其中 電極並觀察平行板電極與基底之間的 孔單晶矽區由乾蝕刻在整個表面上露 本紙铁尺度遒用國家揉率(CNS ) A4J^l格(210X297公釐) 420827 Β8 C8 D8 經濟部t央棣率局具工消費合作社印製 々、申請專利範圍 5. 如申請專利範圍第1項的SOI基底製程,其中 除去多孔單晶矽區的步睫由濕蝕刻實施,其中多孔單晶砂 區的蝕刻率大於非多孔單晶矽區。 6. 如申請專利範圍第1項的SOI基底製程,其中 除去多孔單晶矽區的歩驟由乾蝕刻實施*其中多孔單晶碎 區的蝕刻率大於非多孔單晶矽區* 7. 如申請專利範圍第6項的SOI基底製程.其中 多孔單晶矽區蝕刻率大於非多孔單晶矽區的乾蝕刻使得導 自至少電或光能之分解的活化基進入多孔區的孔,從內部 蝕刻多孔區· 8. 如申請專利範困第1項的SOI基底製程,其中 該移除第一非多孔層單晶矽區的步琛包括:研磨該第一非 多孔單晶矽菡,接著實施活化離子蝕刻。 9. 如申請專利範圍第1項的SOI基底製程,其中 該移除第一非多孔靥單晶矽區的步駭包括:研磨該第一非 多孔單晶矽區*接著實施活化離子蝕刻:其中移除該多晶 矽區的步驟包括:實施溼蝕刻,其非多孔單晶矽區的触刻 率小於多孔單晶矽區;或實施放射蝕刻’其非多孔單晶矽 區的蝕刻率亦小於多孔單晶矽區β 本紙張尺度適用中®國家抹率(CNS)A4说格(2丨0><297公#) 丨Μ:—------裝— (請先閲讀背面之注意事項^ f本頁) 訂 線420827 B & CS • Patent Application No. 85115259 Chinese Patent Application Amendment November 1987 1. A SOI substrate process including the following steps: Making a part of the single crystal silicon substrate porous To form a porous single-crystal silicon region on the first non-porous single-crystal silicon region: forming a second non-porous single-crystal silicon region on the surface of the porous single-crystal silicon region: attach the single-crystal silicon substrate to a supporting substrate in order to obtain A multilayer structure, wherein the second non-porous single crystal silicon region is built into the multilayer structure; removing the first non-porous single crystal silicon region; removing the porous single crystal silicon region: wherein the step of removing the first non-porous single crystal silicon region includes The dry etching step is performed, in which the non-porous single-crystal silicon region has a higher etch rate than the porous single-crystal silicon region J— i Ί. III mounting ti (please read the precautions on the back first iv page) J—Order the central standard of the Ministry of Economic Affairs Printing by the Office of the Consumer Cooperative 2 Removed the part 3 Dry etching in the vertical 4 Etching on the substrate self-biased. For example, a non-porous single crystal grinding application for a patent is applied. If applied, the electricity is applied to the substrate. Provides changes on the surface. * A patented parallel plate with a non-multiple patented or light surface can be used to determine the SOI substrate process of multi-range item 1. The silicon area step is packaged with monocrystalline silicon before the dry etching step. Steps in the zone · Fan 1's SO 1 substrate process, in which the activated ion species are formed freely, and the direction of the activated ion species is accelerated | The reaction occurs on the substrate surface. The so I substrate process of the third item, in which the single crystal silicon region of the electrode and the hole between the parallel plate electrode and the substrate is exposed on the entire surface by dry etching. The iron scale of the paper is used (CNS) A4J ^ l grid (210X297mm) 420827 Β8 C8 D8 Ministry of Economic Affairs, printed by the Central Government Bureau of Industrial and Commercial Cooperatives, patent application scope 5. For the SOI substrate process of the first scope of the patent application, the step of removing the porous single crystal silicon area The eyelashes are implemented by wet etching, in which the etching rate of the porous single crystal sand region is greater than that of the non-porous single crystal silicon region. 6. For example, the SOI substrate process of claim 1 in which the step of removing the porous single crystal silicon region is performed by dry etching * where the etching rate of the porous single crystal fragment region is greater than that of the non-porous single crystal silicon region * 7. The SOI substrate process of item 6 of the patent. The porous single-crystal silicon region has a higher etching rate than the non-porous single-crystal silicon region. The dry etching allows the activation group that leads from the decomposition of at least electrical or optical energy to enter the pores of the porous region and etches from the inside. Porous region 8. The process of removing the first non-porous single-crystal silicon region as described in the patent application for the first SOI substrate process includes: grinding the first non-porous single-crystal silicon region, and then performing activation Ion etching. 9. According to the SOI substrate process of claim 1, the step of removing the first non-porous single crystal silicon region includes: grinding the first non-porous single crystal silicon region * and then performing activated ion etching: where The step of removing the polycrystalline silicon region includes: performing wet etching, the non-porous single crystal silicon region has a lower etching rate than the porous single crystal silicon region; or performing radiation etching, the non-porous single crystal silicon region also has an etching rate lower than that of the porous single crystal silicon region. Crystal silicon area β This paper is applicable in the national standard (CNS) A4 grid (2 丨 0 > &297;#) 丨 M: ————— 装 — (Please read the precautions on the back first ^ f this page)
TW085115259A 1996-12-05 1996-12-10 Fabrication process of SOI substrate TW420827B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32510596A JP3250721B2 (en) 1995-12-12 1996-12-05 Method for manufacturing SOI substrate

Publications (1)

Publication Number Publication Date
TW420827B true TW420827B (en) 2001-02-01

Family

ID=18173186

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085115259A TW420827B (en) 1996-12-05 1996-12-10 Fabrication process of SOI substrate

Country Status (1)

Country Link
TW (1) TW420827B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7911058B2 (en) 2005-11-30 2011-03-22 Elpida Memory Inc. Semiconductor chip having island dispersion structure and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7911058B2 (en) 2005-11-30 2011-03-22 Elpida Memory Inc. Semiconductor chip having island dispersion structure and method for manufacturing the same
US8088673B2 (en) 2005-11-30 2012-01-03 Elpida Memory Inc. Semiconductor chip having island dispersion structure and method for manufacturing the same

Similar Documents

Publication Publication Date Title
KR100236689B1 (en) Fabrication process of soi substrate
US5876497A (en) Fabrication process and fabrication apparatus of SOI substrate
TW404061B (en) Semiconductor substrate and method of manufacturing the same
JP3352340B2 (en) Semiconductor substrate and method of manufacturing the same
TW447127B (en) Substrate and production method thereof
JP5363974B2 (en) Semiconductor on glass insulator fabricated using an improved thinning process
JP3294934B2 (en) Method for manufacturing semiconductor substrate and semiconductor substrate
JP3237888B2 (en) Semiconductor substrate and method of manufacturing the same
TW424330B (en) Semiconductor article and method of manufacturing the same
JP3261685B2 (en) Semiconductor element substrate and method of manufacturing the same
US6103598A (en) Process for producing semiconductor substrate
JP3214631B2 (en) Semiconductor substrate and method of manufacturing the same
JPH11243076A (en) Anodization method and apparatus and manufacture of semiconductor substrate
JPH05217992A (en) Semiconductor substrate and manufacture thereof
JP2000223682A (en) Processing method for basic body and production of semiconductor substrate
JP2901031B2 (en) Semiconductor substrate and method of manufacturing the same
JP2910001B2 (en) Semiconductor substrate and method of manufacturing the same
JP2005311199A (en) Method for manufacturing substrate
JPH05206422A (en) Semiconductor device and its manufacture
TW420827B (en) Fabrication process of SOI substrate
JPH10326884A (en) Semiconductor substrate, its manufacture and its composite member
JP3171463B2 (en) Manufacturing method of semiconductor substrate
JP2000336499A (en) Treatment of substrate and its production as well as anodic chemical conversion apparatus
JP3293688B2 (en) Manufacturing method of semiconductor substrate
JP3293766B2 (en) Semiconductor member manufacturing method

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees