TW420783B - Commandless programmable controller - Google Patents

Commandless programmable controller Download PDF

Info

Publication number
TW420783B
TW420783B TW84110890A TW84110890A TW420783B TW 420783 B TW420783 B TW 420783B TW 84110890 A TW84110890 A TW 84110890A TW 84110890 A TW84110890 A TW 84110890A TW 420783 B TW420783 B TW 420783B
Authority
TW
Taiwan
Prior art keywords
event
scope
patent application
item
control device
Prior art date
Application number
TW84110890A
Other languages
Chinese (zh)
Inventor
Ar-Fu Peter Lam
Original Assignee
Lam Ar Fu Peter
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=21624886&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TW420783(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Lam Ar Fu Peter filed Critical Lam Ar Fu Peter
Priority to TW84110890A priority Critical patent/TW420783B/en
Application granted granted Critical
Publication of TW420783B publication Critical patent/TW420783B/en

Links

Landscapes

  • Programmable Controllers (AREA)

Abstract

The invention discloses a programmable controller which is applied to be used together with a voice synthesizer. The device provides the programmable method the first table form 10 and the second listing form 20. The first table form 10 defines the status (13, 14, 15, 16) of the input/output end 12, and the second listing form 20 defines the executed events (21, 22, 23, 24) when receiving a qualified input signal. The invention also discloses a hardware application example, which combines the pre-determined I/O status memory to specify different I/O status 11. The hardware application is consolidated closely with respect to the programmable method so as to produce low-cost programmable controller.

Description

經濟部智慧財產局員Η消費合作社印製 ^20783 ^ A7 _R7_.五、發明說明(f ) 〔發明領域〕 本發明係關於一種響應於外部電激發的可程式化控制 裝置,其可互動地產生包括類比訊號、數位訊號及模擬訊 號之不同類型的輸出訊號。 〔發明背景〕 習用以微處理器爲基礎之控制裝置係逐行地利用組合 語言程式化過程以組成控制程式。本發明之目的係在於發 展一種具簡易構成程式方法之低成本的可程式化控制裝置 ,該方法並未含有任何難以學習之組合語言指令集,俾使 程式化過程可由普通人所進行,而無需加強訓練組合語言 之槪念與技能,亦無須理解微處理器的構造。 〔發明槪要〕 本發明係針對創新步驟(進步性)爲:硏究可程式化 控制裝置所需要基本構件;建立一簡單到足以讓未接受任 何加強專業訓練的普通人即可施行的圖表模式,以代表一 控制系統的操作;發展出一簡單的程式化格式,以便系統 化提供所需的程式功能,及最終發展出一種可配合該模式 及所發展的簡單程式格式之一編碼系統與一硬體電路,。 本發明的簡單程式化方法,包含:塡入兩表格或兩資 料欄位的步驟。該第一資料欄位命名輸入/輸出端之不同 穩定或變化形態,界定該輸入/輸出端的形態,並設定當 一輸入端接收到一合格的觸發訊號時將被執行的事件。該 第二資料欄位界定當一合格的觸發訊號被接收時之一事件 的響應<= --------'"--------一灯.'-------線 (請先閱讀背面之沒意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A.丨規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 420783 A7 ____D7____五、發明說明(7 ) 本發明的硬體實施例係針對一可程式化裝置的輸入/ 輸出(I /◦)結構及資料記憶體結構,以產生合成的音 頻訊號及/或數位輸出訊號。典型的硬體實施例包含:多 數輸入/輸出端(I/O端)’各I/O端被連接到用以 檢測預定合格輸入訊號的多數訊號鑑別電路;多數輸出訊 號驅動器,用於傳送一輸出訊號:一事件資料記憶體,用 以儲存當一合格訊號被接收時將被執行的事件;一 I / ◦ 形態記憶體,用以儲存設定該等I / 0接腳的輸入/輸出 狀況的構成資料,以及當一合格的觸發訊號被接收時定址 該事件資料記憶體;一事件執行電路,用於自事件資料記 憶體接收資料以產生不同類型的輸出訊號;及一尋址電路 ,定址該事件資料記憶體與該I/ ◦形態記憶體。 該程式化過程之除錯亦係利用簡單的程式化結構。在 許多情況下,該程式除錯過程可藉由互動式定址顯示於一 監測螢幕上一單頁資料表的觸發模式來進行。該簡單程式 化架構實質上削減了所需的硏發成本、程式化時間與除錯 時間,以發展一種具有互動式控制特徵的產品。 與一基於微處理器之控制裝置比較時,本發明的最簡 單且最小型化結構實施例的主要差異係在於,爲既不含任 何程式計數器、運算邏輯單元(A L U )、指令解碼器, 亦不含任何堆疊記憶體。並未具有特定的共用資料匯流排 與定址匯流排,以供控制裝置的大部功能方塊所共享。除 非係因一訊號產生器所需而產生一訊號,否則一時脈訊號 係爲不必要的。一事件的執行可能是瞬間的,而不會有任 4 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格⑵0 X 297公f ) 137 --- 137 --- 經濟部智慧財產局員工消費合作社印製 五、發明說明(.:)) 何與微處理器之時脈電路有關的指令集所造成的延遲。歸 因於該簡單的硬體結構,本發明之控制裝置的成本相較於 一般以微處理器爲基礎的控制器係較爲價廉。 本發明的程式化結構無需如一般組合語言程式化中所 需之順序邏輯次序的程式化過程;程式設計師也無需學習 任何指令集。本發明的簡單結構使得普通人能以最少的訓 練而有效地進行控制裝置的程式化。 藉由加入聲音合成功能,該裝置可應用於一有限能力 之可程式聲音合成器裝置上,可互動地驅動外部換能器( 諸如一發光二極體(LED)陣列)及同時產生模擬聲音 〇 此外,本發明的實施例在許多其它的應用中獲得實用 性,例如邏輯控制器、互動式控制器與計時器。 本發明之新穎特徵係特別界定在附加的申請專利範圍 。在閱讀以下描述並結合附圖時’可利於理解本發明。 〔附圖簡要描述〕 第一圖說明一顯示資料格式以將控制裝置程式化之可 程式化架構表的一種實施例。 第二A圖係一應用例的流程圖。 第二B圖係依據第二A圖之流程圖所程式化的圖表。 第三A圖係另一應用例的流程圖° 第三B圖係依據第三A圖之流程圖所程式化的圖表。 第四A圖係另一應用例的另一流程圖。 第四B圖係依據第四A圖之流程圖所程式化的圖表。 5 本紙張尺度適用中國國家標準(CNS)A.l覘格(210 X 297公f ) . ^ - I ------訂---------線---- (請先閱讀背面之;i意事項再填寫本頁) Λ7 420783 ___B7_ 五、發明說明(4") 第五圖係顯示硬體結構的方塊圖。 第六圖係顯示典型輸入/輸出電路結構的電路圖。 第七圖係顯示該I / 0形態記憶體與該尋址電路的典 型結構之電路圖。 第八圖係顯示典型事件資料記憶體、事件執行電路與 相關尋址電路之介面的電路圖。 第九圖係第八圖之一增強型電路圖。 第十A圖說明一顯示計時程式化功能的可程式化構型 表的一種實施例。 第十B圖說明一顯示間接尋址功能的可程式化構型表 的一種實施例。 第~^--圖係一典型的屏幕顯不以模擬該程式流程’用 以對該程式構型表除錯。 第十二圖係一版面設計的實例,以顯示一積體電路內 部的該I / 0形態記憶體的位置。 [較佳實施例詳細說明] 一理解本發明的較簡單途徑,係界定該可程式化裝置 之一較佳實施例的規格,藉由應用例以說明並硏究該程式 化方法而對可程式化的語音合成器程式化。下一步驟係硏 究數個簡單的應用例。該描述隨後將擴展到所發明之控制 裝置的硬體實施例、與將本發明製造在一積體電路中的方 法及最後爲程序模擬與除錯系統的一較佳實施例。 一典型實施例的詳細說明,將以下列的應用實例來說 明: 6 本紙張尺度適用中國國家標準(CNSW規格(210 X 297公釐> --— 1----—--— -^氏----I J I 訂 *11--—---* (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制仅 經濟部智慧財產局員工消費合作社印製 42 07 83 Λ7 137 五、發明說明($) 1.該控制裝置包含八個可程式化輸入/輸出端及一 附加的音頻輸出端。各端的命名將由一個三位元的二進制 數代表。 2 ·各端可被程式化爲一輸入端、一輸出端或一"可 被忽略〃的高阻抗端。 3 ·各輸入端均被程式化,以便對一具〃合格"特徵 的輸入觸發訊號產生響應。四個典型特徵的輸入訊號被界 定用於較佳實施例,如下: (a ) —訊號,具有一上升緣特徵,以符號〃 R 〃代 表; (b ) —訊號,具有一下降緣特徵,以符號〃 F 〃代 表; (c ) 一訊號,特徵爲當該訊號被取樣時有一邏輯高 電位,以符號〃 1 〃代表;以及 * ( (Γ) 一訊號,特徵爲當該訊號被取樣時有一邏輯低 電位,以符號〃 0 〃代表。 4 ·各輸出端可被程式化,以傳送一輸出訊號。三個 輸出訊號的實例被界定如下: (a ) —邏輯高電位訊號,以符號"H ^代表: (b ) —邏輯低電位訊號,以符號# L "代表: (c ) 一輸出訊號’包含一 6 Η z的方波脈衝’以符 號Ρ 〃代表。Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and a consumer cooperative ^ 20783 ^ A7 _R7_. V. Description of Invention (f) [Field of Invention] The present invention relates to a programmable control device that responds to external electrical excitation, which can interactively generate Different types of output signals such as analog signals, digital signals and analog signals. [Background of the Invention] Conventional microprocessor-based control devices are programmed line-by-line using a combination of languages to compose control programs. The object of the present invention is to develop a low-cost programmable control device with a simple method of programming. The method does not contain any combination of instruction sets that are difficult to learn, so that the programming process can be performed by ordinary people without It is not necessary to understand the structure of microprocessors to strengthen the training of the language and skills of combination languages. [Invention Summary] The present invention is directed to the innovative steps (progressive): to study the basic components required for a programmable control device; to establish a chart mode that is simple enough for ordinary people without any enhanced professional training to implement To represent the operation of a control system; develop a simple programmatic format to systematically provide the required program functions, and finally develop a coding system and a coding system that can match the model and the developed simple program format Hardware circuit, The simple stylized method of the present invention includes the steps of entering two forms or two data fields. The first data field names the different stable or changing shape of the input / output terminal, defines the shape of the input / output terminal, and sets an event to be executed when an input terminal receives a qualified trigger signal. The second data field defines the response of an event when a qualified trigger signal is received < = -------- '" -------- a light .'--- ---- Line (Please read the unintentional matter on the back before filling in this page) This paper size applies to China National Standard (CNS) A. 丨 Specifications (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 420783 A7 ____D7____V. Description of the invention (7) The hardware embodiment of the present invention is directed to the input / output (I / ◦) structure and data memory structure of a programmable device to generate a synthesized audio signal and / or Digital output signal. A typical hardware embodiment includes: a plurality of input / output terminals (I / O terminals). Each I / O terminal is connected to a majority signal discrimination circuit for detecting a predetermined qualified input signal; most output signal drivers are used to transmit a Output signal: an event data memory for storing events that will be executed when a qualified signal is received; an I / ◦ shape memory for storing the input / output status of the I / 0 pins Constituting data, and addressing the event data memory when a qualified trigger signal is received; an event execution circuit for receiving data from the event data memory to generate different types of output signals; and an addressing circuit that addresses the Event data memory and the I / ◦ shape memory. The debugging of the stylization process also uses a simple stylized structure. In many cases, the process of debugging the program can be performed by triggering the display of a single-page data table on a monitor screen with interactive addressing. This simple stylized architecture substantially reduces the development costs, stylization time, and debugging time required to develop a product with interactive control features. Compared with a microprocessor-based control device, the main difference between the simplest and the smallest structure embodiment of the present invention is that it does not contain any program counter, arithmetic logic unit (ALU), instruction decoder, or Does not contain any stacked memory. There are no specific shared data buses and addressing buses for most function blocks of the control device to share. A clock signal is unnecessary unless it is generated by a signal generator. The execution of an event may be instantaneous, and there will be no 4 (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification ⑵0 X 297 male f) 137 --- 137 --- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (. :)) What is the delay caused by the instruction set related to the clock circuit of the microprocessor. Due to the simple hardware structure, the cost of the control device of the present invention is lower than that of a general microprocessor-based controller system. The stylized structure of the present invention does not require the stylization process of the sequential logical order as required in general combinational language stylization; the programmer does not need to learn any instruction set. The simple structure of the present invention enables ordinary people to efficiently program the control device with minimal training. By adding the sound synthesis function, the device can be applied to a programmable sound synthesizer device with limited capabilities, which can interactively drive external transducers (such as a light emitting diode (LED) array) and simultaneously generate analog sounds. In addition, the embodiments of the present invention find utility in many other applications, such as logic controllers, interactive controllers, and timers. The novel features of the present invention are specifically defined in the scope of additional patent applications. It will be helpful to understand the present invention when reading the following description in conjunction with the accompanying drawings. [Brief description of the drawings] The first figure illustrates an embodiment of a programmable architecture table that displays a data format to program a control device. The second A diagram is a flowchart of an application example. The second diagram B is a chart stylized according to the flowchart of the second diagram A. The third diagram A is a flowchart of another application example. The third diagram B is a chart stylized according to the flowchart of the third diagram A. The fourth A diagram is another flowchart of another application example. The fourth diagram B is a chart stylized according to the flowchart of the fourth diagram A. 5 This paper size applies to the Chinese National Standard (CNS) Al Grid (210 X 297 male f). ^-I ------ Order --------- Line ---- (Please read first (I will fill in this page on the back of the page) Λ7 420783 ___B7_ V. Description of the invention (4 ") The fifth picture is a block diagram showing the hardware structure. The sixth diagram is a circuit diagram showing a typical input / output circuit structure. The seventh diagram is a circuit diagram showing a typical structure of the I / 0 form memory and the addressing circuit. The eighth figure is a circuit diagram showing the interface of a typical event data memory, an event execution circuit and a related addressing circuit. The ninth diagram is an enhanced circuit diagram of the eighth diagram. Fig. 10A illustrates an embodiment of a programmable configuration table showing a timing programming function. Fig. 10B illustrates an embodiment of a programmable configuration table showing an indirect addressing function. The first ~ ^-picture is a typical screen display to simulate the program flow 'to debug the program configuration table. The twelfth figure is an example of a layout design to show the location of the I / 0 shape memory inside a integrated circuit. [Detailed description of the preferred embodiment] A simpler way to understand the present invention is to define the specifications of a preferred embodiment of the programmable device, and to explain and investigate the programmable method by applying examples to the programmable Stylized speech synthesizer. The next step is to explore a few simple application examples. The description will then be extended to a hardware embodiment of the invented control device, a method of manufacturing the invention in an integrated circuit, and finally a preferred embodiment of a program simulation and debugging system. A detailed description of a typical embodiment will be described with the following application examples: 6 This paper size applies to Chinese national standards (CNSW specifications (210 X 297 mm >) --- 1 ----------^ ---- IJI order * 11 ------ * (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 42 07 83 Λ7 137 5. Description of the invention ($) 1. The control device includes eight programmable input / output terminals and an additional audio output terminal. The name of each terminal will be represented by a three-digit binary number. 2 · Each terminal can be programmed as an input terminal, an output terminal, or a high-impedance terminal that can be ignored. 3. Each input terminal is programmed to trigger an input signal with "qualified" characteristics. Generate a response. Four typical characteristics of the input signal are defined for use in the preferred embodiment, as follows: (a) — signal with a rising edge characteristic, represented by the symbol 〃 R ;; (b) — signal, with a falling edge Characteristics, represented by the symbol 〃 F ;; (c) a Signal, characterized by a logic high potential when the signal is sampled, represented by the symbol 〃 1 ;; and * ((Γ), a signal characterized by a logic low potential when the signal is sampled, represented by the symbol 〃 0 〃 4. Each output terminal can be programmed to transmit an output signal. Examples of three output signals are defined as follows: (a) — logic high signal, represented by the symbol " H ^: (b) — logic low The potential signal is represented by the symbol # L ": (c) An output signal 'including a square wave pulse of 6 Η z' is represented by the symbol P 〃.

5 該"可被忽略#的高阻抗狀態由符號"x 〃代表 。各端將如上界定,而被設定爲八種可能的狀態之一 :R 7 本紙張尺度適用中S國家標準(CNS)A.l規格(210 X 297公/¾ ) I I II . — — — —— - I 1 I I I I I' ^ ---- — I-- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消f合作社印製 420783 ' A7 __B7 ___________ 五、發明說明(4 ) ' 、F、1、〇、Η ' L、P與X。一端點之八個可能的I /0形態各者,可藉由一個三位元的二進位數代表。 6,最多有1 6種可能的I / 〇形態’設定爲1 / 0 狀態# 0至I /0狀態# 1 5。各I /〇狀態藉由一個四 位元的二進位數代表。僅有一個I / 〇狀態係由程式來設 定’其用以代表控制裝置在某個時刻下的1 /〇形態。I / 0狀態#" 〇 〃被界定爲預設之動作的(active) I / 〇 形態:亦即當控制裝置首先接通電源時,將構成動作的I / 〇形態。 此外,上述狀態# “ 〇 ”的起動功能亦可由一個特定 的事件# “ 0 ”來替代。 7 _無論何時一 I / 0形態之一輸入端收到~合格的 觸發訊號,即直接執行一預定事件。 8 ·最多有3 2項預定事件》各事件以一個五位元的 二進位數代表。 應當注意的是:該實施例之一I / ◦端被規劃的方式 、I / 〇狀態及事件的最大數目係爲示範性。儘管I / 0 形態與事件的數目可爲任何彈性的數目;實際上,較高的 數目在內部暫存器與記憶體資料長度中需要更多的位元, 將因此導致較高的生產成本。一適當的數目最好在控制裝 置的設計中被界定。 根據本發明,可程式化語音合成器之程式化的較佳程 式化方法的一個實例係由第一圖中的程式化格式代表,該 程式化格式包含兩個欄位。第一欄位係藉由圖表1 〇來代 8 本纸張尺度適用中园國家標準(CJ\TS)A4規格(2】〇χ 297公釐) I I I I 1------- 1 —— — — —----- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 420783 ' Λ7 ______B7 _ 五、發明說明(7 ) 、 表,包含列出所有八個I / 〇端的一第一座標1 2與列出 所有I /〇形態的一第二座標1 1。圖表1 0中的各構成 部分代表一端點於一特殊I /〇形態下所處的狀態。該程 式化過程的第一部份係設定表中的各元件,分別具有如界 定的八個符號R、F、1、〇、X、Η、L與P中之一者 。每當·一端被規劃成一輸入端時,一編號的事件將被設定 。此即爲當一合格的輸入訊號被接收時所執行的事件。標 號1 3 〃 F : Ε 1 1 〃係指I / Ο態# 1的端點1 (腳1 )的狀態,而〃 F 〃係指合格訊號爲一下降緣特徵,Ε 1 1是指當一下降緣訊號由端點1接收時事件# 1 1將被執 行。標號1 4是指當一上升緣訊號由端點2檢測時,事件 # 2將被執行。標號1 5 〃 X 〃係指端點6係爲一可被忽 略端。無論何時一輸入端被界定爲〃 X 〃 ,任何由該端收 到的觸發訊號都將被忽略。每當·輸出端被界定成"X 〃 ,該輸出端上將形成高輸出阻抗。 現請參看圖表2 0,其包含該程式化格式的第二部份 ,並界定欲被執行的事件。一事件可能包含一或多個子事 件。當各事件或子事件被執行時,將執行諸如產生一輸出 訊號、修正一動作的I / 0形態、起始計時器計數器或 將執行導向另一事件之任務。圖表2 〇羅列了依據圖表1 0執行的所有事件的細節內容。標號2 1之行係指事件# 1包含三個子事件:2 2 〔狀態# 1 、2 3 (聲音1 ) 、與2 4 (事件# 1 )。假定I / 0狀態# 0係爲動作的 I /0形態;於端點1接收一上升緣訊號時即觸發事件# 9 本紙張尺度適用中园國家標準(CNSM4規格⑵ο χ 297公釐) ---— — — — — — — ^ — — — — — —— ------ I ------ (請先閱讀背面之注咅?事項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 Λ2 83 Α7 ____Β7 五、發明說明(β ) 1 ;即,子事件2 2、2 3與2 4將被依序執行。子事件 2 2是指動作的I / 〇形態自I / 〇狀態# 〇變換到I / ◦狀態# 1 :然後以〃聲音1 #標示的音頻訊號予以複製 。當聲音的複製完成時,子事件2 4被執行,循環回到執 行〃事件#丨〃並重複〃聲音1 〃以作另一循環。該迴路 繼續進行直至I / 〇狀態# 1的端點1至端點4的任一者 收到一合格的訊號爲止。例如,當端點1檢測到一下降緣 訊號時,該與〃事件# 1 〃構成循環的〃聲音1 〃被中斷 且事件# 1 1被執行。事件# 1 1指示控制器回到I /0 狀態# 0,該動作的I / ◦形態及〃結束#符號係指事件 結束時,控制裝置則處在-·等待欲接收之下一合格的輸入 訊號(如I/〇狀態# 〇所界定)的閒置模式中。 在控制裝置啓動時,一 I / 0形態係界定爲預設的起 始I / 0狀態;g卩,控制裝置之電源起動後立即之動作的 I / 0狀態。一方便的標示法爲界定I / ◦狀態# 0爲預 設之啓動I / ◦狀態。相對來說,狀態# 0可由一個事件 # 0來替代,即於啓動時,該事件# 0將首先被執行。 應當注意的是,各I / 0形態彼此係不具序列關係且 圖表1 0可由任何次序排列而成。類似地,圖表2 0中所 列的任何事件與另一事件間亦不具序列關係,除非其被標 示爲如標號2 1之行中另一事件的子事件。事件係可以任 何次序被編號,倘程式設計師要求時,該號碼可被跳過。 所有具序列關係的子事件將排列在一單一事件行列中。該 等排列方式使程式設計師在與列出一般組合語言程式化的 10 本紙張K度適用中國國家標準(CNS)A4規格X 297公釐) -------- ^ ----訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工湞費合作社印製 420783 、 A7 __B7__________ 五、發明說明(f ) ' 多行數列表比較時,可具有一-更淸晰的程式圖示。 儘管第一圖中的程式圖表如所述者構成兩欄位’本發 明之程式化方法保持學習的簡單性與簡易的可追蹤特性, 且程式化圖表的格式結構可有不同變化"例如I /〇狀態 ,欄位可以分割成一個硬性輸入欄位(只有輸入,沒有輸 出)及一個硬性輸出襴位。此時該輸入欄位只標示認可輸 入符號*而相對輸出欄位只標示與輸出有關之符號。 第二A圖與第二B圖說明另一簡單的應用實例,其中 該控制裝置的一觸發接腳被設計爲一不可觸發的觸發輸入 端。第二B圖的標號41之行是指腳2至腳8均爲可被忽 略端。標號4 2表示當·一上升緣訊號由腳1接收時,事件 # 1將被執行。圖表5 0表示事件# 1首先致動子事件# 5 1,其在〃聲音〃(標號5 2 )產生之前設定狀態# 1 爲動作的I / ◦形態。圖表4 0的標號4 5之行表示腳1 在#聲音A (標號5 2 )產生的時間內變換爲高阻抗狀態 ;故而腳1成爲一不可觸發的觸發腳。在聲音播出結束時 ,I /0狀態# 0被標示爲動作狀態,且腳1準備接收另 一合格的觸發訊號。 該二I / ◦的形態與事件# 1可藉由如第二A圖中所 示之一訊號流程圖表示。I / ◦狀態#◦與I /〇狀態# 1之各者係由一方塊表示。該矩形方塊3 1係指I /0狀 態# 0爲一穩定狀態。該橢圓形的方塊3 4係指I / ◦狀 態# 1爲一變換狀態。箭頭3 2表示依據圖表5 0中之事 件# 1的子事件5 1的指令,令動作狀態自I /〇狀態# 1! 本纸張尺度適用中國國家標準(CNS)A4規格(2]〇χ 297公釐) n n n —i n n n It n ·1 I» I ^ 0 I ϋ I n I ^eJ I n n ( Tf n I (請先閱讀背面之注意事項再填寫本頁) A7 420783 _B7 _____ 五、發明說明(…) 、 0被切換到I / 〇狀態# 1。箭頭3 3代表在〃聲音〃( 標號5 2 )被重製後’自動作狀態返回I / 0狀態# 〇的 子事件5 3。 第三A圖與第三B圖說明另一應用實例,其中該控制 裝置界定爲可觸發四個不同聲音(聲音# 1至聲音# 4 ) 的四個觸發端(腳1至腳4 )。在一聲音被播放期間內’ 對應的觸發端由於觸發訊號本身而爲不可觸發的’但其可 藉由其它輸入端收到的合格觸發訊號被中斷並被再次觸發 〇 第三B圖的標號7 7之行係指腳5至腳8均爲可被忽 略端。標號7 4表示當一上升緣訊號由腳4接收時,將執 行事件# 4。圖表8 0表示事件# 4首先致動子事件8 2 ,其在〃聲音# 4 "(標號8 3 )產生之前,先設定I / 0狀態# 4爲動作的I /0形態。圖表7 0的標號7 8之 行表示腳4在A聲音# 4 〃 (標號8 3 )產生時間內變換 爲高阻抗狀態;故而腳4成爲一不可觸發的接腳。標號7 8之行亦指示腳1至腳3維持在可觸發性,故由腳1至腳 3接收到的任何合格觸發訊號將中斷〃聲音# 4 〃的播放 。在聲音播放結束之時,狀態# 0爲依據子事件8 4而被 設定爲動作狀態,且腳4準備接收另一合格的觸發訊號。 該五個I / 0的形態與四項事件可藉由如第三A圖中 所示之一訊號流程_表示。I / 0狀態# 〇至I / 0狀態 # 4之各者係由一方塊表示。該矩形方塊6 4係指I /0 狀態# 0爲一穩定狀態。該橢圓方塊6 1、6 5、6 6與 12 本紙張尺度適用中國國家標準(CNSM·!規柊(210 X 297公釐) -------------壯 -------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印*'< A7 420783 B7____ 五、發明說明(W ~ 6 7係指I /Ο狀態# 1至I / 0狀態# 4爲變換狀態。 箭頭6 9表示動作狀態依據_表8 0中所示事件# 4的子 事件8 2之指令自I / 0狀態# 〇改變爲I / 0狀態# 4 。箭頭7 1代表在〃聲音# 4 # (標號8 3 )被重製後自 動作狀態返回I / 0狀態# 0的子事件8 4。 第二A圖與第三A圖的流程圖分別與程式化圖表4 0 、5 0、7 0與8 0的內容緊密聯結。在更爲複雜的應用 中,使用者將發現極爲有用的是首先草擬一流程圖,對每 一 I / 0形態與事件給予一有意義的名字,而不是一標示 號。依據該流程圖界定所需的I / 0形態與事件之數目’ 並最後爲如流程圖的內連箭頭所述,塡入I / ◦型態表與 事件列表》 第四A圖與第四B圖說明另一應用實例,其中該控制 裝置被界定爲具有兩觸發端(腳1與腳2 )與六個輸出端 (腳3至腳8 );各輸出端被連接以驅動一發光二極體。 該六個發光二極體被連接在一列中’以顯示閃爍效果。腳 1首先被觸發以啓動發光二極體列的順序閃爍’以使各發 光二極體被逐一導通並持續0 . 5秒。當腳1被再次觸發 時,控制裝置係變換到第二個閃光模式’使三個交替的發 光二極體一次被導通並持續約〇 · 5秒。腳1的隨後觸發 將在兩閃光模式之間循環切換。該閃光過程將持續直至腳 2被觸發爲止。 一使用者’首先藉由製訂出一如第四A圖中所示之流 程圖,即可輕易地設計此應用實例。該矩形方塊9 1設定 13 本紙張尺度適用中因國家標準(CNS)A4規格(210 X 297公餐) (請先閱讀背面之注意事項再填寫本I) 訂---------線— 經濟部智慧財產局員工消費合作社印4'1衣 Λ7 420783 _____ B7 五、發明說明(p) I /◦狀態# 〇處於代表開機狀態與待機模式二者下之穩 定狀態。當接收到合格的觸發信號時’順序的L E D閃 光模式9 2藉由代表事件# 1之開始的箭頭線9 4而被啓 動。該環路過程9 7包含六個不同的L E D輸出狀態。環 路過程9 7的各狀態逐一點亮一不同的L E D ’並持續一 〇 _ 5秒的時間。 在腳2收到一停止脈衝時,閃光順序將被中斷,且動 作狀態將透過箭頭線9 5所示的事件# 3返回到I / 〇狀 態# 0。倘腳1隨後接收到合格的訊號,該環路過程9 7 將被中斷並透過箭頭線9 6所示的事件# 2切換到交替的 閃光模式9 3 =該交替的閃光模式之環路過程9 8包含兩 L E D輸出狀態。各狀態點亮三個L E D持續一 0 5秒 時間。當該觸發脈衝被再次接收,該閃光過程透過事件# 1被切回順序的閃光模式9 2。倘一停止脈衝被接收,動 作狀態透*過事件# 3將被切換到方塊9 i,且控制裝置將 返回到待機模式。 由該流程圖可看出 > 程式化過程需要9個I /0形態 。I/O狀態#0代表開機I/O形態以及待機模式。需 要界定六個I / 0形態用於順序式L E D閃光模式,及兩 個I / Ο形態於交替式L E D閃光模式。+除此之外,三個 事件將被設定。事件# 1指向順序的L E D閃光模式,事 件# 2指向交替的L E D閃光模式,且事件# 3指向待機 模式^ 由流程圖第四A圖的揭示,即可建搆成圖表1 〇 〇與 14 本紙張尺度適用中®囤家標準(CNS)A4規格(210 X四7公t ) —I I I - ----I 1 I « ----III— - — — — — 111 — I I <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製5 The high impedance state of the " can be ignored &## is represented by the symbol " x 〃. Each end will be defined as above, and it is set to one of eight possible states: R 7 This paper size is applicable to the National Standard (CNS) Al specification (210 X 297 g / ¾) II II. — — — —- I 1 IIIII '^ ---- — I-- (Please read the notes on the back before filling in this page) Printed by the Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 420783' A7 __B7 ___________ V. Description of Invention (4) ' , F, 1, 0, Η 'L, P, and X. Each of the eight possible I / 0 patterns of an endpoint can be represented by a three-digit binary number. 6, there are up to 16 possible I / 〇 patterns' set to 1/0 state # 0 to I / 0 state # 1 5. Each I / 0 state is represented by a four-digit binary number. There is only one I / 〇 state set by the program ', which is used to represent the 1 / 〇 state of the control device at a certain time. I / 0 state # 〃 界定 is defined as the active I / 〇 form: that is, when the control device is first powered on, it will constitute the I / 〇 form of action. In addition, the start function of the above state # "0" can also be replaced by a specific event # "0". 7 _Whenever an input terminal of an I / 0 mode receives a qualified trigger signal, it directly executes a predetermined event. 8 · There are up to 32 scheduled events. Each event is represented by a five-digit binary number. It should be noted that the manner in which the I / O terminal is planned, the maximum number of I / O states, and events in one of the embodiments is exemplary. Although the number of I / 0 patterns and events can be any flexible number; in fact, higher numbers require more bits in the internal register and memory data length, which will result in higher production costs. An appropriate number is best defined in the design of the control device. According to the present invention, an example of a better programming method of a programmable speech synthesizer is represented by the programmatic format in the first figure, which includes two fields. The first column is based on the chart 10 to replace the paper size of this paper with Zhongyuan National Standard (CJ \ TS) A4 specification (2) 0 x 297 mm. IIII 1 ------- 1 —— — — —----- (Please read the notes on the back before filling out this page) Consumption Cooperation by Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs 420783 'Λ7 ______B7 _ V. Description of the Invention (7), a table, including a list One first coordinate 12 for all eight I / 〇 terminals and one second coordinate 11 for all I / 〇 patterns. Each component in Figure 10 represents the state of an endpoint in a special I / 0 configuration. The first part of the programming process is to set each element in the table to have one of the eight symbols R, F, 1, 0, X, Η, L, and P, as defined. Whenever one end is planned as an input end, a numbered event will be set. This is the event that is executed when a qualified input signal is received. Reference number 1 3 〃 F: Ε 1 1 〃 refers to the state of the end point 1 (pin 1) of I / 〇 state # 1, and 〃 F 指 refers to the pass signal as a falling edge feature, Ε 1 1 refers to when a Event # 1 1 will be executed when the falling edge signal is received by endpoint 1. Reference numeral 14 means that when a rising edge signal is detected by endpoint 2, event # 2 will be executed. The reference number 1 5 〃 X 〃 means that the end point 6 is a negligible end. Whenever an input terminal is defined as 〃 X 〃, any trigger signal received by that terminal will be ignored. Whenever the output is defined as " X 〃, a high output impedance will be formed on the output. Please refer to Figure 20, which contains the second part of the stylized format and defines the events to be executed. An event may contain one or more sub-events. When each event or sub-event is executed, it will perform tasks such as generating an output signal, correcting an I / O pattern of an action, starting a timer counter, or directing execution to another event. Figure 2 lists details of all events performed in accordance with Figure 10. The line labeled 2 1 means that event # 1 contains three sub-events: 2 2 [state # 1, 2 3 (sound 1), and 2 4 (event # 1). Assume I / 0 state # 0 is the action I / 0 pattern; event # 1 is triggered when endpoint 1 receives a rising edge signal. 9 This paper size is applicable to the China National Standard (CNSM4 specification ⑵ο χ 297 mm)- -— — — — — — — ^ — — — — — — ------ I ------ (Please read the note on the back? Matters before filling out this page> Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative Λ2 83 Α7 ____ Β7 V. Invention description (β) 1; that is, sub-events 2, 2, 3, and 24 will be executed in order. Sub-event 22 refers to the I / 〇 form of the action since I / 〇State # 〇Transform to I / ◦State # 1: Then copy the audio signal marked with 〃 音 1 #. When the sound copy is completed, sub-event 24 is executed, and the loop returns to the execution 〃Event # 丨 〃 And repeat "Sound 1" for another cycle. The loop continues until any one of endpoint 1 to endpoint 4 of I / 〇 state # 1 receives a qualified signal. For example, when endpoint 1 detects At the time of a falling edge signal, the "event 1" which constitutes a loop with "event 1" is interrupted and event # 1 1 is executed. Event # 1 1 instructs the controller to return to I / 0 state # 0, the I / ◦ shape and end of the action # symbol means that when the event is over, the control device is in-· waiting to receive a qualified input signal. (As defined by I / 〇 state # 〇) in the idle mode. When the control device is started, an I / 0 pattern is defined as a preset initial I / 0 state; g., Immediately after the power of the control device is started I / 0 status of the action. A convenient notation is to define I / ◦ status # 0 as the default startup I / ◦ status. In contrast, status # 0 can be replaced by an event # 0, that is, at startup The event # 0 will be executed first. It should be noted that the I / 0 patterns are not in a sequence relationship with each other and the chart 10 can be arranged in any order. Similarly, any event listed in chart 20 and another There is also no sequence relationship between events unless they are marked as sub-events of another event in the line 21. Events can be numbered in any order, and the number can be skipped if requested by the programmer. All Sequenced sub-events will be arranged in a single These arrangement methods allow programmers to formulate and print 10 papers that are stylized in a general combination of languages. The Chinese National Standard (CNS) A4 specification X 297 mm is applicable. -------- ^ ---- Order --------- line (please read the notes on the back before filling this page) Printed by the Intellectual Property Cooperative of the Ministry of Economic Affairs and Staff Cooperatives 420783, A7 __B7__________ 5. Description of Invention (f) 'Multi-line list comparisons can have one-clearer program icons. Although the program chart in the first figure constitutes two fields as described above, the stylized method of the present invention keeps learning simple and simple traceability, and the format structure of the program chart can have different changes " for example, I / 〇 status, the field can be divided into a hard input field (only input, no output) and a hard output unit. At this time, the input field only indicates the approved input symbol *, and the relative output field only indicates the output-related symbols. Figures 2A and 2B illustrate another simple application example, in which a trigger pin of the control device is designed as a non-triggerable trigger input terminal. The line 41 in the second B figure means that the feet 2 to 8 are all negligible ends. Reference numeral 4 2 indicates that when a rising edge signal is received by pin 1, event # 1 will be executed. Figure 5 0 indicates that event # 1 first activates sub-event # 5 1, which sets state # 1 as the action I / ◦ state before 〃 sound 〃 (reference 5 2) is generated. Line 4 of the chart 4 0 indicates that foot 1 changes to a high-impedance state within the time of #sound A (reference 5 2); therefore, foot 1 becomes an untriggerable trigger foot. At the end of the sound broadcast, I / 0 state # 0 is marked as the action state, and pin 1 is ready to receive another qualified trigger signal. The two I / ◦ patterns and events # 1 can be represented by a signal flow chart as shown in the second A diagram. Each of I / ◦ state # ◦ and I / 〇 state # 1 is represented by a square. The rectangular block 31 means that the I / 0 state # 0 is a stable state. The elliptical square 3 4 means that I / ◦ state # 1 is a transition state. The arrow 32 indicates that according to the instruction of the sub event 5 1 of the event # 1 in the chart 50, the operation state is from the I / 〇 state # 1! This paper size applies the Chinese National Standard (CNS) A4 specification (2) 〇χ 297 mm) nnn —innn It n · 1 I »I ^ 0 I ϋ I n I ^ eJ I nn (Tf n I (Please read the precautions on the back before filling out this page) A7 420783 _B7 _____ 5. Description of the invention (...), 0 is switched to I / 〇 state # 1. The arrow 3 3 represents the sub-event 5 3 of the 'automatic state return to I / 0 state # 〇 after the 〃 sound 〃 (label 5 2) is reproduced. Figures 3A and 3B illustrate another application example, in which the control device is defined as four triggering ends (pins 1 to 4) that can trigger four different sounds (sound # 1 to sound # 4). During the sound being played, the corresponding trigger terminal is not triggerable due to the trigger signal itself, but it can be interrupted and triggered again by a qualified trigger signal received by other inputs. Lines 5 to 8 are all negligible ends. Reference numeral 7 4 indicates that when a rising edge signal is received by foot 4, it will execute Event # 4. Diagram 8 0 indicates that event # 4 first activates sub-event 8 2, which sets I / 0 state # 4 as the I / 0 form of action before the sound # 4 " (label 8 3) is generated. . The line 7 of the chart 7 0 indicates that the foot 4 changes to a high impedance state within the time of the A sound # 4 标号 (key 8 3); therefore, the foot 4 becomes an untriggerable pin. The line of the 78 Indicate that feet 1 to 3 remain triggerable, so any qualified trigger signal received by feet 1 to 3 will interrupt the playback of 〃 Sound # 4 。. At the end of sound playback, status # 0 is based on the sub-event 8 4 is set to the action state, and foot 4 is ready to receive another qualified trigger signal. The five I / 0 patterns and four events can be represented by one of the signal flow_ shown in Figure 3A Each of I / 0 state # 0 to I / 0 state # 4 is represented by a square. The rectangular box 6 4 refers to I / 0 state # 0 as a stable state. The oval box 6 1, 6 5, 6 6 and 12 This paper size applies to Chinese National Standards (CNSM ·! Regulations (210 X 297 mm) ------------- Zhuang ------- Order ---- ----- line (please first Read the notes on the reverse side and fill out this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * '< A7 420783 B7____ V. Description of the invention (W ~ 6 7 refers to I / 〇 state # 1 to I / 0 state # 4 Is the transition state. The arrow 6 9 indicates that the operation state is changed according to the event # 4 sub-event 8 shown in Table 8 0. The instruction of event 8 2 is changed from I / 0 state # 0 to I / 0 state # 4. The arrow 7 1 represents the sub event 8 4 that returns to I / 0 state # 0 from the action state after the sound # 4 # (reference number 8 3) is reproduced. The flowcharts of the second A and third A graphs are closely linked to the contents of the stylized graphs 40, 50, 70, and 80, respectively. In more complex applications, users will find it extremely useful to first draft a flowchart that gives each I / 0 pattern and event a meaningful name, rather than a label. According to the flowchart, define the required number of I / 0 patterns and events' and finally enter the I / ◦type table and event list as described by the inline arrows of the flowchart. "Figure 4A and 4B The figure illustrates another application example, where the control device is defined as having two trigger terminals (pins 1 and 2) and six output terminals (pins 3 to 8); each output terminal is connected to drive a light emitting diode . The six light-emitting diodes are connected in a row ' to show a blinking effect. Pin 1 is first triggered to start blinking in the order of the light-emitting diode array, so that each light-emitting diode is turned on one by one for 0.5 seconds. When foot 1 is triggered again, the control device is switched to the second flash mode 'so that three alternating light emitting diodes are turned on at a time for about 0.5 seconds. Subsequent triggers on pin 1 will cycle through the two flash modes. This flashing process will continue until foot 2 is triggered. A user 'can easily design this application example by first formulating a flow chart as shown in Figure 4A. The rectangular box 9 1 set 13 This paper size is applicable due to the national standard (CNS) A4 specification (210 X 297 meals) (Please read the precautions on the back before filling in this I) Order --------- Line — Consumer Cooperatives ’Seal of the Intellectual Property Bureau of the Ministry of Economic Affairs 4'1 clothing Λ7 420783 _____ B7 V. Description of the invention (p) I / ◦ State # 〇 is in a stable state representing both the on state and the standby mode. When a qualified trigger signal is received, the 'sequential LED flash mode 9 2 is activated by an arrow line 9 4 representing the beginning of event # 1. The loop process 9 7 contains six different LED output states. Each state of the loop process 9 7 lights up a different L E D ′ one by one and lasts for a time of _ 5 seconds. When a stop pulse is received at pin 2, the flash sequence will be interrupted and the action status will return to I / 〇 state # 0 through event # 3 shown by arrow line 95. If pin 1 subsequently receives a qualified signal, the loop process 9 7 will be interrupted and switched to the alternate flash mode 9 via the event # 2 shown by the arrow line 9 6 3 = the loop process 9 of the alternate flash mode 9 8 contains two LED output states. Each state lights three LEDs for one and a half seconds. When the trigger pulse is received again, the flash process is switched back to the sequential flash mode 9 2 through event # 1. If a stop pulse is received, the operation status through event # 3 will be switched to block 9 i and the control unit will return to standby mode. As can be seen from the flowchart, > The stylization process requires 9 I / 0 patterns. I / O status # 0 represents the power-on I / O mode and standby mode. It is necessary to define six I / 0 patterns for the sequential LED flash mode, and two I / O patterns for the alternate LED flash mode. + In addition, three events will be set. Event # 1 points to the sequential LED flash mode, event # 2 points to the alternate LED flash mode, and event # 3 points to the standby mode ^ From the disclosure of Figure 4A of the flowchart, the chart 1 can be constructed. Standards applicable to China® Standards (CNS) A4 (210 X 4 7 t) —III----- I 1 I «---- III—-— — — — 111 — II < Please read first Note on the back, please fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

經濟部智慧財產局員工消費合作社印K 42 0783 A7 B7 五、發明說明(") 、 圖表1 2 0 »以有意義名稱標示各I / 〇形態與事件’可 取代以數字標示各I / 〇形態與事件。類似地,各I / 0 端亦被命名以有助於該程式化過程。在圖表1 0 0中’腳 1被命名爲撥動觸發腳並以"T G 〃來標示,腳2爲”截 止〃端以停止該閃光過程。腳3至腳8被標示爲L E D 1 至L E D 6,以指示此等端腳分別被連接到L E D 1至L E D 6。I / 〇狀態# 〇被標示如標號1 〇 2指示的〃待 機模式〃 =I / 〇狀態# 1被標示如標號1 0 1中所示的 "L E D 1 Ο N (導通)"。I / 0狀態# 7被標示如 標號1 0 1所示的名稱〃 A L T 1 〃 ,以表示該第一交替 的L E D爲點亮形式。I / 0狀態# 8標示如標號1 1 1 所示之名稱〃 A L T 2 〃 ,以表示該第二交替的L E D爲 點亮形式。 在開機啓動時,ί /◦狀態# 0被設定爲開機動作的 厂/◦形態。僅腳1可檢測一上升緣的合格訊號。所有其 它的端腳均處於高阻抗狀態中。如由代碼標號1 〇 7所指 者,在腳1接收到一合格觸發信號時,事件# 1 ( 1 2 1 )被執行,其如子事件1 2 2所指示’即初始該動作的ί /0狀態令其切換到I /〇狀態# 1 ;並因此逐步地切換 到I / 0狀態# 6。各I / 0形態由延遲〇 . 5 〃的 延遲時間而被保持直至另一 I /〇形態接替控制爲也。依 據I / 0狀態# 1 ,僅有L E D 1被導通0 . 5秒《該環 路過程自腳4至腳8被重複直至腳1或腳2接收〜合格的 觸發訊號。應當注意的是:在I / ◦狀態# 1至I /〇狀 15 本纸張尺度適用中國國家標準(CNS)A.l規格⑵0 X 297公釐) --- - - - - - - ----發---— III ^ « 1 I I I I I I I-i^^ (請先閱讀背面之沭意事頊再瑱窵本寅〕 A7 Λ207 83 ______D7 . _ 五、發明說明(β ) - 態# 6的環路過程期間,任何由腳1接收的合格訊號指向 事件# 2 ( 1 2 4 ),然後爲在I / 〇狀態# 7與I /0 狀態# 8之間依次切換。三個由標號1 1 2指示的交替式 L E D在某一時刻導通,直至另一合格的訊號由腳1或腳 2接收而停止。應當注意的是:當一上升緣訊號在I /〇 狀態# 1至I / 0狀態# 8期間由腳2接收時,由標號1 2 5之行表示的事件# 3將被執行,如以子事件1 2 7所 指者,自動作狀態返回I / 0狀態# 0的待機模式。 該程式化方法的架構提供一種內建結構的方法,其適 用於未受微處理器架構之任何結構程式化槪念或理解以系 統化程式設計一應用軟體之程式設計員。該程式化過程可 以一易於學習、簡單構成且不含任何需遵循的複雜設計規 則之流程圖起始。實際的程式化過程係涉及依據所建立的 流程圖塡入由兩表組成的規格。其中並無二進位或十六進 位數需運算,亦無須知曉記憶體映射之I / 0槪念,無須 憂慮記憶體溢流或其它類型的限制條件,無須注意進入點 或程序計數器,亦無須記住任何指令集。除此之外,免除 了通常包含逐行表列之指令碼與一或多數操作元的指令集 。該程式化方法對該等易被指令集(如〃 L ◦ A D R 1 ,64H"或"JUMP LINE 4FFH")混淆 的一般使用者而言係爲非常友善的。更重要地,該簡單的 流程圖之結構被直接整合到實際的程式化過程中,塡入圖 表之特性爲提供一·程式流程之淸晰易辨的結構°不同I / 〇形態中的各1 / 0端之狀態係完善地組織,並淸晰地羅 16 本纸張尺度適用中國國家標準(CNS)A4規格(2】0 X 297公釐) (請先閱讀背面之注意事項再填寫本頁)Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative K 42 0783 A7 B7 V. Description of the Invention ("), Chart 1 2 0 »Labeling each I / 〇 form and event with a meaningful name can replace the digital I / 〇 form With events. Similarly, each I / 0 end is named to facilitate the stylization process. In the chart 100, 'pin 1 is named as the trigger trigger pin and is marked with " TG ,, and pin 2 is the "cut-off end" to stop the flashing process. Pins 3 to 8 are marked as LED 1 to LED 6, to indicate that these pins are connected to LED 1 to LED 6. I / 〇 state # 〇 is marked as indicated by the number 1 〇 2 standby mode 〃 = I / 〇 state # 1 is marked as the number 1 0 The "LED 1 〇 N (on)" shown in 1 is indicated by the name 〃 ALT 1 如 as indicated by reference numeral 1 0 1 to indicate that the first alternating LED is lit. Form. I / 0 state # 8 is marked with the name as shown by the number 1 1 1 〃 ALT 2 〃 to indicate that the second alternating LED is lit. At power-on, ί / ◦state # 0 is set to Factory / ◦ form of power-on action. Only pin 1 can detect a qualified signal of a rising edge. All other pins are in a high-impedance state. As indicated by code number 107, a pass is received on pin 1. When the signal is triggered, event # 1 (1 2 1) is executed, which is indicated by the sub-event 1 2 2 'that is, the initial / 0 state of the action It switches to I / 〇 state # 1; and therefore gradually switches to I / 0 state # 6. Each I / 0 pattern is maintained by a delay time of 0.5 〃 until another I / 〇 pattern takes over control as Also. According to I / 0 state # 1, only LED 1 is turned on for 0.5 seconds. The loop process is repeated from pin 4 to pin 8 until pin 1 or pin 2 receives a qualified trigger signal. It should be noted that : In I / ◦ State # 1 to I / 〇 State 15 This paper size applies Chinese National Standard (CNS) Al specification ⑵0 X 297 mm) ------------- hair --- — III ^ «1 IIIIII Ii ^^ (please read the intentions on the back first, and then the original version) A7 Λ207 83 ______D7. _ 5. Description of the invention (β)-State # 6 The qualified signal received by pin 1 points to event # 2 (1 2 4), and then switches between I / 〇 state # 7 and I / 0 state # 8 in turn. The three alternating LEDs indicated by the number 1 1 2 are in Turn on at a certain time until another qualified signal is stopped by foot 1 or foot 2. It should be noted that when a rising edge signal is between I / 〇 state # 1 to I / 0 state # 8 Receiving the foot 2, represented by reference numeral event # 125 of row 3 will be executed, such as sub-event 1 2 7 by means, for automatically returns the status I / 0 # 0 state of a standby mode. The framework of the stylized method provides a built-in method that is suitable for programmers who program or program an application software without any programming or understanding of the structure of the microprocessor architecture. The stylization process can begin with a flowchart that is easy to learn, simple to construct, and does not include any complex design rules to follow. The actual stylization process involves entering specifications consisting of two tables according to the established flowchart. There are no binary or hexadecimal digits to calculate, nor do you need to know the memory mapping I / 0 concept, no need to worry about memory overflow or other types of restrictions, no need to pay attention to entry points or program counters, and no need to remember Live any instruction set. In addition, it eliminates the instruction set that usually contains a row-by-row instruction code and one or more operands. This stylized method is very friendly to the average user who is easily confused by the instruction set (such as 〃 L ◦ A D R 1, 64H " or " JUMP LINE 4FFH "). More importantly, the structure of this simple flowchart is directly integrated into the actual stylization process, and the characteristics of the input chart are to provide a clear and easy-to-understand structure of the program flow ° 1 in each of the different I / 〇 patterns The status of the / 0 end is well organized, and it is clear that 16 paper sizes are applicable to China National Standard (CNS) A4 (2) 0 X 297 mm. (Please read the precautions on the back before filling out this page )

I 經濟部智慧財產局員工消費合作社印製I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

-------I -------------------------I 4 2 0 7 8 3 ‘ λ; B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(π) 列在一起,以利於邏輯流程的追縱。通常’完整的程式可 被列在一有助於普逋人掌握整個程式圖的單頁紙上。 應當注意的是,本發明之簡單的程式化方法可施加至 以內含程式之微處理器爲基礎的控制裝置中’藉著設計一 轉換程式’透過以微處理器爲基礎之控制裝置將兩表的程 式化資料轉換成其他程式語言’該其他語言可爲機器語言 、組合語言、巨集指令或諸如BASIC等之高階語言。 再進一步的程式改良爲’審閱已經轉換之程式’去除 重覆部份以節省所佔用之記億體空間’或是加進補充該轉 換語言所編寫之額外程式片段° 由前所述,可以知道該程式化方法的較佳實施例已在 此揭示,而有助於一般人將控制裝置作系統化之程式化。 或者,前述程式編排之事件可包含應用其他語.曰寫成 之子事件。此安排充份利用了系統所谷許之其他fe式語E3 ,並同時"維持了本發明之友善的軟體結構’本發明之簡單 程式編排與其他語言程式段落之相容性’使其成爲一種適 用於I / 0結構有關程式的理想編排方法。 當本發明之簡易程式方法被轉換爲組合語言時,第一 圖之圖表1 〇中的每--I /◦接腳之狀態係被轉換爲用組 合語言寫成之I / 〇程式,無論其狀態有否改變。假若一 微處理器係同於圖表1 0的形式,而其腳1至4僅限於輸 入,腳5至8僅限於輸出,則圖表1 0可以被一分爲二。 第一個分出來的圖表說明輸入端1至4,第二個分出來之 圖表說明輸出端5至8。此一改良將使轉換(translation) III—------— — -鞋--Jill — 訂11111! ^^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規恪(2i0 X 297公餐) A7 420783 ____ΒΓ___' 五、發明說明(4) (請先閱讀背面之注意事項再填寫本頁) 程式簡單化及節省有關程式所耗用之記憶體空間。與揭示 的程式化方法緊密相聯的硬體設計之一種較佳實施例係說 明於第五圖中。爲了便於描述該硬體實施例及與程式化方 法的關係,採用以說明程式化方法陳述的可程式化控制裝 置之規格。可以理解的是,本發明的涵蓋範疇與應用並不 限於本說明書。輸入/輸出電路1 4 4包含如程式化方法 應用實例中所界定的8個端點1 4 5 ;該控制電路供形成 各端點的狀態;當端點界定爲一輸出端時,驅動電路爲驅 動一訊號,又鑑別電路係於該端點被界定爲一輸入端時則 用以檢測一觸發訊號= 經濟部智慧財產局員工消費合作社印則衣 該輸入/輸出電路1 4 4自I / 0形態記憶體(I / 〇狀態記憶體)1 3 2接收控制訊號,以便將該I /◦端 1 4 5界定爲1 6個最大可能的狀態之一.者。I /0形態 記憶體包含1 6頁的記憶體,各頁記憶體代表--含有規劃 8個I / 0端點1 4 5之各者所需的資料之I / ◦形態。 在控制裝置開機時,啓動電路1 3 1致動1 6頁I / 〇形 態記憶體1 3 2之一者爲預設的I / 0形態或動作的I / 〇形態,且該記億體頁的資料被送入輸入/輸出電路1 4 4以規劃其I / 0端點= 收到在一合格的觸發訊號時,自I / 0狀態記憶體1 3 2獲得之對應事件位址訊息被送到事件尋址電路1 4 7 。該對應的事件資料記憶體1 4 9之起始位址爲於位址匯 流排1 4 8處設定,且該事件爲在事件執行電路1 3 8之 控制時而執行。該事件執行電路1 3 8將分析對應事件資 18 本紙張尺度適用中國國家標準(CNS)A4規格<210 x 297公釐) Λ7 42 07 B3 -----Bi------ 五、發明說明(〇) 、 料記憶體1 4 9中所含有的該事件與子事件訊息’並相應 地作出反應。一.產生聲音的子事件將致動位於該事件執行 電路中的聲音重製電路。所獲的音頻訊號係產生作爲·輪出 訊號1 3 5,透過訊號路徑1 4 1與交替式輸出端1 4 0 。或者,諸如6 Η ζ脈衝序列的輸出訊號可如"程式化( Ρ ) 〃 I / 0形態碼所界定者而被產生。此脈衝序列係傳 送通過I / 0端1 4 5之一者與訊號路徑1 3 9。當一子 事件需要起動諸如第.一圖中之子事件2 4的另一事件之操 作時,該事件執行電路將訊息介面至事件尋址電路1 4 7 ,且相應地起動新的事件。 當一子事件需要操作以致動如第一圖之子事件2 2的 另一輸入/輸出形態時f該事件執行電路將訊息介面至I / 0狀態尋址電路1 3 4,以透過控制路徑1 3 3致動另 -一頁的I / 〇狀態記憶體1 3 2。 ^第六圖揭示了第五圖中所述輸入/輸出電路功能方塊 1 4 4之詳細電路圖。電路1 7 2說明端點1的輸入/輸 出電路。具有七個相同電路1 7 3至1 7 4分別對應於如 實施例規格所界定的端點2至端點8。該輸入/輸出電路 之各端自該輸入/輸出形態記憶體1 3 1接收一個三位元 碼1 5 1 ’以界定該端點的形態。該三位元碼將被解碼, 以由3至8線解碼器1 5 7來選擇8種可能輸入/輸出狀 態1 5 8的其中之一者。 鑑別電路1 6 2被設計爲響應於由〃 r 〃、” F * ' "1 〃或〃 0 〃輸入形態碼所界定的特徵訊號。當該端點 19 本紙張尺度適用47國固家標準(CNS)/U規烙(210 X 297公釐) --------^-------訂---------線 <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印*'1衣 Λ7 4207^-3 B7 _ ------~-~~' "" ! 玉、發明說明(π ) - 爲由輸入形態碼〃 R 〃 、〃 F 〃 、〃 1 〃或"0 〃之一·者 而界定爲一輸入端時,一致能線1 6 0對應於選出之輸入 形態,致動該鑑別電路1 6 2對應部份以監測由端點# 1 7 1接收到的訊號。倘一合格的觸發訊號被測得’該鑑別 電路致能線1 7 0允許對應的事件位址指標碼透過邏輯電 路1 5 6到第五圖的事件尋址電路1 4 7。該自第五圖的 I / ◦形態記億體1 3 1獲得的事件位址指標碼1 5 2爲 一個五位元碼,以定址如實施例裝置之設計規格所界定的 3 2個不同事件。 倘該端由〃 Η 〃 、〃 L 〃 、或〃 Ρ 〃碼而界定爲一輸 出端,除非存在一需要該端同時作爲一輸入端與一輸出端 的特殊用途設計時,該鑑別電路通常係禁能。該輸出驅動 器1 6 1依據控制訊號1 5 9提供一適當驅動的輸出訊號 到該端點# 1 7 1。倘該輸出訊號爲--除了〃 Η 〃或〃 L 〃電位外的波形訊號,諸如在設計規格中所界定的6 Η ζ 脈衝,需要一輸出訊號源以提供該波形訊號透過端接腳被 傳送。在實例中,一6 Η ζ的訊號係來自於事作執行電路 1 3 8或一獨立的振盪電路。當〃 Ρ 〃碼被選出時,該訊 號被導至端點# 1 7 1。應當注意的是,除了第五圖之替 代端1 4 0,該設計使得一音頻訊號亦可由輸入/輸出端 之任一者而產生。 倘該端被界定成一輸入線,輸出驅動器電路通常係禁 能。倘該端以一由符號〃 X 〃標示的可忽略狀態或高阻抗 狀態,該鑑別電路與該輸出驅動器電路均係禁能=爲了降 20 本紙張尺度適用中®國家標準(CNS)A4規格297公釐) (請先閱讀背面之注意事項再填寫本頁) --------訂---------線— 經濟邡智慧財產局員工消費合作社印^^ 42 0783 , Α7 Β7 經濟部智慧財產局員工消費合作社印則^ 五、發明說明(ο) ' 低控制裝置的成本’.一牲端點可被設疋储爲輸入端’以菌口 省輸出驅動器電路的成本;而一些端點可被設定爲單純的 輸出端,以節省對應之鑑別電路的成本。 應當注意的是’所設定的8個ί / ◦形態爲示範性’ 任何特定功能的鑑別電路與輸出訊5虎產生器可被加入’以 增強控制裝置的能力。例如’在控制裝置作爲一可程式化 測試裝置而被使用以用於電話產品之測試的情況下’一D T M F音調的檢測可被加入而作爲一鑑別電路’頻率掃 描訊號可產生作爲一輸出訊號。 現請參閱第七圖,其顯示第五圖之輸入/輸出形態記 憶體1 3 2與I / 〇尋址電路1 3 4之一較佳實施例。画己 憶體1 84包含用以定義I/O狀態#0之.8個I/O端 點所需的一頁資料。此記憶體頁包含八個位元組的資料以 定義八個端點。8 M F音·調的檢測可作爲·-鑑別電路被加 入'且在控制裝置作爲-可程式化測試裝置。表示該八個 I /0構成組合的各資料位元組之起始的三位元係界定一 端點之I /0型態,並經資料匯流排1 9 2連接到第六圖 中的3至8線解碼器1 5 7。最後的五位元代表3 2項事 件的起始位址。該五位元資料經資料匯流排1 9 2被連接 到到第六圖的邏輯電路1 5 6,係當一合格的輸入觸發被 接收到時傳送到事件尋址電路。由於該三位元資料與該五 位元資料係成對地工作,其更便於成爲如由較佳實施例所 述同一字元之部分,或被安排在不同記憶體區塊中,以藉 由類似的操作原理而存取。 {請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中固因家標準(CNS)A4規格⑵0 X的7公发) 420733 p A7 B? 經濟部智慧財產局員工消費合作社印製 五、發明說明(》) 倘一 I / ◦端被定義爲一輸出端,該五位元資料的內 容係與事件尋址電路無關。此情況下,該五位元資料可用 於進一步界定輸出訊號的輸出特性,諸如比率因子以調整 輸出訊號的振幅°在另一實施例中’該起始的三位元資料 可定義以界定出一輸出旗標與七個輸入形態。當該輸出旗 標被測得時,剩下的五位元資料用以設定那一類型的輸出 訊號將被產生。此配置有效地擴充了輸入/輸出形態的數 目,以由8位元格式所定址,而並不進一步增加記憶體大 小,但需要更多的硬體以對記憶體的前三位元解碼,並當 輸出旗標被測得時,以記憶體的後五位元做爲控制。 實施例中之標號1 8 0包含1 6頁的I / 0形態記憶 體,以代表1 6個不同的可程式化I / 0形態。僅有一 I / 0形態在某一時刻作爲動作I / 0形態時被設定。如前 所述,其可方便地擷取I / 0狀態# 0作爲啓動時預設之 I / ◦形態。第五圖的I / ◦狀態尋址電路1 3 4可由第 七圖的4至1 6線解碼器1 8 2或一 1 6位元的閂鎖器據 以表示。當事件執行電路接收到一新的動作I /◦形態位 址,該訊息被送入其後解碼位址的解碼器1 8 2,並使得 1 6頁記憶體中的一頁成爲動作的I /〇形態記憶體。該 記憶體頁其後5載入該輸入/輸出電路中,以規劃各I / 0端的形態。 第八圖說明事件資料記憶體、事件執行電路與有關的 尋址電路之一實施例。五位元的事件指標2 〇 5被送入— 5至3 2線位址解碼器中,然後選取儲存在查詢表3 1 2 22 (請先閱讀背面之注音?事項再填寫本頁) Ϊ纸張尺度適用中因國家標準(CNSM4规格⑵0公餐) -------訂---------線!----------------------- 經濟部智慧財產局員工消費合作社印^f 42 07 83 A? _____B7____ _____ 五、發明說明〇/ ) 、 中的3 2項事件起始位址之一者。各事件起始位址係用以 界定一位於事件資料記億體2 1 3中的一事件的起始點° 該起始位址被載入事件位址計數器2 1 1中,並起始事件 執行電路2 0 2,其依據自事件資料記憶體2 1 3獲得的 資料而產生輸出訊號。事件執行電路2 0 2依照控制裝置 之需求可由各種習知電路組成。在一語音合成控制器的實 例中,事件執行電路包含有一般語音合成晶片所需的硬體 電路,如P C Μ解碼器,D / A轉換器’而儲存在事件資 料記憶體中的資料則爲編碼的/壓縮的聲音資料與有關的 時序資料。事件執行電路的另一實施例可由D τ M F音調 產生器、音律產生器與爲控制裝置之特定應用所需的任何 其它訊號操縱或產生電路所構成。在這些情況中’事件資 料記憶體儲存描述欲被產生訊號之資料。由事件執行電路 產生的輸出訊號被耦接到交替式輸出端點2 0 4或耦接到 第六圖的輸出驅動器1 6 1上" 倘事件資料記憶體包含指向如第一圖之子事件2 4所 示而執行另一目標事件之子事件時,則該目標事件的位址 爲由事件執行電路2 0 2經途徑2 0 9被載入至位址計數 器2 1 1中,以開始執行目標事件。倘事件記憶體包含一 指向由第一圖之子事件2 2所示者而致動另一輸入/輸出 形態的子事件時,則4位元的輸入/輸出形態尋址訊號經 途徑2 0 1被送到第七圖的位址解碼器1 8 2 1以致動所 欲的輸入/輸出形態記憶體頁。 該5至3 2線事件位址解碼器2 1 0與事件位址查詢 23 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度通用_國國家標準(CNSM.i規tM210>=297公釐) 經濟部智慧財產局員工消費合作社印製 4207 83 _ A7 _____ B7 ___五、發明說明(^) 表2 1 2可由含五位元位址與〃 Q 〃位元資料的另一記憶 體取代,其中該"Q 〃位元表示通常大於5位元的事件資 料記億體之位址長度。當電路在實際的積體電路製造中實 施時,線解碼器用以節省記億體空間與追蹤路線負荷。類 似地,第六圖的3至8線解碼器1 5 7可藉由使用一 8位 元記憶體以直接地定義I /〇端之下而可免除;且第七圖 的4至1 6線解碼器可藉由一 1 6位元記億體或一 1 6位 元的移位暫存器取代,據以選擇1 6頁I /〇形態記億體 之一者。 在事件執行電路的最簡實施例中,一事件之事件資料 記憶體2 1 3可爲一單一字元的記憶體資料’以設定哪個 事件執行電路的硬體產生器將被導通’並設定後續事件的 位址。在此情況下,事件位址計數器3 0 1與經由途徑2 0 8增量該計數器的時脈電路非爲必需的。在語音合成器 晶片的例子中,需要一時脈逐步地讀取該編碼訊號取樣, 並控制D / A轉換器。在一更爲複雜的實施例中,事件執 行電路2 0 2可包含一微處理器型結構。儘管整個硬體的 成本並不因此降低很多 '但本發明的實施例提供對輸入觸 發的即時響應效果。除此之外,本發明支援微處理器並使 其免除對I / 〇端之循環詢問’而使整個響應時間進一步 改善。更重要地,該結構有效地支援程式設計師一創新且 具使用者友善性的程式化方法。 在大規模生產中’第五圖至第八圖所示的實施例將被 製造於一積體電路(1 c )中。需要一簡單的解碼過程, 24 ^-------訂--------- (請先間讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(21CU297公餐) 經濟部智慧財產局員工消費合作社印製 420783 、‘ Λ7 Β7 五、發明說明(ο) . 以便將應用程式的程式化資料以如第四Β圖的圖表1 〇 〇 與圖表1 2 0轉換爲二進位資料,以儲存在輸入/輸出形 態記憶體1 3 2、第五圖的事件資料記憶體1 4 9與第八 圖的查詢表2 1 2中。遵循製造一積體電路的標準製程, 此等二進位的資料被首先轉換爲一光罩,且所得到的光罩 係透過一般積體電路製造製程用來製造積體電路。通常在 大規模生產中,輸入/輸出形態記憶體1 3 2 '第五圖的 事件資料記憶體1 4 9與第八圖的查詢表2 1 2被製造成 唯讀記憶體(R ◦ Μ )。在程式發展過程的情況中,包含 一·讀寫(隨機存取)記憶體(R A Μ )、可抹除程式化唯 讀記憶體(E P R 0 Μ與E E P R Ο Μ )、或一次可程式 化唯讀記憶體(0 Τ Ρ )等之特定積體電路可用以取代上 述唯讀記憶體,以對程序進行試驗,並提供一展示樣本而 不需經歷整個積體電路製造過程的昂貴成本與時間。該轉 換後的程式資料隨後透過一外部資料源被下載入此等記憶 體區域中。 爲了增強控制裝置的可程式化特徵,一有限量的讀寫 記憶體(R A Μ )或暫存器被加入上述可程式化記憶體區 域是需要的。除了包含加入於事件查詢表2 1 2之兩讀寫 暫存器外,第九圖基本上與第八圖之實施例完全相同。該 第一暫存器被稱爲"計時器(Τ I Μ E R )"暫存器,於 一計時器計數結束時指定須被執行的事件。致動"計時器 暫存器(TIMER REGISTER)" 230的選 通線2 3 4由位於事件執行電路2 0 2中的計時器計數器 25 本紙張尺度適用中因國家標準(CNSM4規格(2】0 X 297公釐) -------訂---------線 (請先閲讀背面之注意事項再填寫本頁) A7 420783 __B7_______ 五、發明說明(W) 、 取得時間訊號。當對事件表予以程式化時’ 一子事件可係 以第十A圖所示之格式被指定,以致動計時器計數器。 依據事件# 1 ( E V E N 丁 # 1 ) 2 9 1的程式化, 與先前第四B圖之圖表1 2 0中的時間格式〃 DELAY 〇.5 SEC"比較時,子事件 2 9 3,TIMER 6 SEC:EVENT#3" 爲相同的操作,除了 一計時器與隨後之的子事件2 9 4平 行運作及當6秒的時序周期結束時起動事件# 3 ( E V E N T # 3 )的執行之外。亦可在計時器的運作期間內,重 新啓動該計時器或停止計時操作。該重新啓動可僅由重新 尋址 〃丁 I Μ E R t S E C : E V E N T # K 〃子事件 而達成。欲停止計時器計數器,則需另一標示〃計時器關 閉(Τ I Μ E R 0 F F ) 〃的子事件= 讀寫暫存器2 3 1使得事件可被間接地定址。此特徵 允許一事件的目標位址不時地依據程式流程需求而改變。 當程式化事件表時,一子事件可透過第十Β圖中所示的方 式被指定,以致動一事件的間接位址。當一上升緣信號首 先依據碼符號3 0 5由腳1 ( 3 0 4 )接收時,事件# 1 (Ε V Ε Ν Τ # 1 ) 3 1 1界定〃可變事件'的位址。每 當T G 1被觸發時,事件# 4 ( Ε V Ε Ν Τ # 4 +) 3 1 7 將被執行。事件# 4 ( Ε V Ε Ν Τ # 4 )首先關閉所有觸 發接腳,並隨後播放一喇叭聲音。然後,播放依據〃可變 事件〃位址的另一聲音。當可變事件被界定以如事件# 1 (Ε V Ε Ν Τ # 1 )般相同於事件 # 2 ( Ε V Ε Ν Τ # 2 )時,一段時期的警報聲音隨後產生。可看出的是,事件 26 本紙張尺度適用中國國家標準(CNS)A.1規格(210 X 297公釐) ----—--I ! 11 I ----!'-訂- ----I I I I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 經濟部智慧財產局員工消費合作社印製 Λ2 0 7Β3 - a7 B7 -------' -----—--- 五、發明說明(w) . # 2 ( E V E N T # 2 )再次界定"可變事件〃爲事件# 3 (EVENT#3) 316,故而下一次當腳1接收〜 合格的觸發訊號且事件#4 (EVENT#4)被執行時 ,該喇叭聲音將如事件# 3 ( E V E iN T # 3 ) 3 i 6所 指,繼之以一引擎開動聲音表示。 每當可變事件# ( E V E N T # V A R )=事件# κ (E V E N T # K )的格式被接收,事件# K ( E V E N T # K )的位址被置於第九圖之〃可變事件暫存器〃 2 3 1。當可變事件(E V E N T # V A R )稍後被定址時, 則由〃可變事件暫存器〃 2 3 1之內容所定址的事件將執 行。 該簡單的單頁程式有利於程式化過程的除錯處理。第 十一圖描述一除錯工具的較佳實施例,其中整個程式被顯 示於一視訊螢幕上’且程式流程被模擬以促進交談式除錯 過程。該動作中的I / 0形態與執行中的事件始終係以高 亮度點亮在螢幕上。該觸發腳按鈕345、346與鑑別 訊號按鈕3 4 1、3 4 2、3 4 3與3 4 4係針對程式設 計師而設計用於模擬觸發一輸入腳。當控制裝置藉由觸發 々起動〃按鈕3 3 8而被起動時’輸入/輸出狀態# 0 ( I / 0 State #0) 321將最亮。腳1隨後藉由觸發P 1按鈕345與上升緣按鈕341而被觸發。事件#1( E V E N T # 1 )的子事件隨後依據邏輯流程被逐一以高 亮度點亮,且圖表3 2 0的高亮度區域依據一 I / ◦形態 被設定爲動作中而變化^假定子事件3 3 2被執行’ I / 27 壯 -------訂---------線 {請先閱讀背面之注意事項再填寫本頁) 本紙張足度適用中國國家標準規格(2〗0 X 297公釐) 經濟部智慧財產局員工消費合作杜印製 42 07 83 * at ___B7___五、發明說明(4) 、 0狀態4 ( I / 〇 State # 4 ) 3 2 3隨後成爲動作狀態 並以高亮度點亮。此時當腳1被觸發時,程式流程將被中 斷且事件# 2 ( E V E N T # 2 )隨後被執行。一自動執 行按鈕3 3 6使得模擬器可藉由自動逐一觸發鑑別的輸入 腳而自動地嘗試所有可能的程式執行組合。任何開路程式 流程或閉路者在自動執行過程完成後被逐一羅列。程式設 計師隨後可檢查開路程式流程或閉路者是否爲所欲求者。 該模擬器除錯工具透過一具外部應用電路之發展系統 的介面電路,藉由與8個I / 0接腳連接,而可被簡便地 修正爲-即時電路模擬器。類似於程式化方法,由於邏輯 流程係明確地高亮度顯示於螢幕上,且以實際應用中的類 似方式被逐一追蹤,故該除錯工具的較佳實施例係對一個 程式設計師爲極具親和力的除錯工具。除此之外,使用者 無須學習複雑的模擬器或電路模擬器控制指令。 由於較佳實施例之不尋常的記憶體結構,該輸入/輸 出形態記憶體係最好與主要的事件記憶體分離,以便當設 計實際的積體電路之佈局時,降低內連線路追縱的負荷。 輸入/輸出形態記憶體的位置最好依據可定址的輸入/輸 出端之數目而被分爲不同的小記憶體方塊。例如,如第七 圖所示,每頁的第一位元組記憶體係與端點1有關。如第 六圖所示,最好係將1 6頁(1 6個I / 0形態)1 8 4 至1 8 8的所有第一位元組均組合在一起,並定位該記憶 體鄰接端點1或該相關的輸出驅動器1 6 1與鑑別電路1 6 2。第十二圖所示之3 8 3位置代表了積體電路實體3 28 (請先閱讀背面之沒意事項再填寫本頁) 本纸張尺度適用中國國家標準(CNTS)A4規格(210x297公釐) A7 420783 ______B7 五、發明說明(^ ) 8 0中之端點1接腳方塊。3 8 2之位置代表第六圖有關 驅動器161及鑑別電路162。381之位置代表了第 七圖中1 8 4至1 86之1 6頁I/O組合形態中之第一 個八位字元。3 8 6之位置代表主要事件記憶體,該位置 與各有關接腳方塊相鄰之I / ◦形態記憶體是分離的。 此配置降低了積體電路的晶片尺寸,並因此爲製造商 與使用者提供成本優勢。此種經濟的積體電路結構可修正 爲--基於微處理器的控制裝置。該微處理器可修正爲包含 專用以界定I / 0端形態的記憶體附加方塊。 由前所述,可以理解的是,控制裝置的硬體實施例在 本文已被充份地揭示,使電子電路工程師可發展一種低成 本的可程式裝置,以有效地與所發明之使用者友善程式化 方法互動。 本文所描述的本發明較佳實施例係爲示範性,大量的 變更、規格變化與電路重新配置均可被預見爲達成一等效 的結果。例如,輸入/輸出端之定義不限於積體電路之接 腳,更可包含位於同 積體電路體內另一功能裝置之“內 置”的輸入/輸出端,如顯示於第五圖之事件執行電路1 3 8可代表一時間計數器,其溢流訊號1 3 9觸動輸入/ 輸出電路1 4 4之某一"內置”輸入端。所有上述變化均 意圖被涵蓋在附加的申請專利範圍之範疇中。 29 本紙張K度適用中阀國家標準(CNS)A4規格(210 X 297公釐) ----3L -------訂----------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製------- I ------------------------- I 4 2 0 7 8 3 'λ; B7 Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by Consumer Cooperatives 5. The invention description (π) is listed together to facilitate the pursuit of logical processes. Usually the complete program can be listed on a single sheet of paper that helps Puer people master the entire program map. It should be noted that the simple programming method of the present invention can be applied to a microprocessor-based control device based on a program containing a program by designing a conversion program. The stylized data of the table is converted into other programming languages. The other languages can be machine languages, combined languages, macro instructions, or higher-level languages such as BASIC. Further program improvement is to "review the converted program" to remove the duplicates to save the memory space occupied by it "or to add additional program fragments written in addition to the conversion language ° As mentioned above, we can know The preferred embodiment of the stylized method has been disclosed here, which helps the average person to systematically program the control device. Alternatively, the programmed events may include child events written in other languages. This arrangement makes full use of the other fe language E3 that the system allows, and at the same time " maintains the friendly software structure of the present invention, 'compatibility of the simple programming of the present invention with other language program paragraphs', making it a An ideal programming method for programs related to I / 0 structure. When the simple program method of the present invention is converted into a combined language, the state of each --I / ◦ pin in the chart 1 of the first figure is converted into an I / 〇 program written in the combined language, regardless of its state. Has it changed. If a microprocessor is in the same form as in Figure 10, and its pins 1 to 4 are limited to input and pins 5 to 8 are limited to output, then chart 10 can be divided into two. The first divided chart shows the input terminals 1 to 4, and the second divided chart shows the output terminals 5 to 8. This improvement will make translation III --------------Shoes-Jill-order 11111! ^^ (Please read the precautions on the back before filling this page) This paper size applies Chinese national standards (CNS) A4 regulations (2i0 X 297 meals) A7 420783 ____ ΒΓ ___ 'V. Description of the invention (4) (Please read the notes on the back before filling this page) Simplify the program and save the memory used by the program space. A preferred embodiment of the hardware design closely linked to the disclosed stylized method is illustrated in the fifth figure. In order to facilitate the description of the hardware embodiment and its relationship with the stylized method, the specifications of the programmable control device stated in the stylized method are adopted. It can be understood that the scope and application of the present invention are not limited to this specification. The input / output circuit 1 4 4 includes 8 end points 1 4 5 as defined in the application example of the stylized method; the control circuit is used to form the states of each end point; when the end point is defined as an output end, the driving circuit is A signal is driven and the identification circuit is used to detect a trigger signal when the endpoint is defined as an input = the input / output circuit of the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economy 1 4 4 from I / 0 The morphological memory (I / 〇 state memory) 1 2 2 receives the control signal in order to define the I / ◦ terminal 1 4 5 as one of the 16 largest possible states. I / 0 form The memory contains 16 pages of memory. Each page of memory represents-an I / ◦ form that contains the data needed to plan each of the 8 I / 0 endpoints 145. When the control device is turned on, the activation circuit 1 3 1 actuates one of 16 pages of I / 〇 shape memory 1 32, which is a preset I / 0 shape or an action I / 〇 shape, and the memory page The data is sent to the input / output circuit 1 4 4 to plan its I / 0 endpoint = when a qualified trigger signal is received, the corresponding event address information obtained from the I / 0 state memory 1 2 2 is sent To the event addressing circuit 1 4 7. The starting address of the corresponding event data memory 149 is set at the address bus 148, and the event is executed under the control of the event execution circuit 138. The event execution circuit 1 3 8 will analyze the corresponding event data. 18 This paper size applies the Chinese National Standard (CNS) A4 specification < 210 x 297 mm. Λ7 42 07 B3 ----- Bi ------ 5 The invention and the description (0), the event and the sub-event message contained in the material memory 149, and respond accordingly. 1. A sound-producing sub-event will activate a sound reproduction circuit located in the event execution circuit. The obtained audio signal is generated as a turn-out signal 1 3 5 through a signal path 1 4 1 and an alternate output terminal 1 4 0. Alternatively, an output signal such as a 6 Η ζ pulse sequence may be generated as defined by the " programmed (P) 〃 I / 0 pattern code. This pulse sequence is transmitted through one of the I / 0 terminals 1 4 5 and the signal path 1 3 9. When a sub-event needs to start another event such as sub-event 2 4 in the first figure, the event execution circuit interfaces the message to the event addressing circuit 1 4 7 and starts a new event accordingly. When a sub-event needs to be operated to actuate another input / output mode like sub-event 2 2 of the first figure, the event execution circuit interfaces the message to the I / 0 state addressing circuit 1 3 4 to pass the control path 1 3 3 Actuate another-one page of I / 〇 state memory 1 2 3. ^ Sixth figure shows a detailed circuit diagram of the input / output circuit function blocks 1 4 4 described in the fifth figure. Circuit 1 7 2 illustrates the input / output circuit of endpoint 1. Having seven identical circuits 1 7 3 to 1 7 4 respectively correspond to endpoints 2 to 8 as defined by the embodiment specifications. Each end of the input / output circuit receives a three-bit code 1 5 1 ′ from the input / output shape memory 1 3 1 to define the shape of the endpoint. The three-bit code will be decoded to select one of the 8 possible input / output states 1 5 8 by the 3 to 8-line decoder 1 5 7. The discriminating circuit 1 6 2 is designed to respond to the characteristic signal defined by 码 r 〃, “F * '" 1 〃 or 〃 0 〃 input form code. When this endpoint 19 this paper standard is applicable to 47 countries’ solid standards (CNS) / U gauge (210 X 297 mm) -------- ^ ------- Order --------- Wire < Please read the precautions on the back first (Fill in this page again) Seal of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * '1 衣 Λ7 4207 ^ -3 B7 _ ------ ~-~~' " "! Jade, invention description (π)- When defined as an input terminal by the input form code 〃 R 〃, 〃 F 〃, 〃 1 〃 or one of " 0 〃, the uniform energy line 1 6 0 corresponds to the selected input form, and the discrimination circuit is actuated. 1 6 2 Corresponding part to monitor the signal received by endpoint # 1 7 1. If a qualified trigger signal is detected, the identification circuit enable line 1 7 0 allows the corresponding event address indicator code to pass through the logic circuit 1 5 6 to the event addressing circuit of the fifth figure 1 4 7. The event address index code 1 5 2 obtained from the I / ◦ shape recorder body 1 3 1 of the fifth figure is a five-digit code. Addressing is as specified by the design specifications of the device of the embodiment Defined 3 2 different events. If the terminal is defined as an output terminal by 〃 Η 〃, 〃 L 〃, or Ρ P 〃 code, unless there is a special-purpose design that requires the terminal to be both an input terminal and an output terminal. At this time, the discriminating circuit is usually disabled. The output driver 16 1 provides an appropriately driven output signal to the terminal # 1 7 1 according to the control signal 1 59. If the output signal is-except 〃 Η 〃 or 〃 L 〃 waveform signals outside the potential, such as the 6 Η ζ pulse defined in the design specifications, require an output signal source to provide the waveform signal to be transmitted through the termination pin. In the example, a 6 Η ζ signal is From the job execution circuit 138 or an independent oscillating circuit. When the 〃 〃 code is selected, the signal is routed to the end point # 1 7 1. It should be noted that except for the alternative end 1 of the fifth figure 40. This design enables an audio signal to be generated by any one of the input / output terminals. If the terminal is defined as an input line, the output driver circuit is usually disabled. If the terminal is marked with a symbol 〃 X 〃 Negligible state or high Resistance status, the identification circuit and the output driver circuit are both disabled = In order to reduce 20 paper standards applicable in the National Standard (CNS) A4 specification 297 mm) (Please read the precautions on the back before filling this page)- ------- Order --------- line—Economic and Intellectual Property Bureau Staff Consumption Cooperative Association ^^ 42 0783, Α7 Β7 Intellectual Property Bureau Staff Consumption Cooperative Association Principle ^ V. Description of Invention (Ο) 'Low cost of control device'. An endpoint can be set as an input terminal to save the cost of the output driver circuit; and some endpoints can be set as simple output terminals to save the corresponding The cost of the identification circuit. It should be noted that ‘the 8 ί / ◦ patterns are set to be exemplary’ Any specific function of the discrimination circuit and output signal can be added ’to enhance the ability of the control device. For example, 'in the case where the control device is used as a programmable test device for testing of a telephone product', a D T M F tone detection can be added as a discrimination circuit 'and a frequency scanning signal can be generated as an output signal. Please refer to the seventh figure, which shows a preferred embodiment of the input / output memory bank 1 32 and the I / 0 addressing circuit 1 34 of the fifth figure. Drawing memory 1 84 contains one page of data needed to define I / O status # 0 to 8 I / O terminals. This memory page contains eight bytes of data to define eight endpoints. 8 M F tone detection can be added as a “-discrimination circuit” and as a programmable test device in the control device. The three digits representing the beginning of each data byte group of the eight I / 0 combinations define the I / 0 type of an endpoint, and are connected to 3 to 6 in the sixth figure via the data bus 1 9 2 8-line decoder 1 5 7. The last five bits represent the starting address of the 32 events. The five-bit data is connected to the logic circuit 156 of the sixth figure via the data bus 19 2 and is transmitted to the event addressing circuit when a qualified input trigger is received. Since the three-bit data and the five-bit data work in pairs, it is more convenient to be part of the same character as described in the preferred embodiment or to be arranged in different memory blocks so that Similar operating principles. {Please read the precautions on the back before filling in this page) This paper size is applicable to Zhongguinjia Standard (CNS) A4 specifications ⑵0 X 7 pubs) 420733 p A7 B? Printed by the Employees ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (") If an I / ◦ terminal is defined as an output terminal, the content of the five-bit data is independent of the event addressing circuit. In this case, the five-bit data can be used to further define the output characteristics of the output signal, such as a ratio factor to adjust the amplitude of the output signal. In another embodiment, 'the initial three-bit data can be defined to define a Output flags and seven input patterns. When the output flag is measured, the remaining five bits of data are used to set which type of output signal will be generated. This configuration effectively expands the number of input / output patterns to be addressed in an 8-bit format without further increasing the memory size, but requires more hardware to decode the first three bits of the memory, and When the output flag is measured, the last five bits of the memory are used as controls. The reference numeral 180 in the embodiment includes 16 pages of I / 0 pattern memory to represent 16 different programmable I / 0 patterns. Only one I / 0 pattern is set at a certain time as the action I / 0 pattern. As mentioned before, it can easily capture the I / 0 status # 0 as the default I / ◦ shape at startup. The I / ◦ state addressing circuit 1 3 4 in the fifth figure can be represented by the latches of the 4 to 16 line decoders 1 8 2 or the 16 bit in the seventh figure. When the event execution circuit receives a new action I / ◦ form address, the message is sent to the decoder 1 8 2 which decodes the address later, and makes a page in 16 pages of memory the action I / 〇 Morphological memory. The next 5 pages of the memory page are loaded into the input / output circuit to plan the shape of each I / 0 terminal. The eighth figure illustrates one embodiment of an event data memory, an event execution circuit, and related addressing circuits. Five-digit event indicator 2 0 5 is sent to — 5 to 3 2 line address decoder, and then selected and stored in the query form 3 1 2 22 (Please read the note on the back? Matters before filling out this page) Ϊpaper Zhang scale is applicable to national standards (CNSM4 specification ⑵0 meals) ------- Order --------- line! ----------------------- Seal of Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ f 42 07 83 A? _____B7____ _____ V. Description of the invention 〇 /), Medium One of 3 2 event start addresses. The start address of each event is used to define the start point of an event located in the event data record 2 1 3 ° The start address is loaded into the event address counter 2 1 1 and the start event The execution circuit 2 0 2 generates an output signal according to the data obtained from the event data memory 2 1 3. The event execution circuit 202 may be composed of various conventional circuits according to the requirements of the control device. In an example of a speech synthesis controller, the event execution circuit includes the hardware circuits required for a general speech synthesis chip, such as a PC M decoder, a D / A converter, and the data stored in the event data memory is Encoded / compressed audio data and related timing data. Another embodiment of the event execution circuit may consist of a D τ M F tone generator, a rhythm generator, and any other signal manipulation or generation circuit required for the particular application of the control device. In these cases, the 'event data memory' stores data describing the signal to be generated. The output signal generated by the event execution circuit is coupled to the alternate output terminal 2 0 4 or to the output driver 1 6 1 of the sixth figure " if the event data memory contains a sub-event 2 as shown in the first figure When the sub-event of another target event is executed as shown in 4, the address of the target event is loaded into the address counter 2 1 1 by the event execution circuit 2 0 2 through the path 2 0 9 to start the execution of the target event. . If the event memory contains a sub-event that points to another input / output pattern that is triggered by the sub-event 2 2 of the first figure, the 4-bit input / output pattern addressing signal is routed through path 2 0 1 The address decoder 1 8 2 1 is sent to the seventh figure to actuate the desired input / output form memory page. The 5 to 3 2 line event address decoder 2 1 0 and event address query 23 (Please read the precautions on the back before filling out this page) This paper is universal _ National Standard (CNSM.i Regulation tM210 > = 297 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4207 83 _ A7 _____ B7 ___ V. Description of the invention (^) Table 2 1 2 Another memory containing a five-digit address and 〃 Q 〃 bit data The "Q" bit represents the address length of the event data record, which is usually larger than 5 bits. When the circuit is implemented in the actual integrated circuit manufacturing, the line decoder is used to save the memory space and track load. Similarly, the 3 to 8-line decoders 1 5 7 of the sixth figure can be eliminated by using an 8-bit memory to directly define the I / 0 side; and the 4 to 16 lines of the seventh figure The decoder can be replaced by a 16-bit memory register or a 16-bit shift register to select one of the 16-page I / 0 memory registers. In the simplest embodiment of the event execution circuit, the event data memory 2 1 3 of an event can be a single character of memory data 'to set which event execution circuit's hardware generator will be turned on' and set the subsequent The address of the event. In this case, the event address counter 3 0 1 and the clock circuit that increments the counter via path 2 0 8 are not necessary. In the example of a speech synthesizer chip, it is necessary to read the coded signal samples step by step and control the D / A converter. In a more complex embodiment, the event execution circuit 202 may include a microprocessor-type structure. Although the cost of the entire hardware is not reduced as a result ', embodiments of the present invention provide instant response to input triggers. In addition, the present invention supports the microprocessor and eliminates the need for circular interrogation of the I / O terminal, thereby further improving the overall response time. More importantly, the structure effectively supports programmers with an innovative and user-friendly stylized approach. In mass production, the embodiments shown in Figs. 5 to 8 will be manufactured in an integrated circuit (1c). Requires a simple decoding process, 24 ^ ------- Order --------- (Please read the precautions on the back before filling this page) This paper size applies to China National Standards (CNS) A4 specification (21CU297 public meal) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 420783, 'Λ7 Β7 V. Description of invention (ο). In order to program the application's stylized data as shown in Figure 4 of Figure 4B and 〇〇 Graph 1 2 0 is converted into binary data to be stored in the input / output shape memory 1 2 2 and the event data memory 1 4 9 of the fifth figure and the lookup table 2 12 of the 8th figure. Following the standard manufacturing process for manufacturing an integrated circuit, these binary data are first converted into a photomask, and the obtained photomask is used to manufacture the integrated circuit through a general integrated circuit manufacturing process. Usually in mass production, the input / output morphological memory 1 3 2 'event data memory 1 5 9 of the fifth figure and lookup table 2 1 2 of the eighth figure are manufactured as read-only memory (R ◦ Μ) . In the case of program development process, it includes: • Read / write (random access) memory (RA Μ), erasable programmable read-only memory (EPR 0 Μ and EEPR Ο Μ), or a programmable Specific integrated circuit such as read memory (TP) can be used to replace the above read-only memory to test the program and provide a demonstration sample without going through the expensive cost and time of the entire integrated circuit manufacturing process. The converted program data is then downloaded into these memory areas via an external data source. In order to enhance the programmable characteristics of the control device, it is necessary that a limited amount of read-write memory (RAM) or a register is added to the above-mentioned programmable memory area. The ninth figure is basically the same as the eighth figure except that it includes two read-write registers added to the event lookup table 2 12. The first register is called a " timer (TI MR) " register and specifies an event to be executed at the end of a timer count. Actuate the "timer register" (230) of the strobe line 2 3 4 by the timer counter located in the event execution circuit 2 0 2 25 This paper is applicable due to national standards (CNSM4 specifications (2 ] 0 X 297 mm) ------- Order --------- Line (Please read the notes on the back before filling this page) A7 420783 __B7_______ V. Description of the invention (W) Time signal. When the event table is stylized, a sub-event can be specified in the format shown in Figure 10A to activate the timer counter. According to the program of event # 1 (EVEN 丁 # 1) 2 9 1 When compared with the time format 〃 DELAY 〇.5 SEC " in the previous chart B of Figure 4B, sub-event 2 9 3, TIMER 6 SEC: EVENT # 3 " is the same operation, except for a timer In addition to running in parallel with subsequent sub-events 2 9 4 and starting the execution of event # 3 (EVENT # 3) when the 6-second sequence period ends. The timer can also be restarted during the operation period of the timer or Stop timing operation. This restart can only be done by readdressing I Μ ER t SEC: EVE NT # K 〃 The sub-event is reached. To stop the timer counter, another sign is required. 〃 The timer is off (TI ER 0 FF). The sub-event = read-write register 2 3 1 so that the event can be indirectly Addressing. This feature allows the target address of an event to be changed from time to time according to the needs of the program flow. When the event table is programmed, a sub-event can be designated in the manner shown in Figure 10B to trigger an event When a rising edge signal is first received by pin 1 (3 0 4) according to code symbol 3 0 5, event # 1 (Ε V Ε Ν Τ # 1) 3 1 1 defines a variable event. Address. Whenever TG 1 is triggered, event # 4 (Ε V Ε Ν Τ # 4 +) 3 1 7 will be executed. Event # 4 (Ε V Ε Ν Τ # 4) first closes all trigger pins, Then, a horn sound is played. Then, another sound according to the “variable event” address is played. When the variable event is defined to be the same as event # 1 (Ε V Ε Ν Τ # 1), Ε V Ε Ν Τ # 2), a period of time after the alarm sounds. It can be seen that the event 26 paper size applies National Standard (CNS) A.1 Specification (210 X 297 mm) -------- I! 11 I ----! '-Order- ---- IIII (Please read the notes on the back first (Fill in this page again) Consumption Cooperation between Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs and Du Duan Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ2 0 7Β3-a7 B7 2. Description of the invention (w). # 2 (EVENT # 2) is again defined " variable event〃 is event # 3 (EVENT # 3) 316, so next time when foot 1 receives ~ qualified trigger signal and event # 4 ( When EVENT # 4) is executed, the horn sound will be referred to as event # 3 (EVE iN T # 3) 3 i 6, followed by an engine start sound. Whenever the variable event # (EVENT # VAR) = event # κ (EVENT # K) format is received, the address of event # K (EVENT # K) is placed in the variable event register in Figure 9 〃 2 3 1. When the variable event (E V E N T # V A R) is later addressed, the event addressed by the contents of the “variable event register” 2 31 will be executed. The simple one-page program facilitates debugging of the stylization process. Figure 11 describes a preferred embodiment of a debugging tool in which the entire program is displayed on a video screen 'and the program flow is simulated to facilitate a conversational debugging process. The I / O pattern in this action and the event in execution are always lit on the screen with high brightness. The trigger pin buttons 345, 346 and the identification signal buttons 3 4 1, 3 4 2, 3 4 3, and 3 4 4 are designed for programmers to simulate an trigger input pin. When the control device is activated by triggering the 々Start〃 button 3 3 8 'input / output state # 0 (I / 0 State # 0) 321 will be the brightest. Pin 1 is then triggered by triggering the P 1 button 345 and the rising edge button 341. The sub-events of event # 1 (EVENT # 1) are then lighted up one by one in accordance with the logic flow, and the high-brightness area of chart 3 2 0 changes according to an I / ◦ form is set to be in action ^ Assume sub-event 3 3 2 was executed 'I / 27 Zhuang ------- Order --------- line {Please read the precautions on the back before filling this page) This paper is fully compliant with Chinese national standards ( 2〗 〖0 X 297 mm) Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs 42 07 83 * at ___B7___ V. Invention Description (4), 0 State 4 (I / 〇State # 4) 3 2 3 The operating state is illuminated with high brightness. At this time, when pin 1 is triggered, the program flow will be interrupted and event # 2 (E V E N T # 2) will be executed subsequently. An auto-execute button 3 3 6 enables the simulator to automatically try all possible program execution combinations by automatically triggering the input pins one by one. Any open-loop process or closed circuit will be listed one after the other by the automated process. The programmer can then check whether the open flow or closed circuit is what they want. This simulator debugging tool can be easily modified into a real-time circuit simulator through the interface circuit of a development system with an external application circuit by connecting with 8 I / 0 pins. Similar to the stylized method, since the logic flow is clearly highlighted on the screen and tracked one by one in a similar manner in practical applications, the preferred embodiment of this debugging tool is extremely useful for a programmer Affinity debugging tools. In addition, the user does not need to learn the complex simulator or circuit simulator control instructions. Due to the unusual memory structure of the preferred embodiment, the input / output morphological memory system is preferably separated from the main event memory in order to reduce the traceability of the interconnected circuits when designing the actual integrated circuit layout. load. The location of the input / output shape memory is preferably divided into different small memory blocks based on the number of addressable input / output terminals. For example, as shown in Figure 7, the first byte memory system of each page is related to endpoint 1. As shown in the sixth figure, it is best to combine all the first bytes of 16 pages (16 I / 0 patterns) 1 8 4 to 1 8 8 and locate the adjacent endpoints of the memory. 1 or the related output driver 1 6 1 and the discrimination circuit 1 6 2. The position 3 8 3 shown in the twelfth figure represents the integrated circuit entity 3 28 (please read the unintentional matter on the back before filling this page) This paper size applies the Chinese National Standard (CNTS) A4 specification (210x297 mm ) A7 420783 ______B7 V. The description of the invention (^) The terminal 1 pin block in 8 0. The position of 3 8 2 represents the driver 161 and the identification circuit 162 in the sixth figure. The position of 381 represents the first eight-bit character in the I / O combination of pages 1 8 4 to 1 86 of 16 in the seventh figure. . The location of 3 8 6 represents the main event memory. This location is separate from the I / ◦ shape memory adjacent to the relevant pin blocks. This configuration reduces the chip size of integrated circuits and therefore provides cost advantages for manufacturers and users. This economical integrated circuit structure can be modified into a microprocessor-based control device. The microprocessor can be modified to include an additional block of memory dedicated to define the I / O configuration. From the foregoing, it can be understood that the hardware embodiment of the control device has been fully disclosed herein, so that electronic circuit engineers can develop a low-cost programmable device to effectively be friendly with the user of the invention Stylized methods of interaction. The preferred embodiment of the present invention described herein is exemplary, and a large number of changes, specification changes, and circuit reconfigurations can be expected to achieve an equivalent result. For example, the definition of the input / output terminal is not limited to the pins of the integrated circuit, but can also include the "built-in" input / output terminal of another functional device in the same integrated circuit, such as the event execution circuit shown in the fifth figure 1 3 8 can represent a time counter whose overflow signal 1 3 9 touches one of the "built-in" input terminals of the input / output circuit 1 4 4. All the above changes are intended to be covered by the scope of additional patent applications 29 paper K degree is applicable to the national valve national standard (CNS) A4 specification (210 X 297 mm) ---- 3L ------- order ---------- line (please first (Read the notes on the back and fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

Claims (1)

420783 Α8 Β8 C8 DS 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 1 · 一種可程式化控制裝置,至少包含: K端,至少設定一第一端設爲一輸入端及一第二端設 爲一輸出端: 至少一鑑別電路機構,可響應於該第一輸入端接收的 特徵訊號; 一第一記憶體,儲存資料以界定一或多個事件,各個 事件分別具有一位於該第一記憶體中可尋址範圍內的對應 起始位址; 一(n + m )位元資料格式的第二記憶體,該m位元 資料係用以界定一端的型態,該η位元資料係用以當該端 被設爲一輸入端時界定該第一記憶體之事件起始位址; 一事件執行電路機構,用以在一第一事件執行時產生 至少一第一事件輸出訊號與一第二事件輸出訊號,該第一 事件輸出訊號被耦合到該輸出端,用於產生一輸出訊號; ' 一第一尋址電路機構,響應於該鑑別電路機構,致動 該事件執行機構以執行由該事件起始位址界定的該第一事 件;及 一第二尋址電路機構,響應於該第二事件輸出訊號, 以更新該第二記憶體的現在位址。 2 ·如申請專利範圍第1項所述之可程式化控制裝置 ,其中該事件執行電路機構產生一第三事件輸出訊號,中 斷該第一尋址電路機構,以致動一第二事件的位址並執行 其第二事件。 3 ·如申請專利範圍第1項所述之可程式化控制裝置 30 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度通用中國國家標準(CNS } Α4規格(210Χ297公釐) ABCD Λ 2 07 83 ^ 六、申請專利範圍 ’更包含一起動電路機構,藉以定義出該可程式化控制裝 置於起動時之狀況。 (請先閱讀背面之注意事項再填寫本頁) 4 ·如申請專利範圍第1項所述之可程式化控制裝置 ,其中至少一端係爲一輸入/輸出端,且該第二記億體的 該m位元資料界定該端的輸入及/或輸出架構。 5 ’如申請專利範圍第4項所述之可程式化控制裝置 ’其中該第二記憶體包含一旗標,以設定該輸入/輸出端 爲一輸出端或高阻抗端,且該η位元資料係用以進一步界 定待產生而通過該輸出端之輸出訊號的特性。 6 ·如申請專利範圍第1項所述之可程式化控制裝置 ’其中該鑑別電路機構係響應於下列特徵訊號之至少一者 :具上升緣的訊號、具下降緣的訊號 '邏輯高電位訊號與 邏輯低電位訊號。 7 ·如申請專利範圍第1項所述之可程式化控制裝置 ’其中該輸出訊號包含下列訊號之至少一者:邏輯高電位 、邏輯低電位、脈衝、與高阻抗狀態。 經消部智慧財產局員工消費合作社印奴 8,如申請專利範圍第1項所述之可程式化控制裝置 ’其中該事件執行機構包含一訊號產生器。 9 .如申請專利範圍第1項所述之可程式化控制裝置 ’其中該鑑別電路機構被耦合到一或多個輸入端。 1 0 如申請專利範圍第1項所述之可程式化控制裝 置’其中該第一記憶體儲存描述一音頻訊號的編碼資料。 1 1 .如申請專利範圍第1 〇項所述之可程式化控制 裝置’其中該事件執行機構產生一對應於該編碼資料的音 31 本紙伕尺度適用令國國家標準(匚~5)六4規格(210/ 297公釐) 經濟部智慧財產局員工消骨合作杜印製 Λ8 4207 83 ^_gj 六、申請專利範圍 頻訊號。 1 2 .如申請專利範圍第1項所述之可程式化控制裝 置,更包含一暫存器’以指示一將被執行事件的位址。 1 3 .如申請專利範圍第1 2項所述之可程式化控制 裝置,其中: 該第一記憶體儲存編碼的時序資料; 該控制裝置更包含一計數器,以操控該編碼的時序資 料; 且該暫存器依據該計數器的計數過程指示一將被執行 事件的位址。 1 4 ·如申請專利範圍第1 2項所述之可程式化控制 裝置,其中該暫存器的內容藉由儲存於第一記憶體中的一 事件予以界定。 1 5 _如申請專利範圍第1項所述之可程式化控制裝 置,其中該第一與第二記憶體包含下列記憶體之至少一者 唯讀記憶體; 可抹除程式化唯讀記憶體; 一次可程式化唯讀記憶體:及 讀寫記憶體。 1 6 ‘如申請專利範圍第1項所述之可程式化控制裝 置,其中該第一尋址電路機構包含一查詢表,以界定該第 一記憶體中之事件的起始位址,該查詢表係藉由該第二記 憶體的η位元資料來定址。 32 夫紙張尺度適用中國國家福準(CNS) Α4規格(210Χ2<Π公釐) 裝 . 訂 線-— (請先閱讀背面之注意事項再填寫本頁) Λ 2 Ο 7 8 3 * as 〇〇 C8 D8 _ 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 1 7 如申請專利範圍第1項所述之可程式化控制裝 置,其中該第二記憶體的該η位元資料記億體與m位元資 料記憶體係爲不同的位址,且第二尋址電路機構界定該η 位元記憶體與m位元記憶體之對應的現在位址。 1 8 .如申請專利範圍第1項所述之可程式化控制裝 置,該裝置係含於一積體電路中。 1 9 如申請專利範圍第1 8項所述之可程式化控制 裝置,其中至少有兩個端點係位在該積體電路內的不同位 置上,且第二記憶體分佈於接近該端點或該鑑別電路機構 之分開位置處。 2 0 _如申請專利範圍第1項所述之可程式化控制裝 置,其中: k係爲一等於或小於1 6的整數; m界定高達16個輸入/輸出形態; η界定高達1 2 8個事件起始位址;及 該第二尋址電路機構界定該第二記憶體之高達6 4個 位址。 經濟部智慧財產局員工消#合作社印製 2 1 . —種對控制裝置程式規畫之程式化方法,響應 於一或多個外部合格的電氣訊號以執行一或多項事件:該 控制裝置包含至少一端點作爲一輸入端及至少一端點作爲 一輸出端,該程式化方法至少包含下列步驟: (1 )設定X端形態’其中χ係等於或大於1的整數 I (2 )設定y事件,其中y係等於或大於1的整數; ·*♦ 本紙張尺度適用中國國家標準(' CNS〉Α4说格(210X29?公釐) ~ ~ " 420783 ABCD 經濟部智慧对產局員工消費合作杜印製 六、申請專利範圍 (3 )對於步驟(1 )的每—形態,對各輸入端設定 一輸入鑑別條件; (4 )對於步驟(3 )的各輸入端,當被連接到該輸 入端的輸入訊號滿足該輸入鑑別條件時,尙設定一將被執 行的事件; (5 )對於步驟(1 )的每一形態,對各輸出端設定 一輸出訊號; (6 )設定該等形態之一者成爲動作中的形態《 2 2 ·如申請專利範圍第2 1項所述之程式化方法, 尙包含一設定至少一事件以包含P個子事件的步驟,其中 P係爲一等於或大於2的整數。 2 3 ‘如申請專利範圍第2 2項所述之程式化方法, 尙包含一設定一事件或子事件以產生下列效果至少一者的 步驟: (a )產生一音頻訊號; (b )產生一時序訊號; (c) 產生一邏輯高/低電位訊號; (d) 產生一脈衝訊號: (e) 致動另一事件;及 (f )設定另一形態作爲動作中的形態。 2 4 ·如申請專利範圍第2 3項所述之程式化方法, 尙包含在該時序訊號結束前設定一欲被執行事件的步驟。 2 5 ·如申請專利範圍第2 1項所述之程式化方法, 其中至少一事件係爲一可變事件,該程式化方法尙包含使 34 ^I (餚先閱讀背面之注意事項再填寫本頁) 訂 線丨丨· 本紙張尺度逋用中國國家標隼(CNS ) Λ4規格(210X297公釐) 8 8 8 8 ABCD 420783 六、申請專利範圍 該可變事件與另一界定的事件相等的步驟。 2 6 ·如申請專利範圍第2 1項所述之程式化方法’ 其中該端點之至少一者係爲一可程式化的輸入/輸出端, 且該程式化方法更包含設定該輸入/輸出端爲一輸入端、 —輸出端 '一輸入/輸出端或一高阻抗端之步驟。 2 7 .如申請專利範圍第2 1項所述之程式化方法, 更包含一使程式規格構成爲兩欄位的步驟’其中該第一欄 位設定一或多個端形態的特性,且該第二欄位設定一或多 個事件與子事件。 2 8 ·如申請專利範圍第2 1項所述之程式化方法, 更包含一由該等步驟設定的資料之至少部份以組成一表格 格式的步驟。 2 9 ·如申請專利範圍第2 1項所述之程式化方法, 更包含一將形態與事件之規格轉換爲數位資料以儲存於該 控制裝置供其事件執行的步驟。 3 0 _如申請專利範圍第2 9項所述之程式化方法, 更包含轉換該數位資料於一光罩上以製造該控制裝置的步 驟。 3 1 如申請專利範圍第2 1項所述之程式化方法, 更包含一將形態與事件規格轉換爲一不同格式的輔助程式 語言的步驟。 3 2 .如申請專利範圍第2 1項所述之程式化方法, 更包含以下步驟以互動地模擬控制裝置的操作於一顯示元 件上: 35 本紙張尺度適用中國國家標準{ CNS ) A4現格(210X297公瘦) (請先閲讀背面之注意事項再填寫本頁) -裝 -1T 經濟部智慧財產局員工消費合作社印製 ABCD Λ2 〇7 83 六、申請專利範圍 (7 )顯示至少—個形態之規格; (8 )顯示至少一事件之規格; (9 )指示該動作中的形態; (1 〇 )設定一端以接收一合格的激勵訊號;及 C11)指示及/或模擬執行中的事件或子事件。 3 3 ·如申請專利範圍第3 2項所述之程式化方法, 更包含編輯所顯示資料的步驟。 3 4 ·如申請專利範圍第3 2項所述之程式化方法, 更包含使該二欄位與一含有方塊及互連該方塊的路徑之流 •程圖相關連的步驟’其中各方塊對應於該第一欄位的一或 多個端形態’且各路徑對應於該第二欄位之一事件。 3 5 ·如申請專利範圍第3 2項所述之程式化方法, 更包含安排響應於該形態與事件規格的輸入/輸出電路機 構之步;且將該輸入/輸出電路機構與一外部應用電路 連接,藉此模擬該控制裝置的操作。 3 6 ·如申請專利範圍第2 1項所述之程式化方法, 其中該X端形態與該y事件的規格相互間係不必以序列關 係列出。 3 7 ‘如申請專利範圍第2 1項所述之程式化方法’ 其中該等程式化步驟並未包含於一行指令集之任一者,該 指令集包含由一操作及至少一個運算元界定的指令。 3 8 · —種含於積體電路中之可程式化控制裝置’包 含: 輸入/輸出電路機構’包含二或多個端,該等端之各 36 本紙張尺度適用中國國家標準(CNS)A4規格(2ί0χ297公釐) ----------^------、奸------手 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製420783 Α8 Β8 C8 DS Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Application for patent scope 1 · A programmable control device at least: K terminal, at least one first terminal is set as an input terminal and a second terminal The terminal is set as an output terminal: at least one identification circuit mechanism can respond to the characteristic signal received by the first input terminal; a first memory stores data to define one or more events, and each event has a location in the first A corresponding start address in an addressable range in a memory; a second memory in an (n + m) bit data format, the m bit data is used to define a type of one end, and the n bit The data is used to define an event start address of the first memory when the terminal is set as an input terminal; an event execution circuit mechanism is used to generate at least one first event output signal when a first event is executed And a second event output signal, the first event output signal is coupled to the output terminal for generating an output signal; 'a first addressing circuit mechanism, in response to the discrimination circuit mechanism, actuating the The first event element actuator to perform a event defined by the start address; and a second addressing circuit means, the second event in response to the output signal to update the current address of the second memory. 2. The programmable control device as described in item 1 of the scope of patent application, wherein the event execution circuit mechanism generates a third event output signal, interrupts the first addressing circuit mechanism, and activates a second event address And execute its second event. 3 · Programmable control device 30 as described in item 1 of the scope of patent application (please read the precautions on the back before filling this page) The paper size is in accordance with the Chinese National Standard (CNS) Α4 specification (210 × 297 mm) ABCD Λ 2 07 83 ^ VI. The scope of patent application 'includes a moving circuit mechanism to define the status of the programmable control device at startup. (Please read the precautions on the back before filling this page) 4 · If applying for a patent The programmable control device described in the first item of the scope, wherein at least one end is an input / output end, and the m-bit data of the second billion body defines the input and / or output structure of the end. 5 '如The programmable control device described in item 4 of the scope of patent application, wherein the second memory includes a flag to set the input / output terminal as an output terminal or a high-impedance terminal, and the n-bit data is used for In order to further define the characteristics of the output signal to be generated through the output terminal. 6 · The programmable control device as described in item 1 of the scope of the patent application, wherein the identification circuit mechanism is responsive to the following At least one of the sign signals: a signal with a rising edge, a signal with a falling edge 'Logic high potential signal and logic low potential signal. 7 · The programmable control device as described in the first patent application scope', where the output The signal contains at least one of the following signals: logic high potential, logic low potential, pulse, and high-impedance status. Employee Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Consumer Affairs, Innu 8, as programmable as described in item 1 of the patent application scope Control device 'where the event execution mechanism includes a signal generator. 9. Programmable control device as described in item 1 of the patent application' wherein the identification circuit mechanism is coupled to one or more inputs. 1 0 Such as Programmable control device described in item 1 of the scope of patent application 'wherein the first memory stores encoded data describing an audio signal. 1 1. Programmable control device described in item 10 of the scope of patent application' Among them, the event executing agency produced a tone corresponding to the coded data. The paper size is applicable to national standards (标准 ~ 5) and 6 specifications (210/297 mm). The Department of Intellectual Property Bureau of the Ministry of Economic Affairs and the People's Republic of China Eliminates Bone Duplication Λ8 4207 83 ^ _gj 6. The patent application frequency signal. 1 2. The programmable control device as described in item 1 of the patent application scope, including a register 'To indicate the address of an event to be executed. 1 3. The programmable control device as described in item 12 of the scope of the patent application, wherein: the first memory stores encoded timing data; the control device further includes A counter to manipulate the coded time-series data; and the register indicates the address of an event to be executed according to the counting process of the counter. 1 4 · Programmable control as described in item 12 of the scope of patent application Device, wherein the content of the register is defined by an event stored in the first memory. 1 5 _ The programmable control device as described in item 1 of the scope of patent application, wherein the first and second memories include at least one of the following memories: read-only memory; the programmable read-only memory can be erased ; Programmable read-only memory at one time: and read-write memory. 16 'The programmable control device as described in item 1 of the scope of patent application, wherein the first addressing circuit mechanism includes a lookup table to define a start address of an event in the first memory, and the query The table is addressed by the n-bit data of the second memory. The paper size of the 32 paper is applicable to China National Standard for Standards (CNS) Α4 (210 × 2 < Πmm). Binding.-(Please read the precautions on the back before filling this page) Λ 2 〇 7 8 3 * as 〇〇 C8 D8 _ 6. Scope of patent application (please read the precautions on the back before filling out this page) 1 7 The programmable control device as described in item 1 of the scope of patent application, where the η bit of the second memory The data memory system and the m-bit data memory system have different addresses, and the second addressing circuit mechanism defines a corresponding current address of the n-bit memory and the m-bit memory. 18. The programmable control device as described in item 1 of the scope of the patent application, which is included in an integrated circuit. 19 The programmable control device as described in item 18 of the scope of patent application, wherein at least two end points are located at different positions in the integrated circuit, and the second memory is distributed near the end point Or a separate location of the identification circuit mechanism. 2 0 _ The programmable control device described in item 1 of the scope of patent application, wherein: k is an integer equal to or less than 16; m defines up to 16 input / output modes; η defines up to 1 2 8 Event start address; and the second addressing circuit mechanism defines up to 64 addresses of the second memory. Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs # Cooperative Society Printing 2 1 — A programmatic method of programming the control device in response to one or more externally qualified electrical signals to perform one or more events: the control device contains at least An end point is used as an input end and at least one end point is used as an output end. The stylized method includes at least the following steps: (1) setting the X-end shape 'where χ is an integer I equal to or greater than 1 (2) setting the y event, where y is an integer equal to or greater than 1; ** This paper size applies the Chinese national standard ('CNS> Α4 grid (210X29? mm) ~ ~ 420783 ABCD Wisdom printed by the Ministry of Economic Affairs on the consumer cooperation of the production bureau staff Sixth, the scope of patent application (3) For each form of step (1), set an input discrimination condition for each input terminal; (4) For each input terminal of step (3), when it is connected to the input signal of the input terminal When the input discrimination condition is satisfied, set an event to be executed; (5) For each form of step (1), set an output signal to each output terminal; (6) Set one of these forms to become The form in action "2 2 · The stylized method as described in item 21 of the scope of patent application, , includes a step of setting at least one event to include P sub-events, where P is an integer equal to or greater than 2. 2 3 'The stylized method described in item 22 of the scope of the patent application, which includes a step of setting an event or sub-event to produce at least one of the following effects: (a) generating an audio signal; (b) generating a temporary Sequence signals; (c) Generate a logic high / low signal; (d) Generate a pulse signal: (e) Activate another event; and (f) Set another shape as the shape in action. 2 4 · 如The stylized method described in item 23 of the scope of patent application, includes the step of setting an event to be executed before the end of the timing signal. 2 5 · The stylized method described in item 21 of scope of patent application, where At least one event is a variable event. The stylized method includes making 34 ^ I (read the precautions on the back before filling out this page). 丨 丨 This paper size uses the Chinese National Standard (CNS) Λ4 specifications (210X297 mm) 8 8 8 8 ABCD 420783 6. The scope of patent application The variable event is equivalent to another defined event. 2 6 • The method of stylization as described in item 21 of the scope of patent application 'where at least one of the endpoints is A programmable input / output terminal, and the programming method further includes the step of setting the input / output terminal as an input terminal, an output terminal, an input / output terminal, or a high-impedance terminal. The stylized method described in item 21 of the patent scope further includes a step of constituting the program specification into two fields, wherein the first field sets one or more characteristics of the end form, and the second field sets One or more events and child events. 2 8 · The stylized method described in item 21 of the scope of patent application, further comprising a step of forming at least part of the data set by these steps into a table format. 2 9 · The stylized method described in item 21 of the scope of patent application, further comprising a step of converting the specifications of the form and event into digital data to be stored in the control device for the event to execute. 3 0 _ The stylized method described in item 29 of the scope of patent application, further comprising the step of converting the digital data on a photomask to manufacture the control device. 31 The method of stylization as described in item 21 of the scope of patent application, further includes a step of converting the form and event specifications into an auxiliary programming language of a different format. 32. The stylized method as described in item 21 of the scope of patent application, further comprising the following steps to interactively simulate the operation of the control device on a display element: 35 This paper size applies the Chinese national standard {CNS) A4 (210X297 male thin) (Please read the precautions on the back before filling out this page)-Install -1T printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ABCD Λ2 〇7 83 VI. The scope of patent application (7) shows at least one form Specifications; (8) specifications showing at least one event; (9) indicating the form in the action; (10) setting one end to receive a qualified incentive signal; and C11) indicating and / or simulating an event or Child event. 3 3 · The stylized method described in item 32 of the scope of patent application, further including the step of editing the displayed data. 3 4 · The stylized method described in item 32 of the scope of patent application, further comprising the step of correlating the two fields with a flow containing a block and a path interconnecting the block, wherein the blocks correspond to each other One or more end forms in the first field 'and each path corresponds to an event in the second field. 3 5 · The stylized method described in item 32 of the scope of patent application, further comprising the step of arranging the input / output circuit mechanism in response to the form and event specifications; and the input / output circuit mechanism and an external application circuit Connect, thereby simulating the operation of the control device. 36. The stylized method as described in item 21 of the scope of patent application, wherein the specifications of the X-terminal form and the specifications of the y event do not need to be listed in series. 3 7 'The stylized method as described in item 21 of the scope of patent application' wherein the stylized steps are not included in any one line of instruction set, and the instruction set includes an operation and at least one operand defined instruction. 3 8 · —A programmable control device included in the integrated circuit 'contains: Input / output circuit mechanism' contains two or more terminals, each of which 36 paper standards are applicable to China National Standard (CNS) A4 Specifications (2ί0χ297mm) ---------- ^ ------, rape ------ hand (Please read the notes on the back before filling this page) Intellectual Property Bureau of the Ministry of Economic Affairs Employee consumption cooperation
TW84110890A 1995-10-17 1995-10-17 Commandless programmable controller TW420783B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW84110890A TW420783B (en) 1995-10-17 1995-10-17 Commandless programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW84110890A TW420783B (en) 1995-10-17 1995-10-17 Commandless programmable controller

Publications (1)

Publication Number Publication Date
TW420783B true TW420783B (en) 2001-02-01

Family

ID=21624886

Family Applications (1)

Application Number Title Priority Date Filing Date
TW84110890A TW420783B (en) 1995-10-17 1995-10-17 Commandless programmable controller

Country Status (1)

Country Link
TW (1) TW420783B (en)

Similar Documents

Publication Publication Date Title
US7724236B2 (en) Methods and systems for providing programmable computerized interactors
US5595489A (en) Electronic audio learning apparatus
JP4057079B2 (en) Programmable sound synthesizer
TW420783B (en) Commandless programmable controller
JP2000089754A (en) Paying support device
JPH022152B2 (en)
JP3796752B2 (en) Music performance program
JP3072336U (en) Educational materials for information processing learning
JPS6311673B2 (en)
JPS6237252Y2 (en)
JPH06230773A (en) Electronic musical instrument
JPS54137317A (en) Musical sound memory for electronic instrument
GB2270178A (en) Generic user configurable keyboard
JPS58114093A (en) Keying indicator for electronic musical instrument
JP2004062072A (en) Electronic musical instrument
JPS5896597U (en) electronic musical instruments
JP2786556B2 (en) Sound display device and sound display method for sound information and display information
JP2564811B2 (en) Performance recorder
JPS6318074Y2 (en)
JP2593297B2 (en) Electronic musical instrument
JPS6316759B2 (en)
JP2560397Y2 (en) Function setting device for electronic devices
CN112669685A (en) Open source hardware teaching tool box
JPS6029958B2 (en) electronic musical instruments
JPS6024945B2 (en) electronic musical instruments

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent
MC4A Revocation of granted patent