418535 A7 B7 五、發明說明（） 本發明與一種半導體之元件有關，特别是一種具有 閘_側氣隙（air-spacer)結構之金氧半場效電晶體 (M:OSFET) ° 經濟部智慧財產局員工消費合作社印製 發明背景 :.金氧半場效電晶體（MOSFET)在積體電路工業中是/ 典型且被廣泛應用於電路設計中的元件之一。在電晶體 中，通道（channel)之區域通常摻雜與汲極/源極相反電 性k離子。操作之過程包含在閘極施以電壓。藉由調整 電壓值，可以將通道之離子電性反轉進而產生通道電流 於其中。一般的場效電晶體其通道、汲極與源極均形成 在單晶矽底材之中。由於積體電路的設計傾向於縮小化， 因Λ在製作金氧半場效電晶體之技術發展過裎中，也面 臨了許多之問題與挑戰。例如，所熟知的熱載子效應便 是其中一種重要之效應，上述之效應已經可以利用輕微 掺雜汲極結構（LDD)來降低熱載子之現象。此外，寄生 電容（parasitic capacitance)是造成金氡半場效電晶體之 操作速度變慢的主要原因之一。且寄生電容也造成金氧 半’場效電晶體需要較高之操作功率。通常形成寄生電容 的.主要原囡爲閘極電容（gate capacitance) '閘極·ί及極重 昼電容（gate-to-drain overlap capacitance)、接面電容418535 A7 B7 V. Description of the invention () The invention relates to a semiconductor device, in particular a metal-oxygen half field effect transistor (M: OSFET) with a gate-side air gap structure (M: OSFET) ° Intellectual property of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau of Invention Background: Metal-oxide-semiconductor field-effect transistor (MOSFET) is one of the typical / widely used components in circuit design in the integrated circuit industry. In a transistor, the region of the channel is usually doped with electrical k ions opposite to the drain / source. The operation involves applying a voltage to the gate. By adjusting the voltage value, the ionicity of the channel can be reversed to generate the channel current in it. In general field-effect transistors, the channel, drain, and source are all formed in a single crystal silicon substrate. Because the design of integrated circuits tends to be smaller, Λ has faced many problems and challenges in the development of the technology for making metal-oxide half-field-effect transistors. For example, the well-known hot carrier effect is one of the important effects. The above-mentioned effects can already use the lightly doped drain structure (LDD) to reduce the phenomenon of hot carriers. In addition, parasitic capacitance is one of the main reasons for the slow operating speed of the gold field half-effect transistor. And the parasitic capacitance also causes the metal oxide half field effect transistor to require higher operating power. The parasitic capacitance is usually formed. The main reason is the gate capacitance, the gate electrode and the heavy day-to-drain overlap capacitance, and the junction capacitance.
(請先閱讀背面之注意事項再填寫本寅) 185 35 A7 B7 五、發明說明（ .(junction capacitance)以及閘極邊際電容（gate fringi capacitance) ° 較低之操作功率以及較快之操作速度爲超大型積體 電路所朝之設計方向。因此，爲達到低操作功率及高操 作速度的互補式金氧半場效電晶體，使其符合超大型積 ‘體電路之需求，降低寄生電容產生爲達到上述目標之方 •法之一。其次’文獻中亦有利用GAS結構來克服寄生電容 之效應。請參閱 “A Gate-side Air-gap Structure (GAS) t。 Reduce the Parasitic Capacitance in MOSFETs, M. Togo et al., 1996，Symposium on VLSI Technology Digest of Technical papers。利用此閘極側氣隙結構可以得到高速度且低操作功 率之MOSFET。因此GAS結構可以顯著降低MOSFET之閘極 邊-際電容（gate fringe capacitance)。 ·» 發'明目的及概述： 5 \本發明之目的爲製作一種具有閘極側氣隙之金氧半 場效電晶體用以降低miller capacitance (Cgd)。 ' 、^· — ! — ί —tr. — — — (靖先閱讀背面之注意亊項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 自可 之度 度長 長之 道道 通通 之其 小 ， 較體。 有晶制 且ί 電限 供效U 提場度 爲半析 的氧解 目金程 一之製 另屬影 之金微 明化前 發矽目 本準破 對突 梯 為 度 濃 雜 摻 之 成 形 自 供 提 爲 的 ί 再 之 明 發 本 本纸張尺度递用中國國家標準（CNS)A4規格（210 X 297公笼） 418535 A7 B7 五、發明說明（ 度漸變之 LDD 結構（graded doped LDD)。 本發明沈積一氮化矽層於基板之上，氧化矽層形成 於氨化矽層之上，另一氮化矽層以低壓化學氣相沈積法 形成於氧化矽層之上，然後利用非等向性蝕刻製程蝕刻 上述之氮化矽層以形成氮化矽侧堃間隙，上述之側壁間 •隙將開口下侧之寬度縮減，利用上述之氧化矽層以及側 ，壁‘間隙作爲離子佈植之罩幕，以離子植入製程植入適合 之離子達入基板，以形成 delta doped離子摻雜區域以 調整元件之臨界電壓（threshold voltage)以及抗底穿（anti pvi.nch through)之摻雜。接著於被曝露之基板上形成由氧 化矽所構成的薄閘極氧化層，此閘極氧化層一般可以在 攝氏溫度約700至1 1 00度之下於氧環境中以熱氧化法 ‘長·成。 _i—.------· ά-------- 訂· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印^； 然後，一掺雜的複晶矽層沈積於閘極氧化層以及氧 化'.梦看之上。利用化學機械研磨法（c h e m i c a 1 .mechanical polishing)將上述之複晶石夕層研磨至氧化 砍層之表面，或是利用回蝕刻製程將上述之複晶矽層蝕 刻至氧化矽層之表面。隨後將曝露之氧化矽層移除，可 以利用稀釋後之氫氟酸（H F)溶液或Β Ο E溶液將氧化矽層 去除。下一步驟爲利用熱磷酸溶液將氮化矽層以及氮化 矽側壁間隙去除，上述之閘極之結構之下側部份較窄， 且其截面之剖面寬度由上至下爲漸進縮小。利用上述之 漸進縮減之閘極結構作爲離子怖植之罩幕，以離子植入 本紙張尺度$用尹囷國家標準（CNS)A4規格（210 X 297公爱） 4 185 35 A7 -------B7 — 五、發明說明（） 製程植入適合之離子部份穿過閘極邊緣進入基板或直接 進入基板’以形成輕微捧雜之離子摻雜區域（LDD)。 •下一步驟爲沈積一絶緣層，如氧化矽層或氮化矽於 基板之上以及閘極結構之上。隨後執行一非等向性之蝕 刻製程独刻上述之絶緣層因而形成倒壁間隙，鄰接於問 極結構。由於閘極結構之兩侧爲往内收縮，因此將形成 ..閘極側氣隙（air-space)位於閘極以及側壁間隙之間。閉 極側氣隙可以降低Miller capacitance (Cgd)。之後，以側 壁間隙以及閘極結構作爲罩幕’進行離子植入形成汲極與 源極。隨後，一金屬層沈積於上述之複晶梦開極與基板 之上。接著，執行一快速熱回火於氮氣中於35〇至7〇〇 C處理’用來反應上述之碎基板與複晶石夕閘極以形成自 對準石夕化金属（self-aligned silicide ; SALICIDE)與複 晶.碎化金屬。接者’再去除未參與反應之金属層。 a戎葫輩説明： 第.一圖爲本發明之形成氮化石夕、氧化層以及氛化梦側壁 .間隙之截面圖。 第二圖爲本發明之形成delta剖面之摻雜區域（deha d〇ped region)與閘極氧化層之截面圖。 第-·:三圖爲本發明之形成複晶矽層之截面圖。 第四圖爲本發明之去除複晶矽層之上部份之截面圖。 •.第五圖爲本發明之去除氣化發以及施以離子佈植之截面 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） · , I. •裝* — ί請先閱讀背面之注帝？事項再填寫本頁} 訂. 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 41S5 35 A7 --------------B7 ~ ___ 五、發明說明（） ..圖..。 •第六圖爲本發明之沈積氧化層之哉面圖。 第七圖爲本發明之形成側壁間隙以及石夕化金屬之截面 圖。 發明詳細説明： 參閲第—圖，提供一晶向爲<100〉之單晶梦做爲晶 圓或基板2,接著，場氧化區域（未圖示）形成於基板2之 上作爲元件之間之絶緣結構並定義元件之主動區間。此 場氧化區域可以利用微影與姓刻激程在二氧化矽層與氮 化矽層複合層上定義將用以形成場氧化之區域，缺後利 用,氧化製程’以上述複合層作爲罩幕形成場氡化區域〇 ，然後去除複合層。一般，淺溝渠絶緣區域技術亦可以 '來製作絶緣結構。 ‘製作完場氧化區域之後，接著，沈積一層氮化矽層 4於基板2 &上。舉例而言，可以利用電漿化學氣相沈 .積法形成氮化矽4，一般可以於反應室中利用、 ΝΗ3、Ν2、Ν20或其他適合之反應物，於溫度攝氏^⑽ 至800度之下形成氮化矽層4。氧化矽層 ;矽層4之上。通常，二氧化矽層6可以利用任何適厶、 ._製;程如化學氣相沉積法來製作二氧化矽層6。^ ° < D 以一實施 例而言，可以利用TEOS作爲反應物進行化 . _ 乎氣相沈穡 以形成TEOS-氧化物。完成上述之氣化妙嚴 切 帶4與氧化矽 良紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公爱） I ^ I ^---- i I ^-11--In (請先閱讀背面之注意事項再填寫本頁) ^5 35(Please read the notes on the back before filling in this book) 185 35 A7 B7 V. Description of the invention (.junction capacitance) and gate fringi capacitance ° Lower operating power and faster operating speed are The design direction of very large integrated circuits. Therefore, in order to achieve low operating power and high operating speed, complementary metal-oxide-semiconductor field-effect transistors meet the needs of very large integrated circuits, reducing parasitic capacitance. One of the methods of the above objectives. Secondly, the literature also uses the GAS structure to overcome the effect of parasitic capacitance. See "A Gate-side Air-gap Structure (GAS) t. Reduce the Parasitic Capacitance in MOSFETs, M. Togo et al., 1996, Symposium on VLSI Technology Digest of Technical papers. Using this gate-side air gap structure can obtain MOSFETs with high speed and low operating power. Therefore, the GAS structure can significantly reduce the gate edge-to-capacitance of the MOSFET ( gate fringe capacitance). »The purpose and outline of the development: 5 \ The purpose of the present invention is to produce a metal-oxygen half field with a gate-side air gap. The effect transistor is used to reduce the miller capacitance (Cgd). ', ^ · —! — Ί —tr. — — — (Jing first read the note on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The degree of self-confidence is long and the way is small, and it is relatively small. There are crystals and ί electric limit power supply U. The degree of oxygen release is semi-analyzed. The eyebrows are designed to be broken, and the shape of the stair is rich and mixed. The paper size of the paper is handed to the Chinese National Standard (CNS) A4 specification (210 X 297 male cage) 418535 A7 B7 V. Invention Description (graded doped LDD structure). The present invention deposits a silicon nitride layer on a substrate, a silicon oxide layer is formed on the ammoniated silicon layer, and another silicon nitride layer is deposited by low-pressure chemical vapor deposition. It is formed on the silicon oxide layer, and then the above silicon nitride layer is etched by an anisotropic etching process to form a silicon nitride side gap. The above-mentioned side wall gap reduces the width of the lower side of the opening. Silicon oxide layer and side The wall 'gap serves as a mask for ion implantation, and suitable ions are implanted into the substrate by an ion implantation process to form a delta doped ion doped region to adjust the threshold voltage and anti-undercutting of the device. pvi.nch through). Next, a thin gate oxide layer made of silicon oxide is formed on the exposed substrate. This gate oxide layer can generally be grown by thermal oxidation in an oxygen environment at a temperature of about 700 to 110 degrees Celsius. to make. _i —.------ ά -------- Order · (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^; The polycrystalline silicon layer is deposited on the gate oxide layer and oxidized. A chemical mechanical polishing method (c h e mi c a 1 .mechanical polishing) is used to grind the polycrystalline stone layer to the surface of the oxidized layer, or an etch-back process is used to etch the polycrystalline silicon layer to the surface of the silicon oxide layer. Subsequently, the exposed silicon oxide layer can be removed, and the silicon oxide layer can be removed by using a diluted hydrofluoric acid (HF) solution or a B0E solution. The next step is to remove the silicon nitride layer and the silicon nitride sidewall gap with a hot phosphoric acid solution. The lower part of the gate structure is narrower, and the cross-sectional width of the cross section is gradually reduced from top to bottom. The above-mentioned progressively reduced gate structure is used as a mask for ion implantation. Ion implantation of this paper size is based on the National Standard (CNS) A4 specification (210 X 297 public love) 4 185 35 A7 ---- --- B7 — V. Description of the invention () The process is to implant a suitable ion portion through the gate edge into the substrate or directly into the substrate 'to form a slightly doped ion-doped region (LDD). • The next step is to deposit an insulating layer such as a silicon oxide layer or silicon nitride on the substrate and the gate structure. Subsequently, an anisotropic etching process is performed to etch the above-mentioned insulating layer, thereby forming an inverted wall gap adjacent to the interfacial structure. Since both sides of the gate structure shrink inwardly, a gate-side air gap is formed between the gate and the side wall gap. The closed-electrode-side air gap reduces Miller capacitance (Cgd). After that, the side wall gap and the gate structure are used as a mask 'for ion implantation to form a drain and a source. Subsequently, a metal layer is deposited on the above-mentioned polycrystalline dream-opening electrode and the substrate. Next, perform a rapid thermal tempering in nitrogen at 350 to 700 ° C to react the above-mentioned broken substrate and the polycrystalline stone gate to form a self-aligned silicide; SALICIDE) and polycrystalline. Shredded metal. Then, the metal layer not participating in the reaction is removed. Description of the Ronghu generation: The first figure is a cross-sectional view of the formation of nitrided stones, oxide layers, and the side wall of the dreaming dream of the present invention. The second figure is a cross-sectional view of a deha doped region and a gate oxide layer forming a delta section of the present invention. No.-: three pictures are cross-sectional views of the polycrystalline silicon layer formed in the present invention. The fourth figure is a cross-sectional view of a portion above the polycrystalline silicon layer of the present invention. • The fifth picture is the cross-section of the present invention for removing vaporized hair and applying ion implantation. The paper dimensions are applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm). ·, I. · 装 * — Please ask Read the Note Emperor on the back first? Please fill in this page again for the items} Order. Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 41S5 35 A7 -------------- B7 ~ ___ V. Description of the invention () .. Figure .. • The sixth figure is a plan view of the deposited oxide layer of the present invention. The seventh figure is a cross-sectional view of the side wall gap and petrified metal of the present invention. Detailed description of the invention: Referring to FIG. 1, a single crystal dream having a crystal orientation of <100> is provided as a wafer or a substrate 2. Then, a field oxidation region (not shown) is formed on the substrate 2 as an element. Insulation structure and define the active area of the component. This field oxidation area can be defined by lithography and lithography on the composite layer of silicon dioxide layer and silicon nitride layer. The area that will be used to form the field oxidation will be defined. A field-induced region 0 is formed, and then the composite layer is removed. In general, shallow trench insulation area technology can also be used to make insulation structures. ‘After the field oxide region is fabricated, a silicon nitride layer 4 is deposited on the substrate 2 & For example, plasma chemical vapor deposition and deposition can be used to form silicon nitride. Generally, it can be used in the reaction chamber, ΝΗ3, Ν2, Ν20, or other suitable reactants at a temperature of ^ ⑽ to 800 ° C Next, a silicon nitride layer 4 is formed. Silicon oxide layer; on silicon layer 4. Generally, the silicon dioxide layer 6 can be formed by any suitable process such as chemical vapor deposition. ^ ° < D In an embodiment, TEOS can be used as a reactant for chemical conversion. _ Almost vapor deposition to form TEOS-oxide. Completion of the above-mentioned gasification and meticulous cutting band 4 and silicon oxide good paper standards are applicable to China National Standard (CNS) A4 specifications (210 * 297 public love) I ^ I ^ ---- i I ^ -11--In (Please (Please read the notes on the back before filling out this page) ^ 5 35
、梦明說明（ 經濟部智慧財產局員工消費入η作社印製 層：6之後，利用微影之技術將上述之兩膜層囷案化以 ,露部份之基板2。 -氮化矽層S以低壓化學氣相沈積法形成於二氧化發 層6之上，然後利用非等向性蚀刻製程蚀刻上述之氮化5夕 :層8以形成氮化矽侧壁間隙8，位於上述圖案開口之側壁 之上，如第一圖所示。上述之側壁間隙8將開口下侧之寬 度縮小。以一實施例而言，利用氮化矽層8沈積之厚度可 .以控制側壁間隙之寬度，囡而可以間接控制縮減後閘極 之::寬度。參閲第二圖，利用上述之氧化矽層6以及侧壁間 隙作爲離子佈植之罩幕，以離子植入製程植入適合之離 子·進入基板2，以形成所謂之delta doped離子摻雜區域 10’用來調整元件之臨界電壓（threshold voltage)以及抗 底.穿（anti punch through)之捧雜。在此步驟之中，離子 植入之能量以及能量分别約爲2 E 1 2至5E13 atoms/cm2，及 2Q至80 KeV。接著於被曝露之基板2上形成由氡化矽所構 成的薄閘極氧化層12，此閘極氧化層12 —般可以在攝氏 ..溫度約7 0 0至1 1 0 0度之下於含氧環境中以熱氧化法長 " < 成’。此外，也可以採用其他方法如化學氣相沈積法 (Ghemical Vapor Deposition, CVD)形成此閘極氧化 ..層1 2。在本實施例中，閘極氧化層4的厚度約爲1 5-250 埃:。 .· f V 參閲第三圖，然後，一摻雜的複晶矽層或金屬14沈 g纸張尺度適用中國圃家標準（CNS)A4規格（210 X 297公釐） ' ^---------:訂·ί**ί·線 J ί請先閱讀背面之注意事項再填'寫本頁) 418535 A7 B7 五、發明說明（ 之子術料 6離技材 層以知矽 碎，習晶 化源以複 氡子。之 及離成述 以爲而上 12H3入成 層 P 摻形 化用子法 氧採離積 極以磷沈 閘可將相 於作法；氣 積製雜‘麥Mengming explained (Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs consumed the printed layer of the company: After 6 years, the lithography technology was used to convert the above two film layers to expose part of the substrate 2. -Silicon nitride The layer S is formed on the dioxide layer 6 by a low-pressure chemical vapor deposition method, and then the above-mentioned nitride is etched using an anisotropic etching process: the layer 8 forms a silicon nitride sidewall gap 8 located in the above pattern Above the sidewall of the opening, as shown in the first figure. The above-mentioned sidewall gap 8 reduces the width of the lower side of the opening. In one embodiment, the thickness of the silicon nitride layer 8 can be used to control the width of the sidewall gap. Therefore, the gate width after reduction can be controlled indirectly. See the second figure, using the above-mentioned silicon oxide layer 6 and the side wall gap as a mask for ion implantation, and implanting suitable ions by the ion implantation process. Enter the substrate 2 to form a so-called delta doped ion doped region 10 'for adjusting the threshold voltage and anti punch through of the device. In this step, the ion implantation The incoming energy and energy are about 2 E 1 2 to 5E13 atoms / cm2, and 2Q to 80 KeV. Next, a thin gate oxide layer 12 made of siliconized silicon is formed on the exposed substrate 2. This gate oxide layer 12 can generally be at Celsius. The temperature is about 700 to 110 degrees Celsius by thermal oxidation in an oxygen-containing environment. "In addition," other methods such as chemical vapor deposition (Ghemical Vapor Deposition, CVD) can also be used. ) To form this gate oxide .. layer 12 2. In this embodiment, the thickness of the gate oxide layer 4 is about 1 to 250 Angstroms:... F V Refer to the third figure, and then a doped Polycrystalline silicon layer or metal 14 sg paper size is applicable to China Garden Standard (CNS) A4 (210 X 297 mm) '^ ---------: Order · ί ** ί · 线 J ί Please read the notes on the back before filling in 'Write this page') 418535 A7 B7 V. Description of the invention (Zi Zi 6 material layer to know the silicon broken, Xi Jing source to restore the cricket. Thought that the above 12H3 into the layer P doped oxygen extraction using the sub-method positively using phosphorus sink gate can be similar to the method; gas production of hybrid wheat
經濟部智慧財產局員工消費合作社印製 如弟四圖所示，利用化學機械研磨法（chemical mechanical polishing)將上述之複晶矽層1 4研磨至氧 化梦層6之表面，或是利用回蚀刻製程將上述之複晶石夕 層蝕刻至氧化矽層6之表面。隨後將曝露之氧化矽層6移 除，可以利用稀釋後之氫氟酸（HF)溶液或BOE溶液將氧 化矽層ό去除。下一步驟爲利用熱磷酸溶液將氮化矽層4 以及氮化矽側壁間隙8去除，剩餘近似Τ形狀之閘極結構 .14與閘極氧化層12留於基板2之上，上述之閘極之結構 之下侧部份較窄’且其截面之剖面寬度由上至下爲漸進 縮十。 -如第五圖所示，利用上述之漸進縮減之閘極結構作 爲離子佈植之罩幕’以離子植入製程植入適合之離子部 份穿過閘極邊緣進入基板2或直接進入基板2，以形成輕 微摻雜之離子摻雜區域（LDD) 16 »由於，部份離子需穿 透閘極進入基板2且其寬度由邊緣至中心漸厚，因此進入 棊板2之離子濃度也隨著越接近問極越小，所以形成一濃 度声一漸進之梯度漸變剖面。離子植入之能量以及能量 分:列約爲 1Ε14 至 1Ε15 atoms/cm2，及 10至 40 KeV。 (請先閱讀背面之注意事項再填寫本頁) k· ί -----tT·-----111 l ' ! ! 本紙張尺度適畀中圉國家標革（CNS)A4規格（210 X 297公釐） 418535 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 參閲第六圖，下一步驟爲沈積一絶緣層18，如氧化矽 層或氮化矽於基板2之上以及閘極結構14之上。隨後執行 一非等向性之蝕刻製程蝕刻上述之絶緣層因而形成側壁間 隙’鄰接於閘極結構1 4。値得注意的是，請參閲第七圖， 由於閑極結構之兩側爲往内收縮，因此將形成閘極側氣隙 (a'ir-space)20位於閘極14以及側壁間隙〗8之間。閘極側氣 :隙20可以降低Miller capacitance (Cgd)。側壁間隙18與該 閘.極1 4分離一距離且位於基板2之上，在侧璧間隙丨8與該 閘極1 4之間形成閘極侧氣隙2 〇，侧壁間隙1 8之上緣與閘極 1 4 ·相接。之後’以側壁間隙1 8以及閘極結構14作爲罩幕，進 ‘行離子植入形成汲極與源極22。 ‘隨後，一金屬層沈積於上述之複晶矽閘極1 4與基板 2之上=舉一實施例，可以沈積一耐火金屬或貴重金屬• (refractory 或 noble metal)，例如可以選用 Ti，Pt，Co, W，Ni， ::Pd, Cr或任何適合之材質沈積於上述之結構之上，接著， ‘執行一快速熱回火於氮氣中於350至700 °C處理，用來 喻 .反i.應上述之矽基板2與複晶矽閘極1 4以形成自對準矽化 金)屬（self-aligned silicide: SALICIDE)24與複晶矽化 金屬2 6分別位於汲極/源極2 2與閘極之上，用以降低電 阻’。接著，再去除未參與反應之金屬層。 *. , - ,· .本發明之氣隙可以提昇元件性能，且本發明之通道 長‘度可以小於微影設備所可以提供之解析度。例如，L2 表紙張.尺_度適用中國國家標準（CNS)A4規格（210 X 297公芨） (請先閱讀背面之注意事項再填寫本頁) 裝 n n 訂·--- I n i Vi t 4 185 3b at _B7 五.、發明說明（） 為利用現有微影設備所能提供之線寬，而利用本發明之 製程可以達到小於L2之通道長度l 1 »綜上所陳，本發明 可以降低所謂之miller capacitance (Cgd)以及降低通 道之長度，且本發明並可以提供delta摻雜區域，此外， 本'發明閘極之上表面積較大，是故本發明具有較低之面 電.f且值（low gate sheet resistance)，再者，本發明之 I * .製.程提供自動形成之#雜濃度為梯度漸變之ldd結構 (graded doped LDD)。 1本發明以較佳實施例説明如上，而熟悉此領域技藝 者，在不脱離本發明之精神範園内，當可作些許更動潤 飾’’其專利保護範圍更當視後附之申請專利範团及其等 同領域而定。 III —·----1-1I — — — — — — — ^ « — — — — — — I— (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公笼）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in Figure 4, using chemical mechanical polishing to polish the above-mentioned polycrystalline silicon layer 14 to the surface of the oxide dream layer 6, or using etch back The process etches the polycrystalline spar layer to the surface of the silicon oxide layer 6. Subsequently, the exposed silicon oxide layer 6 is removed, and the diluted silicon oxide layer can be removed by using a diluted hydrofluoric acid (HF) solution or a BOE solution. The next step is to remove the silicon nitride layer 4 and the silicon nitride sidewall gap 8 using a hot phosphoric acid solution, leaving a gate structure of approximately T shape. 14 and the gate oxide layer 12 are left on the substrate 2. The above gate The lower part of the structure is narrower and the cross-sectional width of the cross section is gradually reduced from top to bottom. -As shown in the fifth figure, the above-mentioned progressively reduced gate structure is used as a mask for ion implantation. 'The appropriate ion part is implanted through the ion implantation process into the substrate 2 through the gate edge or directly into the substrate 2. To form a lightly doped ion-doped region (LDD) 16 »Because some ions need to penetrate the gate and enter the substrate 2 and the width gradually increases from the edge to the center, the ion concentration entering the ytterbium plate 2 also varies with The closer to the pole, the smaller it is, so a concentration sound and a progressive gradient profile are formed. The energy and energy points of ion implantation: about 1E14 to 1E15 atoms / cm2, and 10 to 40 KeV. (Please read the precautions on the back before filling this page) k · ί ----- tT · ----- 111 l '!! This paper is suitable for China National Standard Leather (CNS) A4 Specification (210 X 297 mm) 418535 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Referring to the sixth figure, the next step is to deposit an insulating layer 18, such as a silicon oxide layer or silicon nitride on the substrate 2 Above and above the gate structure 14. A non-isotropic etching process is subsequently performed to etch the above-mentioned insulating layer, thereby forming a sidewall gap 'adjacent to the gate structure 14. It should be noted that, please refer to the seventh figure, because the two sides of the idle pole structure shrink inwardly, a gate-side air gap (a'ir-space) 20 will be formed at the gate 14 and the side wall gap. 8 between. Gate-side air: gap 20 can reduce Miller capacitance (Cgd). The side wall gap 18 is separated from the gate electrode 14 by a distance and is located above the substrate 2. A gate-side air gap 2 0 is formed between the side gap 8 and the gate electrode 14 and the side wall gap 18 is above The edge is connected to the gate 1 4 ·. After that, the sidewall gap 18 and the gate structure 14 are used as a mask, and an ion implantation is performed to form a drain electrode and a source electrode 22. 'Later, a metal layer is deposited on the above-mentioned polycrystalline silicon gate 14 and the substrate 2 = For example, a refractory metal or a noble metal can be deposited (refractory or noble metal), for example, Ti, Pt can be selected. , Co, W, Ni, :: Pd, Cr or any suitable material is deposited on the above structure, and then, 'Perform a rapid thermal tempering in nitrogen at 350 to 700 ° C, which is used as a metaphor. i. The above-mentioned silicon substrate 2 and the polycrystalline silicon gate 1 4 should be used to form a self-aligned silicide (SALICIDE) 24 and the polycrystalline silicon silicide 2 6 respectively located at the drain / source 2 2 And gate to reduce resistance. Then, the metal layer not participating in the reaction is removed. *.,-, ... The air gap of the present invention can improve the performance of the device, and the channel length of the present invention can be smaller than the resolution provided by the lithographic equipment. For example, L2 sheet paper. Ruler_degree applies to China National Standard (CNS) A4 specification (210 X 297 cm) (Please read the precautions on the back before filling this page) Binding Order --- I ni Vi t 4 185 3b at _B7 V. Description of the invention () In order to use the line width provided by the existing lithographic equipment, the process of the present invention can be used to achieve a channel length less than L2. L 1 »In summary, the present invention can reduce the so-called Miller capacitance (Cgd) and reduced channel length, and the invention can provide delta doped regions. In addition, the surface area above the gate of the invention is larger, so the invention has a lower surface charge. F and value (Low gate sheet resistance) Furthermore, the I *. Manufacturing process of the present invention provides an automatically formed #dd concentration structure with a gradient of graded doped LDDs. 1 The present invention is described above with a preferred embodiment, and those skilled in the art can make some changes and embellishments without departing from the spirit of the present invention. The scope of patent protection should be regarded as the attached patent application. Mission and its equivalent. III — · ---- 1-1I — — — — — — — — ^ «— — — — — — I— (Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 male cage)