TW418488B - Semiconductor processing method for overcoming corner thinning effect - Google Patents

Abstract

The present invention discloses a semiconductor processing method which provides a HTO inside the trench as the gate sidewall and a HDP oxide as the bottom oxide in the trench, so as to overcome the corner thinning effect. The present invention comprises: providing a semiconductor device having a semiconductor substrate sequentially formed thereon a pad oxide and a first dielectric; using the photolithography and etching method to form a plurality of trenches in the semiconductor substrate; further, forming a second dielectric on top of the first dielectric and in the trench such that the second dielectric layer only fills the bottom of the trench; then, depositing the third dielectric layer on the semiconductor substrate and the sidewall in the trench; depositing the polysilicon layer on top of the semiconductor substrate and using the reactive ion etching method and back-etching method to remove part of the polysilicon layer so as to make the upper surface of the polysilicon layer being lower than the top of the trench; depositing the fourth dielectric layer on the semiconductor device and in the trench, such that the fourth dielectric is planarized by the chemical mechanical polishing method; and using the chemical mechanical polishing and back-etching methods to remove the fourth dielectric, part of the third dielectric and the second dielectric until exposing the upper surface of the polysilicon layer.

Description

Λ 18 4 3 8 V. Description of the invention (1) -1 Field of invention ΐ ΐThe purpose is to provide a high-temperature oxide layer in the trench as an 8 ", A φ degree plasma oxide layer as the bottom oxide layer of the trench, using the generation of phenomena and obtaining high -2 Background of the Invention: Recently the demand for semiconductor components The rapid increase due to the use of a large number of electronic parts. Especially the rapid popularization of computers has increased the demand for semiconductor components. Because it requires hundreds or thousands of transistors to form a complex integrated circuit manufactured on a single semiconductor wafer, 'in order to increase The integration degree of electronic components in integrated circuits and the reduction of layout area must make semiconductor devices with better performance and maintain the original characteristics of the components, so it is important to improve the quality of semiconductor components. Πσ The manufacturing method uses thermal oxidation to form a gate oxide layer on the inner sidewall of the trench. However, after the oxide layer is grown inside the trench, two problems need to be solved. One is that the intersection angle between the bottom of the trench and the sidewall of the trench will There is a phenomenon of thinning (corner th i nn i ng). Another problem is the silicon nitride layer and trench over the semiconductor substrate. The crossing angle will cause the tip of the case wall thinning due to the phenomenon of 'cross angle of this phenomenon will result in thinning of the leak current element (current leakage) is generated.

Page 5 According to the above-mentioned purpose, a semiconductor substrate is provided, and the conductive substrate is sequentially formed over the conductive substrate. Use lithography and the inside of a semiconductor substrate. Furthermore, the top of the shaped layer and the inside of the trench, its first. Next, a third dielectric layer is deposited. 4 184 88 V. Description of the invention (2) Therefore, it is urgent to overcome the occurrence of the corner thinning phenomenon and obtain a high-quality semiconductor device. 5-3 Purpose and summary of the invention: In view of the above-mentioned background of the invention, the existing semiconductor devices have many shortcomings. The main purpose of the present invention is to provide the inside of the trench-a high temperature oxide layer as the gate sidewall, and a high density plasma The oxide layer is used as the bottom oxide layer of the trench to overcome the occurrence of corner thinning and obtain high-quality semiconductor devices. Another object of the present invention is to provide a method for manufacturing a semiconductor device, which provides a third oxide layer over the second oxide layer and the polycrystalline silicon layer, so as to prevent the second oxide layer on the sidewall of the trench from being etched. If the silicon nitride layer is not deposited, and the first oxide layer on the gasified stone layer is directly removed by using nitric acid, the second oxide layer on the sidewall of the trench is also etched at the same time. The present invention provides a semiconductor device in which a pad oxide layer and a first dielectric layer are semi-etched to form a plurality of trenches to form a second dielectric layer and a first dielectric layer and a second dielectric layer. Fill the bottom of the trench above the semiconductor substrate and inside the trench

V. Description of the invention (3) Isolation: The dream layer is above the semiconductor substrate, and a part of the polycrystalline stone layer is removed by a reactive engraving method so that the upper surface of the polycrystalline dream layer is lower than the upper part of the trench. Deposition of a fourth dielectric layer: the fourth dielectric layer above the semiconductor element and in the trench is planarized by the chemical mechanical polishing method (MP). Finally, the chemical mechanical polishing method (CMP) and The etch back method is used to remove the fourth dielectric layer, and part of the third dielectric layer and the second dielectric layer are exposed until the upper surface of the polycrystalline layer in the trench is exposed. The figure is not simple. Knowing the half groove area and the half groove in the example, the half layer and the half layer in the example, the etching of the body substrate is the first diagram A and the first diagram B, which includes the second picture system of the conventional trench. The schematic diagram of the implementation of the present invention 'which includes the trench region and the third diagram is a schematic diagram of the implementation of the present invention, which includes the first high-temperature oxygen, the fourth diagram is the implementation diagram of the present invention' which includes the third oxidation, and the fifth diagram is another schematic diagram of the invention, It includes the formation of the oxide at the bottom of the trench in each step of the semiconducting first emulsion layer and the first oxide layer of the conductor element. The formation of the oxide in each step of the conductor element. The operation of each step of the conductor element Each of the conductor elements The movement of the step and its planarization. The third oxide layer above each step of the middle semiconductor device, and the representative symbols of the main parts. Page 7 V. Description of the invention (4) 100 silicon substrate 120 pad oxide layer 140 The first oxide layer 160A above the semiconductor substrate of the silicon nitride layer 160A The first oxide layer 180 inside the trench is thinned at the intersection angle 10 Silicon substrate 12 Pad oxide layer 14 The silicon nitride layer 16A is above the semiconductor substrate An oxide layer 1 6 B The first oxide layer at the bottom of the trench 18 The second oxide layer above the semiconductor substrate 1 8 A The second oxide layer at the inner side wall of the trench 20 The polycrystalline silicon layer 22 The third oxide layer 5-5 Detailed description of the invention: The fifth figure shows a cross-sectional view of the semiconductor element in the embodiment of the present invention. The second to fourth figures show the exploded schematic diagram of the method for manufacturing the semiconductor element. The same elements are denoted by the same reference numerals. The second figure shows: The semiconductor substrate 10 is a P-type silicon substrate; however, an η-type silicon substrate can also be used. Using traditional thermal oxygen

4 184 88

In the oxygen-containing environment, a pad oxidation layer 12 is grown on the surface of the semiconductor substrate by thermal oxidation in a oxygen-containing environment, and has a thickness of about 100 to 300 angstroms. Next, a low-pressure chemical vapor deposition (LPCVD) method is used to deposit a silicon nitride layer with a thickness between about 1000 and 3000 angstroms over the pad oxide layer 2. Then the whole wafer will be subjected to a lithography process, using photoresist as a mask, and anisotropic etching methods such as reactive ion etching (R 丨 E) will be used to etch the local silicon nitride layer. 4. The pad oxide layer 12 and semiconductor In the substrate 10, a trench is etched into the semiconductor substrate. Next, a high-temperature plasma (HDP) chemical vapor deposition (CVD) method is used to form a first oxide layer above the silicon nitride layer and inside the trench. The silicon nitride remaining on both sides of the sidewall of the trench is utilized. It is removed by hydrofluoric acid (HF). The first oxide layer inside the trench is used as the bottom oxide filling the trench. Using a high-temperature oxidation chemical vapor deposition method, a second oxide layer 18 having a thickness of about 200 to 500 angstroms is deposited on the silicon substrate and the inner sidewall of the trench, and is used as a leakage prevention layer on the third As shown. Next, a polycrystalline silicon layer 20 is deposited over the second oxide layer 8 and the polycrystalline silicon layer 20 is completely filled in the shallow trench. The polycrystalline silicon layer in the polished portion is planarized by using reactive ion etching (RIE) and etch-back techniques. 20, so that the upper surface of the polycrystalline silicon layer 20 is about 2000 angstroms below the trench, and its height is about the same as that of the pad oxide layer 12. A third oxide layer 22 is deposited on the second oxide layer 18 and the polycrystalline silicon layer 20, and the third oxide layer 22 'is planarized and polished using a chemical mechanical polishing technique so that the third oxide layer 22 is planarized in the fourth figure. As shown. If a silicon nitride layer 22 is not deposited above the second oxide layer 18 and the polycrystalline silicon layer 20 at this time,

4184 8D V. Description of the invention (6) If the first oxide layer 16A on the silicon nitride layer is removed by hydrofluoric acid, the second oxide layer 18 on the sidewall of the trench will be etched away at the same time. Before the first oxide layer 16A on the chemical conversion layer 14 is removed, a third oxide layer 22 is deposited on the semiconductor substrate, and then the surface is planarized by a chemical mechanical polishing method. Finally, the third oxide layer 22, the local second oxide layer 18, and the first oxide layer 16A over the semiconductor substrate are etched by a planarization technique of chemical mechanical polishing until the upper surface of the polycrystalline silicon layer 20 is exposed as shown in the fifth figure. In the implementation of the present invention, the second oxide layer 18 A is used as the gate side wall, and the above process can be used to solve the problem of corner thinning. The above description is only the preferred embodiments of the present invention, and is not intended to limit the scope of patent application of the present invention; any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent applications.

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Claims (1)

4 184 88 VI. Application for patent scope '' —— ι_ A method for manufacturing a semiconductor device includes at least the following: providing a semiconductor device with a semiconductor substrate; forming an oxide layer over the semiconductor substrate; depositing a first A dielectric layer is formed over the pad oxide layer; a plurality of trenches are formed inside the bottom by lithography and etching methods; and a second dielectric layer is formed over the first dielectric layer using a substrate. And inside the trench 'its second dielectric layer only fills the bottom of the trench; X' deposits a third dielectric layer over the semiconductor substrate and the inner sidewall of the trench: a deposits a polycrystalline silicon layer on the semiconductor substrate Top 'uses reactive ion etching (R IE) and etch back to remove part of the polycrystalline silicon layer, so that the upper surface of the polycrystalline silicon layer is lower than the upper part of the trench; depositing a fourth dielectric layer on Above the element and inside the trench, the fourth dielectric layer is planarized by a chemical mechanical polishing method (CMP); and the fourth dielectric layer is removed by a chemical mechanical polishing method (CMP) and an etch-back method Dielectric Layer, part of the third dielectric layer and the second dielectric layer until the upper surface of the polycrystalline layer is exposed to β 2 · The method for manufacturing a semiconductor device according to item 1 of the patent application range, wherein the first The dielectric layer contains at least gasified sand. 3. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, which Page 11 4 184 88 VI. Patent application scope The second dielectric layer mentioned above contains at least an oxide. 4. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the third dielectric layer mentioned above contains at least an oxide. 5. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the fourth dielectric layer described above contains at least an oxide. 6. The method for manufacturing a semiconductor device according to item 1 of the scope of the patent application, wherein the above-mentioned isolation region includes at least an oxide and polycrystalline silicon. 7. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the gate oxide layer described above is made by a thermal oxidation method. 8. The method for manufacturing a semiconductor device according to item 1 of the scope of the patent application, wherein the second dielectric layer is prepared by a high-density plasma (HDP) chemical vapor deposition method. 9. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the third dielectric layer is prepared by a high-temperature oxidation chemical vapor deposition method. 10. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the above-mentioned trenches are made by a non-isotropic etching method. Page 12 2. Scope of patent application The method for manufacturing a semiconductor device as described in item 1 of the scope of patent application, wherein the fourth dielectric layer planarization method mentioned above is made by chemical mechanical method or etching method. A method for manufacturing a semiconductor device, comprising at least the following steps: providing a semiconductor device having a silicon substrate; forming a pad oxide layer over the silicon substrate; depositing a silicon nitride layer over the hafnium oxide layer; Lithography and etching methods are used to form a plurality of trenches inside the silicon substrate. A high-temperature plasma (HDP) chemical vapor deposition method is used to form a first oxide layer over the silicon nitride layer and the trenches. Internally, "the first oxide layer only fills the bottom of the trench; using a high temperature oxidation method, a second oxide layer is deposited over the silicon substrate and the inner wall of the trench; a polycrystalline silicon layer is deposited over the silicon substrate" using a reaction Removable ion etching (R IE) and etch-back to remove the polycrystalline silicon layer of the portion, so that the upper surface of the polycrystalline silicon layer is lower than the upper portion of the trench; depositing a third oxide layer over the semiconductor element and the trench Internally, the third oxide layer is planarized by a chemical mechanical polishing method (CMP); and the third oxide layer is removed by a chemical mechanical polishing method (CMP) and an etch-back method, and a portion of the second oxide layer is removed. oxygen Layer and first oxide layer up to the polycrystalline layer Page 13 13. The method for manufacturing a semiconductor device according to item 12 of the scope of the patent application, wherein the above-mentioned / oxide layer 'placed inside the trench is disposed at the bottom of the trench. 14. The method for manufacturing a semiconductor element according to item 丨 2 of the scope of the patent application, wherein the above is placed on the inner side wall of the trench; the oxide layer is a resistance layer for leakage current. 15. The method for manufacturing a semiconductor device as described in the scope of the application for patent 2 丨 2, wherein the second oxide layer placed on the inner side wall of the trench is a gate oxide layer on the side wall of the gate. 16. The method for manufacturing a semiconductor device according to item 2 of the scope of the patent application, wherein the fourth dielectric layer planarization method 'is made by a chemical mechanical waste method or an etching method. 17. A method for manufacturing a semiconductor device includes at least the following steps. A semiconductor device is provided having a silicon substrate; a pad oxide layer is formed over the silicon substrate; a silicon nitride layer is deposited on the pad oxide layer Over; forming a photoresist layer over the silicon nitride layer; using the photoresist layer as a photomask, etching the pad oxide layer, silicon nitride, silicon substrate, and silicon substrate to form a shallow trench isolation region on silicon Inside the substrate; and 184 8 3 6. The scope of the patent application forms a crystalline silicon layer over the silicon substrate and inside the shallow trench isolation region ', and the crystalline silicon layer is used as a liner layer to deposit one or two inside the shallow trench isolation region. Mechanical polishing of silicon oxide over the semiconductor element to flatten the silicon dioxide layer; and removing the silicon nitride layer silicon layer by chemical mechanical polishing to the upper surface of the silicon substrate. 18. The silicon nitride layer of a semiconductor as described in item 17 of the scope of patent application can be made by a low-pressure chemical vapor deposition method, which uses a chemical rhenium oxide layer and a crystalline element / V. 19. · A method for manufacturing a semiconductor device 'includes at least the following steps: providing a semiconductor device having a silicon substrate; forming a pad oxide layer over the dream substrate; depositing a nitride oxide layer over the pad oxide layer Forming a photoresist layer over the silicon nitride layer; using the photoresist layer as a photomask, etching the pad oxide layer, the silicon nitride layer and the edge substrate to form a shallow trench isolation region; Inside the sand substrate; forming a thermal oxidation layer inside the shallow trench isolation area; > a day-to-day stone xi layer above the stone xi substrate and above the thermal oxidation layer of the shallow trench isolation area; Depositing silicon dioxide on the semiconductor device is to planarize the silicon dioxide layer by chemical mechanical polishing method; and remove the nitride by chemical mechanical polishing method; ε layer, hafnium oxide layer and crystal Page 15 4 184 88 Page 16