417295 A7 B7 經濟部中央揉率局員工消费合作社印S. 五、發明説明（） 發明領述：_ 本發明係有關於一種半導體記憶體之製程’特别是 有關於一種靜態随機存取記憶體之複晶電陴器及其製程 之方法。 發明背景： 靜態隨機存取記憶體（SRAM)具有快速和低電能消 耗且於系統中容易使用之特性，其原囡不外是SRAM不 像動態隨機儲取記憶體DRAM那樣需要有阉期性充電 (refresh)。因此，SRAM經常使用於高性能之小型系统， 在此，操作特性係高速且不需要快取。此外SRAM由於 僅需要低待命電能，因此也特别適用於以電池操作之系 統。就個人電腦而言，SRAM也常用於做爲快取記憶體 以改善系統處理器的等待時間。 圈一所示爲傳統之四電晶體兩複晶電阻器之SRAM 的電路圖。其中存取電晶體（access transistor)ll和12 分别連接節點N1和N2至位元線2 1和22。複晶電阻器 31和32和驅動電晶體41和42則用以操控節點Νι和 N2之電壓値。複晶電阻器31和32分别連接於一節點 N1和N2和一只電源供應器Vcce驅動電晶體41和42 則分别連接於節點N 1和N2和電壓參考源Vss之間，並 且其各别之閘極分别和節點N2和N1交又耦合β 本紙張尺度逋用中國國家標率（CNS > A4规格UIOX297公釐） 'I i i 裝 i i 訂 I i i 線 (请先M讀背面之注意事坧·,‘填寫本頁) 4Π295 A7 __B7 五、發明说明（） 在穩態下’節點N1和N2夕* z <各别的電壓値是互相 的。在節點N1之電壓値若是高 凡间I壓位準，將使得驅务 電晶體42之電壓開啓，此即將節 I卞即點N2之電壓位準拉7 至低電壓位準。當在節點N2之雷厭抒θ ^•尾壓値是低電壓位準， 則將使得驅動電晶體4 1之電壓關ρΕ| _ 电卺關閉，此即將節點N1泛 電壓位準拉同至高電壓位準β因办 ^ ^ 此—位元之資料就被Κ 住（latch)或者詋儲存於SRAM記愔睑c， 丨'《胞5疋内。除非有資 料要求寫入’否則儲存之資料將不含 1霄是動。此時儲取電 晶體之字語線1 〇將需要先開啓。 位π線2丨接至低重 位’此時將使得已問住之位元資料變動。 値得注意的是’電流1(和12，—直將維持在一電流 位準，例如電晶"關閉而電晶禮42帛啓時，此時 IiWVcc-Vds)/!^ ’ 而電流 i2 = (vc V cc Vth)/r2。因此，如果 欲使傳統方法之電流再進一步降低给 平低除非增大複晶電 器之阻値H這並不是—好的辦法，目爲其將使得 將資料留存於記憶胞内變得不穩定。換言之，製造高姓 能之複晶電阻器以解決上述之問題是一件重要的事二 發明目的及概述： (請先閱讀脊面之注意事項4填寫本育) -装· 订 經濟部中央揉準局貝工消費合作社印裝 本發明之一目的係提供一具有新穎結構之複^ 阻器之SRAM結構及其製造方法。 本發明之另一目的在提供比傳統之SRAM之4 電流値低。這是囡爲兩複晶電阻器之其尹之—複晶1 本紙張尺度追用中國國家搮準（CNS ) A4洗格（210X297公釐） 417295 A7 B7 經濟部中央橾率局貝工消費合作杜印製 五、發明説明（） 器的阻値會受偏壓而增大的緣故。 本發明係一種形成於半導體基板之靜態隨機存取 SRAM記憶胞，該半導體基板有第—驅動體電晶體 '第 一複晶電阻器及第一存取體電晶體在第一元件區而第 二驅動體電晶體、第二複晶電阻器及第二存取體電晶體 則在在第二元件區且以隔離區分隔β第一複晶電阻器形 成於一第一下埋接觸區上，該下埋接觸區由一第一複晶 矽層構成並且連接至第二驅動電晶體之閘極。第二複晶 電阻器則形成於一第二下埋接觸區上，速由第一複晶矽 層連接至第一驅動電晶體之閘極。一第一介複晶矽氧化 層（IP D1)形成於所有的區域。一第—連接線由_第二複 晶矽層建構於該IPD1層上，並經由一穿越IPD1之接觸 洞連接第一驅動電晶體閘極並與第一複晶電阻器連 接。一第二連接線由該第二複晶矽層建構於該IPD】層 上，經由一穿越IPD1之接觸洞連接該第二驅動電晶體 閘極及第二複晶電阻器。一第二介複晶矽氧化層（IPD2) 接著形成於第一連接線及第二連接線及IPD1的其他區 域上。 接著’在第三複晶矽層建構於IPD2建構第三至第 六連接線，其中之第三連接線連接一接地參考電位及經 由一穿越IPD2及IPD1之一第一源極接觸洞連接第一驅 動電晶體之源極。一第四.連接線連接一接地參考電-位及 經由第一源極接觸洞連接第一驅動電晶體之源極。第五 連接線連接一電源參考電位與該第一複晶電阻器，而第 本紙張尺度逋用中a國家標率（CNS } A4規格（2丨0X297公釐） .'----------^----.--^------0 {請先閲讀背面之注意事ΪΡ.4瑱寫本頁) 417295 八7 B7 五、發明説明（） 六連接線則連接上述電源參考電位與該第二複晶電阻 器。 圈式簡單説明： 本發明的較佳實施例將於往後之説明文字中輔以 下列圓形做更詳細的閣述： 圖一顯示一以傳統方法形成之4T-2R SRAM記憶胞 線路示意圖。 圖二顯示依據本發明之方法形成之4T_2R SRAM記 憶胞線路示意圖。 圖三顇示依據本發明之方法4T-2R SRAM記憶胞線 路怖局概略示意圖 圉四A及圖四B顯示依據本發明之方法的形成驅動 電晶體閘極及下埋區之分别沿圖三之a-a’線及b-b ’之橫 截面示意圈； 圖五 A及圖五 B顯示依據本發明之方法的形成 IPD 1、閘極接觸洞及第二複晶矽層之分别沿闺三之a_a’ 線及b-b’之橫截面示意圖； 圖六A及圖六B顯示依據本發明之方法圖案化第二 複晶矽層以形成連接線及形成IPD2後之分别沿圖三之 a-a’線及b-b’之橫截面示意圈； 圖七A及圖七B顯示依據本發明之方法的定義複晶 電阻器接觸洞位置後之分别沿囷三之a-a，線及b-b’之橫 本纸張尺度適用中國國家標率（CNS ) A4規格（210 X 297公釐） ^^|_ (#先閲讀脊面之注意事項彳填寫本頁 •ΤΓ 線 經濟部中央標準局員工消费合作社印装 經濟部中央樣準局貝工消费合作社印裝 417295 A7 B7 五、發明説明（） 截面示意圖； 圖八A及圖八B顯示依據本發明之方法的形成侧壁 氧化層於電阻器接觸洞側壁後之分别沿圖三之a_a’線及 b-b’之橫截面示意圖； 圖九A及圖九B顯示依據本發明之方法的形成P-型複晶矽於電―阻器接觸洞後之分别沿圈三之a'a’線及 b-b’之橫截面示意圈； 圖十A及圖十B顯示依據本發明之方法的形成驅動 電晶體源極接觸洞後之分别沿圖三之a_a’線及b-b，之橫 截面示意圖； 圖十一 A及圖十一 B顯示依據本發明之方法的形成 Vcc與複晶電阻器連接線與Vss與驅動電晶體連接線 後之分别沿圖三之a-a，線及b-b’之橫截面示意圈； 圖十二A及圖十二B顯示依據本發明之方法的形成 ILD以平坦化SRAM記憶胞後之分别沿圖三之a_a，線及 b-b’之橫截面示意圖；及 圖十三顯示依據本發明之方法形成之垂直複晶電 阻器受到偏壓後形成空乏區之示意圖。 發明詳細説明： 有鑑於發明背景所述，傳統之四電晶體二電阻的靜 態随機存取記憶體SRAM若欲進一步再減少待命下之 電流消耗時，純以增加複晶電阻器之電阻之方法並不實 本紙張尺度適用中國國家揉準（CNS > Α4规格（2丨0X297公釐） >----------^-------ΐτ------0 (請先閲讀膂面之注意事項七填寫本頁} 417^95 A7 B7 經濟部中央樣率局肩工消费合作杜印製 五、發明説明（） 際’因爲那會同時造成儲存之資料的保留變得不穩定。 因此這是一待克服的問題。 請參考圖二，示一 SRAM記憶胞1〇〇，類似於圖一之 電路圖’具有四個電晶體存取電晶體71和丁2和驅動電 时體TA和TB與兩只新結構之複晶電阻器ra和rb β其 中複晶電阻器ra和Rb是垂直的電阻器元件，分别連接 於節點N1和N2和一共同之電源供應器Vcc，此外，複 晶電阻器RA和Rb分别具有一端點，以交又耦合於節點 N2和N1。每一複晶電阻器係建構於一和深埋接觸區之 接觸洞（contact hole)之肀^其中接觸洞的側堃是一氧 化層。一 η-型雜質複晶矽層形成於接觸洞的底部，與接 觸洞之頂部。而一 ρ-型雜質摻雜的複晶矽層形成於上下 兩個複晶矽層之間。驅動電晶體ΤΑ和ΤΒ分别連接於節 點Ν1和Ν2與一共同之參考電壓Vss並且閘極交又糗合 於節點N2和N 1。兩個存取電晶體τ,和丁2則分别連接 於位元線71和72。 在記憶胞中假設一位元資料是被鬥住或者説被儲 存’使得節點N1和N 2分别爲高和低位準》當節點N j 是高電位時’複晶電阻器rb即被施以正偏壓（請參考囷 十二將給詳細的説明）於側壁上。因此，造成一空乏區 於電阻器内使得複晶電阻器RB之阻値升高。因此待命 之電流h將降低。不過，另一複晶電阻器R_a則因-爲沒 有任何偏壓而因此待命電流h不會受到影響，因此資料 保存於記憶胞1 0 0之電流不會受影響。 本紙張尺度適用中歯菌家揉準（CNS ) A4規格（210X297公釐） ；----------^------,ΤΓ------Μ. {請先閲讀背面之注意事贷4.填寫本頁) 417?95 Α7 Β7 五、發明説明（） 經濟部中央橾準局員工消费合作社印裝 以下將描繪形成高性能之複晶電阻器之SRAM記憶 胞： 圖三示分閘字語線（split-word-line)具有四電晶體及 兩個複晶電阻器之SRAM記憶胞1 00之佈局圖，圈中並 示依一實施例，其多層複晶矽層佈局如圖示。困四至圖 十二A及B之〜橫截面示意圖，將配合圖三一起描,續·，i I 且係沿著囷三中之a - a ’線和b - b，緣的截面.圖。請注意， SRAM分閘字語線將使得SRAM記憶胞對稱，因此，以 下的内容將只針對上述a-a’線和b-b’線的截面囷而言， 其餘之部分不存描繪。 請參考圏四A和圖四B，SRAM記憶胞係形成於半導 體基板1 02由形成隔離區1 04圍繞者元件區1 〇6開始。 其中隔離區104可以是場氧化層（FOX)以傳統區域氧化 層形成方法形成。半導體基板1 02則是一單晶矽摻雜以 硼》 在形成場氧化層104之後，施以高溫的熱氧化製程 以形成一閘極氧化層110於矽基板上。閘極氧化層11〇 在一較佳實施例中之厚度約爲5-7nm。之後，定義下埋 接觸區的位置112。再全面形成一複晶夕層12〇於所有 區域之上。以一較佳的實施例而言，形成之方法係以低 壓化學氣栢沉積法LPCVD同步摻雜以η-型導電性雜 質。當然也可以用其他的方法掺雜，例如沉積後再_施以 離子佈植，或者使基板在雜質源中擴散以雜質。接著在 施以微影和蝕刻技術以定義出電晶體ΤΑ和：後_里^屬 8 本纸張尺度速用中菌國家揉準（CNS ) Α4洗格（210X297公釐） ----------襄----：--ΐτ------^ t请先Mit背面之注意ί〆·*.填寫本X) 417295 a? B7五、發明説明（）417295 A7 B7 Printed by the Consumer Cooperative of the Central Rubbing Bureau of the Ministry of Economic Affairs S. V. Description of the Invention () Invention Summary: _ The present invention relates to a process for a semiconductor memory, and more particularly to a static random access memory. Complex crystal electric device and its manufacturing method. Background of the invention: Static random access memory (SRAM) has the characteristics of fast and low power consumption and easy to use in the system. The reason is that SRAM does not require periodic charging like dynamic random access memory DRAM. (refresh). Therefore, SRAM is often used in high-performance small systems. Here, the operating characteristics are high-speed and no cache is required. In addition, SRAM is particularly suitable for battery-operated systems because it only requires low standby power. For personal computers, SRAM is also commonly used as cache memory to improve system processor latency. Circle 1 shows the circuit diagram of the traditional SRAM with four transistors and two complex resistors. The access transistors 11 and 12 connect the nodes N1 and N2 to the bit lines 2 1 and 22, respectively. The multiple crystal resistors 31 and 32 and the driving transistors 41 and 42 are used to control the voltages 値 of the nodes No and N2. Compound resistors 31 and 32 are respectively connected to a node N1 and N2 and a power supply Vcce driving transistor 41 and 42 are respectively connected between nodes N 1 and N2 and a voltage reference source Vss, and they are respectively The gates are connected to nodes N2 and N1, respectively, and are coupled β This paper standard uses the Chinese national standard (CNS > A4 specification UIOX297 mm) 'I ii Binding ii Order I ii line (please read the precautions on the back first) ·, 'Fill in this page) 4Π295 A7 __B7 V. Description of the invention () In the steady state, the nodes N1 and N2 * z < the respective voltages 値 are mutually. If the voltage at the node N1 is higher than the voltage level I, the voltage of the driving transistor 42 will be turned on. This is the time when the voltage level at the point N2 is pulled to 7 to a low voltage level. When the thunder at the node N2 θ ^ • the tail voltage 値 is a low voltage level, the voltage of the driving transistor 41 will be turned off ρΕ | _ The electric voltage is turned off, which brings the general voltage level of node N1 to the high voltage Level β due to this ^ ^ This—bit data is latched or stored in the SRAM memory 愔 愔 eyebrow c, '' 《Cell 5 疋. Unless there is a data request for writing ’, the stored data will not contain any changes. At this time, the zigzag line 10 of the transistor will need to be turned on first. Bit π line 2 丨 is connected to the low-order bit ', which will cause the bit data that has been requested to change. It should be noted that 'current 1 (and 12, — will be maintained at a current level, such as when the transistor " is turned off and the transistor Jingli 42 is on, IiWVcc-Vds) /! ^' And the current i2 = (vc V cc Vth) / r2. Therefore, if you want to reduce the current of the traditional method to a lower level unless you increase the resistance of the polycrystalline electronics, this is not a good way. The purpose is to make the data stored in the memory cell unstable. In other words, it is an important matter to manufacture high-resistance multi-crystal resistors to solve the above problems. The purpose and summary of the invention: (Please read the notes on the ridge first and fill in this education.) One objective of the present invention is to provide a SRAM structure with a novel structure of a resistor and a manufacturing method thereof. Another object of the present invention is to provide a current lower than that of a conventional SRAM. This is one of the two complex crystal resistors—the compound one. The paper size follows the Chinese National Standards (CNS) A4 wash (210X297 mm) 417295 A7 B7. The central government bureau of the Ministry of Economic Affairs and the shellfish consumer cooperation Du printed 5. Invention Description The resistance of the device will increase due to bias. The invention relates to a static random access SRAM memory cell formed on a semiconductor substrate. The semiconductor substrate has a first driving body transistor, a first complex crystal resistor and a first access body transistor in a first element region and a second The driving body transistor, the second polycrystalline resistor and the second accessing body transistor are formed on a first lower buried contact region in the second element region and separated by an isolation region. The first polycrystalline resistor is formed by The buried contact region is composed of a first polycrystalline silicon layer and is connected to the gate of the second driving transistor. A second polycrystalline resistor is formed on a second buried contact region, and is connected from the first polycrystalline silicon layer to the gate of the first driving transistor. A first dielectric polycrystalline silicon oxide layer (IP D1) is formed in all regions. A first-connecting line is constructed on the IPD1 layer by a second polycrystalline silicon layer, and is connected to the first driving transistor gate through a contact hole passing through the IPD1 and is connected to the first polycrystalline resistor. A second connection line is constructed on the IPD layer by the second polycrystalline silicon layer, and the second driving transistor gate and the second polycrystalline resistor are connected through a contact hole passing through the IPD1. A second dielectric polycrystalline silicon oxide layer (IPD2) is then formed on the first and second connection lines and other areas of IPD1. Next, 'the third polycrystalline silicon layer is constructed on IPD2 to construct the third to sixth connection lines, wherein the third connection line is connected to a ground reference potential and connected to the first via a first source contact hole passing through IPD2 and IPD1. Source of driving transistor. A fourth. The connecting line connects a ground reference potential and the source of the first driving transistor through the first source contact hole. The fifth connection line connects a power reference potential to the first compound resistor, and the national standard (CNS} A4 specification (2 丨 0X297 mm) of the first paper standard is used .'------ ---- ^ ----.-- ^ ------ 0 {Please read the notes on the back (PP.4) first write this page) 417295 8 7 B7 5. Description of the invention () Connect the power supply reference potential to the second compound resistor. Brief description of the circle method: The preferred embodiment of the present invention will be supplemented by the following circles in the following explanatory text: Figure 1 shows a schematic diagram of a 4T-2R SRAM memory cell circuit formed by a conventional method. Figure 2 shows a schematic diagram of a 4T_2R SRAM memory cell circuit formed according to the method of the present invention. Figure 3 shows a schematic diagram of a 4T-2R SRAM memory cell circuit according to the method of the present invention. Figures 4A and 4B show the formation of a driving transistor gate and a buried region according to the method of the present invention. A-a 'line and bb' cross-section schematic circle; Figure 5A and Figure 5B show the formation of IPD 1, gate contact hole and second polycrystalline silicon layer along the third a_a according to the method of the present invention. Schematic cross-sections of 'line and b-b'; Figures 6A and 6B show the second polycrystalline silicon layer patterned according to the method of the present invention to form a connection line and a-a along Figure 3 after forming IPD2, respectively. A cross-section schematic circle of 'line and b-b'; FIG. 7A and FIG. 7B show the definition of the polycrystalline resistor contact hole position according to the method of the present invention along the lines aa, b, and b-b ' The horizontal paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ^^ | _ (#Read the precautions for the ridge first. Fill out this page. ΤΓ Department of Economics Central Standards Bureau staff consumption Cooperative Cooperatives Printed by the Central Procurement Bureau of the Ministry of Economic Affairs Shellfish Consumer Cooperatives 417295 A7 B7 V. Description of Invention ( Fig. 8A and Fig. 8B show cross-sectional schematic diagrams of forming a sidewall oxide layer according to the method of the present invention after the resistor contacts the sidewall of the hole along a_a 'line and b-b' in Fig. 3; Fig. 9 A and FIG. 9B show the schematic cross-sections of the P-type polycrystalline silicon according to the method of the present invention after the electrical-resistor contact hole along the a'a 'line and b-b' of circle three, respectively; Fig. 10A and Fig. 10B show cross-sectional schematic diagrams along the lines a_a 'and bb' of Fig. 3, respectively, after forming the source contact hole of the driving transistor according to the method of the present invention; Fig. 11A and Fig. 11B show the basis In the method of the present invention, after forming the connection lines of Vcc and complex crystal resistors and the connection lines of Vss and driving transistor, the schematic cross-sections along the lines aa, line and b-b 'in FIG. 3 are respectively; FIG. 12A and FIG. 2B shows a schematic cross-sectional view along the lines a_a, line and b-b 'of FIG. 3 after forming the ILD to flatten the SRAM memory cell according to the method of the present invention; and FIG. 13 shows a vertical formed by the method of the present invention Schematic diagram of forming a depletion region after a complex resistor is biased. Detailed description of the invention In view of the background of the invention, if the traditional four-transistor two-resistor static random access memory SRAM wants to further reduce the current consumption under standby, the method of purely increasing the resistance of the compound resistor is not practical Paper size applies to Chinese national standard (CNS > Α4 size (2 丨 0X297mm) > ---------- ^ ------- ΐτ ------ 0 (Please First read the precautions on the front page 7. Fill in this page} 417 ^ 95 A7 B7 Printed by the Ministry of Economic Affairs, Central Sample Rate Bureau, Consumer Cooperation, Du V. Invention Description (International) Because it will also cause the retention of stored data to become Unstable. So this is a problem to be overcome. Please refer to FIG. 2, which shows a SRAM memory cell 100, which is similar to the circuit diagram of FIG. 1. It has four transistor access transistors 71 and D2, and drive transistors TA and TB with two new structures. Resistors ra and rb β, where the polycrystalline resistors ra and Rb are vertical resistor elements, which are respectively connected to the nodes N1 and N2 and a common power supply Vcc. In addition, the polycrystalline resistors RA and Rb each have an end point. Is coupled to nodes N2 and N1 with intersection. Each polycrystalline resistor is formed in a contact hole of a deep buried contact area. The side of the contact hole is an oxide layer. An η-type impurity polycrystalline silicon layer is formed on the bottom of the contact hole and on the top of the contact hole. A p-type impurity-doped polycrystalline silicon layer is formed between the upper and lower polycrystalline silicon layers. The driving transistors TA and TB are respectively connected to the nodes N1 and N2 and a common reference voltage Vss and the gate intersections are coupled to the nodes N2 and N1. Two access transistors τ, and D2 are connected to bit lines 71 and 72, respectively. In the memory cell, it is assumed that a piece of metadata is held or stored so that the nodes N1 and N2 are at the high and low levels, respectively. When the node N j is at a high potential, the compound resistor rb is applied positively. Bias (please refer to the detailed description of XII) on the side wall. Therefore, the formation of an empty region in the resistor increases the resistance of the polycrystalline resistor RB. Therefore, the standby current h will decrease. However, the other complex resistor R_a has no bias voltage, so the standby current h will not be affected, so the current stored in the memory cell 100 will not be affected. The size of this paper is applicable to the standard CNS A4 (210X297 mm); ---------- ^ ------, TΓ ------ M. {Please First read the note on the back 4. Fill out this page) 417? 95 Α7 Β7 V. Description of the invention () Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs The following will depict the SRAM memory cell that forms a high-performance compound resistor : Figure 3 shows the layout of a SRAM memory cell 100 with a split-word-line with four transistors and two complex-crystal resistors. The circle shows a multi-layer complex-crystal according to an embodiment. The layout of the silicon layer is shown in the figure. Figures 4 through 12 are schematic cross-sections of A and B. They will be described in conjunction with Figure 3. Continued, i I is a cross-section of the edge along the line a-a ′ and b-b, in Figure 3. Please note that the SRAM opening word line will make the SRAM memory cell symmetrical. Therefore, the following content will only refer to the cross section 囷 of the a-a ′ line and b-b ’line above, and the rest will not be depicted. Please refer to FIG. 4A and FIG. 4B. The SRAM memory cell is formed on the semiconductor substrate 102 by forming the isolation region 104 and surrounding the device region 106. The isolation region 104 may be a field oxide layer (FOX) formed by a conventional area oxide layer formation method. The semiconductor substrate 102 is a single crystal silicon doped with boron. After the field oxide layer 104 is formed, a high-temperature thermal oxidation process is performed to form a gate oxide layer 110 on the silicon substrate. The gate oxide layer 110 has a thickness of about 5-7 nm in a preferred embodiment. After that, the position 112 of the buried contact area is defined. Then, a complex crystal layer 12 is formed on all regions. In a preferred embodiment, the formation method is simultaneous doping with η-type conductive impurities by low pressure chemical vapor deposition method LPCVD. Of course, other methods can be used for doping, for example, after deposition, ion implantation can be performed, or the substrate can be diffused with impurities in the impurity source. Next, lithography and etching techniques were applied to define the transistor TA and the rear-line genus. 8 paper-scale quick-use medium bacteria national standard (CNS) Α4 wash grid (210X297 mm) ----- ----- XIANG ----: --ΐτ ------ ^ t Please note the back of Mit first 〆 · *. Fill out this X) 417295 a? B7 V. Description of the invention ()
經濟部智慧財產局員工消費合作社印製 1 1 2以形成複晶電阻器R a如圖四；\所示。此外，第一複 晶矽層I 2 0也連接複晶電阻器RA和電晶體T3與存取電 晶體ΤI如圖四Β所示。 仍請參考圖四Α和圖四Β，接著，在閉極電極和下埋 接觸區形成之後以離子佈植以形成源/汲極區1 3 0 » 如圖五A和圖五B所示，一第一介複晶矽介電層（以 下稱為I PD 1 )接著形成於所有之電晶體和Ts，T1以及 複晶電阻器L上》IPDI係一氧化層如LPTEOS或臭氧 TEOS，例如以LPCVD方法配合以TEOS氣體以形成，厚度 約為2 0 0 - 4 0 0 nm »為形成連接部分，微影和蝕刻依序實 施以定義電晶體之閘極1 2 0的接觸洞丨4 0以及電晶體 T3之閘極的接觸洞145於IPD1之中。在去除微影之光 阻後，第二複晶矽層1 5 0接著形成以填入接觸洞1 4 0和 1 4 5。與及在I PD 1的其他位置》第二複晶矽層1 5 0之摻 雜方法則類似於第一複晶矽層同屬於η -盤導電性雜質 摻雜。 請參考圖六Α和圖六Β °對第二複晶石夕層1 5 0施以圖 案化用以連接驅動電晶體，例如電晶體Τα和複晶電阻器 RA。第二介複晶矽介電層I PD2 1 6 0再接著沉積於第二複 晶矽層丨5 0之上以及I PD 1上之其餘位置。I PD2 1 6 0則 係以類似IP D 1之方法形成。 請參考圖七A和圖七B。一光阻圖案（未圖示）具有一 開口區對準其下之下埋接觸區1丨2 (開口在下埋接觸區 範圍内），形成於I PD2上以定義複晶電阻器L。接著， J-------1¾衣-------W-------^ (請先閱讀背面之注意事項再填.{马本貫) 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨Ο X 297公釐} 經濟部中央橾準局員工消费合作社印製 417295 A7 B7 五、發明説明（） 再以非等向性蝕刻去除未遮罩之IPD2 1 60，並穿過第二 複晶矽層150、IPD1 135並停止於第一複晶矽12〇上。 再去除光阻圖案（未圖示以一較佳的實施例而言，蚀 刻係分段完成，即先以蝕刻氧化層的蝕刻氣體配方蚀刻 IPD2 1 60，再換以蝕刻複晶矽層的配方，最後再更換以 蝕刻氧化層的配方蝕刻IPD1 1 3 5。 請參考圖八A和圈八B，一薄的氧化層首先以PECVD 法或者以高溫的熱氧化製程形成於接觸洞18〇之内壁和 底部’再施以非等向性蝕刻法形成於側壁氧化層19〇。 形成之側壁氧化層190的厚度約介於20-50 nm之間。 围九A和圖九B示形成p-型雜質掺雜之複晶矽層 195摻雜以硼離子以回填上述之接觸洞，並且掺雜之濃 度約爲lxl015-lxl〇16/Cm3再施以回蝕刻以氧化層爲終 止層，以形成複晶電阻器r A。 如圖十A和囷十B示形成一接觸洞開口 210，用以 接觸源極區130。形成之步雄係先以光阻（未圊示）形成 於IPD2 160上以定義接觸區21〇，再施以非等向性蝕刻 以去除未罩幕之IPD2 160、和IP D1 135至半導體基板 102之源極區130。再去除光阻囷案。 請參照圖十一 A和圔十一 b，一第三複晶矽層220 具有η-型雜質摻雜，接著形成以回填接觸洞210及接觸 洞1 8 0。然後再施以微影’和蝕刻以圈案化第三複晶梦層 220用以連接複晶電阻器Ra至電源供應Vcc，及連接驅 動電晶趙TB及TA至接地參考電位vss。 本紙張尺度通用中國國家揉準（CNS ) A4规格（210X297公釐） ：----------^----^--ΤΓ------0 (請先閲讀背面之注意Ϋπ·-)·.填寫本頁) 417295 A7 B7 五、發明説明（） 最後，請參考圖十二A和圖十二B，再形成内連線 介電層23 0以塡平所有區域以便進行金屬導線連接之製 程。 圖十三係複晶電阻器RB受正偏壓之情形。換言之， 節點N 1的電壓位準是高電位。圖中之空乏區2 4 0沿侧 壁形成於p-型複晶矽層之中，致使RB之電阻値升高。 t * 箭頭所示爲電流h之方向。 本發明所提供之四電晶體二電阻的形成技術，具有 以下之優點： (1) 新型複晶電阻器可以使本發明之SRAM比傳 統方法SRAM之待命電流大量減少。 (2) 在相同之電流消耗基準而言，本發明之SRAM 可以有更佳的資料穩定度。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之申請專利範圍：凡其它未脱離本發明所揭 示之精神下所完成之等效改變或修飾，均應包含在下述 之申請專利範圍内。 ----------¾.------tr------0 (請先閲讀背面之注意事π .-ft填寫本頁) 經濟部中央標準局貝工消費合作杜印製 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐）The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed 1 1 2 to form a complex crystal resistor R a as shown in Figure 4; In addition, the first polycrystalline silicon layer I 2 0 also connects the polycrystalline resistor RA, the transistor T3, and the access transistor TI as shown in FIG. 4B. Still referring to FIG. 4A and FIG. 4B, then, after the closed electrode and the buried contact region are formed, ion implantation is performed to form a source / drain region 1 3 0 »As shown in FIGS. 5A and 5B, A first dielectric polycrystalline silicon dielectric layer (hereinafter referred to as I PD 1) is then formed on all transistors and Ts, T1 and the polycrystalline resistor L. An IPDI-based oxide layer such as LPTEOS or ozone TEOS, for example, based on The LPCVD method is formed with TEOS gas and has a thickness of about 2 0-4 0 0 nm. »To form the connection part, lithography and etching are sequentially performed to define the contact hole of the gate 1 2 0 of the transistor. 4 0 and The contact hole 145 of the gate of the transistor T3 is in IPD1. After the photoresist of the lithography is removed, a second polycrystalline silicon layer 150 is then formed to fill the contact holes 140 and 145. The doping method of the second polycrystalline silicon layer 150 in other locations of I PD 1 is similar to that of the first polycrystalline silicon layer, which is also doped with n-disk conductive impurities. Please refer to FIG. 6A and FIG. 6B to pattern the second polycrystalline stone layer 150 to connect the driving transistor, such as the transistor Tα and the compound resistor RA. A second dielectric polycrystalline silicon dielectric layer I PD2 16 0 is then deposited on the second polycrystalline silicon layer 5 0 and the remaining positions on I PD 1. I PD2 1 6 0 is formed in a similar way to IP D 1. Please refer to Figure 7A and Figure 7B. A photoresist pattern (not shown) has an opening area aligned with the lower buried contact area 1 丨 2 (the opening is in the range of the lower buried contact area), and is formed on the I PD2 to define the polycrystalline resistor L. Next, J ------- 1¾ clothing ------- W ------- ^ (Please read the notes on the back before filling in. {马 本)) This paper size applies to Chinese national standards ( CNS) A4 specification (2 丨 〇 X 297 mm) printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 417295 A7 B7 V. Description of the invention () Then remove the unmasked IPD2 1 60 by anisotropic etching, and Pass through the second polycrystalline silicon layer 150, IPD1 135 and stop on the first polycrystalline silicon 120. Then remove the photoresist pattern (not shown in a preferred embodiment, the etching is completed in sections, that is, First etch IPD2 1 60 with the etching gas formula for etching the oxide layer, then change the formula for etching the polycrystalline silicon layer, and finally change the formula for etching the oxide layer with IPD1 1 3 5. Please refer to Figure 8A and circle 8B. A thin oxide layer is first formed on the inner wall and the bottom of the contact hole 180 by PECVD or a high-temperature thermal oxidation process, and then is formed on the sidewall oxide layer 19 by anisotropic etching. The formed sidewall oxide layer 190 The thickness is about 20-50 nm. Wai Jiu A and Figure 9B show the formation of a p-type impurity-doped polycrystalline silicon layer 195 doped with boron. The backfill is filled with the above-mentioned contact hole, and the doping concentration is about lxl015-lx1016 / Cm3, and then an etchback is performed with the oxide layer as a termination layer to form a polycrystalline resistor r A. B shows the formation of a contact hole opening 210 for contacting the source region 130. The step of formation is to form a photoresist (not shown) on the IPD2 160 to define the contact region 21, and then apply anisotropy Etching to remove the unmasked IPD2 160 and IP D1 135 to the source region 130 of the semiconductor substrate 102. Then remove the photoresist scheme. Please refer to Figures 11A and 11b, a third polycrystalline silicon layer 220 is doped with n-type impurities, and is then formed to backfill the contact hole 210 and the contact hole 180. Then lithography and etching are used to circle the third polycrystalline dream layer 220 to connect the polycrystalline resistor Ra to the power supply Vcc, and to connect the drive transistor Zhao TB and TA to the ground reference potential vss. This paper size is common Chinese National Standard (CNS) A4 specification (210X297 mm): ---------- ^ ---- ^-ΤΓ ------ 0 (Please read the note on the back Ϋπ ·-) ·. Fill out this page) 417295 A7 B7 V. Description of the invention () Finally, Referring to FIG. 12A and FIG. 12B, an interconnect dielectric layer 230 is formed to flatten all areas for metal wire connection. FIG. 13 shows a case where a complex crystal resistor RB is subjected to a positive bias. In other words, the voltage level of the node N 1 is a high potential. The empty region 240 in the figure is formed in the p-type polycrystalline silicon layer along the side wall, which causes the resistance RB of the RB to increase. The t * arrow shows the direction of the current h. The formation technology of the four-transistor two-resistor provided by the present invention has the following advantages: (1) The new type of multi-crystal resistor can greatly reduce the standby current of the SRAM of the present invention over the conventional method SRAM. (2) In terms of the same current consumption benchmark, the SRAM of the present invention can have better data stability. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention: all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of the patent application. ---------- ¾ .------ tr ------ 0 (Please read the note on the back π.-ft to fill out this page) The Central Standards Bureau of the Ministry of Economy Cooperative Du printed paper size applicable to China National Standard (CNS) A4 (210X297 mm)