WO2019142081A1 - Semiconductor device and method for operating same - Google Patents

Semiconductor device and method for operating same Download PDF

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Publication number
WO2019142081A1
WO2019142081A1 PCT/IB2019/050207 IB2019050207W WO2019142081A1 WO 2019142081 A1 WO2019142081 A1 WO 2019142081A1 IB 2019050207 W IB2019050207 W IB 2019050207W WO 2019142081 A1 WO2019142081 A1 WO 2019142081A1
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Prior art keywords
voltage
transistor
circuit
semiconductor device
switch
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PCT/IB2019/050207
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French (fr)
Japanese (ja)
Inventor
國武寛司
本田龍之介
熱海知昭
Original Assignee
株式会社半導体エネルギー研究所
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Priority to CN201980007097.XA priority Critical patent/CN111542880A/en
Priority to US16/959,771 priority patent/US11430791B2/en
Priority to KR1020207019634A priority patent/KR20200108835A/en
Priority to JP2019566003A priority patent/JP7196103B2/en
Publication of WO2019142081A1 publication Critical patent/WO2019142081A1/en
Priority to US17/892,190 priority patent/US11963343B2/en
Priority to JP2022199322A priority patent/JP7444959B2/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G11C11/4023—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • This specification describes a semiconductor device, an operation method thereof, a manufacturing method thereof, and the like.
  • a semiconductor device is a device utilizing semiconductor characteristics, and refers to a circuit including a semiconductor element (eg, a transistor, a diode, a photodiode, or the like), a device including the circuit, or the like. In addition, it refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including the integrated circuit, and an electronic component in which the chip is stored in a package are examples of a semiconductor device.
  • the memory device, the display device, the light-emitting device, the lighting device, the electronic device, and the like may each be a semiconductor device and may include the semiconductor device.
  • IGZO In-Ga-Zn oxides called “IGZO”, "Igoso”, etc. are representative of multi-element metal oxides.
  • CAAC c-axis aligned crystalline
  • nc nanocrystalline
  • a transistor having a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as an “oxide semiconductor transistor” or an “OS transistor”) is reported to have a minimal off-state current (eg, non-off current).
  • Various semiconductor devices using OS transistors have been manufactured (for example, Non-Patent Documents 3 and 4).
  • the manufacturing process of the OS transistor can be incorporated into a CMOS process with a conventional Si transistor, and the OS transistor can be stacked on the Si transistor (for example, Non-Patent Document 4).
  • the Si transistor can easily control the threshold voltage by introducing an impurity.
  • highly reliable manufacturing techniques for controlling the threshold voltage of the OS transistor have not been established. Therefore, the OS transistor is provided with a first gate electrode (also referred to as a gate or a front gate) and a second gate electrode (also referred to as a back gate), and the voltage of the second gate electrode is controlled.
  • the threshold voltage is controlled (for example, Patent Document 1).
  • An object of one embodiment of the present invention is, for example, to provide a semiconductor device capable of acquiring a threshold voltage of a transistor, to provide a semiconductor device in which performance variation due to temperature is suppressed, and to provide a highly reliable semiconductor device. Or providing a low power consumption semiconductor device.
  • One embodiment of the present invention is a semiconductor device including a first transistor, a first capacitive element, a first output terminal, a first switch, and a second switch, and the gate and the source of the first transistor are electrically connected.
  • the first terminal and the first output terminal of the first capacitive element are electrically connected to the back gate of the first transistor, the second terminal of the first capacitive element is electrically connected to the source, and the first switch is
  • the semiconductor device controls an input of a first voltage to the back gate, a second voltage is input to a drain of the first transistor, and a second switch controls an input of a third voltage to a source.
  • One mode of the present invention is a method of operating the semiconductor device of the above mode (1), wherein the first switch and the second switch are turned on, the first switch is turned on, and the second switch is turned on. Turning off, turning off the first switch and turning off the second switch, turning off the first switch, and turning on the second switch.
  • ordinal numbers such as “first”, “second”, “third” and the like may be used to represent the order. Or, it may be used to avoid confusion of components. In these cases, the use of ordinal does not limit the number of components of one aspect of the invention.
  • the “first” can be replaced with the “second” or the “third” to describe one embodiment of the present invention.
  • X and Y are functionally connected when X and Y are electrically connected, and It is assumed that the case and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, the present invention is not limited to a predetermined connection relation, for example, the connection relation shown in the figure or the sentence, and it is assumed that something other than the connection relation shown in the figure or the sentence is also disclosed in the figure or the sentence.
  • X and Y each denote an object (eg, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like).
  • the voltage often indicates the potential difference between a certain potential and a reference potential (for example, the ground potential (GND) or the source potential). Therefore, the voltage can be reworded as a potential. Note that the potential is relative. Therefore, even if it is described as GND, it may not necessarily mean 0V.
  • a reference potential for example, the ground potential (GND) or the source potential.
  • a node can be reworded as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on a circuit configuration, a device structure, and the like.
  • terminals, wires, and the like can be paraphrased as nodes.
  • membrane and layer can be interchanged with one another, as the case may be or depending on the circumstances. For example, it may be possible to change the term “conductive layer” to the term “conductive film”. For example, it may be possible to change the term “insulating film” to the term “insulating layer”.
  • a semiconductor device capable of acquiring a threshold voltage of a transistor, a semiconductor device having suppressed performance fluctuation due to temperature, a semiconductor device having high reliability, or It becomes possible to provide a semiconductor device with low power consumption.
  • FIG. 2 is a functional block diagram showing a configuration example of a semiconductor device.
  • A A diagram illustrating a transistor having a back gate.
  • B Equivalent circuit diagram of a transistor having a back gate.
  • A A circuit diagram showing a configuration example of a monitor circuit.
  • B A timing chart showing an operation example of the monitor circuit.
  • a to D A circuit diagram showing an operation example of a monitor circuit.
  • A Input waveform of monitor circuit in simulation.
  • B A diagram showing simulation results of the monitor circuit.
  • FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device.
  • 5 is a timing chart showing an operation example of a semiconductor device.
  • FIG. 2 is a functional block diagram showing a configuration example of a semiconductor device.
  • FIG. 2 is a functional block diagram showing a configuration example of a semiconductor device.
  • A A circuit diagram showing a configuration example of a circuit.
  • B Timing chart showing an operation example of the circuit.
  • a to D A circuit diagram showing a configuration example of a memory cell array.
  • FIG. 2 is a functional block diagram showing a configuration example of a storage device.
  • B Timing chart showing an example of power gating of a storage device.
  • FIG. 2 is a functional block diagram showing an exemplary configuration of a processor.
  • FIG. 7 is a circuit diagram showing an example of the configuration of a flip flop.
  • FIG. 8 illustrates an example of an electronic device.
  • B, C sectional views showing an example of configuration of an OS transistor.
  • B, C A cross-sectional view showing a configuration example of an OS transistor.
  • the power supply potential VDD may be abbreviated as potential VDD, VDD, or the like.
  • potential VDD voltages, circuits, elements, electrodes, wirings, etc.
  • the second wiring GL is described as a wiring GL [2].
  • FIG. 1 is a functional block diagram of the semiconductor device 100.
  • the semiconductor device 100 includes a semiconductor device 110 and a voltage output circuit 120.
  • the semiconductor device 110 has a transistor M1.
  • the voltage output circuit 120 has a monitor circuit 130.
  • the monitor circuit 130 has a function of monitoring fluctuations in the electrical characteristics of the transistor M1.
  • the voltage output circuit 120 adjusts the voltage VOT1 based on the information acquired by the monitor circuit 130.
  • the semiconductor device 110 is supplied with the voltage VOT1 from the voltage output circuit 120.
  • the threshold voltage of the transistor M1 will be described with reference to FIGS. 2A and 2B.
  • the transistor M1 includes a source (S), a drain (D), a gate (G), a back gate (BG), and a semiconductor layer.
  • the gate and the back gate are disposed above and below the semiconductor layer, and a channel formation region is provided in the semiconductor layer.
  • the transistor M1 is turned on or off according to the voltage difference between the gate and the source (hereinafter referred to as voltage Vgs) or the back gate and the source (hereinafter referred to as voltage Vbgs).
  • voltage Vgs becomes larger than VTg
  • a channel may be formed (or carriers may be induced) in the region on the gate side of the semiconductor layer.
  • the transistor M1 has two threshold voltages VTg and VTbg.
  • VTg is a threshold voltage for the voltage Vgs
  • VTbg is a threshold voltage for the voltage Vbgs.
  • the transistor M1 When Vgs> VTg or Vbgs> VTbg, the transistor M1 is turned on. Therefore, the transistor M1 has a function equivalent to that of the circuit 10 (see FIG. 2B) in which the transistor Ma1 having a threshold voltage of VTg and the transistor Ma2 having a threshold voltage of VTbg are electrically connected in parallel. It can be said that
  • VTg depends on Vbgs
  • VTbg depends on Vgs.
  • the conditions under which the transistor M1 is turned on may be expressed by the following formula (1.1).
  • VT 0 is a constant voltage
  • Cg is a gate capacitance per unit area between the gate and the semiconductor layer
  • Cbg is a back gate per unit area between the back gate and the semiconductor layer It is a capacity.
  • VTg can be represented by a linear function of Vbgs shown in equation (1.2).
  • VTg (1 + Cbg / Cg) ⁇ VT 0 ⁇ Cbg / Cg ⁇ Vbgs (1.2)
  • the threshold voltage VTg may indicate the voltage Vgs when Id ⁇ L / W is 1 ⁇ 10 ⁇ 12 [A].
  • the threshold voltage VTbg may indicate a voltage Vbgs when Vgs is 0 V and Id ⁇ L / W is 1 ⁇ 10 ⁇ 12 [A].
  • the threshold voltage VTg of the transistor having a back gate is calculated from the Vgs ⁇ Id 1/2 characteristic when Vbgs is 0V.
  • FIG. 3A shows a circuit configuration example of the monitor circuit 130.
  • the monitor circuit 130 includes transistors M1r, M11, and M12, a capacitive element C11, nodes Srb and Srs, and terminals a1 to a6.
  • the transistors M1r, M11, and M12 are OS transistors having a back gate.
  • the nodes Srb and Srs correspond to the back gate and the source of the transistor M1r, respectively.
  • the voltage VBGM1 is input to the back gates of the transistors M11 and M12. A voltage different from the voltage VBGM1 may be input to the back gate of the transistor M12.
  • the gate and drain of the transistor M1r are electrically connected to the node Srs and the terminal a4, respectively.
  • the gate, source, and drain of the transistor M11 are electrically connected to the terminal a1, the node Srb, and the terminal a3, respectively.
  • the gate, source, and drain of the transistor M12 are electrically connected to the terminals a2 and a5 and the node Srs, respectively.
  • the first terminal and the second terminal of the capacitive element C11 are electrically connected to the nodes Srb and Srs, respectively.
  • Terminals a1 and a2 receive the signals MON1 and MON2, respectively.
  • the low level (“L”) and the high level (“H") of the signals MON1 and MON2 are VSSA and VDDA, respectively.
  • the voltage VSSA may be, for example, 0 V or GND.
  • Terminals a3, a4, and a5 receive voltages V1, V2, and VSSA, respectively.
  • the terminal a6 is an output terminal of the monitor circuit 130, and is electrically connected to the node Srb.
  • the monitor circuit 130 has a function of monitoring the threshold voltage VTbg of the transistor M1r.
  • the transistor M1r is typically a replica transistor of the transistor M1 and has the same specifications as the transistor M1. For example, by changing the back gate voltage Vbg and / or the gate voltage Vg of the transistor M1 based on the information on the threshold voltage VTbg of the transistor M1r acquired by the monitor circuit 130, the threshold voltage of the transistor M1 Variations of VTg and / or VTbg can be corrected.
  • threshold voltages VTg (T) and VTbg (T) of the transistor M1r and voltages Vgs, Vbgs and Vds are denoted as VTg (T) _r, VTbg (T) _r, Vgs_r, Vbgs_r and Vds_r, respectively.
  • VTg (T) _r threshold voltages VTg (T) _r
  • VTbg (T) _r voltages, Vbgs_r and Vds_r
  • the operating temperature range of the semiconductor device 100 is Tmin or more and Tmax or less, and the best case and the worst case of the temperature are Tmin and Tmax, respectively.
  • FIG. 3B is a timing chart of the monitor circuit 130 in the periods TT1 to TT4.
  • FIGS. 4A to 4D are simplified circuit diagrams showing the operation of the monitor circuit 130 in the periods TT1 to TT4, respectively.
  • the transistors M11 and M12 are indicated by switches.
  • Vrs and Vrb are voltages of the nodes Srs and Srb, respectively, and Id_r is a drain current of the transistor M1r.
  • the temperature is Tm.
  • Period TT1 Initialization operation
  • the monitor circuit 130 receives the “H” signals MON1 and MON2.
  • VSSA and V1 are input to the nodes Srs and Srb, respectively.
  • V1r is an n-channel transistor
  • V2 V1-VTbg (Tmax) _r + Va> VSSA (2.2)
  • Period TT2 In order to turn off the transistor M12, the signal MON2 of "L" is input to the monitor circuit 130.
  • the node Srs is electrically floating.
  • the capacitive element C11 is charged by the drain current Id_r, and the voltage Vrs rises. Therefore, the voltage Vbgs_r decreases, and the transistor M1r operates in the subthreshold region.
  • the transistor M1r is turned off, and the voltage Vrs converges to V1-VTbg (Tm) _r. Note that in order to facilitate understanding of the operation of the monitor circuit 130, leakage currents of the transistors M1r, M11, and M12 are ignored.
  • the voltage Vds_r of the transistor M1r is larger than 0 V in the operating temperature range even in the state where the voltage Vrs converges to V1-VTbg (Tm) _r.
  • the voltage VBGM1 is preferably a sufficiently low voltage to suppress the fluctuation of the voltage Vbgs_r.
  • the signal MON2 of “H” is input to the monitor circuit 130 in order to turn on the transistor M12 in the period TT4.
  • the voltage VSSA is input to the node Srs. Since the voltage difference between the node Srb and the node Srs is fixed to VTbg (Tm) _r, the voltage Vrb is VTbg (Tm) _r + VSSA.
  • the voltage Vrb is output from the terminal a6 as the voltage Vmon. Since the voltage VSSA is a power supply voltage and does not depend on the electrical characteristics of the transistor M1r, acquiring the voltage Vmon of the terminal a6 corresponds to acquiring the threshold voltage VTbg (Tm) _r. For example, if the voltage VSSA is 0 V, the voltage Vmon is equal to the threshold voltage VTbg (Tm) _r.
  • the threshold voltages VTbg (Tm) _r and VTg (Tm) _r have the relationship of formula (1.3), and the transistor M1r is a replica transistor of the transistor M1. Therefore, by using voltage Vmon, temperature-induced variations in threshold voltage VTg and / or VTbg of transistor M1 can be corrected.
  • Voltage output circuit 120 generates voltage VOT1 based on voltage Vmon. For example, by using the voltage VOT1 as a bias voltage input to the back gate of the transistor M1, a change in temperature of the threshold voltage VTg of the transistor M1 can be corrected. In another example, in the semiconductor device 110, by adjusting the voltage of “H” and / or “L” of the gate voltage of the transistor M1 based on the voltage VOT1, the on current characteristics and the off current characteristics of the transistor M1 are obtained. Changes due to temperature can be corrected.
  • FIG. 5A is a timing chart of the monitor circuit 130 in simulation.
  • the voltages VSSA, VDDD, V1, and V2 are 0 V, 3.3 V, 2.5 V, and 2.9 V, respectively.
  • the voltage VBGM1 is 0V. Since the voltage VSSA is 0 V, the voltage Vmon is equal to the threshold voltage VTbg_r. Assuming that only the threshold voltages VTg_r and VTbg_r of the transistor M1r change with temperature, several voltage values were set to the threshold voltage VTg_r, and the voltage Vmon was calculated for each voltage value.
  • FIG. 5B is a simulation result, showing the change of the voltage Vmon with respect to the threshold voltage VTg_r. FIG. 5B shows that the change of the threshold voltage VTg_r with temperature can be monitored by acquiring the voltage Vmon.
  • the monitor circuit 130 Since the number of elements of the monitor circuit 130 is very small, the monitor circuit 130 can be easily provided in the vicinity of the transistor M1. In this case, the electrical characteristics of the transistor M1 can be corrected with higher accuracy. By using the monitor circuit 130, temperature correction of the electrical characteristics of the transistor M1 can be performed without providing a temperature sensor. Therefore, by using the monitor circuit 130, even when the temperature correction function of the threshold voltage of the transistor M1 is added to the semiconductor device 100, the penalty of the area and energy of the semiconductor device 100 can be suppressed. Further, the monitor circuit 130 itself can be used as a temperature sensor.
  • the transistors M11 and M12 are not limited to the OS transistors.
  • an n-channel or p-channel Si transistor can be used.
  • the transistors M11 and M12 are Si transistors, the off-current characteristics of the transistors M11 and M12 are not sufficient. Therefore, if the operating frequency is too low, fluctuations in the voltages Vrb and Vrs are not allowed in the periods TT3 and TT4. .
  • the transistors M11 and M12 are OS transistors with extremely small off-state current, the fluctuation of the voltages Vrb and Vrs can be suppressed, so the operating frequency of the monitor circuit 130 does not have to be higher than necessary. Therefore, dynamic power consumption of the monitor circuit 130 can be suppressed.
  • the transistors M11 and M12 can be transistors without back gates. In this case, in order to improve the off current characteristics of the transistors M11 and M12, for example, when the transistors M11 and M12 are n-channel transistors, “L” of the signals MON1 and MON2 may be lower than VSSA. If the transistors M11 and M12 are p-channel transistors, “H” of the signals MON1 and MON2 may be higher than VDDA.
  • the transistor M1 can be a back gateless transistor.
  • the difference between the transistor M1r and the transistor M1 is the presence or absence of a back gate. Correcting the variation of the on current characteristic and / or the off current characteristic of the transistor M1 by adjusting the voltage of “H” and / or “L” input to the gate of the transistor M1 using the voltage Vmon it can.
  • the transistors M1 and M1r are not limited to OS transistors, and are not limited to n-channel transistors.
  • the transistors M1 and M1r can be, for example, n-channel or p-channel Si transistors.
  • FIG. 6 shows a circuit diagram of a monitor circuit 131 using a p-channel transistor M2r in place of the transistor M1r. Since the function of the monitor circuit 131 is the same as that of the monitor circuit 130, the same sign as that of the monitor circuit 130 is used as the sign of the voltage and current of the monitor circuit 131.
  • the voltage VDDA is input to the terminal a5.
  • the voltages V1, V2, Va are set such that the polarities of the voltages Vgs_r, Vbgs_r, Vds_r of the transistor M2r and the drain current Id_r are opposite to those of the transistor M1r.
  • the voltages V1, V2, and Va satisfy the equations (2.4) to (2.6).
  • V2 V1 ⁇ VTbg (Tmax) _r + Va ⁇ VDDA (2.5) VTbg (Tmin) _r ⁇ VTbg (Tmax) _r + Va ⁇ 0 (2.6)
  • the operation of the monitor circuit 131 will be described using the timing chart of FIG. 3B.
  • the operation of the monitor circuit 131 is the same as that of the monitor circuit 130, so the description is simplified.
  • Period TT1 The transistors M11 and M12 are on, and the nodes Srs and Srb receive the voltages VDDA and V1.
  • the transistor M2r exhibits normally on characteristics in order to satisfy the formulas (2.4) to (2.6).
  • the voltage Vds_r is smaller than 0V. Thus, the drain current Id_r flows.
  • Period TT4 The transistor M12 is turned on, and the voltage VDDA is input to the node Srs. Since the voltage difference between the node Srb and the node Srs is fixed to VTbg (Tm) _r, the voltage Vrb is VTbg (Tm) _r + VDDA. The voltage Vrb is output from the terminal a6 as the voltage Vmon. Since the voltage VDDA is a power supply voltage and does not depend on the electrical characteristics of the transistor M2r, the threshold voltage VTbg (Tm) _r can be acquired from the voltage Vmon of the terminal a6.
  • a semiconductor device 101 illustrated in FIG. 7 includes a semiconductor device 110 and a voltage output circuit 122.
  • the voltage output circuit 122 has a voltage correction circuit 150, a voltage generation circuit 170, and an output terminal OUT2.
  • the voltage generation circuit 170 outputs a voltage Vpw.
  • the voltage correction circuit 150 corrects the voltage Vpw to generate a voltage VOT2.
  • the output terminal OUT2 outputs a voltage VOT2.
  • the voltage VOT2 is used as a voltage VBG1 input to the back gate of the transistor M1 in the semiconductor device 110.
  • the voltage correction circuit 150 includes a monitor circuit 130, capacitive elements C12 and C13, a reset circuit 132, a source follower circuit 134, an operational amplifier 136, and a switch circuit 138.
  • the first terminal and the second terminal of the capacitive element C12 are electrically connected to the output terminal (node Srb) of the monitor circuit 130 and the input terminal of the source follower circuit 134, respectively.
  • nodes corresponding to the input terminal and the output terminal of the source follower circuit 134 are referred to as nodes Srt and Ssf, respectively.
  • the reset circuit 132 is a circuit for resetting the node Srt, and includes a transistor M14.
  • the transistor M14 is an OS transistor having a back gate.
  • the source of the transistor M14 is electrically connected to the node Srt, and the signal RST1 and the voltages VBGR1 and V4 are input to the gate, the back gate, and the drain, respectively.
  • the source follower circuit 134 includes transistors M15 and M16 electrically connected in series.
  • the transistors M15 and M16 are n-channel Si transistors.
  • Voltages VBIS1 and VSSA are input to the gate and source of the transistor M15.
  • the gate of the transistor M16 corresponds to the node Srt.
  • the voltage V3 is input to the drain of the transistor M16.
  • the inverting input terminal of the operational amplifier 136 is electrically connected to the node Ssf, and the voltage VSSA is input to the non-inverting input terminal.
  • the node Sap corresponds to the output terminal of the operational amplifier.
  • Ri and Rf are an input resistance and a feedback resistance, respectively.
  • the transistor of the operational amplifier 136 is, for example, a Si transistor.
  • the first terminal and the second terminal of the capacitive element C13 are electrically connected to the node Sap and the output terminal OUT2, respectively.
  • the capacitive element C13 holds the voltage VOT2 of the output terminal OUT2.
  • Switch circuit 138 controls an electrical connection between the output terminal of voltage generation circuit 170 and output terminal OUT2.
  • the switch circuit 138 includes, for example, an analog switch circuit 138a and an inverter circuit 138b.
  • the signal SET1 controls the on / off of the analog switch circuit 138a.
  • the analog switch circuit 138a and the inverter circuit 138b are configured by, for example, Si transistors.
  • the voltage generation circuit 170 includes a control circuit 171 and a charge pump circuit 173.
  • Control circuit 171 generates gated clock signal GCLK1 (hereinafter referred to as clock signal GCLK1) in response to signal WAKE1 and clock signal CLK1.
  • the clock signal GCLK1 is input to the charge pump circuit 173.
  • charge pump circuit 173 operates.
  • the charge pump circuit 173 shown in FIG. 8 is a four-stage step-down charge pump circuit, and generates a voltage Vpw from GND.
  • the charge pump circuit 173 includes two inverter circuits, four diode-connected transistors, and four capacitive elements.
  • the transistor is an OS transistor having a back gate, and the back gate and the drain are electrically connected to each other.
  • the transistor of the charge pump circuit 173 may be an OS transistor having no back gate.
  • the transistor may be an n-channel or p-channel Si transistor, not limited to an OS transistor.
  • the OS transistor is suitable for the charge pump circuit 173 because the ratio of the on current / off current is higher in the OS transistor than in the Si transistor.
  • the voltage generation circuit 170 may not be provided in the voltage output circuit 122, and GND or the voltage VSSA may be input to the voltage correction circuit 150 as the voltage Vpw.
  • t0 to t8 represent time.
  • the temperature Tm between t0 and t5 is Tp1
  • the temperature Tm between t6 and t8 is Tp2.
  • the control circuit 171 Since the signal WAKE1 is “H” during t0 to t1, the control circuit 171 generates an active clock signal GCLK1.
  • the charge pump circuit 173 performs a step-down operation.
  • the voltage Vpw decreases and eventually reaches the voltage VINT.
  • the transistor M1 of the semiconductor device 101 is not driven.
  • the signal WAKE1 becomes "L", and the charge pump circuit 173 stops the step-down operation.
  • the signals RST1 and SET1 are set to "H" to initialize the node Srt and the output terminal OUT2.
  • the voltages V4 and VINT are input to the node Srt and the output terminal OUT2.
  • the voltage V4 may be, for example, VDDA / 2.
  • the monitor circuit 130 is operated while the signals SET1 and RST1 are fixed at "H” to acquire the threshold voltage VTbg_r (Tp1).
  • the voltage Vrb is VTbg_r (Tp1) + VSS.
  • the voltages of the signals MON1 and MON2 are undefined.
  • the signal SET1 is set to "L” to stop the input of the voltage VINT to the output terminal OUT2.
  • the relationship between the threshold voltage VTbg_r and the threshold voltage VTg_r is represented by a linear function
  • the relationship between the threshold voltage VTg_r and the back gate voltage Vbg_r is represented by a linear function
  • the operating temperature In the range, it is preferable to set the threshold voltages of the transistors M14 and M15 and the voltages V4 and VBIS1 so that the input / output characteristics of the source follower circuit 134 exhibit linearity.
  • the operational amplifier 136 amplifies the voltage Vsf to generate a voltage Vap. Therefore, voltage Vap depends on threshold voltage VTbg_r (Tp1). Since the switch circuit 138 is off, the voltage VOT2 changes according to the voltage Vap, the capacitance of the capacitive element C13, and the parasitic capacitance of the output terminal OUT2, to become VINT + ⁇ Vout2 (Tp1).
  • the voltage ⁇ Vout2 (Tp1) is a correction voltage of the voltage VOT2 at the temperature Tp1.
  • the gain, the resistances of Rf and Ri), the capacitances of the capacitive elements C12 and C13, and the like are set.
  • ⁇ Vout2 (Tm) depends on the output voltage Vrb of the monitor circuit 130. When the temperature Tm rises, the voltage Vrb increases. In order to correct the fluctuation of the threshold voltage VTg of the transistor M1, ⁇ Vout2 (Tm) is decreased as the temperature Tm increases, and ⁇ Vout2 (Tm) is increased as the temperature Tm decreases. From the above, the operational amplifier 136 is configured by an inverting amplifier circuit.
  • the voltage VOUT2 changes from VINT and eventually stabilizes at Vbg (Tp1).
  • driving of the transistor M1 is started at time t5.
  • the voltage Vbg (Tp1) is input to the back gate of the transistor M1.
  • the monitor circuit 130 is operated to acquire the threshold voltage VTbg_r (Tm) again.
  • the driving of the transistor M1 is stopped.
  • the monitor circuit 130 acquires the threshold voltage VTbg_T (Tm2).
  • the voltage Vrb is fixed at VTbg_r (Tm2) + VSS
  • the voltage VOUT2 is stabilized at Vbg (Tm2).
  • the driving of the transistor M1 is resumed at time t8.
  • the operations of t5 to t8 are repeated. For example, after the operation of t5 to t8 is performed a predetermined number of times, the operation of t0 to t6 may be performed.
  • the threshold voltage VTbg_r (Tm) is periodically acquired by the monitor circuit 130, whereby a voltage suitable for the operating temperature can be input to the back gate of the transistor M1. As a result, it is possible to periodically correct the variation of the threshold voltage VTg of the transistor M1 due to the temperature.
  • a semiconductor device 102 illustrated in FIG. 10 includes a semiconductor device 112 and a voltage output circuit 124.
  • the semiconductor device 112 has N (N is an integer of 1 or more) power domains 118 [1] to 118 [N] to which the voltage VBG1 is supplied.
  • a transistor M1 is provided in each of the power domains 118 [1] to 118 [N].
  • the voltage output circuit 124 has a voltage generation circuit 170, a voltage correction circuit 160, and N output terminals OUT2 [1] to OUT2 [N].
  • the voltage correction circuit 160 includes N voltage correction circuits 150 [1] to 151 [N].
  • the voltage generation circuit 170 supplies the voltage Vpw to the voltage correction circuits 150 [1] to 151 [N].
  • the voltage correction circuits 150 [1] to 150 [N] correct the voltages VOT2 [1] to VOT2 [N] of the output terminals OUT2 [1] to OUT2 [N].
  • a semiconductor device 103 illustrated in FIG. 11 includes a semiconductor device 113 and a voltage output circuit 122.
  • the semiconductor device 113 includes a driver circuit 114, a wiring GL2, and a transistor M2.
  • the gate of the transistor M2 is electrically connected to the wiring GL2.
  • the driver circuit 114 receives the voltages VDDA, VIH2, VSSA, and VIL2.
  • the voltages VDDA and VSSA are power supply voltages.
  • the output voltage VOT2 of the voltage output circuit 122 is used as a voltage VIL2 in the driver circuit 114.
  • the voltage output circuit 124 illustrated in FIG. 10 may be used.
  • the voltage correction circuit 150 corrects "L" of the wiring GL2 in accordance with the temperature. For example, let VINT be VIL2 (Tref) at the reference temperature Tref.
  • the difference between the transistor M1r and the transistor M2 is the presence or absence of a back gate.
  • the transistor M2 may have a back gate. In this case, the back gate inputs a constant voltage. Alternatively, it is electrically connected to any one of the gate, the source, and the drain.
  • the driver circuit 114 has a circuit 114A shown in FIG. 12A.
  • the circuit 114A generates a signal SELG for selecting the wiring GL.
  • Voltages VIH2, VIL2, VSSA, and signals WIN, WINB are input to the circuit 114A.
  • Signal WINB is an inverted signal of signal WIN.
  • FIG. 12B shows a timing chart of the circuit 114A.
  • the circuit 114A outputs the signal SELG of "H” to the wiring GL when the signal WIN is “H”, and outputs the signal SELG of "L” to the wiring GL when the signal WIN is “L”.
  • the “H” and “L” of the signals WIN and WINB are the voltages VDDA and VSSA, respectively.
  • the “H” and “L” of the signal SELG are the voltages VIH2 and VIL2.
  • the circuit 114A is used as a level shifter for level shifting the signal WIN.
  • the voltage VIL2 is adjusted by the voltage output circuit 122, the voltage VIL2 decreases as the temperature rises. Therefore, even if the threshold voltage VTg of the transistor M2 is lowered due to the temperature rise, the increase of the off current of the transistor M2 can be canceled by lowering the voltage VIL2.
  • the semiconductor device 103 may be provided with a voltage output circuit that adjusts the voltage VIH2.
  • the operational amplifier of the voltage output circuit be constituted by a non-inverted amplifier circuit. Even if the threshold voltage VTg of the transistor M2 is increased due to the temperature decrease, the voltage VIH2 can be increased, so that the decrease of the on current of the transistor M2 can be canceled.
  • the storage device 200 illustrated in FIG. 13A includes power domains 210 and 211, and power switches 241 to 243.
  • a control circuit 220 and a peripheral circuit 221 are provided in the power domain 210.
  • a memory cell array 222 and a voltage output circuit 271 are provided in the power domain 211.
  • the storage device 200 receives the voltages VDDD, VSSS, VDHW, VDHR, the clock signal GCLK2, the address signal ADDR, the signal PSE1, and a command signal (eg, chip enable signal CE, write enable signal WE, byte write enable signal BW). .
  • the voltages, signals, and the like input to the storage device 200 are appropriately discarded according to the circuit configuration, the operation method, and the like of the storage device 200.
  • the control circuit 220 generally controls the entire storage device 200 to write and read data.
  • the control circuit 220 processes the address signal ADDR and an external command signal to generate a control signal of the peripheral circuit 221.
  • the signal PSE1 controls on / off of the power switches 241-243.
  • the signal PSE1 is transmitted from, for example, a PMU (power management device).
  • the power switches 241 to 243 respectively control inputs of the voltages VDDD, VDHW, and VDHR to the power domain 210. While the control circuit 220 and the peripheral circuit 221 do not need to be operated, the power switches 241 to 243 are turned off to powergate the power domain 210.
  • the memory cell array 222 includes a memory cell 20, a write word line WWL, a read word line RWL, a write bit line WBL, a read bit line RBL, and wirings PL and BGCL1.
  • the wiring BGCL1 is electrically connected to the voltage output circuit 271.
  • the voltages VDDD and VSSS are voltages representing data “1” and “0”, respectively.
  • the voltages VDHW and VHDR are voltages of "H" of the write word line WWL and the read word line RWL, respectively.
  • the peripheral circuit 221 has, for example, a function of selecting the memory cell 20 specified by the address signal ADDR. Specifically, peripheral circuit 221 has a function of selecting write word line WWL and read word line RWL in the selected row, a function of writing data in write bit line WBL in a column designated by address signal ADDR, and It has a function of reading data from the column read bit line RBL.
  • the memory cell 20 is a 2T1C (two-transistor / one-capacitance) type gain cell, and includes transistors M21 and M25 and a capacitive element C25.
  • the capacitive element C25 is a holding capacitance for holding the gate voltage of the transistor M25.
  • the transistors M21 and M25 are a write transistor and a read transistor, respectively.
  • the transistor M21 is an OS transistor having a back gate
  • the transistor M25 is a p-channel Si transistor.
  • the transistor M25 can be an n-channel Si transistor or an OS transistor.
  • the memory cell array 222 can be stacked on the control circuit 220 and the peripheral circuit 221, so that the memory device 200 can be miniaturized.
  • the voltage output circuit 124 is applied to the voltage output circuit 271.
  • the voltage output circuit 271 includes a voltage generation circuit 276 and a voltage correction circuit 277.
  • the voltage generation circuit 276 steps down the voltage VSSS to generate a voltage Vpw.
  • the voltage correction circuit 277 is provided with a replica transistor of the transistor M21.
  • the voltage VOT2 generated by the voltage correction circuit 277 is input to the wiring BGCL1 as a voltage VBGC1.
  • the voltage generation circuit 276 may be provided outside the storage device 200.
  • the voltage generation circuit 276 may not be provided.
  • the driver circuit 114 illustrated in FIG. 11 may be applied to a circuit that generates a signal for selecting the write word line WWL of the peripheral circuit 221.
  • the voltage output circuit 271 may not be provided, and a constant voltage may be input from the outside as the voltage VBGC1.
  • the number of rewrites of the memory cell 20 is not limited, and data rewrite can be performed with low energy, and no power is consumed for data retention.
  • the memory cell 20 can hold data for a long time because the transistor M ⁇ b> 21 is a minimal off-current OS.
  • the change of the threshold voltage VTg of the transistor M21 changes the write time and the hold time of the memory cell 20.
  • the threshold voltage VTg is lowered, so that the holding time is shortened.
  • the threshold voltage VTg increases, so that the write time becomes longer.
  • the storage device 200 can realize the same performance as that at the reference temperature Tref.
  • the memory cell array 222 is divided into a plurality of blocks to which the voltage VBGC1 is input, providing the monitor circuit in the vicinity of the memory cell array 222 enables the performance of the process-induced memory cell 20 to be reduced. The effect of correcting the variation is obtained. Therefore, a storage device 200 with high retention characteristics, long life, low power consumption, and high reliability can be provided.
  • the memory cell array 223A shown in FIG. 14A includes a memory cell 21, a write word line WWL, a read word line RWL, a write bit line WBL, a read bit line RBL, and wirings PL, CNL, and BGCL1.
  • the memory cell 21 is a 3T gain cell, and includes transistors M21, M25, and M26, and a capacitive element C25.
  • the transistor M26 is a selection transistor.
  • the transistors M25 and M26 may be n-channel Si transistors or OS transistors.
  • the memory cell array 223B shown in FIG. 14B includes the memory cells 22, the write word lines WWL, the read word lines RWL, the write bit lines WBL, the read bit lines RBL, and the wirings PL, BGCL1 to BGCL3.
  • the memory cell 22 includes transistors M21 to M23 and a capacitive element C22.
  • the transistors M22 and M23 are a read transistor and a select transistor, respectively.
  • the capacitive element C22 is a storage capacitor that holds the gate voltage of the read transistor M22.
  • the transistors M22 and M23 are OS transistors having a back gate.
  • the back gates of the transistors M22 and M23 are electrically connected to the wirings BGCL2 and BGCL3, respectively.
  • the voltages VBGC2 and VBGC3 are input from the voltage output circuits 272 and 273 to the wirings BGCL2 and BGCL3, respectively.
  • the voltage output circuits 272 and 273 have the same configuration as the voltage output circuit 271, and are provided in the power domain 212.
  • the voltage output circuits 272 and 273 are provided with replica transistors of the transistors M22 and M23, respectively.
  • the threshold voltages VTg of the transistors M21 to M23 can be optimized by the voltages VBGC1 to VBGC3. In order to increase the retention time, the threshold voltage VTg of the transistor M21 is maximized. In order to improve the reading speed, VTg of the transistor M22 is lowered to improve the on-current characteristic. In this case, an increase in the leakage current from the non-selected memory cell 22 to the read bit line RWL becomes a problem. The leakage current from the non-selected memory cell 22 not only shortens the retention time but also causes a data read error. Therefore, it is preferable that the transistor M23 gives priority to the off current characteristic over the on current characteristic. Therefore, VTg of the transistor M23 is smaller than VTg of the transistor M22. It is preferable that VBGC1 to VBGC3 satisfy VBGC1 ⁇ VBGC3 ⁇ VBGC2.
  • a part of the voltages VBGC1 to VBGC3 may not be temperature-corrected.
  • a constant voltage is input to the wiring BGCL3, and the voltages of the wirings BGCL1 and BGDL2 are corrected by the voltage output circuits 271 and 272.
  • a memory cell array 222C shown in FIG. 14C is a modification of the memory cell array 223B, and includes a memory cell 23, a write word line WWL, a read word line RWL, a write bit line WBL, a read bit line RBL, and wirings PL, BGCL1 to BGCL2.
  • the memory cell 23 differs in the connection between the memory cell 22 and the capacitive element C22.
  • Memory cell 23 has the same features as memory cell 22.
  • a memory cell array 223D illustrated in FIG. 14D includes memory cells 24, bit lines BL and BLB, word lines WL, and wirings CNL and BGCL1.
  • the memory cell 23 is a 1T1C type cell, and includes a transistor M21 and a capacitive element C21.
  • the memory cell arrays 223B to 223D are formed of the OS transistor and the capacitor, and thus can be stacked over the control circuit 220 and the peripheral circuit 221.
  • the storage device 202 illustrated in FIG. 15 includes power domains 213 to 215 and power switches 244 to 248.
  • the storage device 202 includes voltages VDDD, VSSS, VDDM, VDML, VSSM, an address signal ADDR, a clock signal GCLK3, command signals (eg, chip enable signal CE, write enable signal WE, byte write enable signal BW), signals PSE3 to PSE5.
  • command signals eg, chip enable signal CE, write enable signal WE, byte write enable signal BW
  • PG power gating
  • control signals shown as PG control signals in the figure
  • Voltages, signals, and the like input to the storage device 202 are appropriately discarded according to the circuit configuration, the operation method, and the like.
  • the signal PSE3 controls on / off of the power switches 244, 245.
  • the power switches 244, 245 control the supply of the voltages VDDD, VDHB to the power domain 213.
  • the power domain 213 is provided with a control circuit 225, a peripheral circuit 226, and a backup control circuit 227.
  • the signal PSE4 controls the on / off of the power switches 246 and 247
  • the signal PSE5 controls the on / off of the power switch 248.
  • the power switches 246 to 248 control the supply of the voltages VDDM, VSSM and VDML to the power domain 214.
  • a memory cell array 228 is provided in the power domain 214. Memory cell array 228 has a plurality of memory cells 30.
  • Power domain 215 is not power gated.
  • the power domain 215 is provided with a voltage output circuit 274.
  • the voltage output circuit 274 has the same configuration as the voltage output circuit 271 and includes a voltage generation circuit 278 and a voltage correction circuit 279.
  • the voltage VOT2 generated by the voltage correction circuit 279 is input to the memory cell array 228 as a voltage VBGC4.
  • the memory cell array 228 illustrated in FIG. 15 includes a memory cell 30, a word line WL, bit lines BL and BLB, and wirings OGL, BGCL4, V_VDM, and V_VSM.
  • the wiring V_VDM is a virtual power supply line whose input of voltage is controlled by the power switches 246 and 248, and the wiring V_VSM is a virtual power supply line whose input of voltage is controlled by the power switch 247.
  • the voltage VDHB is a high level voltage of the wiring OGL and is a voltage higher than VDDM.
  • the memory cell 30 has a memory cell 32 and a backup circuit 35.
  • the memory cell 32 has the same circuit configuration as a standard 6T (transistor) SRAM cell, and includes transistors MT1 and MT2, nodes Q / Qb, and a latch circuit 33.
  • the latch circuit 33 is electrically connected to the word line WL, the bit lines BL and BLB, and the wirings V_VDM and V_VSM.
  • Wiring V_VDM is a virtual power supply line whose input of voltage is controlled by power switches 246 and 248.
  • Wiring V_VSM is a virtual power supply line whose input of voltage is controlled by power switch 247.
  • the power switch 247 can be omitted. In this case, in place of the wiring V_VSM, for example, a wiring for supplying the voltage VSSS may be provided.
  • the backup circuit 35 backs up the data of the memory cell 32.
  • the backup circuit 35 has a pair of two T1C-type memory cells including transistors M31 and M32, and capacitive elements C31 and C32.
  • the holding nodes of these memory cells are the nodes SN21 and SN22.
  • the transistors M31 and M32 are OS transistors having a back gate.
  • the gates of the transistors M31 and M32 are electrically connected to the wiring OGL.
  • the wiring OGL is driven by the backup control circuit 227.
  • the back gates of the transistors M31 and M32 are electrically connected to the wiring BGCL4.
  • the voltage VBG4 from the voltage correction circuit 279 is input to the wiring BGCL4.
  • the specifications of the transistors M31 and M32 are the same, and the voltage correction circuit 279 is provided with a replica transistor of the transistor M31. Therefore, since the variation due to the temperature of the threshold voltage VTg of the transistors M31 and M32 can be corrected by the voltage VBG4, the highly reliable backup circuit 35 can be provided.
  • the driver circuit 114 may be applied to the backup control circuit 227 to control the gate voltage of the transistors M31 and M32. In this case, the voltage output circuit 274 may not be provided.
  • the PG control signal determines the low power consumption mode of the storage device 202.
  • the low power consumption mode is set based on the signals PSE4 to PSE6 and the PG control signal. These signals are transmitted from, for example, the PMU. By providing a plurality of low power consumption modes with different BETs, the power consumption of the storage device 202 can be efficiently reduced.
  • bit line floating mode the bit line pair (BL, BLB) is brought into a floating state.
  • the data in the memory cell 31 is not lost.
  • power domain 214 is supplied with voltage VDML lower than voltage VDDM.
  • the voltage VDML is a size that does not cause the data in the memory cell 32 to disappear.
  • the bit line pair (BL, BLB) is in a floating state.
  • the power switches 246 to 248 are turned off to stop the supply of the voltages VDDM, VDML, and VSSM to the power domain 214.
  • the bit line pair (BL, BLB) is brought into a floating state. The data in memory cell 32 is lost.
  • ⁇ Power gating sequence> An example of a power gating sequence for the power domain 214 is shown in FIG. 16B.
  • the state of the storage device 202 is a normal operation state (write state or read state).
  • the storage device 202 operates similarly to a single port SRAM.
  • the power switches 244, 246 to 248 are on, and the power switch 245 is off.
  • the control circuit 225 centrally controls the entire storage device 202 to write and read data.
  • the control circuit 225 processes the address signal ADDR and an external command signal (for example, a chip enable signal CE, a write enable signal WE, a byte write enable signal BW) to generate a control signal of the peripheral circuit 226.
  • an external command signal for example, a chip enable signal CE, a write enable signal WE, a byte write enable signal BW
  • the backup sequence starts in response to the PG control signal.
  • the backup control circuit 227 sets all the wires OGL to "H".
  • node Q / Qb is "H” / "L”
  • node SN31 / SN32 is "L” / "H”. Therefore, when transistors M31 and M32 are turned on, the voltage of node SN31 Increases from VSSM to VDDM, and the voltage of the node SN32 drops from VDDM to VSSM.
  • the signal PGM becomes "L” at time t2
  • the backup operation is completed. Data of node Q / Qb at time t1 is written to node SN31 / SN32.
  • the peripheral circuit 226 and the backup control circuit 227 perform the recovery operation according to the PG control signal.
  • latch circuit 33 functions as a sense amplifier for detecting data on nodes Q / Qb.
  • peripheral circuit 226 precharges all bit line pairs (BL, BLB).
  • Voltage Vpr2 is input to all bit line pairs (BL, BLB).
  • peripheral circuit 226 sets all word lines WL to the selected state.
  • the wirings V_VDM and V_VSM are precharged to the voltage Vpr2, and the nodes Q and Qb are fixed to the voltage Vpr2.
  • the backup control circuit 227 makes all the wiring OGL "H".
  • the transistors M31 and M32 are turned on.
  • the charge of the capacitive element C31 is distributed to the node Q and the node SN31
  • the charge of the capacitive element C32 is distributed to the node Qb and the node SN32
  • a voltage difference occurs between the node Q and the node Qb.
  • the power switches 246 and 247 are turned on to resume the input of the voltages VDDM and VSSM to the power domain 214.
  • latch circuit 33 amplifies the voltage difference between node Q and node Qb.
  • the voltages of the nodes Q and SN31 become VDDM, and the voltages of the nodes Qb and SN32 become VSSM. That is, the state of the node Q / Qb returns to the state ("H" / "L") at time t1.
  • the recovery operation is finished, and the normal operation is started.
  • the backup circuit 35 can realize performance similar to that at the reference temperature Tref. Therefore, it is possible to suppress the shortening of the retention time due to the temperature rise and the increase of the backup and recovery time due to the temperature fall. Therefore, the storage device 202 with high reliability and low power consumption can be provided.
  • a monitor circuit 130 can be provided as a temperature sensor.
  • the refresh cycle or the timing of power gating can be changed according to the output voltage of the monitor circuit 130.
  • the processor 300 illustrated in FIG. 17 includes buses 305 and 306, a bus bridge 307, a CPU 310, a storage device 312, a PMU 314, a clock control circuit 315, a power supply circuit 316, a memory control circuit 317, a functional unit 318, and an interface (I / F) unit. It has 319.
  • the internal circuit of the processor 300 is discarded as appropriate.
  • the processor 300 may be provided with a GPU.
  • the internal circuits of the processor 300 are connected to be able to transmit and receive data mutually by buses 305 and 306 and a bus bridge 307.
  • the PMU 314 controls the clock control circuit 315 and the power supply circuit 316.
  • the PMU 314 controls clock gating and power gating of internal circuits (for example, the CPU 310, the storage device 312, the bus 305, and the like) of the processor 300.
  • the memory control circuit 317 controls an external storage device.
  • the processor 300 can be used as an application processor. Therefore, various circuits are provided in the function unit 318 and the interface unit 319 so that the processor 300 can control various peripheral devices.
  • the functional circuits provided in the functional unit 318 include, for example, a display control circuit 321, a graphic processing circuit 322, a video processing circuit 323, an audio processing circuit 324, an audio processing circuit, a timer circuit, an ADC (analog digital conversion circuit), etc. .
  • the interface unit 319 includes, for example, peripheral component interconnect express (ePCI), I-squared-C (I-squared-C, inter integrated circuit), mobile industry processor interface (MIPI), universal serial bus (USB), serial peripheral interface (SPI) Such as HDMI (registered trademark) / DP (High-Definition Multimedia Interface / Display Port), eDP (embedded Display Port), DSI (Display Serial Interface), etc. Circuit corresponding to the rank is provided.
  • ePCI peripheral component interconnect express
  • I-squared-C I-squared-C, inter integrated circuit
  • MIPI mobile industry processor interface
  • USB universal serial bus
  • SPI serial peripheral interface
  • HDMI registered trademark
  • DP High-Definition Multimedia Interface / Display Port
  • eDP embedded Display Port
  • DSI Display Serial Interface
  • the storage device of the second embodiment is applied to the storage device 312.
  • a plurality of types of storage devices 312 may be provided in the processor 300.
  • the PMU 314 generates a control signal of the power switch used by the storage device 312 and a PG control signal.
  • the voltage generation circuit 276 may be provided in the power supply circuit 316. The same applies to the storage device 202.
  • the CPU 310 includes a CPU core, a cache memory device, a voltage output circuit 345, a level shifter 348, a power switch 349, and the like (see FIG. 18).
  • the CPU core is provided with a flip flop 340 shown in FIG.
  • the power switch 349 controls the supply of the voltage VDD to the CPU core.
  • the on / off of the power switch 349 is controlled by a signal PSE9 generated by the PMU 314.
  • the flip flop 340 has a scan flip flop 341 and a backup circuit 342. Providing the backup circuit 342 in the flip flop 340 enables power gating of the CPU core.
  • the scan flip flop 341 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 341A.
  • the clock buffer circuit 341A has two inverters, nodes CK1 and CKB1.
  • the node RT is an input node of the reset signal.
  • the circuit configuration of the scan flip flop 341 is not limited to that shown in FIG.
  • the flip flops provided in the standard circuit library can be applied.
  • the node D1 is a data input node
  • the node Q1 is a data output node
  • the node SD is an input node for scan test data, and is electrically connected to the node SD_IN of the backup circuit 342.
  • the scan enable signal SCE, the reset signal RST4, and the clock signal GCLK4 are input to the nodes SE, CK, and RT.
  • the scan enable signal SCE is generated by the PMU 314, and the reset signal RST 4 and the clock signal GCLK 4 are generated by the clock control circuit 315.
  • the PMU 314 generates a recovery signal RC and a backup signal BK.
  • the level shifter 348 shifts the level of the recovery signal RC and the backup signal BK, and outputs the recovery signal RCH and the backup signal BKH to the backup circuit 342.
  • the backup circuit 342 includes nodes SD_IN and SN35, transistors M35 to M37, and a capacitive element C35.
  • Node SD_IN is electrically connected to node Q 1 of another scan flip flop 341.
  • the node SN35 is a holding node of the backup circuit 342.
  • Capacitive element C35 is a holding capacitance for holding the voltage of node SN35.
  • the parasitic capacitance due to the transistor M35 is to be added to the node Q1, it is smaller than the parasitic capacitance due to the logic circuit connected to the node Q1, so there is no influence on the operation of the scan flip flop 341. That is, even when the backup circuit 342 is provided, the performance of the flip flop 340 is not substantially reduced.
  • the transistors M35 to M37 have the same specifications and are OS transistors having a back gate.
  • the back gates of the transistors M35 to M37 are electrically connected to the wiring BGFL.
  • the voltage VBGF from the voltage output circuit 345 is input to the wiring BGFL.
  • the voltage output circuit of the first embodiment is applied to the voltage output circuit 345, and includes a voltage generation circuit 346 and a voltage correction circuit 347.
  • the voltage generation circuit 346 steps down the voltage VSSS to generate a voltage Vpw.
  • the voltage generation circuit 346 may be provided in the power supply circuit 316.
  • the voltage correction circuit 347 is provided with a replica transistor of the transistor M35.
  • the voltage VOT2 generated by the voltage correction circuit 347 is input to the wiring BGFL as a voltage VBGF.
  • the circuit 114A and the voltage output circuit of the first embodiment may be applied to the level shifter 348 to correct the voltage of “H” and / or “L” of the recovery signal RCH and the backup signal BK. In this case, the voltage output circuit 345 may not be provided.
  • the signal BK is set to "H”.
  • M35 is turned on, and the data of node Q1 is written to node SN35.
  • the power switch 349 is turned off to stop the supply of the voltage VDDD to the CPU core.
  • the data of the scan flip flop 341 is written back to the backup circuit 342.
  • the power switch 349 is turned on to start supply of the voltage VDDD to the CPU core.
  • the PMU 314 outputs the signals RC and SCE of "H”.
  • the transistor M36 is turned on, and the charge of the capacitive element C35 is distributed to the node SN35 and the node SD. Since the node SE is "H", the data of the node SD is written to the input-side latch circuit of the scan flip-flop 341.
  • the PMU 314 controls the clock control circuit 315 to activate the clock signal GCLK4.
  • the data of the input side latch circuit is written to node Q1. That is, the data of the node SN35 is written to the node Q1.
  • the PMU 314 sets the signals RC and SCE to "L". Recovery operation ends.
  • the backup circuit 342 can realize the same performance as the reference temperature Tref in the operating temperature range. Therefore, it is possible to suppress the shortening of the retention time due to the temperature rise and the increase of the backup and recovery time due to the temperature fall. Therefore, the processor 300 with high reliability and low power consumption can be provided.
  • the memory device and / or the flip flop 340 of Embodiment 2 can be applied to the functional unit 318, the interface unit 319, and the like.
  • the processor of this embodiment can be provided with a monitor circuit 130 as a temperature sensor. In this case, for example, depending on the output voltage of the monitor circuit 130, the refresh cycle of the storage device or the timing of the power gating of the processor can be changed.
  • the electronic device illustrated in FIG. 19 includes an electronic component 7020 and / or an electronic component 7030.
  • the electronic component 7020 incorporates the storage device of the second embodiment, and the electronic component 7030 incorporates the processor of the third embodiment.
  • the robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (an infrared sensor, an ultrasonic sensor, an acceleration sensor, a piezo sensor, an optical sensor, a gyro sensor, and the like), a moving mechanism, and the like.
  • the electronic component 7030 controls these peripheral devices.
  • the electronic component 7020 stores, for example, data acquired by the sensor.
  • the microphone has a function of detecting an acoustic signal such as a user's voice and an environmental sound.
  • the speaker has a function of emitting audio signals such as voice and warning sound.
  • the robot 7100 can analyze an audio signal input through a microphone and emit a necessary audio signal from a speaker.
  • the robot 7100 can communicate with a user using a microphone and a speaker.
  • the camera has a function of imaging the periphery of the robot 7100.
  • the robot 7100 has a function of moving using a moving mechanism.
  • the robot 7100 can capture an image of the surroundings using a camera and analyze the image to detect the presence or absence of an obstacle when moving.
  • a flying object 7120 has a propeller, a camera, a battery, and the like, and has a function to fly autonomously.
  • the electronic component 7030 controls these peripheral devices.
  • the electronic component 7030 analyzes image data captured by a camera and detects the presence or absence of an obstacle when moving. For example, image data is stored in the electronic component 7020.
  • the cleaning robot 7140 has a display disposed on the top, a plurality of cameras disposed on the side, brushes, operation buttons, various sensors, and the like. Although not shown, the cleaning robot 7140 is provided with a tire, a suction port and the like. The cleaning robot 7140 can self-propelled, detect dust, and suction dust from a suction port provided on the lower surface.
  • the electronic component 7030 analyzes an image captured by a camera, and determines the presence or absence of an obstacle such as a wall, furniture, or a step. When the image analysis detects an object that is likely to be entangled in the brush, such as wiring, the rotation of the brush is stopped.
  • the automobile 7160 has an engine, tires, brakes, a steering device, a camera and the like.
  • the electronic component 7030 performs control for optimizing the traveling state of the automobile 7160 based on data such as navigation information, speed, engine state, gear selection state, and brake use frequency.
  • image data captured by a camera is stored in the electronic component 7020.
  • the electronic component 7020 and / or the electronic component 7030 can be incorporated in a TV set (television receiver) 7200, a smartphone 7210, a PC (personal computer) 7220, 7230, a game console 7240, a game console 7260, and the like.
  • a TV set television set
  • a PC personal computer
  • an electronic component 7030 incorporated in the TV set 7200 functions as an image engine.
  • the electronic component 7030 performs image processing such as noise removal and resolution upconversion.
  • the smartphone 7210 is an example of a portable information terminal.
  • the smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display portion.
  • the electronic component 7030 controls these peripheral devices.
  • the PC 7220 and the PC 7230 are examples of a notebook PC and a stationary PC, respectively.
  • a keyboard 7232 and a monitor device 7233 can be connected to the PC 7230 wirelessly or by wire.
  • the game machine 7240 is an example of a portable game machine.
  • the game machine 7260 is an example of a stationary game machine.
  • a controller 7262 is connected to the game machine 7260 wirelessly or by wire.
  • the controller 7262 can also incorporate an electronic component 7020 and / or an electronic component 7030.
  • ⁇ OS transistor 590> 20A to 20C are a top view of the OS transistor 590, a cross-sectional view in the channel length direction, and a cross-sectional view in the channel width direction, respectively.
  • the L1-L2 line and the W1-W2 line shown in FIG. 20A are cutting lines.
  • FIG. 20A omits some components for the sake of clarity of the figure.
  • the OS transistor 590, the insulating layer 510, the insulating layer 512, the insulating layer 514, the insulating layer 516, the insulating layer 580, the insulating layer 582, the insulating layer 584, the conductive layer 546a, the conductive layer 546b, and the conductive layer Layer 503 is shown.
  • the conductive layer 546a and the conductive layer 546b form a contact plug
  • the conductive layer 503 forms a wiring.
  • the OS transistor 590 includes a conductive layer 560 functioning as a gate (a conductive layer 560a and a conductive layer 560b), a conductive layer 505 functioning as a back gate (a conductive layer 505a and a conductive layer 505b), and an insulating layer functioning as a gate insulating layer 550, an insulating layer 520, 522, 524 which functions as a back gate insulating layer, an oxide layer 530 (an oxide layer 530a, an oxide layer 530b, and an oxide layer 530c) having a channel formation region, a source region or Conductive layers 540 a and 540 b which function as drain regions and an insulating layer 574 are provided.
  • the oxide layer 530 c, the insulating layer 550, and the conductive layer 560 are disposed in the opening provided in the insulating layer 580 with the insulating layer 574 interposed therebetween.
  • the oxide layer 530c, the insulating layer 550, and the conductive layer 560 are disposed between the conductive layer 540a and the conductive layer 540b.
  • the insulating layers 510 and 512 function as interlayer films.
  • the insulating layer 512 preferably has a lower dielectric constant than the insulating layer 510.
  • parasitic capacitance generated between wirings can be reduced.
  • the insulating layers 510 and 512 are not limited to a single layer, and may be stacked. Other insulating layers, conductive layers, and oxide layers may be single-layered or stacked similarly.
  • An insulator such as TiO 3 (BST) can be used in a single layer or a stack.
  • aluminum oxide, bismuth oxide, germanium oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulating layer 510 preferably has a barrier property to suppress entry of impurities such as water or hydrogen into the OS transistor 590.
  • the insulating material of the insulating layer 510 has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are unlikely to permeate), or oxygen (eg, oxygen) It is preferable that it is an insulating material (it is hard to permeate
  • the insulating material having such a function include aluminum oxide and silicon nitride.
  • the conductive layer 503 is formed to be embedded in the insulating layer 512.
  • the height of the top surface of the conductive layer 503 and the height of the top surface of the insulating layer 512 can be approximately the same.
  • the conductive layer 503 is preferably formed using a highly conductive conductive material containing tungsten, copper, or aluminum as a main component.
  • the conductive layer 505 and the conductive layer 560 are provided to overlap with each other, when a potential is applied to the conductive layer 560 and the conductive layer 505, the electric field generated from the conductive layer 560 and the electric field generated from the conductive layer 505 are connected to each other.
  • the channel formation region formed in the object layer 530 can be covered. That is, the electric field of the gate and the electric field of the back gate can electrically surround the channel formation region.
  • a structure of a transistor which electrically surrounds a channel formation region by an electric field of a gate and a back gate is referred to as a surrounded channol (S-channel) structure.
  • the insulating layers 514 and 516 function as interlayer films in the same manner as the insulating layer 510.
  • the insulating layer 514 is preferably a barrier film which suppresses diffusion of impurities, in order to suppress entry of impurities such as water or hydrogen into the OS transistor 590.
  • the insulating layer 516 preferably has a dielectric constant lower than that of the insulating layer 514 in order to reduce parasitic capacitance generated between the wirings.
  • a conductive layer 505 is formed in contact with the inner wall of the opening of the insulating layers 514 and 516.
  • the heights of the top surfaces of the conductive layer 505 a and the conductive layer 505 b can be approximately the same as the height of the top surface of the insulating layer 516.
  • the conductive layer 505 a may be a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (conductive materials to which impurities are unlikely to permeate), or oxygen (eg, oxygen atoms) It is preferable to use a conductive material (hereinafter referred to as a conductive material which hardly transmits oxygen) which has a function of suppressing the diffusion of oxygen molecules and the like (the above-mentioned oxygen is difficult to transmit).
  • the function of suppressing the diffusion of the impurity or oxygen is a function of suppressing the diffusion of at least one of the impurity and the oxygen.
  • the conductive layer 505 b can be suppressed from being oxidized to be lowered in conductivity.
  • the conductive layer 505 b includes a conductive layer containing tungsten, copper, or aluminum as a main component.
  • the conductive layer 505 b may be, for example, a stack of titanium or titanium nitride and the above conductive layer.
  • a conductive material layer having high conductivity is preferably used. In that case, the conductive layer 503 may not necessarily be provided.
  • the insulating layer 522 preferably has a barrier property.
  • the insulating layer 522 functions as a layer which suppresses entry of an impurity such as hydrogen from the peripheral portion of the OS transistor 590 to the OS transistor 590.
  • the insulating layer 522 is made of, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or It is preferable to use an insulator containing a so-called high-k material such as Ba, Sr) TiO 3 (BST) in a single layer or a laminate. As the miniaturization and higher integration of the OS transistor progress, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a high-k material for the gate insulating layer, the gate voltage can be reduced while maintaining the physical thickness.
  • the insulating layer 520 is preferably thermally stable.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • a gate insulating layer with a stacked structure with high thermal stability and high dielectric constant can be obtained.
  • the oxide semiconductor layer of the OS transistor preferably includes a metal oxide containing at least indium or zinc.
  • the metal oxide preferably comprises, in particular, indium and zinc.
  • aluminum, gallium, yttrium or tin is preferably contained.
  • one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.
  • the metal oxide contains indium, the element M and zinc.
  • the element M is, for example, aluminum, gallium, yttrium or tin.
  • Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.
  • the element M a plurality of the aforementioned elements may be combined in some cases.
  • metal oxides having nitrogen are also included in the category of metal oxides.
  • metal oxides having nitrogen may be referred to as metal oxynitrides.
  • the oxide layer 530 has a region where the oxide layers 530a to 530c are stacked. This region is a channel formation region, and a channel is mainly formed in the oxide layer 530b.
  • the presence of the oxide layers 530 a and 530 c in the oxide layer 530 can suppress diffusion of impurities into the oxide layer 530 b.
  • the oxide layer 530 c is preferably provided in the opening provided in the insulating layer 580 with the insulating layer 574 interposed therebetween.
  • the insulating layer 574 has a barrier property, diffusion of impurities from the insulating layer 580 into the oxide layer 530 can be suppressed.
  • a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing any of these as a main component can be used.
  • metal nitride films such as tantalum nitride are preferable because they have a barrier property to hydrogen or oxygen and high oxidation resistance.
  • a copper-magnesium-aluminium alloy film, a titanium film, or a titanium film or a tungsten film is formed by stacking a tungsten film over a tantalum nitride film.
  • a laminated film in which a copper film is laminated on a tungsten film may be used.
  • a molybdenum nitride film a three-layer structure in which an aluminum film or a copper film is stacked on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed thereon.
  • a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.
  • a barrier layer having a barrier property to oxygen or hydrogen may be provided over the conductive layers 540a and 540b.
  • a metal oxide can be used.
  • an insulating material having a barrier property to oxygen and hydrogen is preferably used.
  • a silicon nitride layer formed by a CVD method may be used.
  • Providing the barrier layer over the conductive layers 540a and 540b improves the material selectivity of the conductive layers 540a and 540b.
  • a material with low oxidation resistance such as tungsten or aluminum, but high conductivity can be used.
  • a conductor which can be easily formed or processed can be used.
  • the insulating layer 550 is preferably provided in the opening provided in the insulating layer 580 with the oxide layer 530 c and the insulating layer 574 interposed therebetween. As the miniaturization and higher integration of transistors progress, problems such as leakage current may become apparent due to thinning of the gate insulating layer.
  • the insulating layer 550 forms a gate insulating layer and can have the same structure as the above-described back gate insulating layer.
  • the conductive layer 560 a is preferably formed using a conductive material having a function of suppressing diffusion of impurities or oxygen, similarly to the conductive layer 505 a.
  • the conductive layer 560a has a function of suppressing the diffusion of oxygen, whereby oxidation of the conductive layer 560b can be suppressed and a decrease in conductivity can be prevented. Therefore, material selectivity of the conductive layer 560b can be improved.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide or the like is preferably used.
  • a metal oxide that can be used as the oxide layer 530 can be used as the conductive layer 560a.
  • the electric resistance value of the conductive layer 560a can be reduced to be a conductor. This can be called an OC (Oxide Conductor) electrode.
  • the conductive layer 560 functions as a wiring
  • the conductive layer 560 b is preferably formed using a conductor with high conductivity. It is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component for the conductive layer 560b.
  • the insulating layer 574 preferably has a barrier property to suppress diffusion of impurities such as water or hydrogen and oxygen. With the insulating layer 574, diffusion of impurities such as water and hydrogen included in the insulating layer 580 to the oxide layer 530b through the oxide layer 530c and the insulating layer 550 can be suppressed. Further, oxidation of the conductive layer 560 can be suppressed by excess oxygen contained in the insulating layer 580.
  • aluminum oxide or hafnium oxide is preferably used.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • the insulating layers 580, 582, and 584 function as interlayer films.
  • the insulating layer 582 preferably functions as a barrier layer which prevents impurities such as water or hydrogen from entering the OS transistor 590 from the outside.
  • the insulating layers 580 and 584 preferably have a lower dielectric constant than the insulating layer 582. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • the OS transistor 590 may be electrically connected to another structure through a plug or a wiring such as the conductive layer 546a or the conductive layer 546b embedded in the insulating layers 580, 582, and 584.
  • the material of the conductive layer 546 a and the conductive layer 546 b is similar to that of the conductive layer 505, and is a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material.
  • a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity.
  • it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.
  • the conductive layer 546a and the conductive layer 546b are layers of, for example, tantalum nitride or the like having a barrier property to hydrogen and oxygen and tungsten having high conductivity, so that the conductivity as a wiring is maintained, Diffusion of impurities from the outside can be suppressed.
  • ⁇ OS transistor 592> 21A to 21C are a top view of the OS transistor 592, a cross-sectional view in the channel length direction, and a cross-sectional view in the channel width direction, respectively.
  • the L1-L2 line and the W1-W2 line shown in FIG. 21A are cutting lines.
  • FIG. 21A omits some components for the sake of clarity of the figure.
  • the OS transistor 592 is a modification of the OS transistor 592, mainly the points different from the OS transistor 592 will be described.
  • the OS transistor 592 has a region in which each of the conductive layers 540 a and 540 b overlaps with the oxide layer 530 c, the insulating layer 550, and the conductive layer 560. With this structure, an OS transistor with high on-state current can be provided. In addition, an OS transistor with high controllability can be provided.
  • the conductive layer 560 includes a conductive layer 560b over the conductive layer 560a.
  • the conductive layer 560a is preferably formed using a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms.
  • a conductive material having a function of suppressing the diffusion of oxygen eg, at least one of oxygen atom, oxygen molecule, and the like.
  • the conductive layer 560 a having a function of suppressing the diffusion of oxygen, oxidation of the conductive layer 560 b can be suppressed and a decrease in conductivity can be prevented. Thus, material selectivity of the conductive layer 560b can be improved.
  • the insulating layer 574 is preferably provided to cover the top surface and the side surfaces of the conductive layer 560, the side surface of the insulating layer 550, and the side surface of the oxide layer 530c.
  • an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen can be used.
  • aluminum oxide or hafnium oxide is preferably used.
  • metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • oxidation of the conductive layer 560 can be suppressed.
  • diffusion of impurities such as water and hydrogen which the insulating layer 580 has into the OS transistor 592 can be suppressed.
  • the insulating layer 576 (the insulating layer 576a and the insulating layer 576b) having a barrier property may be provided between the conductive layer 546a and the conductive layer 546b and the insulating layer 580.
  • oxygen in the insulating layer 580 can be reacted with the conductive layers 546a and 5b to suppress oxidation of the conductive layers 546a and 546b.
  • the range of material selection of a conductor used for a plug or a wiring can be expanded.
  • the conductive layer 546a and the conductive layer 546b have a property of absorbing oxygen, and by using a metal material with high conductivity, a semiconductor device with low power consumption can be provided.
  • materials having low oxidation resistance, such as tungsten and aluminum, but having high conductivity can be used.
  • a conductor which can be easily formed or processed can be used.

Abstract

[Abstract] Provided is a semiconductor device with which it is possible to acquire a threshold value voltage for a transistor. The semiconductor device has a first transistor, a first capacitive element, a first output terminal, a first switch, and a second switch. The gate and source of the first transistor are electrically connected. The first terminal of the first capacitive element is electrically connected to the source. The first output terminal and the second terminal of the first capacitive element are electrically connected to a back gate of the first transistor. The first switch controls the input of a first voltage to the back gate. A second voltage is inputted to the drain of the first transistor. The second switch controls the input of a third voltage to the source.

Description

半導体装置、及びその動作方法Semiconductor device and method of operating the same
　本明細書は、半導体装置、並びにその動作方法と作製方法等について説明する。 This specification describes a semiconductor device, an operation method thereof, a manufacturing method thereof, and the like.
　本明細書において、半導体装置とは、半導体特性を利用した装置であり、半導体素子（トランジスタ、ダイオード、フォトダイオード等）を含む回路、同回路を有する装置等をいう。また、半導体特性を利用することで機能しうる装置全般をいう。例えば、集積回路、集積回路を備えたチップや、パッケージにチップを収納した電子部品は半導体装置の一例である。また、記憶装置、表示装置、発光装置、照明装置及び電子機器等は、それ自体が半導体装置であり、半導体装置を有している場合がある。 In this specification, a semiconductor device is a device utilizing semiconductor characteristics, and refers to a circuit including a semiconductor element (eg, a transistor, a diode, a photodiode, or the like), a device including the circuit, or the like. In addition, it refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including the integrated circuit, and an electronic component in which the chip is stored in a package are examples of a semiconductor device. In addition, the memory device, the display device, the light-emitting device, the lighting device, the electronic device, and the like may each be a semiconductor device and may include the semiconductor device.
　トランジスタに適用可能な半導体として金属酸化物が注目されている。“ＩＧＺＯ”、“イグゾー”などと呼ばれるＩｎ−Ｇａ−Ｚｎ酸化物は、多元系金属酸化物の代表的なものである。ＩＧＺＯに関する研究において、単結晶でも非晶質でもない、ＣＡＡＣ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌｌｉｎｅ）構造、およびｎｃ（ｎａｎｏｃｒｙｓｔａｌｌｉｎｅ）構造が見出された（例えば、非特許文献１）。 Metal oxides have attracted attention as semiconductors applicable to transistors. In-Ga-Zn oxides called "IGZO", "Igoso", etc. are representative of multi-element metal oxides. In the research on IGZO, a c-axis aligned crystalline (CAAC) structure and an nc (nanocrystalline) structure, which are neither single crystal nor amorphous, have been found (for example, Non-Patent Document 1).
　チャネル形成領域に金属酸化物半導体を有するトランジスタ（以下、「酸化物半導体トランジスタ」、または「ＯＳトランジスタ」と呼ぶ場合がある。）は、極小オフ電流であることが報告されている（例えば、非特許文献１、２）。ＯＳトランジスタが用いられた様々な半導体装置が作製されている（例えば、非特許文献３、４）。ＯＳトランジスタの製造プロセスは、従来のＳｉトランジスタとのＣＭＯＳプロセスに組み込むことができ、ＯＳトランジスタはＳｉトランジスタに積層することが可能である（例えば、非特許文献４）。 A transistor having a metal oxide semiconductor in a channel formation region (hereinafter sometimes referred to as an “oxide semiconductor transistor” or an “OS transistor”) is reported to have a minimal off-state current (eg, non-off current). Patent documents 1, 2). Various semiconductor devices using OS transistors have been manufactured (for example, Non-Patent Documents 3 and 4). The manufacturing process of the OS transistor can be incorporated into a CMOS process with a conventional Si transistor, and the OS transistor can be stacked on the Si transistor (for example, Non-Patent Document 4).
　Ｓｉトランジスタは、不純物導入によりしきい値電圧の制御が容易にできる。他方、ＯＳトランジスタのしきい値電圧を制御する高い信頼性の製造技術は確立されていない。そこで、ＯＳトランジスタに、第１ゲート電極（ゲート、またはフロントゲートともいう）、および第２ゲート電極（バックゲートともいう）を設け、第２ゲート電極の電圧を制御することで、ＯＳトランジスタのしきい値電圧を制御している（例えば、特許文献１）。 The Si transistor can easily control the threshold voltage by introducing an impurity. On the other hand, highly reliable manufacturing techniques for controlling the threshold voltage of the OS transistor have not been established. Therefore, the OS transistor is provided with a first gate electrode (also referred to as a gate or a front gate) and a second gate electrode (also referred to as a back gate), and the voltage of the second gate electrode is controlled. The threshold voltage is controlled (for example, Patent Document 1).
特開２０１２−６９９３２号公報JP 2012-69932 A
　本発明の一形態の課題は、例えば、トランジスタのしきい値電圧を取得できる半導体装置を提供すること、温度による性能変動が抑えられた半導体装置を提供すること、高信頼性の半導体装置を提供すること、又は低消費電力の半導体装置を提供することである。 An object of one embodiment of the present invention is, for example, to provide a semiconductor device capable of acquiring a threshold voltage of a transistor, to provide a semiconductor device in which performance variation due to temperature is suppressed, and to provide a highly reliable semiconductor device. Or providing a low power consumption semiconductor device.
　複数の課題の記載は、互いの課題の存在を妨げるものではない。本発明の一形態は、例示した全ての課題を解決する必要はない。また、列記した以外の課題が、本明細書の記載から、自ずと明らかとなり、このような課題も、本発明の一形態の課題となり得る。 The descriptions of multiple issues do not disturb the existence of each other's issues. One form of the present invention does not have to solve all the problems illustrated. In addition, problems other than those listed are naturally apparent from the description of the present specification, and such a problem may also be a problem of one embodiment of the present invention.
（１）本発明の一形態は、第１トランジスタ、第１容量素子、第１出力端子、第１スイッチおよび第２スイッチを有する半導体装置であり、第１トランジスタのゲートとソースは電気的に接続され、第１容量素子の第１端子および第１出力端子は第１トランジスタのバックゲートに電気的に接続され、第１容量素子の第２端子はソースに電気的に接続され、第１スイッチはバックゲートへの第１電圧の入力を制御し、第１トランジスタのドレインは第２電圧が入力され、第２スイッチはソースへの第３電圧の入力を制御する半導体装置である。 (1) One embodiment of the present invention is a semiconductor device including a first transistor, a first capacitive element, a first output terminal, a first switch, and a second switch, and the gate and the source of the first transistor are electrically connected. The first terminal and the first output terminal of the first capacitive element are electrically connected to the back gate of the first transistor, the second terminal of the first capacitive element is electrically connected to the source, and the first switch is The semiconductor device controls an input of a first voltage to the back gate, a second voltage is input to a drain of the first transistor, and a second switch controls an input of a third voltage to a source.
（２）本発明の一形態は、上記形態（１）の半導体装置を動作する方法であり、第１スイッチおよび第２スイッチをオンにすること、第１スイッチをオンにし、かつ第２スイッチをオフにすること、第１スイッチをオフにし且つ第２スイッチをオフにすること、第１スイッチをオフにし、かつ第２スイッチをオンにすることを含む。 (2) One mode of the present invention is a method of operating the semiconductor device of the above mode (1), wherein the first switch and the second switch are turned on, the first switch is turned on, and the second switch is turned on. Turning off, turning off the first switch and turning off the second switch, turning off the first switch, and turning on the second switch.
　本明細書において、「第１」、「第２」、「第３」などの序数詞は、順序を表すために使用される場合がある。または、構成要素の混同を避けるために使用する場合がある。これらの場合、序数詞の使用は発明の一態様の構成要素の個数を限定するものではない。また、例えば、「第１」を「第２」または「第３」に置き換えて、本発明の一形態を説明することができる。 In the present specification, ordinal numbers such as "first", "second", "third" and the like may be used to represent the order. Or, it may be used to avoid confusion of components. In these cases, the use of ordinal does not limit the number of components of one aspect of the invention. In addition, for example, the “first” can be replaced with the “second” or the “third” to describe one embodiment of the present invention.
　発明の一態様の構成要素の位置関係は、相対的である。従って、図面を参照して構成要素を説明する場合、位置関係を示す「上に」、「下に」等の語句は便宜的に用いられる場合がある。構成要素の位置関係は、本明細書の記載内容に限定されず、状況に応じて適切に言い換えることができる。 The positional relationship between components of one embodiment of the present invention is relative. Therefore, when the components are described with reference to the drawings, words such as “on” and “down” indicating the positional relationship may be used for convenience. The positional relationship of the components is not limited to the description of the present specification, and can be appropriately rephrased depending on the situation.
　本明細書等において、ＸとＹとが接続されていると記載されている場合は、ＸとＹとが電気的に接続されている場合と、ＸとＹとが機能的に接続されている場合と、ＸとＹとが直接接続されている場合とが、本明細書等に開示されているものとする。したがって、所定の接続関係、例えば、図または文章に示された接続関係に限定されず、図面または文章に示された接続関係以外のものも、図または文章に開示されているものとする。Ｘ、Ｙは、対象物（例えば、装置、素子、回路、配線、電極、端子、導電膜、層など）であるとする。 In the present specification and the like, when it is described that X and Y are connected, X and Y are functionally connected when X and Y are electrically connected, and It is assumed that the case and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, the present invention is not limited to a predetermined connection relation, for example, the connection relation shown in the figure or the sentence, and it is assumed that something other than the connection relation shown in the figure or the sentence is also disclosed in the figure or the sentence. X and Y each denote an object (eg, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, or the like).
　電圧は、ある電位と、基準の電位（例えば接地電位（ＧＮＤ）、またはソース電位）との電位差のことを示す場合が多い。よって、電圧を電位と言い換えることが可能である。なお、電位とは相対的なものである。よって、ＧＮＤと記載されていても、必ずしも０Ｖを意味しない場合もある。 The voltage often indicates the potential difference between a certain potential and a reference potential (for example, the ground potential (GND) or the source potential). Therefore, the voltage can be reworded as a potential. Note that the potential is relative. Therefore, even if it is described as GND, it may not necessarily mean 0V.
　ノードは、回路構成やデバイス構造等に応じて、端子、配線、電極、導電層、導電体、不純物領域等と言い換えることが可能である。また、端子、配線等をノードと言い換えることが可能である。 A node can be reworded as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on a circuit configuration, a device structure, and the like. In addition, terminals, wires, and the like can be paraphrased as nodes.
　本明細書において、「膜」という言葉と「層」という言葉とは、場合によっては、または、状況に応じて、互いに入れ替えることが可能である。例えば、「導電層」という用語を「導電膜」という用語に変更することが可能な場合がある。例えば、「絶縁膜」という用語を「絶縁層」という用語に変更することが可能な場合がある。 In the present specification, the terms "membrane" and "layer" can be interchanged with one another, as the case may be or depending on the circumstances. For example, it may be possible to change the term "conductive layer" to the term "conductive film". For example, it may be possible to change the term "insulating film" to the term "insulating layer".
　図面において、大きさ、層の厚さ、又は領域は、明瞭化のために誇張されている場合がある。よって、必ずしもそのスケールに限定されない。なお図面は、理想的な例を模式的に示したものであり、図面に示す形状又は値などに限定されない。例えば、ノイズによる信号、電圧、若しくは電流のばらつき、又は、タイミングのずれによる信号、電圧、若しくは電流のばらつきなどを含むことが可能である。 In the drawings, the size, layer thicknesses or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, variations in signal, voltage or current due to noise, or variations in signal, voltage or current due to timing deviation can be included.
　本発明の一形態によって、トランジスタのしきい値電圧を取得できる半導体装置を提供すること、温度による性能変動が抑えられた半導体装置を提供すること、高信頼性の半導体装置を提供すること、または低消費電力の半導体装置を提供することが可能になる。 According to one embodiment of the present invention, there is provided a semiconductor device capable of acquiring a threshold voltage of a transistor, a semiconductor device having suppressed performance fluctuation due to temperature, a semiconductor device having high reliability, or It becomes possible to provide a semiconductor device with low power consumption.
　複数の効果の記載は、他の効果の存在を妨げるものではない。また、本発明の一形態は、必ずしも、例示した効果の全てを有する必要はない。また、本発明の一形態について、上記以外の課題、効果、および新規な特徴については、本明細書の記載および図面から自ずと明らかになるものである。 The recitation of a plurality of effects does not preclude the presence of other effects. In addition, one embodiment of the present invention does not necessarily have to have all of the illustrated effects. In addition, with regard to one aspect of the present invention, other problems, effects, and novel features than those described above will be apparent from the description and the drawings of this specification.
半導体装置の構成例を示す機能ブロック図。FIG. 2 is a functional block diagram showing a configuration example of a semiconductor device. Ａ：バックゲートを有するトランジスタを説明する図。Ｂ：バックゲートを有するトランジスタの等価回路図。A: A diagram illustrating a transistor having a back gate. B: Equivalent circuit diagram of a transistor having a back gate. Ａ：モニタ回路の構成例を示す回路図。Ｂ：モニタ回路の動作例を示すタイミングチャート。A: A circuit diagram showing a configuration example of a monitor circuit. B: A timing chart showing an operation example of the monitor circuit. Ａ~Ｄ：モニタ回路の動作例を示す回路図。A to D: A circuit diagram showing an operation example of a monitor circuit. Ａ：シミュレーションでのモニタ回路の入力波形。Ｂ：モニタ回路のシミュレーション結果を示す図。A: Input waveform of monitor circuit in simulation. B: A diagram showing simulation results of the monitor circuit. モニタ回路の構成例を示す回路図。The circuit diagram which shows the structural example of a monitor circuit. 半導体装置の構成例を示す回路図。FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device. 電圧生成回路の構成例を示す回路図。The circuit diagram which shows the structural example of a voltage generation circuit. 半導体装置の動作例を示すタイミングチャート。5 is a timing chart showing an operation example of a semiconductor device. 半導体装置の構成例を示す機能ブロック図。FIG. 2 is a functional block diagram showing a configuration example of a semiconductor device. 半導体装置の構成例を示す機能ブロック図。FIG. 2 is a functional block diagram showing a configuration example of a semiconductor device. Ａ：回路の構成例を示す回路図。Ｂ：回路の動作例を示すタイミングチャート。A: A circuit diagram showing a configuration example of a circuit. B: Timing chart showing an operation example of the circuit. Ａ：記憶装置の構成例を示す機能ブロック図。Ｂ：メモリセルアレイの構成例を示す回路図。A: Functional block diagram showing a configuration example of a storage device. B: A circuit diagram showing a configuration example of a memory cell array. Ａ~Ｄ：メモリセルアレイの構成例を示す回路図。A to D: A circuit diagram showing a configuration example of a memory cell array. 記憶装置の構成例を示す機能ブロック図。FIG. 2 is a functional block diagram showing a configuration example of a storage device. Ａ：メモリセルアレイの構成例を示す回路図。Ｂ：記憶装置のパワーゲーティングの例を示すタイミングチャート。A: A circuit diagram showing a configuration example of a memory cell array. B: Timing chart showing an example of power gating of a storage device. プロセッサの構成例を示す機能ブロック図。FIG. 2 is a functional block diagram showing an exemplary configuration of a processor. フリップフロップの構成例を示す回路図。FIG. 7 is a circuit diagram showing an example of the configuration of a flip flop. 電子機器の例を示す図。FIG. 8 illustrates an example of an electronic device. Ａ：ＯＳトランジスタの構成例を示す上面図。Ｂ、Ｃ：ＯＳトランジスタの構成例を示す断面図。A: Top view showing a configuration example of an OS transistor. B, C: sectional views showing an example of configuration of an OS transistor. Ａ：ＯＳトランジスタの構成例を示す上面図。Ｂ、Ｃ：ＯＳトランジスタの構成例を示す断面図。A: Top view showing a configuration example of an OS transistor. B, C: A cross-sectional view showing a configuration example of an OS transistor.
　以下に、本発明の実施の形態を説明する。ただし、本発明の一形態は、以下の説明に限定されず、本発明の趣旨およびその範囲から逸脱することなくその形態および詳細を様々に変更し得ることは、当業者であれば容易に理解される。したがって、本発明の一形態は、以下に示す実施の形態の記載内容に限定して解釈されるものではない。 Hereinafter, embodiments of the present invention will be described. However, one skilled in the art would readily understand that one embodiment of the present invention is not limited to the following description, and that various changes may be made in the configuration and details without departing from the spirit and scope of the present invention. Be done. Therefore, one embodiment of the present invention is not construed as being limited to the description of the embodiment modes described below.
　以下に示される複数の実施の形態は適宜組み合わせることが可能である。また１の実施の形態の中に、複数の構成例（作製方法例、動作方法例、使用方法例等も含む。）が示される場合は、互いの構成例を適宜組み合わせること、および他の実施の形態に記載された１または複数の構成例と適宜組み合わせることも可能である。 Several embodiments shown below can be combined as appropriate. In addition, in the case where a plurality of configuration examples (including an example of a manufacturing method, an example of an operation method, an example of usage, and the like) are shown in one embodiment, combining the configuration examples of each other as appropriate It is also possible to appropriately combine with one or a plurality of configuration examples described in the form of.
　図面において、同一の要素または同様な機能を有する要素、同一の材質の要素、あるいは同時に形成される要素等には同一の符号を付す場合があり、その繰り返しの説明は省略する場合がある。 In the drawings, the same elements or elements having similar functions, elements of the same material, or elements formed simultaneously may be denoted by the same reference numerals, and repeated descriptions thereof may be omitted.
　本明細書において、例えば、電源電位ＶＤＤを、電位ＶＤＤ、ＶＤＤ等と省略して記載する場合がある。これは、他の構成要素（例えば、信号、電圧、回路、素子、電極、配線等）についても同様である。 In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, or the like. The same applies to other components (eg, signals, voltages, circuits, elements, electrodes, wirings, etc.).
　また、複数の要素に同じ符号を用いる場合、特に、それらを区別する必要があるときには、符号に“＿１”、”＿２”、”［ｎ］”、”［ｍ，ｎ］”等の識別用の符号を付記して記載する場合がある。例えば、２番目の配線ＧＬを配線ＧＬ［２］と記載する。 In addition, when the same code is used for a plurality of elements, in particular, when it is necessary to distinguish between them, for identification of codes such as “_1”, “_2”, “[n]”, “[m, n]”, etc. In some cases, it will be written with the symbol of. For example, the second wiring GL is described as a wiring GL [2].
〔実施の形態１〕
　本実施の形態では、バックゲートを有するトランジスタを有する半導体装置等について説明する。 First Embodiment
In this embodiment mode, a semiconductor device or the like including a transistor having a back gate is described.
＜＜半導体装置１００＞＞
　図１は半導体装置１００の機能ブロック図である。半導体装置１００は、半導体装置１１０、および電圧出力回路１２０を有する。半導体装置１１０はトランジスタＭ１を有する。電圧出力回路１２０はモニタ回路１３０を有する。モニタ回路１３０は、トランジスタＭ１の電気特性の変動を監視する機能を備える。モニタ回路１３０が取得した情報に基づいて、電圧出力回路１２０は電圧ＶＯＴ１を調整する。半導体装置１１０は、電圧出力回路１２０から電圧ＶＯＴ１が供給される。 << semiconductor device 100 >>
FIG. 1 is a functional block diagram of the semiconductor device 100. As shown in FIG. The semiconductor device 100 includes a semiconductor device 110 and a voltage output circuit 120. The semiconductor device 110 has a transistor M1. The voltage output circuit 120 has a monitor circuit 130. The monitor circuit 130 has a function of monitoring fluctuations in the electrical characteristics of the transistor M1. The voltage output circuit 120 adjusts the voltage VOT1 based on the information acquired by the monitor circuit 130. The semiconductor device 110 is supplied with the voltage VOT1 from the voltage output circuit 120.
　図２Ａ、図２Ｂを参照して、トランジスタＭ１のしきい値電圧について説明する。トランジスタＭ１はソース（Ｓ）、ドレイン（Ｄ）、ゲート（Ｇ）、バックゲート（ＢＧ）、半導体層を有する。ゲートとバックゲートとは半導体層を挟んで上下に配置され、半導体層にはチャネル形成領域が設けられている。 The threshold voltage of the transistor M1 will be described with reference to FIGS. 2A and 2B. The transistor M1 includes a source (S), a drain (D), a gate (G), a back gate (BG), and a semiconductor layer. The gate and the back gate are disposed above and below the semiconductor layer, and a channel formation region is provided in the semiconductor layer.
　ゲートとソース間の電圧差（以下、電圧Ｖｇｓと呼ぶ）、またはバックゲートとソース間の電圧差（以下、電圧Ｖｂｇｓと呼ぶ）に従って、トランジスタＭ１はオンまたはオフになる。電圧ＶｇｓがＶＴｇよりも大きくなると、半導体層のゲート側の領域にはチャネルが形成される（または、キャリアが誘起される）場合がある。電圧ＶｂｇｓがＶＴｂｇよりも大きくなると、半導体層のバックゲート側の領域にはチャネルが形成される（または、キャリアが誘起される）場合がある。つまり、トランジスタＭ１には、ＶＴｇ、ＶＴｂｇという２つのしきい値電圧が存在する。ＶＴｇは電圧Ｖｇｓに対するしきい値電圧であり、ＶＴｂｇは電圧Ｖｂｇｓに対するしきい値電圧である。 The transistor M1 is turned on or off according to the voltage difference between the gate and the source (hereinafter referred to as voltage Vgs) or the back gate and the source (hereinafter referred to as voltage Vbgs). When the voltage Vgs becomes larger than VTg, a channel may be formed (or carriers may be induced) in the region on the gate side of the semiconductor layer. When the voltage Vbgs becomes larger than VTbg, a channel may be formed (or carriers may be induced) in the region on the back gate side of the semiconductor layer. That is, the transistor M1 has two threshold voltages VTg and VTbg. VTg is a threshold voltage for the voltage Vgs, and VTbg is a threshold voltage for the voltage Vbgs.
　Ｖｇｓ＞ＶＴｇ、または、Ｖｂｇｓ＞ＶＴｂｇとなる場合に、トランジスタＭ１はオンになる。従って、しきい値電圧がＶＴｇであるトランジスタＭａ１と、しきい値電圧がＶＴｂｇであるトランジスタＭａ２とが電気的に並列接続された回路１０（図２Ｂ参照）と等価な機能をトランジスタＭ１は有しているといえる。 When Vgs> VTg or Vbgs> VTbg, the transistor M1 is turned on. Therefore, the transistor M1 has a function equivalent to that of the circuit 10 (see FIG. 2B) in which the transistor Ma1 having a threshold voltage of VTg and the transistor Ma2 having a threshold voltage of VTbg are electrically connected in parallel. It can be said that
　トランジスタＭ１のチャネルの形成は、ゲート電圧Ｖｇとバックゲート電圧Ｖｂｇとによって制御されるため、ＶＴｇはＶｂｇｓに依存し、ＶＴｂｇはＶｇｓに依存する。例えば、トランジスタＭ１がオンとなる条件は、下記式（１．１）で表される場合がある。式（１．１）において、ＶＴ０は定電圧であり、Ｃｇはゲートと半導体層の間の単位面積当たりのゲート容量であり、Ｃｂｇはバックゲートと半導体層の間の単位面積当たりのバックゲート容量である。 Since the formation of the channel of the transistor M1 is controlled by the gate voltage Vg and the back gate voltage Vbg, VTg depends on Vbgs, and VTbg depends on Vgs. For example, the conditions under which the transistor M1 is turned on may be expressed by the following formula (1.1). In equation (1.1), VT 0 is a constant voltage, Cg is a gate capacitance per unit area between the gate and the semiconductor layer, and Cbg is a back gate per unit area between the back gate and the semiconductor layer It is a capacity.
（Ｃｇ×Ｖｇｓ＋Ｃｂｇ×Ｖｂｇｓ）／（Ｃｇ＋Ｃｂｇ）＞ＶＴ０（１．１） (Cg × Vgs + Cbg × Vbgs) / (Cg + Cbg)> VT 0 (1.1)
　上記の場合において、ＶＴｇは、式（１．２）に示すＶｂｇｓの線形関数で表すことができる。
　ＶＴｇ＝（１＋Ｃｂｇ／Ｃｇ）×ＶＴ０−Ｃｂｇ／Ｃｇ×Ｖｂｇｓ（１．２） In the above case, VTg can be represented by a linear function of Vbgs shown in equation (1.2).
VTg = (1 + Cbg / Cg) × VT 0 −Cbg / Cg × Vbgs (1.2)
　ゲートと半導体層間の電界強度はゲートと半導体層の間のゲート容量に依存し、バックゲートと半導体層間の電界強度は、バックゲートと半導体層の間のバックゲート容量に依存する。そのため、式（１．３）に示すように、ＶＴｂｇは、ＶＴｇを変数とする線形関数で表される場合がある。βは係数であり、Ｖβは定電圧である。
　ＶＴｂｇ＝β×ＶＴｇ＋Ｖβ（１．３） The electric field strength between the gate and the semiconductor layer depends on the gate capacitance between the gate and the semiconductor layer, and the electric field strength between the back gate and the semiconductor layer depends on the back gate capacitance between the back gate and the semiconductor layer. Therefore, VTbg may be represented by a linear function with VTg as a variable, as shown in equation (1.3). β is a coefficient, and V β is a constant voltage.
VTbg = β × VTg + V β (1.3)
　なお、本明細書では、しきい値電圧ＶＴｇは、電圧Ｖｇｓを横軸、ドレイン電流Ｉｄの平方根を縦軸にプロットしたＶｇｓ−Ｉｄ１／２特性曲線において、最大傾きである接線を外装した直線と、Ｉｄ１／２＝０Ａとの交点における電圧Ｖｇｓである。同様に、しきい値電圧ＶＴｂｇは、Ｖｇｓが０ＶのときのＶｂｇｓ−Ｉｄ１／２特性曲線において、最大傾きである接線を外装した直線とＩｄ１／２＝０Ａとの交点における電圧Ｖｂｇｓである。 In the present specification, the threshold voltage VTg is a straight line obtained by covering a tangent having a maximum slope in the Vgs-Id1 / 2 characteristic curve in which the voltage Vgs is plotted on the abscissa and the square root of the drain current Id is plotted on the ordinate. And the voltage Vgs at the intersection of Id 1/2 = 0A. Similarly, threshold voltage VTbg is voltage Vbgs at the intersection of a straight line obtained by covering a tangent having a maximum slope and Id 1/2 = 0A in the Vbgs-Id 1/2 characteristic curve when Vgs is 0 V. .
　または、トランジスタのチャネル長／チャネル幅がＬ／Ｗであるとき、しきい値電圧ＶＴｇは、Ｉｄ×Ｌ／Ｗが１×１０−１２［Ａ］であるときの電圧Ｖｇｓを指す場合がある。また、しきい値電圧ＶＴｂｇは、Ｖｇｓが０Ｖであり、Ｉｄ×Ｌ／Ｗが１×１０−１２［Ａ］であるときの電圧Ｖｂｇｓを指す場合がある。 Alternatively, when the channel length / channel width of the transistor is L / W, the threshold voltage VTg may indicate the voltage Vgs when Id × L / W is 1 × 10 −12 [A]. The threshold voltage VTbg may indicate a voltage Vbgs when Vgs is 0 V and Id × L / W is 1 × 10 −12 [A].
　なお、本明細書では、バックゲートを有するトランジスタのしきい値電圧ＶＴｇは、Ｖｂｇｓが０Ｖであるときの、Ｖｇｓ−Ｉｄ１／２特性から算出される。 Note that, in the present specification, the threshold voltage VTg of the transistor having a back gate is calculated from the Vgs−Id 1/2 characteristic when Vbgs is 0V.
　トランジスタの電気特性には温度依存性がある。温度ＴのときのＶＴｇ（Ｔ）とＶｂｇ（Ｔ）との関係は、式（１．４）で表されることを確認している。Ｔｒｅｆは基準温度であり、αは係数である。
　Ｖｂｇ（Ｔ）−Ｖｂｇ（Ｔｒｅｆ）
　＝α（ＶＴｇ（Ｔ）−ＶＴｇ（Ｔｒｅｆ））（１．４） The electrical characteristics of the transistor have temperature dependence. It has been confirmed that the relationship between VTg (T) and Vbg (T) at the temperature T is expressed by equation (1.4). Tref is a reference temperature, and α is a coefficient.
Vbg (T)-Vbg (Tref)
= Α (VTg (T)-VTg (Tref)) (1.4)
＜モニタ回路１３０＞
　図３Ａはモニタ回路１３０の回路構成例を示す。モニタ回路１３０は、トランジスタＭ１ｒ、Ｍ１１、Ｍ１２、容量素子Ｃ１１、ノードＳｒｂ、Ｓｒｓ、および端子ａ１~ａ６を有する。 <Monitor circuit 130>
FIG. 3A shows a circuit configuration example of the monitor circuit 130. As shown in FIG. The monitor circuit 130 includes transistors M1r, M11, and M12, a capacitive element C11, nodes Srb and Srs, and terminals a1 to a6.
　ここでは、トランジスタＭ１ｒ、Ｍ１１、Ｍ１２は、バックゲートを有するＯＳトランジスタである。ノードＳｒｂ、Ｓｒｓは、トランジスタＭ１ｒのバックゲート、ソースにそれぞれ対応する。トランジスタＭ１１、Ｍ１２のバックゲートは電圧ＶＢＧＭ１が入力される。トランジスタＭ１２のバックゲートに、電圧ＶＢＧＭ１と異なる電圧を入力してもよい。 Here, the transistors M1r, M11, and M12 are OS transistors having a back gate. The nodes Srb and Srs correspond to the back gate and the source of the transistor M1r, respectively. The voltage VBGM1 is input to the back gates of the transistors M11 and M12. A voltage different from the voltage VBGM1 may be input to the back gate of the transistor M12.
　トランジスタＭ１ｒのゲート、ドレインはノードＳｒｓ、端子ａ４にそれぞれ電気的に接続されている。トランジスタＭ１１のゲート、ソース、ドレインは端子ａ１、ノードＳｒｂ、端子ａ３にそれぞれ電気的に接続されている。トランジスタＭ１２のゲート、ソース、ドレインは端子ａ２、ａ５、ノードＳｒｓにそれぞれ電気的に接続されている。容量素子Ｃ１１の第１端子、第２端子はノードＳｒｂ、Ｓｒｓにそれぞれ電気的に接続されている。 The gate and drain of the transistor M1r are electrically connected to the node Srs and the terminal a4, respectively. The gate, source, and drain of the transistor M11 are electrically connected to the terminal a1, the node Srb, and the terminal a3, respectively. The gate, source, and drain of the transistor M12 are electrically connected to the terminals a2 and a5 and the node Srs, respectively. The first terminal and the second terminal of the capacitive element C11 are electrically connected to the nodes Srb and Srs, respectively.
　端子ａ１、ａ２は信号ＭＯＮ１、ＭＯＮ２がそれぞれ入力される。信号ＭＯＮ１、ＭＯＮ２の低レベル（“Ｌ”）、高レベル（“Ｈ”）はそれぞれＶＳＳＡ、ＶＤＤＡである。電圧ＶＳＳＡは例えば、０ＶまたはＧＮＤとすればよい。端子ａ３、ａ４、ａ５は電圧Ｖ１、Ｖ２、ＶＳＳＡがそれぞれ入力される。端子ａ６はモニタ回路１３０の出力端子であり、ノードＳｒｂに電気的に接続されている。 Terminals a1 and a2 receive the signals MON1 and MON2, respectively. The low level ("L") and the high level ("H") of the signals MON1 and MON2 are VSSA and VDDA, respectively. The voltage VSSA may be, for example, 0 V or GND. Terminals a3, a4, and a5 receive voltages V1, V2, and VSSA, respectively. The terminal a6 is an output terminal of the monitor circuit 130, and is electrically connected to the node Srb.
　モニタ回路１３０は、トランジスタＭ１ｒのしきい値電圧ＶＴｂｇを監視する機能を備える。トランジスタＭ１ｒは代表的にはトランジスタＭ１のレプリカトランジスタであり、トランジスタＭ１と同じ仕様である。モニタ回路１３０で取得されたトランジスタＭ１ｒのしきい値電圧ＶＴｂｇに関する情報をもとに、例えば、トランジスタＭ１のバックゲート電圧Ｖｂｇ及び／又はゲート電圧Ｖｇを変更することで、トランジスタＭ１のしきい値電圧ＶＴｇ及び／又はＶＴｂｇの変動を補正することができる。 The monitor circuit 130 has a function of monitoring the threshold voltage VTbg of the transistor M1r. The transistor M1r is typically a replica transistor of the transistor M1 and has the same specifications as the transistor M1. For example, by changing the back gate voltage Vbg and / or the gate voltage Vg of the transistor M1 based on the information on the threshold voltage VTbg of the transistor M1r acquired by the monitor circuit 130, the threshold voltage of the transistor M1 Variations of VTg and / or VTbg can be corrected.
　図３Ａ、図３Ｂ、図４Ａ~図４Ｄを参照して、モニタ回路１３０の動作例を説明する。以下の説明において、トランジスタＭ１ｒのしきい値電圧ＶＴｇ（Ｔ）、ＶＴｂｇ（Ｔ）、ならびに電圧Ｖｇｓ、Ｖｂｇｓ、ＶｄｓをそれぞれＶＴｇ（Ｔ）＿ｒ、ＶＴｂｇ（Ｔ）＿ｒ、Ｖｇｓ＿ｒ、Ｖｂｇｓ＿ｒ、Ｖｄｓ＿ｒと表す。本明細書では、ＰＶＴ（プロセス・電圧・温度）のベストケース、ワーストケースでのトランジスタのしきい値電圧の絶対値は、最大、最小であるとする。半導体装置１００の動作温度範囲はＴｍｉｎ以上Ｔｍａｘ以下であり、温度のベストケース、ワーストケースはそれぞれＴｍｉｎ、Ｔｍａｘである。 An operation example of the monitor circuit 130 will be described with reference to FIGS. 3A, 3B, and 4A to 4D. In the following description, threshold voltages VTg (T) and VTbg (T) of the transistor M1r, and voltages Vgs, Vbgs and Vds are denoted as VTg (T) _r, VTbg (T) _r, Vgs_r, Vbgs_r and Vds_r, respectively. . In this specification, it is assumed that the absolute value of the threshold voltage of the transistor in the best case and the worst case of PVT (process, voltage, temperature) is maximum and minimum. The operating temperature range of the semiconductor device 100 is Tmin or more and Tmax or less, and the best case and the worst case of the temperature are Tmin and Tmax, respectively.
　図３Ｂは、期間ＴＴ１~ＴＴ４でのモニタ回路１３０のタイミングチャートである。図４Ａ~図４Ｄは、それぞれ、期間ＴＴ１~ＴＴ４でのモニタ回路１３０の動作を示す簡略化された回路図であり、トランジスタＭ１１、Ｍ１２はスイッチで示されている。Ｖｒｓ、ＶｒｂはそれぞれノードＳｒｓ、Ｓｒｂの電圧であり、Ｉｄ＿ｒはトランジスタＭ１ｒのドレイン電流である。温度はＴｍとする。 FIG. 3B is a timing chart of the monitor circuit 130 in the periods TT1 to TT4. FIGS. 4A to 4D are simplified circuit diagrams showing the operation of the monitor circuit 130 in the periods TT1 to TT4, respectively. The transistors M11 and M12 are indicated by switches. Vrs and Vrb are voltages of the nodes Srs and Srb, respectively, and Id_r is a drain current of the transistor M1r. The temperature is Tm.
（期間ＴＴ１：初期化動作）
　期間ＴＴ１では、ノードＳｒｓ、Ｓｒｂの初期化が行われる。トランジスタＭ１１、Ｍ１２をオンにするため、モニタ回路１３０には“Ｈ”の信号ＭＯＮ１、ＭＯＮ２が入力される。ノードＳｒｓ、ＳｒｂにはそれぞれＶＳＳＡ、Ｖ１が入力される。 (Period TT1: Initialization operation)
In the period TT1, initialization of the nodes Srs and Srb is performed. In order to turn on the transistors M11 and M12, the monitor circuit 130 receives the “H” signals MON1 and MON2. VSSA and V1 are input to the nodes Srs and Srb, respectively.
　トランジスタＭ１ｒはｎチャネル型トランジスタであるため、式（２．１）~（２．３）を満たすように電圧Ｖ１、Ｖ２、Ｖａはそれぞれ設定されている。Ｖａは定電圧である。
　Ｖ１＞ＶＴｂｇ（Ｔｍｉｎ）＿ｒ　　　　　　　　　　　　　　　　（２．１）
　Ｖ２＝Ｖ１−ＶＴｂｇ（Ｔｍａｘ）＿ｒ＋Ｖａ＞ＶＳＳＡ　　　　（２．２）
　ＶＴｂｇ（Ｔｍｉｎ）＿ｒ−ＶＴｂｇ（Ｔｍａｘ）＿ｒ＋Ｖａ＞０（２．３） Because the transistor M1r is an n-channel transistor, the voltages V1, V2, and Va are set to satisfy the equations (2.1) to (2.3). Va is a constant voltage.
V1> VTbg (Tmin) _r (2.1)
V2 = V1-VTbg (Tmax) _r + Va> VSSA (2.2)
VTbg (Tmin) _r-VTbg (Tmax) _r + Va> 0 (2.3)
　式（２．１）を満たしたしているため、動作温度範囲において、トランジスタＭ１ｒはノーマリオン特性を示す。式（２．１）~（２．３）を満たしているため、電圧Ｖｄｓ＿ｒ＝Ｖ２−ＶＳＳＡは０Ｖよりも大きい。従って、ドレイン電流Ｉｄ＿ｒが流れる。 Since the equation (2.1) is satisfied, the transistor M1r exhibits normally on characteristics in the operating temperature range. Since the expressions (2.1) to (2.3) are satisfied, the voltage Vds_r = V2-VSSA is larger than 0V. Therefore, the drain current Id_r flows.
（期間ＴＴ２）
　トランジスタＭ１２をオフにするため、モニタ回路１３０には“Ｌ”の信号ＭＯＮ２が入力される。ノードＳｒｓは電気的に浮遊状態になる。 (Period TT2)
In order to turn off the transistor M12, the signal MON2 of "L" is input to the monitor circuit 130. The node Srs is electrically floating.
　ドレイン電流Ｉｄ＿ｒによって、容量素子Ｃ１１は充電され、電圧Ｖｒｓは上昇する。そのため、電圧Ｖｂｇｓ＿ｒは低下し、トランジスタＭ１ｒはサブスレショルド領域で動作する。電圧Ｖｂｇｓ＿ｒがしきい値電圧ＶＴｂｇ（Ｔｍ）＿ｒに至ると、トランジスタＭ１ｒはオフ状態となるため、電圧Ｖｒｓは、Ｖ１−ＶＴｂｇ（Ｔｍ）＿ｒに収束する。なお、モニタ回路１３０の動作の理解を容易にするため、トランジスタＭ１ｒ、Ｍ１１、Ｍ１２のリーク電流を無視している。 The capacitive element C11 is charged by the drain current Id_r, and the voltage Vrs rises. Therefore, the voltage Vbgs_r decreases, and the transistor M1r operates in the subthreshold region. When the voltage Vbgs_r reaches the threshold voltage VTbg (Tm) _r, the transistor M1r is turned off, and the voltage Vrs converges to V1-VTbg (Tm) _r. Note that in order to facilitate understanding of the operation of the monitor circuit 130, leakage currents of the transistors M1r, M11, and M12 are ignored.
　式（２．１）~（２．３）を満たしているので、電圧ＶｒｓがＶ１−ＶＴｂｇ（Ｔｍ）＿ｒに収束した状態でも、動作温度範囲においてトランジスタＭ１ｒの電圧Ｖｄｓ＿ｒは０Ｖよりも大きい。 Since the equations (2.1) to (2.3) are satisfied, the voltage Vds_r of the transistor M1r is larger than 0 V in the operating temperature range even in the state where the voltage Vrs converges to V1-VTbg (Tm) _r.
（期間ＴＴ３）
　トランジスタＭ１１をオフにするため、モニタ回路１３０には“Ｌ”の信号ＭＯＮ１が入力される。期間ＴＴ３では、ノードＳｒｓ、Ｓｒｂは電気的に浮遊状態になる。ノードＳｒｂとノードＳｒｓ間の電圧差は、Ｖ１−（Ｖ１−ＶＴｂｇ（Ｔｍ）＿ｒ）＝ＶＴｂｇ（Ｔｍ）＿ｒである。つまり、容量素子Ｃ１１によって、電圧Ｖｂｇｓ＿ｒはＶＴｂｇ（Ｔｍ）＿ｒに固定されているので、トランジスタＭ１ｒはオフ状態が維持される。 (Period TT3)
In order to turn off the transistor M11, the signal MON1 of "L" is input to the monitor circuit 130. In the period TT3, the nodes Srs and Srb are in an electrically floating state. The voltage difference between the node Srb and the node Srs is V1− (V1−VTbg (Tm) _r) = VTbg (Tm) _r. That is, since the voltage Vbgs_r is fixed to VTbg (Tm) _r by the capacitive element C11, the transistor M1r is maintained in the off state.
　温度Ｔｍａｘにおいても、電圧Ｖｂｇｓ＿ｒの変動を抑えるため、電圧ＶＢＧＭ１は十分に低い電圧であることが好ましい。 Also at the temperature Tmax, the voltage VBGM1 is preferably a sufficiently low voltage to suppress the fluctuation of the voltage Vbgs_r.
（期間ＴＴ４）
　期間ＴＴ４でトランジスタＭ１２をオンにするため、モニタ回路１３０には“Ｈ”の信号ＭＯＮ２が入力される。ノードＳｒｓには電圧ＶＳＳＡが入力される。ノードＳｒｂとノードＳｒｓ間の電圧差はＶＴｂｇ（Ｔｍ）＿ｒに固定されているので、電圧ＶｒｂはＶＴｂｇ（Ｔｍ）＿ｒ＋ＶＳＳＡとなる。電圧Ｖｒｂが電圧Ｖｍｏｎとして端子ａ６から出力される。電圧ＶＳＳＡは電源電圧であって、トランジスタＭ１ｒの電気特性に依存しないため、端子ａ６の電圧Ｖｍｏｎを取得することは、しきい値電圧ＶＴｂｇ（Ｔｍ）＿ｒを取得することに相当する。例えば、電圧ＶＳＳＡが０Ｖであれば、電圧Ｖｍｏｎはしきい値電圧ＶＴｂｇ（Ｔｍ）＿ｒと同じになる。 (Period TT4)
The signal MON2 of “H” is input to the monitor circuit 130 in order to turn on the transistor M12 in the period TT4. The voltage VSSA is input to the node Srs. Since the voltage difference between the node Srb and the node Srs is fixed to VTbg (Tm) _r, the voltage Vrb is VTbg (Tm) _r + VSSA. The voltage Vrb is output from the terminal a6 as the voltage Vmon. Since the voltage VSSA is a power supply voltage and does not depend on the electrical characteristics of the transistor M1r, acquiring the voltage Vmon of the terminal a6 corresponds to acquiring the threshold voltage VTbg (Tm) _r. For example, if the voltage VSSA is 0 V, the voltage Vmon is equal to the threshold voltage VTbg (Tm) _r.
　しきい値電圧ＶＴｂｇ（Ｔｍ）＿ｒ、ＶＴｇ（Ｔｍ）＿ｒには式（１．３）の関係があり、トランジスタＭ１ｒは、トランジスタＭ１のレプリカトランジスタである。したがって、電圧Ｖｍｏｎを用いることで、トランジスタＭ１のしきい値電圧ＶＴｇ及び／又はＶＴｂｇの温度による変動を補正することができる。 The threshold voltages VTbg (Tm) _r and VTg (Tm) _r have the relationship of formula (1.3), and the transistor M1r is a replica transistor of the transistor M1. Therefore, by using voltage Vmon, temperature-induced variations in threshold voltage VTg and / or VTbg of transistor M1 can be corrected.
　電圧出力回路１２０は、電圧Ｖｍｏｎに基づいて電圧ＶＯＴ１を生成する。例えば、トランジスタＭ１のバックゲートに入力されるバイアス電圧として、電圧ＶＯＴ１を用いることで、トランジスタＭ１のしきい値電圧ＶＴｇの温度による変化を補正することができる。別の例では、半導体装置１１０において、電圧ＶＯＴ１に基づいて、トランジスタＭ１のゲート電圧の“Ｈ”及び／又は“Ｌ”の電圧を調整することで、トランジスタＭ１のオン電流特性およびオフ電流特性の温度による変化を補正することができる。 Voltage output circuit 120 generates voltage VOT1 based on voltage Vmon. For example, by using the voltage VOT1 as a bias voltage input to the back gate of the transistor M1, a change in temperature of the threshold voltage VTg of the transistor M1 can be corrected. In another example, in the semiconductor device 110, by adjusting the voltage of “H” and / or “L” of the gate voltage of the transistor M1 based on the voltage VOT1, the on current characteristics and the off current characteristics of the transistor M1 are obtained. Changes due to temperature can be corrected.
　モニタ回路１３０の動作をシミュレーションによって確認した。図５Ａは、シミュレーションでのモニタ回路１３０のタイミングチャートである。電圧ＶＳＳＡ、ＶＤＤＤ、Ｖ１、Ｖ２は、それぞれ０Ｖ、３．３Ｖ、２．５Ｖ、２．９Ｖである。電圧ＶＢＧＭ１は０Ｖである。電圧ＶＳＳＡが０Ｖであるため、電圧Ｖｍｏｎはしきい値電圧ＶＴｂｇ＿ｒと同じになる。トランジスタＭ１ｒのしきい値電圧ＶＴｇ＿ｒ、ＶＴｂｇ＿ｒのみが温度によって変化すると想定し、しきい値電圧ＶＴｇ＿ｒに幾つかの電圧値を設定し、各電圧値について電圧Ｖｍｏｎを算出した。図５Ｂはシミュレーション結果であり、しきい値電圧ＶＴｇ＿ｒに対する電圧Ｖｍｏｎの変化を示している。図５Ｂは、電圧Ｖｍｏｎを取得することで、温度によるしきい値電圧ＶＴｇ＿ｒの変化を監視できることを示している。 The operation of the monitor circuit 130 was confirmed by simulation. FIG. 5A is a timing chart of the monitor circuit 130 in simulation. The voltages VSSA, VDDD, V1, and V2 are 0 V, 3.3 V, 2.5 V, and 2.9 V, respectively. The voltage VBGM1 is 0V. Since the voltage VSSA is 0 V, the voltage Vmon is equal to the threshold voltage VTbg_r. Assuming that only the threshold voltages VTg_r and VTbg_r of the transistor M1r change with temperature, several voltage values were set to the threshold voltage VTg_r, and the voltage Vmon was calculated for each voltage value. FIG. 5B is a simulation result, showing the change of the voltage Vmon with respect to the threshold voltage VTg_r. FIG. 5B shows that the change of the threshold voltage VTg_r with temperature can be monitored by acquiring the voltage Vmon.
　モニタ回路１３０の素子は非常に少ないので、トランジスタＭ１に近接してモニタ回路１３０を設けることが容易である。この場合、トランジスタＭ１の電気特性をより高精度に補正することができる。モニタ回路１３０を用いることで、温度センサを設けなくとも、トランジスタＭ１の電気特性の温度補正を行うことが可能である。したがって、モニタ回路１３０を用いることで、トランジスタＭ１のしきい値電圧の温度補正機能を半導体装置１００に加えても、半導体装置１００の面積およびエネルギーのペナルティーを抑えることができる。また、モニタ回路１３０自体を温度センサとして用いることができる。 Since the number of elements of the monitor circuit 130 is very small, the monitor circuit 130 can be easily provided in the vicinity of the transistor M1. In this case, the electrical characteristics of the transistor M1 can be corrected with higher accuracy. By using the monitor circuit 130, temperature correction of the electrical characteristics of the transistor M1 can be performed without providing a temperature sensor. Therefore, by using the monitor circuit 130, even when the temperature correction function of the threshold voltage of the transistor M1 is added to the semiconductor device 100, the penalty of the area and energy of the semiconductor device 100 can be suppressed. Further, the monitor circuit 130 itself can be used as a temperature sensor.
　以下、半導体装置１００の幾つかの変形例を示す。 Hereinafter, some modifications of the semiconductor device 100 will be described.
　トランジスタＭ１１、Ｍ１２はＯＳトランジスタに限定されない。例えば、ｎチャネル型またはｐチャネル型Ｓｉトランジスタとすることができる。なお、トランジスタＭ１１、Ｍ１２がＳｉトランジスタである場合、トランジスタＭ１１、Ｍ１２のオフ電流特性が十分ではないため、動作周波数が低すぎると、期間ＴＴ３、ＴＴ４において、電圧Ｖｒｂ、Ｖｒｓの変動が許容されなくなる。他方、トランジスタＭ１１、Ｍ１２が極小オフ電流のＯＳトランジスタであれば、電圧Ｖｒｂ、Ｖｒｓの変動を抑えることができるので、モニタ回路１３０の動作周波数を必要以上に高くしなくてもよい。よって、モニタ回路１３０の動的消費電力を抑えることができる。 The transistors M11 and M12 are not limited to the OS transistors. For example, an n-channel or p-channel Si transistor can be used. When the transistors M11 and M12 are Si transistors, the off-current characteristics of the transistors M11 and M12 are not sufficient. Therefore, if the operating frequency is too low, fluctuations in the voltages Vrb and Vrs are not allowed in the periods TT3 and TT4. . On the other hand, if the transistors M11 and M12 are OS transistors with extremely small off-state current, the fluctuation of the voltages Vrb and Vrs can be suppressed, so the operating frequency of the monitor circuit 130 does not have to be higher than necessary. Therefore, dynamic power consumption of the monitor circuit 130 can be suppressed.
　トランジスタＭ１１、Ｍ１２はバックゲートの無いトランジスタとすることができる。この場合、トランジスタＭ１１、Ｍ１２のオフ電流特性を向上させるため、例えば、トランジスタＭ１１、Ｍ１２がｎチャネル型トランジスタであれば、信号ＭＯＮ１、ＭＯＮ２の“Ｌ”をＶＳＳＡよりも低くしてもよい。トランジスタＭ１１、Ｍ１２がｐチャネル型トランジスタであれば、信号ＭＯＮ１、ＭＯＮ２の“Ｈ”をＶＤＤＡよりも高くしてもよい。 The transistors M11 and M12 can be transistors without back gates. In this case, in order to improve the off current characteristics of the transistors M11 and M12, for example, when the transistors M11 and M12 are n-channel transistors, “L” of the signals MON1 and MON2 may be lower than VSSA. If the transistors M11 and M12 are p-channel transistors, “H” of the signals MON1 and MON2 may be higher than VDDA.
　トランジスタＭ１はバックゲートの無いトランジスタとすることができる。この場合、トランジスタＭ１ｒとトランジスタＭ１の差異は、バックゲートの有無になる。電圧Ｖｍｏｎを用いて、トランジスタＭ１のゲートに入力される“Ｈ”及び／又は“Ｌ”の電圧を調整することで、トランジスタＭ１のオン電流特性及び／又はオフ電流特性の変動を補正することができる。 The transistor M1 can be a back gateless transistor. In this case, the difference between the transistor M1r and the transistor M1 is the presence or absence of a back gate. Correcting the variation of the on current characteristic and / or the off current characteristic of the transistor M1 by adjusting the voltage of “H” and / or “L” input to the gate of the transistor M1 using the voltage Vmon it can.
　トランジスタＭ１、Ｍ１ｒはＯＳトランジスタに限定されず、ｎチャネル型トランジスタにも限定されない。トランジスタＭ１、Ｍ１ｒは例えば、ｎチャネル型またはｐチャネル型Ｓｉトランジスタとすることができる。図６は、トランジスタＭ１ｒに代えてｐチャネル型トランジスタＭ２ｒを用いたモニタ回路１３１の回路図を示す。モニタ回路１３１の機能は、モニタ回路１３０と同様であるので、モニタ回路１３１の電圧、電流の符号には、モニタ回路１３０と同じものを用いる。 The transistors M1 and M1r are not limited to OS transistors, and are not limited to n-channel transistors. The transistors M1 and M1r can be, for example, n-channel or p-channel Si transistors. FIG. 6 shows a circuit diagram of a monitor circuit 131 using a p-channel transistor M2r in place of the transistor M1r. Since the function of the monitor circuit 131 is the same as that of the monitor circuit 130, the same sign as that of the monitor circuit 130 is used as the sign of the voltage and current of the monitor circuit 131.
　端子ａ５には電圧ＶＤＤＡが入力される。トランジスタＭ２ｒの電圧Ｖｇｓ＿ｒ、Ｖｂｇｓ＿ｒ、Ｖｄｓ＿ｒ、ドレイン電流Ｉｄ＿ｒの極性がトランジスタＭ１ｒのものと反対になるように、電圧Ｖ１、Ｖ２、Ｖａが設定される。具体的には、電圧Ｖ１、Ｖ２、Ｖａは式（２．４）~（２．６）を満たす。
　Ｖ１＜ＶＴｂｇ（Ｔｍｉｎ）＿ｒ　　　　　　　　　　　　　　　　（２．４）
　Ｖ２＝Ｖ１ーＶＴｂｇ（Ｔｍａｘ）＿ｒ＋Ｖａ＜ＶＤＤＡ　　　　（２．５）
　ＶＴｂｇ（Ｔｍｉｎ）＿ｒーＶＴｂｇ（Ｔｍａｘ）＿ｒ＋Ｖａ＜０（２．６） The voltage VDDA is input to the terminal a5. The voltages V1, V2, Va are set such that the polarities of the voltages Vgs_r, Vbgs_r, Vds_r of the transistor M2r and the drain current Id_r are opposite to those of the transistor M1r. Specifically, the voltages V1, V2, and Va satisfy the equations (2.4) to (2.6).
V1 <VTbg (Tmin) _r (2.4)
V2 = V1−VTbg (Tmax) _r + Va <VDDA (2.5)
VTbg (Tmin) _r−VTbg (Tmax) _r + Va <0 (2.6)
　図３Ｂのタイミングチャートを用いて、モニタ回路１３１の動作を説明する。モニタ回路１３１の動作はモニタ回路１３０と同様なため、説明を簡略している。 The operation of the monitor circuit 131 will be described using the timing chart of FIG. 3B. The operation of the monitor circuit 131 is the same as that of the monitor circuit 130, so the description is simplified.
（期間ＴＴ１）
　トランジスタＭ１１、Ｍ１２がオンであり、ノードＳｒｓ、Ｓｒｂは電圧ＶＤＤＡ、Ｖ１が入力される。式（２．４）~（２．６）を満たすため、トランジスタＭ２ｒはノーマリオン特性を示す。電圧Ｖｄｓ＿ｒは０Ｖよりも小さい。よって、ドレイン電流Ｉｄ＿ｒが流れる。 (Period TT1)
The transistors M11 and M12 are on, and the nodes Srs and Srb receive the voltages VDDA and V1. The transistor M2r exhibits normally on characteristics in order to satisfy the formulas (2.4) to (2.6). The voltage Vds_r is smaller than 0V. Thus, the drain current Id_r flows.
（期間ＴＴ２）
　トランジスタＭ１２がオフであるので、ノードＳｒｓは電気的に浮遊状態である。ドレイン電流Ｉｄ＿ｒが流れているため、電圧Ｖｒｓは低下する。やがて、電圧Ｖｒｓは、Ｖ１−ＶＴｂｇ（Ｔｍ）＿ｒに収束し、ドレイン電流Ｉｄ＿ｒは流れなくなる。式（２．４）~（２．６）を満たしているので、電圧ＶｒｓがＶ１−ＶＴｂｇ（Ｔｍ）＿ｒに収束した状態でも、動作温度範囲において電圧Ｖｄｓ＿ｒは０Ｖよりも小さい。 (Period TT2)
Since the transistor M12 is off, the node Srs is electrically floating. Since the drain current Id_r is flowing, the voltage Vrs decreases. Eventually, the voltage Vrs converges to V1-VTbg (Tm) _r, and the drain current Id_r stops flowing. Since Expressions (2.4) to (2.6) are satisfied, the voltage Vds_r is smaller than 0 V in the operating temperature range even in the state where the voltage Vrs converges to V1-VTbg (Tm) _r.
（期間ＴＴ３）
　トランジスタＭ１１がオフになるため、ノードＳｒｓ、Ｓｒｂは電気的に浮遊状態になる。容量素子Ｃ１１によって、電圧Ｖｂｇｓ＿ｒがＶＴｂｇ（Ｔｍ）＿ｒに固定されているので、トランジスタＭ２ｒはオフ状態が維持される。 (Period TT3)
Since the transistor M11 is turned off, the nodes Srs and Srb are in an electrically floating state. Since the voltage Vbgs_r is fixed to VTbg (Tm) _r by the capacitive element C11, the transistor M2r is maintained in the off state.
（期間ＴＴ４）
　トランジスタＭ１２がオンになり、ノードＳｒｓには電圧ＶＤＤＡが入力される。ノードＳｒｂとノードＳｒｓ間の電圧差はＶＴｂｇ（Ｔｍ）＿ｒに固定されているので、電圧ＶｒｂはＶＴｂｇ（Ｔｍ）＿ｒ＋ＶＤＤＡになる。電圧Ｖｒｂが電圧Ｖｍｏｎとして端子ａ６から出力される。電圧ＶＤＤＡは電源電圧であってトランジスタＭ２ｒの電気特性に依存しないため、端子ａ６の電圧Ｖｍｏｎからしきい値電圧ＶＴｂｇ（Ｔｍ）＿ｒを取得することができる。 (Period TT4)
The transistor M12 is turned on, and the voltage VDDA is input to the node Srs. Since the voltage difference between the node Srb and the node Srs is fixed to VTbg (Tm) _r, the voltage Vrb is VTbg (Tm) _r + VDDA. The voltage Vrb is output from the terminal a6 as the voltage Vmon. Since the voltage VDDA is a power supply voltage and does not depend on the electrical characteristics of the transistor M2r, the threshold voltage VTbg (Tm) _r can be acquired from the voltage Vmon of the terminal a6.
＜＜半導体装置１０１＞＞
　図７に示す半導体装置１０１は、半導体装置１１０、電圧出力回路１２２を有する。電圧出力回路１２２は、電圧補正回路１５０、電圧生成回路１７０、出力端子ＯＵＴ２を有する。電圧生成回路１７０は電圧Ｖｐｗを出力する。電圧補正回路１５０は、電圧Ｖｐｗを補正し、電圧ＶＯＴ２を生成する。出力端子ＯＵＴ２は電圧ＶＯＴ２を出力する。電圧ＶＯＴ２は、半導体装置１１０においてトランジスタＭ１のバックゲートに入力される電圧ＶＢＧ１として用いられる。 << semiconductor device 101 >>
A semiconductor device 101 illustrated in FIG. 7 includes a semiconductor device 110 and a voltage output circuit 122. The voltage output circuit 122 has a voltage correction circuit 150, a voltage generation circuit 170, and an output terminal OUT2. The voltage generation circuit 170 outputs a voltage Vpw. The voltage correction circuit 150 corrects the voltage Vpw to generate a voltage VOT2. The output terminal OUT2 outputs a voltage VOT2. The voltage VOT2 is used as a voltage VBG1 input to the back gate of the transistor M1 in the semiconductor device 110.
＜電圧補正回路１５０＞
　電圧補正回路１５０は、モニタ回路１３０、容量素子Ｃ１２、Ｃ１３、リセット回路１３２、ソースフォロワ回路１３４、オペアンプ１３６、スイッチ回路１３８を有する。容量素子Ｃ１２の第１端子、第２端子は、モニタ回路１３０の出力端子（ノードＳｒｂ）、ソースフォロワ回路１３４の入力端子にそれぞれ電気的に接続されている。ここでは、ソースフォロワ回路１３４の入力端子、出力端子に相当するノードをそれぞれノードＳｒｔ、Ｓｓｆと呼ぶ。 <Voltage Correction Circuit 150>
The voltage correction circuit 150 includes a monitor circuit 130, capacitive elements C12 and C13, a reset circuit 132, a source follower circuit 134, an operational amplifier 136, and a switch circuit 138. The first terminal and the second terminal of the capacitive element C12 are electrically connected to the output terminal (node Srb) of the monitor circuit 130 and the input terminal of the source follower circuit 134, respectively. Here, nodes corresponding to the input terminal and the output terminal of the source follower circuit 134 are referred to as nodes Srt and Ssf, respectively.
　リセット回路１３２は、ノードＳｒｔをリセットするための回路であり、トランジスタＭ１４を有する。ここでは、トランジスタＭ１４はバックゲートを有するＯＳトランジスタである。トランジスタＭ１４のソースはノードＳｒｔに電気的に接続され、ゲート、バックゲート、ドレインには信号ＲＳＴ１、電圧ＶＢＧＲ１、Ｖ４がそれぞれ入力される。 The reset circuit 132 is a circuit for resetting the node Srt, and includes a transistor M14. Here, the transistor M14 is an OS transistor having a back gate. The source of the transistor M14 is electrically connected to the node Srt, and the signal RST1 and the voltages VBGR1 and V4 are input to the gate, the back gate, and the drain, respectively.
　ソースフォロワ回路１３４は、直列に電気的に接続されているトランジスタＭ１５、Ｍ１６を有する。ここでは、トランジスタＭ１５、Ｍ１６はｎチャネル型Ｓｉトランジスタである。トランジスタＭ１５のゲート、ソースは電圧ＶＢＩＳ１、ＶＳＳＡが入力される。トランジスタＭ１６のゲートがノードＳｒｔに相当する。トランジスタＭ１６のドレインには電圧Ｖ３が入力される。 The source follower circuit 134 includes transistors M15 and M16 electrically connected in series. Here, the transistors M15 and M16 are n-channel Si transistors. Voltages VBIS1 and VSSA are input to the gate and source of the transistor M15. The gate of the transistor M16 corresponds to the node Srt. The voltage V3 is input to the drain of the transistor M16.
　オペアンプ１３６の反転入力端子はノードＳｓｆに電気的に接続され、非反転入力端子は電圧ＶＳＳＡが入力される。ノードＳａｐはオペアンプの出力端子に対応する。Ｒｉ、Ｒｆはそれぞれ、入力抵抗、帰還抵抗である。オペアンプ１３６のトランジスタは、例えば、Ｓｉトランジスタである。 The inverting input terminal of the operational amplifier 136 is electrically connected to the node Ssf, and the voltage VSSA is input to the non-inverting input terminal. The node Sap corresponds to the output terminal of the operational amplifier. Ri and Rf are an input resistance and a feedback resistance, respectively. The transistor of the operational amplifier 136 is, for example, a Si transistor.
　容量素子Ｃ１３の第１端子、第２端子は、ノードＳａｐ、出力端子ＯＵＴ２にそれぞれ電気的に接続される。容量素子Ｃ１３は、出力端子ＯＵＴ２の電圧ＶＯＴ２を保持する。 The first terminal and the second terminal of the capacitive element C13 are electrically connected to the node Sap and the output terminal OUT2, respectively. The capacitive element C13 holds the voltage VOT2 of the output terminal OUT2.
　スイッチ回路１３８は、電圧生成回路１７０の出力端子と出力端子ＯＵＴ２との間の電気的接続を制御する。スイッチ回路１３８は、例えば、アナログスイッチ回路１３８ａ、インバータ回路１３８ｂを有する。信号ＳＥＴ１はアナログスイッチ回路１３８ａのオンオフを制御する。アナログスイッチ回路１３８ａ、インバータ回路１３８ｂは、例えば、Ｓｉトランジスタで構成される。 Switch circuit 138 controls an electrical connection between the output terminal of voltage generation circuit 170 and output terminal OUT2. The switch circuit 138 includes, for example, an analog switch circuit 138a and an inverter circuit 138b. The signal SET1 controls the on / off of the analog switch circuit 138a. The analog switch circuit 138a and the inverter circuit 138b are configured by, for example, Si transistors.
＜電圧生成回路１７０＞
　図８に電圧生成回路１７０の一例を示す。電圧生成回路１７０は制御回路１７１、チャージポンプ回路１７３を有する。 <Voltage Generation Circuit 170>
An example of the voltage generation circuit 170 is shown in FIG. The voltage generation circuit 170 includes a control circuit 171 and a charge pump circuit 173.
　制御回路１７１は、信号ＷＡＫＥ１及びクロック信号ＣＬＫ１に応じて、ゲーテッドクロック信号ＧＣＬＫ１（以下、クロック信号ＧＣＬＫ１と呼ぶ。）を生成する。クロック信号ＧＣＬＫ１は、チャージポンプ回路１７３に入力される。クロック信号ＧＣＬＫ１がアクティブであるとき、チャージポンプ回路１７３は動作する。 Control circuit 171 generates gated clock signal GCLK1 (hereinafter referred to as clock signal GCLK1) in response to signal WAKE1 and clock signal CLK1. The clock signal GCLK1 is input to the charge pump circuit 173. When clock signal GCLK1 is active, charge pump circuit 173 operates.
　図８に示すチャージポンプ回路１７３は、４段降圧型チャージポンプ回路であり、ＧＮＤから電圧Ｖｐｗを生成する。チャージポンプ回路１７３は、２個のインバータ回路、４個のダイオード接続されたトランジスタ、４個の容量素子を有する。トランジスタは、バックゲートを有するＯＳトランジスタであり、バックゲートとドレインとが互いに電気的に接続されている。 The charge pump circuit 173 shown in FIG. 8 is a four-stage step-down charge pump circuit, and generates a voltage Vpw from GND. The charge pump circuit 173 includes two inverter circuits, four diode-connected transistors, and four capacitive elements. The transistor is an OS transistor having a back gate, and the back gate and the drain are electrically connected to each other.
　チャージポンプ回路１７３のトランジスタは、バックゲートを有さないＯＳトランジスタでもよい。もちろん、トランジスタはＯＳトランジスタに限定されない、ｎチャネル型またはｐチャネル型Ｓｉトランジスタであってもよい。なお、オン電流／オフ電流の比は、ＯＳトランジスタのほうがＳｉトランジスタよりも高いため、ＯＳトランジスタはチャージポンプ回路１７３に適している。 The transistor of the charge pump circuit 173 may be an OS transistor having no back gate. Of course, the transistor may be an n-channel or p-channel Si transistor, not limited to an OS transistor. The OS transistor is suitable for the charge pump circuit 173 because the ratio of the on current / off current is higher in the OS transistor than in the Si transistor.
　例えば、電圧ＶｐｗをＧＮＤまたは電圧ＶＳＳＡにできる場合は、電圧出力回路１２２に電圧生成回路１７０を設けず、電圧Ｖｐｗとして、ＧＮＤまたは電圧ＶＳＳＡを電圧補正回路１５０に入力すればよい。 For example, when the voltage Vpw can be GND or the voltage VSSA, the voltage generation circuit 170 may not be provided in the voltage output circuit 122, and GND or the voltage VSSA may be input to the voltage correction circuit 150 as the voltage Vpw.
＜電圧出力回路１２２の動作例＞
　図７~図９を参照して、電圧出力回路１２２の動作例を説明する。図９において、ｔ０~ｔ８は時刻を表す。なお、ｔ０~ｔ５の間の温度ＴｍはＴｐ１であり、ｔ６~ｔ８の間の温度ＴｍはＴｐ２であるとする。 <Operation Example of Voltage Output Circuit 122>
An operation example of the voltage output circuit 122 will be described with reference to FIGS. 7 to 9. In FIG. 9, t0 to t8 represent time. The temperature Tm between t0 and t5 is Tp1, and the temperature Tm between t6 and t8 is Tp2.
　ｔ０~ｔ１の間、信号ＷＡＫＥ１は“Ｈ”であるため、制御回路１７１はアクティブなクロック信号ＧＣＬＫ１を生成する。チャージポンプ回路１７３は降圧動作を行う。電圧Ｖｐｗは低下し、やがて電圧ＶＩＮＴに達する。半導体装置１０１のトランジスタＭ１は駆動されない。時刻ｔ１で、信号ＷＡＫＥ１は“Ｌ”になり、チャージポンプ回路１７３は降圧動作を停止する。 Since the signal WAKE1 is “H” during t0 to t1, the control circuit 171 generates an active clock signal GCLK1. The charge pump circuit 173 performs a step-down operation. The voltage Vpw decreases and eventually reaches the voltage VINT. The transistor M1 of the semiconductor device 101 is not driven. At time t1, the signal WAKE1 becomes "L", and the charge pump circuit 173 stops the step-down operation.
　時刻ｔ１で、信号ＲＳＴ１、ＳＥＴ１を“Ｈ”にして、ノードＳｒｔ、出力端子ＯＵＴ２を初期化する。ノードＳｒｔ、出力端子ＯＵＴ２は、電圧Ｖ４、ＶＩＮＴが入力される。電圧Ｖ４は、例えば、ＶＤＤＡ／２とすればよい。 At time t1, the signals RST1 and SET1 are set to "H" to initialize the node Srt and the output terminal OUT2. The voltages V4 and VINT are input to the node Srt and the output terminal OUT2. The voltage V4 may be, for example, VDDA / 2.
　ｔ２~ｔ３の間、信号ＳＥＴ１、ＲＳＴ１を“Ｈ”に固定したまま、モニタ回路１３０を動作して、しきい値電圧ＶＴｂｇ＿ｒ（Ｔｐ１）を取得する。電圧ＶｒｂはＶＴｂｇ＿ｒ（Ｔｐ１）＋ＶＳＳである。信号ＭＯＮ１、ＭＯＮ２の電圧は不定である。 During t2 to t3, the monitor circuit 130 is operated while the signals SET1 and RST1 are fixed at "H" to acquire the threshold voltage VTbg_r (Tp1). The voltage Vrb is VTbg_r (Tp1) + VSS. The voltages of the signals MON1 and MON2 are undefined.
　時刻ｔ３で信号ＳＥＴ１を“Ｌ”にして、出力端子ＯＵＴ２への電圧ＶＩＮＴの入力を停止する。 At time t3, the signal SET1 is set to "L" to stop the input of the voltage VINT to the output terminal OUT2.
　時刻ｔ４で信号ＲＳＴ１を“Ｌ”にして、トランジスタＭ１４をオフにする。ノードＳｒｔは電気的に浮遊状態になるので、容量素子Ｃ１２の電荷量に応じた電流がノードＳｒｔを流れる。ソースフォロワ回路１３４は、ノードＳｒｔを流れる電流を電圧に変換する。容量素子Ｃ１２の電荷量は、電圧Ｖｒｂ＝ＶＴｂｇ＿ｒ（Ｔｐ１）＋ＶＳＳに依存するため、電圧Ｖｓｆはしきい値電圧ＶＴｂｇ＿ｒ（Ｔｐ１）に依存する。 At time t4, the signal RST1 is set to "L" to turn off the transistor M14. Since the node Srt is electrically floated, a current according to the charge amount of the capacitive element C12 flows through the node Srt. Source follower circuit 134 converts the current flowing through node Srt into a voltage. Since the charge amount of the capacitive element C12 depends on the voltage Vrb = VTbg_r (Tp1) + VSS, the voltage Vsf depends on the threshold voltage VTbg_r (Tp1).
　上掲したように、しきい値電圧ＶＴｂｇ＿ｒとしきい値電圧ＶＴｇ＿ｒとの関係は線形関数で表され、しきい値電圧ＶＴｇ＿ｒとバックゲート電圧Ｖｂｇ＿ｒとの関係が線形関数で表される場合、動作温度範囲において、ソースフォロワ回路１３４の入出力特性が線形性を示すように、トランジスタＭ１４、Ｍ１５のしきい値電圧、電圧Ｖ４、ＶＢＩＳ１を設定することが好ましい。 As described above, the relationship between the threshold voltage VTbg_r and the threshold voltage VTg_r is represented by a linear function, and when the relationship between the threshold voltage VTg_r and the back gate voltage Vbg_r is represented by a linear function, the operating temperature In the range, it is preferable to set the threshold voltages of the transistors M14 and M15 and the voltages V4 and VBIS1 so that the input / output characteristics of the source follower circuit 134 exhibit linearity.
　オペアンプ１３６は電圧Ｖｓｆを増幅し、電圧Ｖａｐを生成する。そのため、電圧Ｖａｐは、しきい値電圧ＶＴｂｇ＿ｒ（Ｔｐ１）に依存する。スイッチ回路１３８はオフであるので、電圧Ｖａｐ、容量素子Ｃ１３の容量および出力端子ＯＵＴ２の寄生容量に応じて、電圧ＶＯＴ２は変化し、ＶＩＮＴ＋ΔＶｏｕｔ２（Ｔｐ１）となる。電圧ΔＶｏｕｔ２（Ｔｐ１）は、温度Ｔｐ１のときの電圧ＶＯＴ２の補正電圧である。ＶＩＮＴ＋ΔＶｏｕｔ２（Ｔｍ）がバックゲート電圧Ｖｂｇ＿ｒ（Ｔｍ）と等しくなるように、電圧ＶＩＮＴ、ソースフォロワ回路１３４の仕様（例えば、Ｍ１５とＭ１６のしきい値電圧、電圧Ｖ４）、オペアンプ１３６の仕様（例えば、ゲイン、ＲｆとＲｉの抵抗値）、容量素子Ｃ１２、Ｃ１３の容量値などが設定される。 The operational amplifier 136 amplifies the voltage Vsf to generate a voltage Vap. Therefore, voltage Vap depends on threshold voltage VTbg_r (Tp1). Since the switch circuit 138 is off, the voltage VOT2 changes according to the voltage Vap, the capacitance of the capacitive element C13, and the parasitic capacitance of the output terminal OUT2, to become VINT + ΔVout2 (Tp1). The voltage ΔVout2 (Tp1) is a correction voltage of the voltage VOT2 at the temperature Tp1. The voltage VINT, specifications of the source follower circuit 134 (for example, threshold voltages of M15 and M16, voltage V4), and specifications of the operational amplifier 136 (for example, so that VINT + ΔVout2 (Tm) becomes equal to the back gate voltage Vbg_r (Tm). The gain, the resistances of Rf and Ri), the capacitances of the capacitive elements C12 and C13, and the like are set.
　例えば、電圧ＶＩＮＴが、基準温度ＴｒｅｆのときのトランジスタＭ１のバックゲート電圧Ｖｂｇ（Ｔｒｅｆ）である場合、ΔＶｏｕｔ２（Ｔｍ）は、ΔＶｏｕｔ２（Ｔｍ）＝Ｖｂｇ（Ｔｍ）−Ｖｂｇ（Ｔｒｅｆ）＝Ｖｂｇ＿ｒ（Ｔｍ）−Ｖｂｇ＿ｒ（Ｔｒｅｆ）であればよい。 For example, when the voltage VINT is the back gate voltage Vbg (Tref) of the transistor M1 at the reference temperature Tref, ΔVout2 (Tm) is ΔVout2 (Tm) = Vbg (Tm) −Vbg (Tref) = Vbg_r (Tm) )-Vbg_r (Tref).
　ΔＶｏｕｔ２（Ｔｍ）はモニタ回路１３０の出力電圧Ｖｒｂに依存する。温度Ｔｍが上昇すると電圧Ｖｒｂは大きくなる。トランジスタＭ１のしきい値電圧ＶＴｇの変動を補正するためには、温度Ｔｍが高くなるとΔＶｏｕｔ２（Ｔｍ）を小さくし、温度Ｔｍが下がるとΔＶｏｕｔ２（Ｔｍ）を大きくする。以上のことから、オペアンプ１３６を反転増幅回路で構成している。 ΔVout2 (Tm) depends on the output voltage Vrb of the monitor circuit 130. When the temperature Tm rises, the voltage Vrb increases. In order to correct the fluctuation of the threshold voltage VTg of the transistor M1, ΔVout2 (Tm) is decreased as the temperature Tm increases, and ΔVout2 (Tm) is increased as the temperature Tm decreases. From the above, the operational amplifier 136 is configured by an inverting amplifier circuit.
　時刻ｔ４以降、電圧ＶＯＵＴ２はＶＩＮＴから変化し、やがてＶｂｇ（Ｔｐ１）で安定する。電圧ＶＯＵＴ２が安定した後、時刻ｔ５でトランジスタＭ１の駆動を開始する。ｔ５~ｔ６の期間、トランジスタＭ１のバックゲートには、電圧Ｖｂｇ（Ｔｐ１）が入力される。 After time t4, the voltage VOUT2 changes from VINT and eventually stabilizes at Vbg (Tp1). After the voltage VOUT2 is stabilized, driving of the transistor M1 is started at time t5. During a period from t5 to t6, the voltage Vbg (Tp1) is input to the back gate of the transistor M1.
　時刻ｔ２から一定期間経過後、モニタ回路１３０を動作させて、しきい値電圧ＶＴｂｇ＿ｒ（Ｔｍ）を再度取得する。まず、時刻ｔ６で、トランジスタＭ１の駆動を停止する。ｔ７~ｔ８の期間に、モニタ回路１３０によってしきい値電圧ＶＴｂｇ＿Ｔ（Ｔｍ２）を取得する。電圧ＶｒｂがＶＴｂｇ＿ｒ（Ｔｍ２）＋ＶＳＳで固定されると、電圧ＶＯＵＴ２はＶｂｇ（Ｔｍ２）で安定する。電圧ＶＯＵＴ２が安定した後、時刻ｔ８でトランジスタＭ１の駆動を再開する。時刻ｔ８以降、ｔ５~ｔ８の動作が繰り返される。例えば、ｔ５~ｔ８の動作が所定の回数行われたあとに、ｔ０~ｔ６の動作を実行してもよい。 After a certain period of time has elapsed from time t2, the monitor circuit 130 is operated to acquire the threshold voltage VTbg_r (Tm) again. First, at time t6, the driving of the transistor M1 is stopped. In the period from t7 to t8, the monitor circuit 130 acquires the threshold voltage VTbg_T (Tm2). When the voltage Vrb is fixed at VTbg_r (Tm2) + VSS, the voltage VOUT2 is stabilized at Vbg (Tm2). After the voltage VOUT2 stabilizes, the driving of the transistor M1 is resumed at time t8. After time t8, the operations of t5 to t8 are repeated. For example, after the operation of t5 to t8 is performed a predetermined number of times, the operation of t0 to t6 may be performed.
　上掲したように、モニタ回路１３０によって、しきい値電圧ＶＴｂｇ＿ｒ（Ｔｍ）を定期的に取得することで、動作温度に適した電圧をトランジスタＭ１のバックゲートに入力できる。その結果、トランジスタＭ１のしきい値電圧ＶＴｇの温度による変動を定期的に補正することができる。 As described above, the threshold voltage VTbg_r (Tm) is periodically acquired by the monitor circuit 130, whereby a voltage suitable for the operating temperature can be input to the back gate of the transistor M1. As a result, it is possible to periodically correct the variation of the threshold voltage VTg of the transistor M1 due to the temperature.
＜＜半導体装置１０２＞＞
　図１０に示す半導体装置１０２は、半導体装置１１２、電圧出力回路１２４を有する。半導体装置１１２は、電圧ＶＢＧ１が供給されるＮ（Ｎは１以上の整数）個のパワードメイン１１８［１］~１１８［Ｎ］を有する。パワードメイン１１８［１］~１１８［Ｎ］にはトランジスタＭ１が設けられている。電圧出力回路１２４は、電圧生成回路１７０、電圧補正回路１６０、Ｎ個の出力端子ＯＵＴ２［１］~ＯＵＴ２［Ｎ］を有する。電圧補正回路１６０はＮ個の電圧補正回路１５０［１］~１５１［Ｎ］を有する。電圧生成回路１７０は電圧補正回路１５０［１］~１５１［Ｎ］に電圧Ｖｐｗを供給する。電圧補正回路１５０［１］~１５０［Ｎ］は、出力端子ＯＵＴ２［１］~ＯＵＴ２［Ｎ］の電圧ＶＯＴ２［１］~ＶＯＴ２［Ｎ］を補正する。 << Semiconductor Device 102 >>
A semiconductor device 102 illustrated in FIG. 10 includes a semiconductor device 112 and a voltage output circuit 124. The semiconductor device 112 has N (N is an integer of 1 or more) power domains 118 [1] to 118 [N] to which the voltage VBG1 is supplied. A transistor M1 is provided in each of the power domains 118 [1] to 118 [N]. The voltage output circuit 124 has a voltage generation circuit 170, a voltage correction circuit 160, and N output terminals OUT2 [1] to OUT2 [N]. The voltage correction circuit 160 includes N voltage correction circuits 150 [1] to 151 [N]. The voltage generation circuit 170 supplies the voltage Vpw to the voltage correction circuits 150 [1] to 151 [N]. The voltage correction circuits 150 [1] to 150 [N] correct the voltages VOT2 [1] to VOT2 [N] of the output terminals OUT2 [1] to OUT2 [N].
＜＜半導体装置１０３＞＞
　図１１に示す半導体装置１０３は、半導体装置１１３、電圧出力回路１２２を有する。半導体装置１１３は、ドライバ回路１１４、配線ＧＬ２、トランジスタＭ２を有する。トランジスタＭ２のゲートは配線ＧＬ２に電気的に接続されている。 << semiconductor device 103 >>
A semiconductor device 103 illustrated in FIG. 11 includes a semiconductor device 113 and a voltage output circuit 122. The semiconductor device 113 includes a driver circuit 114, a wiring GL2, and a transistor M2. The gate of the transistor M2 is electrically connected to the wiring GL2.
　ドライバ回路１１４は、電圧ＶＤＤＡ、ＶＩＨ２、ＶＳＳＡ、ＶＩＬ２が入力される。電圧ＶＤＤＡ、ＶＳＳＡは電源電圧である。電圧出力回路１２２の出力電圧ＶＯＴ２は、ドライバ回路１１４において、電圧ＶＩＬ２として用いられる。なお、電圧ＶＩＬ２が供給されるＮ個のパワードメインを半導体装置１１２が有する場合は、図１０に示す電圧出力回路１２４を用いればよい。 The driver circuit 114 receives the voltages VDDA, VIH2, VSSA, and VIL2. The voltages VDDA and VSSA are power supply voltages. The output voltage VOT2 of the voltage output circuit 122 is used as a voltage VIL2 in the driver circuit 114. When the semiconductor device 112 includes N power domains to which the voltage VIL2 is supplied, the voltage output circuit 124 illustrated in FIG. 10 may be used.
　電圧補正回路１５０は配線ＧＬ２の“Ｌ”を温度に応じて補正する。例えば、ＶＩＮＴを、基準温度ＴｒｅｆのときのＶＩＬ２（Ｔｒｅｆ）とする。トランジスタＭ１ｒとトランジスタＭ２の差異は、バックゲートの有無である。なお、トランジスタＭ２はバックゲートを有していてもよい。この場合、バックゲートは定電圧を入力する。または、ゲート、ソースおよびドレインの何れか１に電気的に接続される。 The voltage correction circuit 150 corrects "L" of the wiring GL2 in accordance with the temperature. For example, let VINT be VIL2 (Tref) at the reference temperature Tref. The difference between the transistor M1r and the transistor M2 is the presence or absence of a back gate. Note that the transistor M2 may have a back gate. In this case, the back gate inputs a constant voltage. Alternatively, it is electrically connected to any one of the gate, the source, and the drain.
　ドライバ回路１１４は、図１２Ａに示す回路１１４Ａを有する。回路１１４Ａは、配線ＧＬを選択するための信号ＳＥＬＧを生成する。回路１１４Ａには、電圧ＶＩＨ２、ＶＩＬ２、ＶＳＳＡ、信号ＷＩＮ、ＷＩＮＢが入力される。信号ＷＩＮＢは、信号ＷＩＮの反転信号である。 The driver circuit 114 has a circuit 114A shown in FIG. 12A. The circuit 114A generates a signal SELG for selecting the wiring GL. Voltages VIH2, VIL2, VSSA, and signals WIN, WINB are input to the circuit 114A. Signal WINB is an inverted signal of signal WIN.
　図１２Ｂは回路１１４Ａのタイミングチャートを示す。回路１１４Ａは、信号ＷＩＮが“Ｈ”のとき“Ｈ”の信号ＳＥＬＧを配線ＧＬに出力し、信号ＷＩＮが“Ｌ”のとき“Ｌ”の信号ＳＥＬＧを配線ＧＬに出力する。信号ＷＩＮ、ＷＩＮＢの“Ｈ”、“Ｌ”は、それぞれ電圧ＶＤＤＡ、ＶＳＳＡである。信号ＳＥＬＧの“Ｈ”、“Ｌ”は、電圧ＶＩＨ２、ＶＩＬ２である。回路１１４Ａは、信号ＷＩＮをレベルシフトするレベルシフタとして用いられている。 FIG. 12B shows a timing chart of the circuit 114A. The circuit 114A outputs the signal SELG of "H" to the wiring GL when the signal WIN is "H", and outputs the signal SELG of "L" to the wiring GL when the signal WIN is "L". The "H" and "L" of the signals WIN and WINB are the voltages VDDA and VSSA, respectively. The "H" and "L" of the signal SELG are the voltages VIH2 and VIL2. The circuit 114A is used as a level shifter for level shifting the signal WIN.
　電圧ＶＩＬ２は電圧出力回路１２２によって調整されるので、温度が上昇すると、電圧ＶＩＬ２は小さくなる。よって、温度上昇によりトランジスタＭ２のしきい値電圧ＶＴｇが低下しても、電圧ＶＩＬ２を低下させることで、トランジスタＭ２のオフ電流の増加をキャンセルすることができる。 Since the voltage VIL2 is adjusted by the voltage output circuit 122, the voltage VIL2 decreases as the temperature rises. Therefore, even if the threshold voltage VTg of the transistor M2 is lowered due to the temperature rise, the increase of the off current of the transistor M2 can be canceled by lowering the voltage VIL2.
　半導体装置１０３に、電圧ＶＩＨ２を調整する電圧出力回路を設けてもよい。この場合、電圧出力回路のオペアンプは非反転増幅回路で構成することが好ましい。温度低下によりトランジスタＭ２のしきい値電圧ＶＴｇが上昇しても、電圧ＶＩＨ２を大きくできるため、トランジスタＭ２のオン電流の低下をキャンセルすることができる。 The semiconductor device 103 may be provided with a voltage output circuit that adjusts the voltage VIH2. In this case, it is preferable that the operational amplifier of the voltage output circuit be constituted by a non-inverted amplifier circuit. Even if the threshold voltage VTg of the transistor M2 is increased due to the temperature decrease, the voltage VIH2 can be increased, so that the decrease of the on current of the transistor M2 can be canceled.
〔実施の形態２〕
　本実施の形態では、ＯＳトランジスタが用いられた半導体装置について説明する。 Second Embodiment
In this embodiment, a semiconductor device in which an OS transistor is used will be described.
＜記憶装置２００＞
　図１３Ａに示す記憶装置２００は、パワードメイン２１０、２１１、パワースイッチ２４１~２４３を有する。パワードメイン２１０には、制御回路２２０、周辺回路２２１が設けられている。パワードメイン２１１には、メモリセルアレイ２２２、電圧出力回路２７１が設けられている。 <Storage device 200>
The storage device 200 illustrated in FIG. 13A includes power domains 210 and 211, and power switches 241 to 243. In the power domain 210, a control circuit 220 and a peripheral circuit 221 are provided. In the power domain 211, a memory cell array 222 and a voltage output circuit 271 are provided.
　記憶装置２００は、電圧ＶＤＤＤ、ＶＳＳＳ、ＶＤＨＷ、ＶＤＨＲ、クロック信号ＧＣＬＫ２、アドレス信号ＡＤＤＲ、信号ＰＳＥ１、コマンド信号（例えば、チップイネーブル信号ＣＥ、書き込みイネーブル信号ＷＥ、バイト書き込みイネーブル信号ＢＷ）が入力される。記憶装置２００に入力される電圧、信号等は、記憶装置２００の回路構成、動作方法などに応じて適宜取捨される。 The storage device 200 receives the voltages VDDD, VSSS, VDHW, VDHR, the clock signal GCLK2, the address signal ADDR, the signal PSE1, and a command signal (eg, chip enable signal CE, write enable signal WE, byte write enable signal BW). . The voltages, signals, and the like input to the storage device 200 are appropriately discarded according to the circuit configuration, the operation method, and the like of the storage device 200.
　制御回路２２０は記憶装置２００全体を統括的に制御し、データの書き込み、読み出しを行う。制御回路２２０は、アドレス信号ＡＤＤＲ、外部からのコマンド信号を処理して、周辺回路２２１の制御信号を生成する。 The control circuit 220 generally controls the entire storage device 200 to write and read data. The control circuit 220 processes the address signal ADDR and an external command signal to generate a control signal of the peripheral circuit 221.
　信号ＰＳＥ１はパワースイッチ２４１~２４３のオンオフを制御する。信号ＰＳＥ１は、例えば、ＰＭＵ（電源管理装置）から送信される。パワースイッチ２４１~２４３は、パワードメイン２１０への電圧ＶＤＤＤ、ＶＤＨＷ、ＶＤＨＲの入力をそれぞれ制御する。制御回路２２０、周辺回路２２１を動作させる必要がない期間、パワースイッチ２４１~２４３をオフにして、パワードメイン２１０をパワーゲーティングする。 The signal PSE1 controls on / off of the power switches 241-243. The signal PSE1 is transmitted from, for example, a PMU (power management device). The power switches 241 to 243 respectively control inputs of the voltages VDDD, VDHW, and VDHR to the power domain 210. While the control circuit 220 and the peripheral circuit 221 do not need to be operated, the power switches 241 to 243 are turned off to powergate the power domain 210.
　図１３Ｂにメモリセルアレイ２２２の回路図を示す。メモリセルアレイ２２２は、メモリセル２０、書込みワード線ＷＷＬ、読出しワード線ＲＷＬ、書込みビット線ＷＢＬ、読出しビット線ＲＢＬ、配線ＰＬ、ＢＧＣＬ１を有する。配線ＢＧＣＬ１は、電圧出力回路２７１に電気的に接続される。電圧ＶＤＤＤ、ＶＳＳＳはそれぞれデータ“１”、“０”を表す電圧である。電圧ＶＤＨＷ、ＶＨＤＲはそれぞれ書込みワード線ＷＷＬ、読出しワード線ＲＷＬの“Ｈ”の電圧である。 A circuit diagram of the memory cell array 222 is shown in FIG. 13B. The memory cell array 222 includes a memory cell 20, a write word line WWL, a read word line RWL, a write bit line WBL, a read bit line RBL, and wirings PL and BGCL1. The wiring BGCL1 is electrically connected to the voltage output circuit 271. The voltages VDDD and VSSS are voltages representing data “1” and “0”, respectively. The voltages VDHW and VHDR are voltages of "H" of the write word line WWL and the read word line RWL, respectively.
　周辺回路２２１は、例えば、アドレス信号ＡＤＤＲが指定するメモリセル２０を選択する機能を有する。具体的にいえば、周辺回路２２１は、選択された行の書込みワード線ＷＷＬ、読出しワード線ＲＷＬを選択する機能、アドレス信号ＡＤＤＲが指定する列の書込みビット線ＷＢＬにデータを書き込む機能、および当該列の読出しビット線ＲＢＬからデータを読み出す機能をもつ。 The peripheral circuit 221 has, for example, a function of selecting the memory cell 20 specified by the address signal ADDR. Specifically, peripheral circuit 221 has a function of selecting write word line WWL and read word line RWL in the selected row, a function of writing data in write bit line WBL in a column designated by address signal ADDR, and It has a function of reading data from the column read bit line RBL.
　メモリセル２０は２Ｔ１Ｃ（２トランジスタ１容量）型のゲインセルであり、トランジスタＭ２１、Ｍ２５、容量素子Ｃ２５を有する。容量素子Ｃ２５は、トランジスタＭ２５のゲート電圧を保持するための保持容量である。トランジスタＭ２１、Ｍ２５はそれぞれ書き込みトランジスタ、読出しトランジスタである。トランジスタＭ２１はバックゲートを有するＯＳトランジスタであり、トランジスタＭ２５はｐチャネル型Ｓｉトランジスタである。トランジスタＭ２５はｎチャネル型ＳｉトランジスタまたはＯＳトランジスタとすることができる。トランジスタＭ２１、Ｍ２５がＯＳトランジスタであると、メモリセルアレイ２２２を制御回路２２０、周辺回路２２１に積層できるため、記憶装置２００を小型化できる。 The memory cell 20 is a 2T1C (two-transistor / one-capacitance) type gain cell, and includes transistors M21 and M25 and a capacitive element C25. The capacitive element C25 is a holding capacitance for holding the gate voltage of the transistor M25. The transistors M21 and M25 are a write transistor and a read transistor, respectively. The transistor M21 is an OS transistor having a back gate, and the transistor M25 is a p-channel Si transistor. The transistor M25 can be an n-channel Si transistor or an OS transistor. When the transistors M21 and M25 are OS transistors, the memory cell array 222 can be stacked on the control circuit 220 and the peripheral circuit 221, so that the memory device 200 can be miniaturized.
　電圧出力回路２７１には、電圧出力回路１２４が適用されている。電圧出力回路２７１は、電圧生成回路２７６、電圧補正回路２７７を有する。電圧生成回路２７６は、電圧ＶＳＳＳを降圧して、電圧Ｖｐｗを生成する。電圧補正回路２７７には、トランジスタＭ２１のレプリカトランジスタが設けられている。電圧補正回路２７７が生成する電圧ＶＯＴ２は、電圧ＶＢＧＣ１として、配線ＢＧＣＬ１に入力される。 The voltage output circuit 124 is applied to the voltage output circuit 271. The voltage output circuit 271 includes a voltage generation circuit 276 and a voltage correction circuit 277. The voltage generation circuit 276 steps down the voltage VSSS to generate a voltage Vpw. The voltage correction circuit 277 is provided with a replica transistor of the transistor M21. The voltage VOT2 generated by the voltage correction circuit 277 is input to the wiring BGCL1 as a voltage VBGC1.
　なお、電圧生成回路２７６を記憶装置２００の外部に設けてもよい。電圧Ｖｐｗとして電圧ＶＳＳＳを用いることができる場合は、電圧生成回路２７６を設けなくてもよい。例えば、周辺回路２２１の書込みワード線ＷＷＬを選択する信号を生成する回路に、図１１に示すドライバ回路１１４を適用してもよい。この場合、電圧出力回路２７１を設けず、電圧ＶＢＧＣ１として定電圧を外部から入力してもよい。 Note that the voltage generation circuit 276 may be provided outside the storage device 200. When the voltage VSSS can be used as the voltage Vpw, the voltage generation circuit 276 may not be provided. For example, the driver circuit 114 illustrated in FIG. 11 may be applied to a circuit that generates a signal for selecting the write word line WWL of the peripheral circuit 221. In this case, the voltage output circuit 271 may not be provided, and a constant voltage may be input from the outside as the voltage VBGC1.
　メモリセル２０は原理的に書き換え回数に制限はなく、データの書き換えを低エネルギーで行え、データの保持に電力を消費しない。トランジスタＭ２１が極小オフ電流のＯＳであるため、メモリセル２０は長時間データを保持することが可能である。しかしながら、トランジスタＭ２１のしきい値電圧ＶＴｇの変化は、メモリセル２０の書込み時間、保持時間を変化させる。温度が上がるとしきい値電圧ＶＴｇが下がるため、保持時間が短くなる。他方、温度が下がるとしきい値電圧ＶＴｇが上がるため、書込み時間が長くなる。 In principle, the number of rewrites of the memory cell 20 is not limited, and data rewrite can be performed with low energy, and no power is consumed for data retention. The memory cell 20 can hold data for a long time because the transistor M <b> 21 is a minimal off-current OS. However, the change of the threshold voltage VTg of the transistor M21 changes the write time and the hold time of the memory cell 20. When the temperature rises, the threshold voltage VTg is lowered, so that the holding time is shortened. On the other hand, when the temperature decreases, the threshold voltage VTg increases, so that the write time becomes longer.
　電圧出力回路２７１によって、動作温度に適した電圧ＶＢＧＣ１をトランジスタＭ２１のバックゲートに入力することができるため、トランジスタＭ２１のしきい値電圧ＶＴｇの温度による変化を補正することができる。例えば、動作温度範囲において記憶装置２００は、基準温度Ｔｒｅｆのときと同程度の性能を実現することができる。図１３Ａの例では、メモリセルアレイ２２２は、電圧ＶＢＧＣ１が入力される複数のブロックに分割されているため、メモリセルアレイ２２２に近接してモニタ回路を設けることで、プロセス起因のメモリセル２０の性能のばらつきを補正する効果が得られる。したがって、高い保持特性、長寿命、低消費電力、高信頼性の記憶装置２００を提供することができる。 Since the voltage VBGC1 suitable for the operating temperature can be input to the back gate of the transistor M21 by the voltage output circuit 271, a change in temperature of the threshold voltage VTg of the transistor M21 can be corrected. For example, in the operating temperature range, the storage device 200 can realize the same performance as that at the reference temperature Tref. In the example of FIG. 13A, since the memory cell array 222 is divided into a plurality of blocks to which the voltage VBGC1 is input, providing the monitor circuit in the vicinity of the memory cell array 222 enables the performance of the process-induced memory cell 20 to be reduced. The effect of correcting the variation is obtained. Therefore, a storage device 200 with high retention characteristics, long life, low power consumption, and high reliability can be provided.
　以下に、メモリセルアレイ２２２の他の構成例を説明する。図１４Ａに示すメモリセルアレイ２２３Ａは、メモリセル２１、書込みワード線ＷＷＬ、読出しワード線ＲＷＬ、書込みビット線ＷＢＬ、読出しビット線ＲＢＬ、配線ＰＬ、ＣＮＬ、ＢＧＣＬ１を有する。メモリセル２１は３Ｔゲインセルであり、トランジスタＭ２１、Ｍ２５、Ｍ２６、容量素子Ｃ２５を有する。トランジスタＭ２６は選択トランジスタである。トランジスタＭ２５、Ｍ２６はｎチャネル型Ｓｉトランジスタ、またはＯＳトランジスタであってもよい。 Hereinafter, another configuration example of the memory cell array 222 will be described. The memory cell array 223A shown in FIG. 14A includes a memory cell 21, a write word line WWL, a read word line RWL, a write bit line WBL, a read bit line RBL, and wirings PL, CNL, and BGCL1. The memory cell 21 is a 3T gain cell, and includes transistors M21, M25, and M26, and a capacitive element C25. The transistor M26 is a selection transistor. The transistors M25 and M26 may be n-channel Si transistors or OS transistors.
　図１４Ｂに示すメモリセルアレイ２２３Ｂは、メモリセル２２、書込みワード線ＷＷＬ、読出しワード線ＲＷＬ、書込みビット線ＷＢＬ、読出しビット線ＲＢＬ、配線ＰＬ、ＢＧＣＬ１~ＢＧＣＬ３を有する。メモリセル２２はトランジスタＭ２１~Ｍ２３、容量素子Ｃ２２を有する。トランジスタＭ２２、Ｍ２３はそれぞれ、読出しトランジスタ、選択トランジスタである。容量素子Ｃ２２は読出しトランジスタＭ２２のゲート電圧を保持する保持容量である。 The memory cell array 223B shown in FIG. 14B includes the memory cells 22, the write word lines WWL, the read word lines RWL, the write bit lines WBL, the read bit lines RBL, and the wirings PL, BGCL1 to BGCL3. The memory cell 22 includes transistors M21 to M23 and a capacitive element C22. The transistors M22 and M23 are a read transistor and a select transistor, respectively. The capacitive element C22 is a storage capacitor that holds the gate voltage of the read transistor M22.
　トランジスタＭ２２、Ｍ２３は、バックゲートを有するＯＳトランジスタである。トランジスタＭ２２、Ｍ２３のバックゲートはそれぞれ配線ＢＧＣＬ２、ＢＧＣＬ３に電気的に接続されている。配線ＢＧＣＬ２、ＢＧＣＬ３には、電圧出力回路２７２、２７３から電圧ＶＢＧＣ２、ＶＢＧＣ３がそれぞれ入力される。電圧出力回路２７２、２７３は電圧出力回路２７１と同様の構成であり、パワードメイン２１２に設けられる。電圧出力回路２７２、２７３には、トランジスタＭ２２、Ｍ２３のレプリカトランジスタがそれぞれ設けられている。 The transistors M22 and M23 are OS transistors having a back gate. The back gates of the transistors M22 and M23 are electrically connected to the wirings BGCL2 and BGCL3, respectively. The voltages VBGC2 and VBGC3 are input from the voltage output circuits 272 and 273 to the wirings BGCL2 and BGCL3, respectively. The voltage output circuits 272 and 273 have the same configuration as the voltage output circuit 271, and are provided in the power domain 212. The voltage output circuits 272 and 273 are provided with replica transistors of the transistors M22 and M23, respectively.
　トランジスタＭ２２のゲートと読出しビット線ＲＢＬとは容量結合しているため、データ“１”を読み出すとき、ブートストラップ効果が得られ、読出しビット線ＲＢＬの充電が加速される。つまり、読出し時間を短縮することができる。 Since the gate of the transistor M22 and the read bit line RBL are capacitively coupled, when data "1" is read, a bootstrap effect is obtained and charging of the read bit line RBL is accelerated. That is, the read time can be shortened.
　電圧ＶＢＧＣ１~ＶＢＧＣ３によって、トランジスタＭ２１~Ｍ２３のしきい値電圧ＶＴｇを最適化することができる。保持時間を長くするために、トランジスタＭ２１のしきい値電圧ＶＴｇを最も高くする。読出し速度の向上のため、トランジスタＭ２２のＶＴｇを低くし、オン電流特性を向上させる。この場合、非選択メモリセル２２から読出しビット線ＲＷＬへのリーク電流の増加が問題になる。非選択メモリセル２２からのリーク電流は、保持時間を短くするだけでなく、データの読出しエラーの原因となる。そのため、トランジスタＭ２３はオン電流特性よりもオフ電流特性を優先することが好ましい。よって、トランジスタＭ２３のＶＴｇは、トランジスタＭ２２のＶＴｇよりも小さくする。ＶＢＧＣ１~ＶＢＧＣ３は、ＶＢＧＣ１≦ＶＢＧＣ３＜ＶＢＧＣ２であることが好ましい。 The threshold voltages VTg of the transistors M21 to M23 can be optimized by the voltages VBGC1 to VBGC3. In order to increase the retention time, the threshold voltage VTg of the transistor M21 is maximized. In order to improve the reading speed, VTg of the transistor M22 is lowered to improve the on-current characteristic. In this case, an increase in the leakage current from the non-selected memory cell 22 to the read bit line RWL becomes a problem. The leakage current from the non-selected memory cell 22 not only shortens the retention time but also causes a data read error. Therefore, it is preferable that the transistor M23 gives priority to the off current characteristic over the on current characteristic. Therefore, VTg of the transistor M23 is smaller than VTg of the transistor M22. It is preferable that VBGC1 to VBGC3 satisfy VBGC1 ≦ VBGC3 <VBGC2.
　電圧ＶＢＧＣ１~ＶＢＧＣ３の一部を温度補正しない構成としてもよい。例えば、配線ＢＧＣＬ３には定電圧を入力し、配線ＢＧＣＬ１、ＢＧＤＬ２の電圧を電圧出力回路２７１、２７２で補正する。 A part of the voltages VBGC1 to VBGC3 may not be temperature-corrected. For example, a constant voltage is input to the wiring BGCL3, and the voltages of the wirings BGCL1 and BGDL2 are corrected by the voltage output circuits 271 and 272.
　図１４Ｃに示すメモリセルアレイ２２２Ｃはメモリセルアレイ２２３Ｂの変形例であり、メモリセル２３、書込みワード線ＷＷＬ、読出しワード線ＲＷＬ、書込みビット線ＷＢＬ、読出しビット線ＲＢＬ、配線ＰＬ、ＢＧＣＬ１~ＢＧＣＬ２を有する。メモリセル２３は、メモリセル２２と容量素子Ｃ２２の接続が異なる。メモリセル２３はメモリセル２２と同様の特長をもつ。 A memory cell array 222C shown in FIG. 14C is a modification of the memory cell array 223B, and includes a memory cell 23, a write word line WWL, a read word line RWL, a write bit line WBL, a read bit line RBL, and wirings PL, BGCL1 to BGCL2. The memory cell 23 differs in the connection between the memory cell 22 and the capacitive element C22. Memory cell 23 has the same features as memory cell 22.
　図１４Ｄに示すメモリセルアレイ２２３Ｄは、メモリセル２４、ビット線ＢＬ、ＢＬＢ、ワード線ＷＬ、配線ＣＮＬ、ＢＧＣＬ１を有する。メモリセル２３は１Ｔ１Ｃ型セルであり、トランジスタＭ２１、容量素子Ｃ２１を有する。 A memory cell array 223D illustrated in FIG. 14D includes memory cells 24, bit lines BL and BLB, word lines WL, and wirings CNL and BGCL1. The memory cell 23 is a 1T1C type cell, and includes a transistor M21 and a capacitive element C21.
　メモリセルアレイ２２３Ｂ~２２３ＤはＯＳトランジスタと容量素子とで構成されるため、制御回路２２０、周辺回路２２１に積層することができる。 The memory cell arrays 223B to 223D are formed of the OS transistor and the capacitor, and thus can be stacked over the control circuit 220 and the peripheral circuit 221.
＜記憶装置２０２＞
　図１５に示す記憶装置２０２は、パワードメイン２１３~２１５、パワースイッチ２４４~２４８を有する。記憶装置２０２は、電圧ＶＤＤＤ、ＶＳＳＳ、ＶＤＤＭ、ＶＤＭＬ、ＶＳＳＭ、アドレス信号ＡＤＤＲ、クロック信号ＧＣＬＫ３、コマンド信号（例えば、チップイネーブル信号ＣＥ、書き込みイネーブル信号ＷＥ、バイト書き込みイネーブル信号ＢＷ）、信号ＰＳＥ３~ＰＳＥ５、ＰＧ（パワーゲーティング）制御信号（図中、ＰＧ　ｃｏｎｔｒｏｌ　ｓｉｇｎａｌｓと図示）が入力される。記憶装置２０２に入力される電圧、信号等は回路構成、動作方法などに応じて適宜取捨される。 <Storage device 202>
The storage device 202 illustrated in FIG. 15 includes power domains 213 to 215 and power switches 244 to 248. The storage device 202 includes voltages VDDD, VSSS, VDDM, VDML, VSSM, an address signal ADDR, a clock signal GCLK3, command signals (eg, chip enable signal CE, write enable signal WE, byte write enable signal BW), signals PSE3 to PSE5. , PG (power gating) control signals (shown as PG control signals in the figure) are input. Voltages, signals, and the like input to the storage device 202 are appropriately discarded according to the circuit configuration, the operation method, and the like.
　信号ＰＳＥ３は、パワースイッチ２４４、２４５のオンオフを制御する。パワースイッチ２４４、２４５は、パワードメイン２１３への電圧ＶＤＤＤ、ＶＤＨＢの供給を制御する。パワードメイン２１３には、制御回路２２５、周辺回路２２６、バックアップ制御回路２２７が設けられている。信号ＰＳＥ４はパワースイッチ２４６、２４７のオンオフを制御し、信号ＰＳＥ５はパワースイッチ２４８のオンオフを制御する。パワースイッチ２４６~２４８は、パワードメイン２１４への電圧ＶＤＤＭ、ＶＳＳＭ、ＶＤＭＬの供給を制御する。パワードメイン２１４には、メモリセルアレイ２２８が設けられている。メモリセルアレイ２２８は複数のメモリセル３０を有する。 The signal PSE3 controls on / off of the power switches 244, 245. The power switches 244, 245 control the supply of the voltages VDDD, VDHB to the power domain 213. The power domain 213 is provided with a control circuit 225, a peripheral circuit 226, and a backup control circuit 227. The signal PSE4 controls the on / off of the power switches 246 and 247, and the signal PSE5 controls the on / off of the power switch 248. The power switches 246 to 248 control the supply of the voltages VDDM, VSSM and VDML to the power domain 214. In the power domain 214, a memory cell array 228 is provided. Memory cell array 228 has a plurality of memory cells 30.
　パワードメイン２１５はパワーゲーティングされない。パワードメイン２１５には電圧出力回路２７４が設けられている。電圧出力回路２７４は、電圧出力回路２７１と同様の構成であり、電圧生成回路２７８、電圧補正回路２７９を有する。電圧補正回路２７９が生成する電圧ＶＯＴ２は、電圧ＶＢＧＣ４として、メモリセルアレイ２２８に入力される。 Power domain 215 is not power gated. The power domain 215 is provided with a voltage output circuit 274. The voltage output circuit 274 has the same configuration as the voltage output circuit 271 and includes a voltage generation circuit 278 and a voltage correction circuit 279. The voltage VOT2 generated by the voltage correction circuit 279 is input to the memory cell array 228 as a voltage VBGC4.
（メモリセルアレイ２２８）
　図１５に示すメモリセルアレイ２２８は、メモリセル３０、ワード線ＷＬ、ビット線ＢＬ、ＢＬＢ、配線ＯＧＬ、ＢＧＣＬ４、Ｖ＿ＶＤＭ、Ｖ＿ＶＳＭを有する。なお、配線Ｖ＿ＶＤＭは、パワースイッチ２４６、２４８によって、電圧の入力が制御されるバーチャル電源線であり、配線Ｖ＿ＶＳＭは、パワースイッチ２４７によって、電圧の入力が制御されるバーチャル電源線である。電圧ＶＤＨＢは、配線ＯＧＬの高レベル電圧であり、ＶＤＤＭよりも高い電圧である。 (Memory cell array 228)
The memory cell array 228 illustrated in FIG. 15 includes a memory cell 30, a word line WL, bit lines BL and BLB, and wirings OGL, BGCL4, V_VDM, and V_VSM. The wiring V_VDM is a virtual power supply line whose input of voltage is controlled by the power switches 246 and 248, and the wiring V_VSM is a virtual power supply line whose input of voltage is controlled by the power switch 247. The voltage VDHB is a high level voltage of the wiring OGL and is a voltage higher than VDDM.
　図１６Ａに示すように、メモリセル３０は、メモリセル３２とバックアップ回路３５を有する。メモリセル３２は、標準的な６Ｔ（トランジスタ）ＳＲＡＭセルと同じ回路構成であり、トランジスタＭＴ１、ＭＴ２、ノードＱ／Ｑｂ、ラッチ回路３３を有する。ラッチ回路３３は、ワード線ＷＬ、ビット線ＢＬ、ＢＬＢ、配線Ｖ＿ＶＤＭ、Ｖ＿ＶＳＭに電気的に接続されている。 As shown in FIG. 16A, the memory cell 30 has a memory cell 32 and a backup circuit 35. The memory cell 32 has the same circuit configuration as a standard 6T (transistor) SRAM cell, and includes transistors MT1 and MT2, nodes Q / Qb, and a latch circuit 33. The latch circuit 33 is electrically connected to the word line WL, the bit lines BL and BLB, and the wirings V_VDM and V_VSM.
　ワード線ＷＬ、ビット線ＢＬ、ＢＬＢは周辺回路２２６によって駆動される。配線Ｖ＿ＶＤＭは、パワースイッチ２４６、２４８によって電圧の入力が制御されるバーチャル電源線である。配線Ｖ＿ＶＳＭは、パワースイッチ２４７によって電圧の入力が制御されるバーチャル電源線である。パワースイッチ２４７を設けない構成することができる。この場合、配線Ｖ＿ＶＳＭに代えて、例えば、電圧ＶＳＳＳを供給する配線を設ければよい。 The word line WL and the bit lines BL and BLB are driven by the peripheral circuit 226. Wiring V_VDM is a virtual power supply line whose input of voltage is controlled by power switches 246 and 248. Wiring V_VSM is a virtual power supply line whose input of voltage is controlled by power switch 247. The power switch 247 can be omitted. In this case, in place of the wiring V_VSM, for example, a wiring for supplying the voltage VSSS may be provided.
　バックアップ回路３５は、メモリセル３２のデータをバックアップする。バックアップ回路３５は、トランジスタＭ３１、Ｍ３２、容量素子Ｃ３１、Ｃ３２でなる一対の２個Ｔ１Ｃ型メモリセルを有する。これらメモリセルの保持ノードが、ノードＳＮ２１、ＳＮ２２である。メモリセル３０にバックアップ回路３５を設けることで、パワードメイン２１４をパワーゲーティングできる。 The backup circuit 35 backs up the data of the memory cell 32. The backup circuit 35 has a pair of two T1C-type memory cells including transistors M31 and M32, and capacitive elements C31 and C32. The holding nodes of these memory cells are the nodes SN21 and SN22. By providing the backup circuit 35 in the memory cell 30, the power domain 214 can be power gated.
　トランジスタＭ３１、Ｍ３２はバックゲートを有するＯＳトランジスタである。トランジスタＭ３１、Ｍ３２のゲートは配線ＯＧＬに電気的に接続している。配線ＯＧＬはバックアップ制御回路２２７によって駆動される。トランジスタＭ３１、Ｍ３２のバックゲートは、配線ＢＧＣＬ４に電気的に接続されている。配線ＢＧＣＬ４には、電圧補正回路２７９から電圧ＶＢＧ４が入力される。トランジスタＭ３１、Ｍ３２の仕様は同じであり、電圧補正回路２７９には、トランジスタＭ３１のレプリカトランジスタが設けられる。したがって、電圧ＶＢＧ４によって、トランジスタＭ３１、Ｍ３２のしきい値電圧ＶＴｇの温度による変動を補正することができるため、高信頼性のバックアップ回路３５を提供することができる。 The transistors M31 and M32 are OS transistors having a back gate. The gates of the transistors M31 and M32 are electrically connected to the wiring OGL. The wiring OGL is driven by the backup control circuit 227. The back gates of the transistors M31 and M32 are electrically connected to the wiring BGCL4. The voltage VBG4 from the voltage correction circuit 279 is input to the wiring BGCL4. The specifications of the transistors M31 and M32 are the same, and the voltage correction circuit 279 is provided with a replica transistor of the transistor M31. Therefore, since the variation due to the temperature of the threshold voltage VTg of the transistors M31 and M32 can be corrected by the voltage VBG4, the highly reliable backup circuit 35 can be provided.
　バックアップ制御回路２２７に、ドライバ回路１１４を適用して、トランジスタＭ３１、Ｍ３２のゲート電圧を制御してもよい。この場合、電圧出力回路２７４を設けなくてもよい。 The driver circuit 114 may be applied to the backup control circuit 227 to control the gate voltage of the transistors M31 and M32. In this case, the voltage output circuit 274 may not be provided.
＜＜記憶装置２０２の動作例＞＞
　ＰＧ制御信号によって、記憶装置２０２の低消費電力モードが決定される。損益分岐時間（ＢＥＴ）が異なる４種類の低消費電力モード、（１）ビット線フローティングモード、（２）スリープモード、（３）セルアレイドメインＰＧモード、（４）全ドメインＰＧモードがある。信号ＰＳＥ４~ＰＳＥ６、ＰＧ制御信号に基づき、低消費電力モードが設定される。これら信号は、例えば、ＰＭＵから送信される。ＢＥＴの異なる複数の低消費電力モードを設けることで、記憶装置２０２の消費電力を効率良く低減することができる。 << Operation Example of Storage Device 202 >>
The PG control signal determines the low power consumption mode of the storage device 202. There are four types of low power consumption modes having different break-even times (BET), (1) bit line floating mode, (2) sleep mode, (3) cell array domain PG mode, and (4) all domain PG mode. The low power consumption mode is set based on the signals PSE4 to PSE6 and the PG control signal. These signals are transmitted from, for example, the PMU. By providing a plurality of low power consumption modes with different BETs, the power consumption of the storage device 202 can be efficiently reduced.
　ビット線フローティングモードでは、ビット線対（ＢＬ，ＢＬＢ）をフローティング状態にする。メモリセル３１のデータは消失しない。 In the bit line floating mode, the bit line pair (BL, BLB) is brought into a floating state. The data in the memory cell 31 is not lost.
　スリープモードでは、パワードメイン２１４に電圧ＶＤＤＭよりも低い電圧ＶＤＭＬを供給する。電圧ＶＤＭＬは、メモリセル３２のデータが消失しない大きさである。ビット線対（ＢＬ，ＢＬＢ）はフローティング状態である。 In the sleep mode, power domain 214 is supplied with voltage VDML lower than voltage VDDM. The voltage VDML is a size that does not cause the data in the memory cell 32 to disappear. The bit line pair (BL, BLB) is in a floating state.
　セルアレイドメインＰＧモードでは、パワースイッチ２４６~２４８をオフにして、パワードメイン２１４への電圧ＶＤＤＭ、ＶＤＭＬ、ＶＳＳＭの供給を停止する。ビット線対（ＢＬ，ＢＬＢ）をフローティング状態とする。メモリセル３２のデータは消失する。 In the cell array domain PG mode, the power switches 246 to 248 are turned off to stop the supply of the voltages VDDM, VDML, and VSSM to the power domain 214. The bit line pair (BL, BLB) is brought into a floating state. The data in memory cell 32 is lost.
　全ドメインＰＧモードでは、パワーゲーティング可能な全てのドメインがパワーゲーティングされる。パワースイッチ２４４~２４８はオフである。 In the all domain PG mode, power gating is performed on all the domains that can be power gated. The power switches 244 to 248 are off.
＜パワーゲーティングシーケンス＞
　図１６Ｂに、パワードメイン２１４に対するパワーゲーティングシーケンスの一例を示す。 <Power gating sequence>
An example of a power gating sequence for the power domain 214 is shown in FIG. 16B.
（通常動作（図中、Ｎｏｒｍａｌ　Ｏｐｅｒａｔｉｏｎと図示））
　時刻ｔ１以前では、記憶装置２０２の状態は、通常動作状態（書き込み状態または読み出し状態）である。通常動作時は、記憶装置２０２はシングルポートＳＲＡＭと同様に動作する。パワースイッチ２４４、２４６~２４８はオンであり、パワースイッチ２４５はオフである。制御回路２２５は、記憶装置２０２全体を統括的に制御し、データの書き込み、読み出しを行う。制御回路２２５は、アドレス信号ＡＤＤＲ、外部からのコマンド信号（例えば、チップイネーブル信号ＣＥ、書き込みイネーブル信号ＷＥ、バイト書き込みイネーブル信号ＢＷ）を処理して、周辺回路２２６の制御信号を生成する。 (Normal operation (shown as Normal Operation in the figure))
Before time t1, the state of the storage device 202 is a normal operation state (write state or read state). During normal operation, the storage device 202 operates similarly to a single port SRAM. The power switches 244, 246 to 248 are on, and the power switch 245 is off. The control circuit 225 centrally controls the entire storage device 202 to write and read data. The control circuit 225 processes the address signal ADDR and an external command signal (for example, a chip enable signal CE, a write enable signal WE, a byte write enable signal BW) to generate a control signal of the peripheral circuit 226.
（バックアップ（図中、Ｂａｃｋｕｐと図示））
　時刻ｔ１で、ＰＧ制御信号に応じてバックアップシーケンスが開始する。バックアップ制御回路２２７は、全て配線ＯＧＬを“Ｈ”にする。ここでは、時刻ｔ１でノードＱ／Ｑｂは“Ｈ”／“Ｌ”であり、ノードＳＮ３１／ＳＮ３２は“Ｌ”／“Ｈ”であるので、トランジスタＭ３１、Ｍ３２がオンになると、ノードＳＮ３１の電圧はＶＳＳＭからＶＤＤＭに上昇し、ノードＳＮ３２の電圧はＶＤＤＭからＶＳＳＭに低下する。時刻ｔ２で信号ＰＧＭが“Ｌ”となることで、バックアップ動作が終了する。ノードＳＮ３１／ＳＮ３２には、時刻ｔ１でのノードＱ／Ｑｂのデータが書き込まれる。 (Backup (shown as Backup in the figure))
At time t1, the backup sequence starts in response to the PG control signal. The backup control circuit 227 sets all the wires OGL to "H". Here, at time t1, node Q / Qb is "H" / "L", and node SN31 / SN32 is "L" / "H". Therefore, when transistors M31 and M32 are turned on, the voltage of node SN31 Increases from VSSM to VDDM, and the voltage of the node SN32 drops from VDDM to VSSM. When the signal PGM becomes "L" at time t2, the backup operation is completed. Data of node Q / Qb at time t1 is written to node SN31 / SN32.
（パワーゲーティング（図中、Ｐｏｗｅｒ−ｇａｔｉｎｇと図示））
　時刻ｔ２で、信号ＰＳＥ４を“Ｌ”にして、パワースイッチ２４６、２４７をオフすることで、パワードメイン２１４のパワーゲーティングが開始する。配線Ｖ＿ＶＤＭと配線Ｖ＿ＶＳＭの電圧差が低下することで、ラッチ回路３３は非アクティブになる。メモリセル３２のデータは消失するが、バックアップ回路３５はデータを保持し続ける。 (Power gating (shown as Power-gating in the figure))
At time t2, by setting the signal PSE4 to "L" and turning off the power switches 246 and 247, power gating of the power domain 214 is started. The decrease in voltage difference between the wiring V_VDM and the wiring V_VSM makes the latch circuit 33 inactive. Although the data in the memory cell 32 is lost, the backup circuit 35 keeps holding the data.
（リカバリ（図中、Ｒｅｃｏｖｅｒｙと図示））
　周辺回路２２６、バックアップ制御回路２２７は、ＰＧ制御信号に従い、リカバリ動作を行う。リカバリ動作では、ラッチ回路３３は、ノードＱ／Ｑｂのデータを検知するためのセンスアンプとして機能する。まず、ノードＱ、Ｑｂのリセット動作が行われる。時刻ｔ３で、周辺回路２２６は、全ビット線対（ＢＬ，ＢＬＢ）をプリチャージする。全ビット線対（ＢＬ，ＢＬＢ）には電圧Ｖｐｒ２が入力される。次に、周辺回路２２６は、全ワード線ＷＬを選択状態にする。配線Ｖ＿ＶＤＭ、Ｖ＿ＶＳＭは電圧Ｖｐｒ２にプリチャージされ、ノードＱ、Ｑｂは電圧Ｖｐｒ２に固定される。 (Recovery (shown as Recovery in the figure))
The peripheral circuit 226 and the backup control circuit 227 perform the recovery operation according to the PG control signal. In the recovery operation, latch circuit 33 functions as a sense amplifier for detecting data on nodes Q / Qb. First, the reset operation of the nodes Q and Qb is performed. At time t3, peripheral circuit 226 precharges all bit line pairs (BL, BLB). Voltage Vpr2 is input to all bit line pairs (BL, BLB). Next, peripheral circuit 226 sets all word lines WL to the selected state. The wirings V_VDM and V_VSM are precharged to the voltage Vpr2, and the nodes Q and Qb are fixed to the voltage Vpr2.
　時刻ｔ４で、バックアップ制御回路２２７は、全て配線ＯＧＬを“Ｈ”にする。トランジスタＭ３１、Ｍ３２がオンになる。容量素子Ｃ３１の電荷がノードＱ、ノードＳＮ３１に分配され、容量素子Ｃ３２の電荷がノードＱｂ、ノードＳＮ３２に分配され、ノードＱとノードＱｂとに電圧差が生じる。 At time t4, the backup control circuit 227 makes all the wiring OGL "H". The transistors M31 and M32 are turned on. The charge of the capacitive element C31 is distributed to the node Q and the node SN31, the charge of the capacitive element C32 is distributed to the node Qb and the node SN32, and a voltage difference occurs between the node Q and the node Qb.
　時刻ｔ５で、パワースイッチ２４６、２４７をオンにして、パワードメイン２１４への電圧ＶＤＤＭ、ＶＳＳＭの入力を再開する。ラッチ回路３３はアクティブになると、ノードＱとノードＱｂの電圧差を増幅する。最終的にノードＱ、ＳＮ３１の電圧はＶＤＤＭとなり、ノードＱｂ、ＳＮ３２の電圧はＶＳＳＭとなる。つまり、ノードＱ／Ｑｂの状態は、時刻ｔ１での状態（“Ｈ”／“Ｌ”）に復帰する。時刻ｔ７でリカバリ動作が終了し、通常動作が開始される。 At time t5, the power switches 246 and 247 are turned on to resume the input of the voltages VDDM and VSSM to the power domain 214. When activated, latch circuit 33 amplifies the voltage difference between node Q and node Qb. Finally, the voltages of the nodes Q and SN31 become VDDM, and the voltages of the nodes Qb and SN32 become VSSM. That is, the state of the node Q / Qb returns to the state ("H" / "L") at time t1. At time t7, the recovery operation is finished, and the normal operation is started.
　トランジスタＭ３１、Ｍ３２のしきい値電圧ＶＴｇの温度による変動を補正できるため、例えば、動作温度範囲において、バックアップ回路３５は基準温度Ｔｒｅｆのときと同程度の性能を実現することができる。よって、温度の上昇による保持時間の短縮、温度の低下によるバックアップ及びリカバリ時間の増加を抑えることができる。したがって、高信頼性、低消費電力の記憶装置２０２を提供することができる。 Since variations in the threshold voltage VTg of the transistors M31 and M32 due to temperature can be corrected, for example, in the operating temperature range, the backup circuit 35 can realize performance similar to that at the reference temperature Tref. Therefore, it is possible to suppress the shortening of the retention time due to the temperature rise and the increase of the backup and recovery time due to the temperature fall. Therefore, the storage device 202 with high reliability and low power consumption can be provided.
　本実施の形態の記憶装置に、温度センサとしてモニタ回路１３０を設けることができる。この場合、例えば、モニタ回路１３０の出力電圧に応じて、リフレッシュのサイクル、又はパワーゲーティングのタイミングを変更することができる。 In the memory device of this embodiment, a monitor circuit 130 can be provided as a temperature sensor. In this case, for example, the refresh cycle or the timing of power gating can be changed according to the output voltage of the monitor circuit 130.
〔実施の形態３〕
　本実施の形態では、ＯＳトランジスタが用いられた半導体装置について説明する。 Third Embodiment
In this embodiment, a semiconductor device in which an OS transistor is used will be described.
＜＜プロセッサ３００＞＞
　図１７に示すプロセッサ３００は、バス３０５、３０６、バスブリッジ３０７、ＣＰＵ３１０、記憶装置３１２、ＰＭＵ３１４、クロック制御回路３１５、電源回路３１６、メモリ制御回路３１７、機能部３１８、インターフェース（Ｉ／Ｆ）部３１９を有する。プロセッサ３００の内部回路は適宜取捨される。例えば、プロセッサ３００にＧＰＵを設けてもよい。 << Processor 300 >>
The processor 300 illustrated in FIG. 17 includes buses 305 and 306, a bus bridge 307, a CPU 310, a storage device 312, a PMU 314, a clock control circuit 315, a power supply circuit 316, a memory control circuit 317, a functional unit 318, and an interface (I / F) unit. It has 319. The internal circuit of the processor 300 is discarded as appropriate. For example, the processor 300 may be provided with a GPU.
　図１７に示すように、バス３０５、３０６、バスブリッジ３０７によって、プロセッサ３００の内部回路が相互にデータの授受が可能に接続される。ＰＭＵ３１４は、クロック制御回路３１５、電源回路３１６を制御する。ＰＭＵ３１４は、プロセッサ３００の内部回路（例えば、ＣＰＵ３１０、記憶装置３１２、バス３０５等）のクロックゲーティング、およびパワーゲーティングを制御する。メモリ制御回路３１７は、外部記憶装置を制御する。プロセッサ３００は、アプリケーションプロセッサとして用いることができる。そのため、各種の周辺機器をプロセッサ３００で制御できるように、機能部３１８、インターフェース部３１９には各種の回路が設けられる。 As shown in FIG. 17, the internal circuits of the processor 300 are connected to be able to transmit and receive data mutually by buses 305 and 306 and a bus bridge 307. The PMU 314 controls the clock control circuit 315 and the power supply circuit 316. The PMU 314 controls clock gating and power gating of internal circuits (for example, the CPU 310, the storage device 312, the bus 305, and the like) of the processor 300. The memory control circuit 317 controls an external storage device. The processor 300 can be used as an application processor. Therefore, various circuits are provided in the function unit 318 and the interface unit 319 so that the processor 300 can control various peripheral devices.
　機能部３１８に設けられる機能回路は、例えば、ディスプレイ制御回路３２１、グラフィック処理回路３２２、ビデオ処理回路３２３、オーディオ処理回路３２４、音声処理回路、タイマー回路、ＡＤＣ（アナログデジタル変換回路）などが設けられる。 The functional circuits provided in the functional unit 318 include, for example, a display control circuit 321, a graphic processing circuit 322, a video processing circuit 323, an audio processing circuit 324, an audio processing circuit, a timer circuit, an ADC (analog digital conversion circuit), etc. .
　インターフェース部３１９には、例えば、ｅＰＣＩ（Ｐｅｒｉｐｈｅｒａｌ　Ｃｏｍｐｏｎｅｎｔ　Ｉｎｔｅｒｃｏｎｎｅｃｔ　Ｅｘｐｒｅｓｓ）、Ｉ２Ｃ（Ｉ−ｓｑｕａｒｅｄ−Ｃ、Ｉｎｔｅｒ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）、ＭＩＰＩ（Ｍｏｂｉｌｅ　Ｉｎｄｕｓｔｒｙ　Ｐｒｏｃｅｓｓｏｒ　Ｉｎｔｅｒｆａｃｅ）、ＵＳＢ（Ｕｎｉｖｅｒｓａｌ　Ｓｅｒｉａｌ　Ｂｕｓ）、ＳＰＩ（Ｓｅｒｉａｌ　Ｐｅｒｉｐｈｅｒａｌ　Ｉｎｔｅｒｆａｃｅ）、ＨＤＭＩ（登録商標）／ＤＰ（Ｈｉｇｈ−Ｄｅｆｉｎｉｔｉｏｎ　Ｍｕｌｔｉｍｅｄｉａ　Ｉｎｔｅｒｆａｃｅ／ＤｉｓｐｌａｙＰｏｒｔ）、ｅＤＰ（ｅｍｂｅｄｄｅｄ　ＤｉｓｐｌａｙＰｏｒｔ）、ＤＳＩ（Ｄｉｓｐｌａｙ　Ｓｅｒｉａｌ　Ｉｎｔｅｒｆａｃｅ）などの規格に対応する回路が設けられる。 The interface unit 319 includes, for example, peripheral component interconnect express (ePCI), I-squared-C (I-squared-C, inter integrated circuit), mobile industry processor interface (MIPI), universal serial bus (USB), serial peripheral interface (SPI) Such as HDMI (registered trademark) / DP (High-Definition Multimedia Interface / Display Port), eDP (embedded Display Port), DSI (Display Serial Interface), etc. Circuit corresponding to the rank is provided.
　記憶装置３１２には、実施の形態２の記憶装置が適用される。複数種類の記憶装置３１２をプロセッサ３００に設けてもよい。ＰＭＵ３１４は、記憶装置３１２が使用するパワースイッチの制御信号およびＰＧ制御信号を生成する。記憶装置２００をプロセッサ３００に設ける場合、例えば、電圧生成回路２７６は、電源回路３１６に設けてもよい。記憶装置２０２についても同様である。 The storage device of the second embodiment is applied to the storage device 312. A plurality of types of storage devices 312 may be provided in the processor 300. The PMU 314 generates a control signal of the power switch used by the storage device 312 and a PG control signal. In the case where the memory device 200 is provided in the processor 300, for example, the voltage generation circuit 276 may be provided in the power supply circuit 316. The same applies to the storage device 202.
　ＣＰＵ３１０は、ＣＰＵコア、キャッシュメモリ装置、電圧出力回路３４５、レベルシフタ３４８、パワースイッチ３４９等を有する（図１８参照）。ＣＰＵコアには、図１８に示すフリップフロップ３４０が設けられる。パワースイッチ３４９はＣＰＵコアへの電圧ＶＤＤの供給を制御する。パワースイッチ３４９のオンオフは、ＰＭＵ３１４が生成する信号ＰＳＥ９によって制御される。 The CPU 310 includes a CPU core, a cache memory device, a voltage output circuit 345, a level shifter 348, a power switch 349, and the like (see FIG. 18). The CPU core is provided with a flip flop 340 shown in FIG. The power switch 349 controls the supply of the voltage VDD to the CPU core. The on / off of the power switch 349 is controlled by a signal PSE9 generated by the PMU 314.
＜フリップフロップ３４０＞
　フリップフロップ３４０はスキャンフリップフロップ３４１、バックアップ回路３４２を有する。フリップフロップ３４０にバックアップ回路３４２を設けることで、ＣＰＵコアのパワーゲーティングが可能となる。 <Flip-flop 340>
The flip flop 340 has a scan flip flop 341 and a backup circuit 342. Providing the backup circuit 342 in the flip flop 340 enables power gating of the CPU core.
　スキャンフリップフロップ３４１は、ノードＤ１、Ｑ１、ＳＤ、ＳＥ、ＲＴ、ＣＫ、クロックバッファ回路３４１Ａを有する。クロックバッファ回路３４１Ａは、２個のインバータ、ノードＣＫ１、ＣＫＢ１を有する。ノードＲＴはリセット信号の入力ノードである。スキャンフリップフロップ３４１の回路構成は、図１８に限定されない。標準的な回路ライブラリに用意されているフリップフロップを適用することができる。 The scan flip flop 341 has nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 341A. The clock buffer circuit 341A has two inverters, nodes CK1 and CKB1. The node RT is an input node of the reset signal. The circuit configuration of the scan flip flop 341 is not limited to that shown in FIG. The flip flops provided in the standard circuit library can be applied.
　ノードＤ１はデータ入力ノードであり、ノードＱ１はデータ出力ノードであり、ノードＳＤはスキャンテスト用データの入力ノードであり、バックアップ回路３４２のノードＳＤ＿ＩＮに電気的に接続される。ノードＳＥ、ＣＫ、ＲＴには、スキャンイネーブル信号ＳＣＥ、リセット信号ＲＳＴ４、クロック信号ＧＣＬＫ４が入力される。スキャンイネーブル信号ＳＣＥはＰＭＵ３１４で生成され、リセット信号ＲＳＴ４、クロック信号ＧＣＬＫ４はクロック制御回路３１５で生成される。ＰＭＵ３１４は、リカバリ信号ＲＣ、バックアップ信号ＢＫを生成する。レベルシフタ３４８はリカバリ信号ＲＣ、バックアップ信号ＢＫをレベルシフトし、リカバリ信号ＲＣＨ、バックアップ信号ＢＫＨをバックアップ回路３４２に出力する。 The node D1 is a data input node, the node Q1 is a data output node, and the node SD is an input node for scan test data, and is electrically connected to the node SD_IN of the backup circuit 342. The scan enable signal SCE, the reset signal RST4, and the clock signal GCLK4 are input to the nodes SE, CK, and RT. The scan enable signal SCE is generated by the PMU 314, and the reset signal RST 4 and the clock signal GCLK 4 are generated by the clock control circuit 315. The PMU 314 generates a recovery signal RC and a backup signal BK. The level shifter 348 shifts the level of the recovery signal RC and the backup signal BK, and outputs the recovery signal RCH and the backup signal BKH to the backup circuit 342.
　バックアップ回路３４２は、ノードＳＤ＿ＩＮ、ＳＮ３５、トランジスタＭ３５~Ｍ３７、容量素子Ｃ３５を有する。ノードＳＤ＿ＩＮは他のスキャンフリップフロップ３４１のノードＱ１に電気的に接続される。ノードＳＮ３５は、バックアップ回路３４２の保持ノードである。容量素子Ｃ３５はノードＳＮ３５の電圧を保持するための保持容量である。 The backup circuit 342 includes nodes SD_IN and SN35, transistors M35 to M37, and a capacitive element C35. Node SD_IN is electrically connected to node Q 1 of another scan flip flop 341. The node SN35 is a holding node of the backup circuit 342. Capacitive element C35 is a holding capacitance for holding the voltage of node SN35.
　トランジスタＭ３５による寄生容量がノードＱ１に付加することになるが、ノードＱ１に接続される論理回路による寄生容量と比較して小さいので、スキャンフリップフロップ３４１の動作に影響はない。つまり、バックアップ回路３４２を設けても、フリップフロップ３４０の性能は実質的に低下しない。 Although the parasitic capacitance due to the transistor M35 is to be added to the node Q1, it is smaller than the parasitic capacitance due to the logic circuit connected to the node Q1, so there is no influence on the operation of the scan flip flop 341. That is, even when the backup circuit 342 is provided, the performance of the flip flop 340 is not substantially reduced.
　トランジスタＭ３５~Ｍ３７は同じ仕様であり、バックゲートを有するＯＳトランジスタである。トランジスタＭ３５~Ｍ３７のバックゲートは、配線ＢＧＦＬに電気的に接続されている。配線ＢＧＦＬには、電圧出力回路３４５から電圧ＶＢＧＦが入力される。 The transistors M35 to M37 have the same specifications and are OS transistors having a back gate. The back gates of the transistors M35 to M37 are electrically connected to the wiring BGFL. The voltage VBGF from the voltage output circuit 345 is input to the wiring BGFL.
　電圧出力回路３４５は実施の形態１の電圧出力回路が適用され、電圧生成回路３４６および電圧補正回路３４７を有する。電圧生成回路３４６は、電圧ＶＳＳＳを降圧して、電圧Ｖｐｗを生成する。例えば、電圧生成回路３４６を電源回路３１６に設けてもよい。電圧ＶｐｗがＶＳＳＳにすることができる場合は、電圧生成回路３４６を設けず、電圧ＶＳＳＳを電圧補正回路３４７に出力すればよい。電圧補正回路３４７には、トランジスタＭ３５のレプリカトランジスタが設けられている。電圧補正回路３４７が生成する電圧ＶＯＴ２は、電圧ＶＢＧＦとして、配線ＢＧＦＬに入力される。 The voltage output circuit of the first embodiment is applied to the voltage output circuit 345, and includes a voltage generation circuit 346 and a voltage correction circuit 347. The voltage generation circuit 346 steps down the voltage VSSS to generate a voltage Vpw. For example, the voltage generation circuit 346 may be provided in the power supply circuit 316. When the voltage Vpw can be set to VSSS, the voltage generation circuit 346 is not provided, and the voltage VSSS may be output to the voltage correction circuit 347. The voltage correction circuit 347 is provided with a replica transistor of the transistor M35. The voltage VOT2 generated by the voltage correction circuit 347 is input to the wiring BGFL as a voltage VBGF.
　レベルシフタ３４８に回路１１４Ａおよび、実施の形態１の電圧出力回路を適用し、リカバリ信号ＲＣＨ、バックアップ信号ＢＫの“Ｈ”及び／又は“Ｌ”の電圧を補正するようにしてもよい。この場合、電圧出力回路３４５を設けなくてもよい。 The circuit 114A and the voltage output circuit of the first embodiment may be applied to the level shifter 348 to correct the voltage of “H” and / or “L” of the recovery signal RCH and the backup signal BK. In this case, the voltage output circuit 345 may not be provided.
＜パワーゲーティング＞
　ＣＰＵコアが通常動作を行っている間は、パワースイッチ３４９はオンであり、信号ＲＣ、ＢＫは“Ｌ”に固定される。通常動作状態からパワーゲーティング状態に移行する場合には、スキャンフリップフロップ３４１のデータをバックアップ回路３４２にバックアップする動作が行われる。 <Power gating>
While the CPU core is operating normally, the power switch 349 is on, and the signals RC and BK are fixed at "L". When transitioning from the normal operation state to the power gating state, an operation of backing up data of the scan flip flop 341 to the backup circuit 342 is performed.
　クロック信号ＧＣＬＫ４を非アクティブにする。信号ＢＫを“Ｈ”にする。Ｍ３５がオンになり、ノードＱ１のデータがノードＳＮ３５に書き込まれる。次に、パワースイッチ３４９をオフにして、ＣＰＵコアへの電圧ＶＤＤＤの供給を停止する。 Deactivate clock signal GCLK4. The signal BK is set to "H". M35 is turned on, and the data of node Q1 is written to node SN35. Next, the power switch 349 is turned off to stop the supply of the voltage VDDD to the CPU core.
　パワーゲーティング状態から通常動作状態に移行する場合には、スキャンフリップフロップ３４１のデータをバックアップ回路３４２に書き戻す。先ず、パワースイッチ３４９をオンにして、ＣＰＵコアへの電圧ＶＤＤＤの供給を開始する。次に、ＰＭＵ３１４は“Ｈ”の信号ＲＣ、ＳＣＥを出力する。トランジスタＭ３６はオンになり、容量素子Ｃ３５の電荷がノードＳＮ３５とノードＳＤとに分配される。ノードＳＥは“Ｈ”であるので、スキャンフリップフロップ３４１の入力側ラッチ回路にノードＳＤのデータが書き込まれる。次に、ＰＭＵ３１４は、クロック制御回路３１５を制御し、クロック信号ＧＣＬＫ４をアクティブにする。入力側ラッチ回路のデータがノードＱ１に書き込まれる。つまり、ノードＳＮ３５のデータがノードＱ１に書き込まれたことになる。次に、ＰＭＵ３１４は信号ＲＣ、ＳＣＥを“Ｌ”にする。リカバリ動作が終了する。 When transitioning from the power gating state to the normal operation state, the data of the scan flip flop 341 is written back to the backup circuit 342. First, the power switch 349 is turned on to start supply of the voltage VDDD to the CPU core. Next, the PMU 314 outputs the signals RC and SCE of "H". The transistor M36 is turned on, and the charge of the capacitive element C35 is distributed to the node SN35 and the node SD. Since the node SE is "H", the data of the node SD is written to the input-side latch circuit of the scan flip-flop 341. Next, the PMU 314 controls the clock control circuit 315 to activate the clock signal GCLK4. The data of the input side latch circuit is written to node Q1. That is, the data of the node SN35 is written to the node Q1. Next, the PMU 314 sets the signals RC and SCE to "L". Recovery operation ends.
　トランジスタＭ３５、Ｍ３６のしきい値電圧ＶＴｇの温度による変動を補正できるため、例えば、動作温度範囲においてバックアップ回路３４２は、基準温度Ｔｒｅｆのときと同程度の性能を実現することができる。よって、温度の上昇による保持時間の短縮、温度の低下によるバックアップ及びリカバリ時間の増加を抑えることができる。したがって、高信頼性、低消費電力のプロセッサ３００を提供することができる。 Since the variation due to temperature of the threshold voltage VTg of the transistors M35 and M36 can be corrected, for example, the backup circuit 342 can realize the same performance as the reference temperature Tref in the operating temperature range. Therefore, it is possible to suppress the shortening of the retention time due to the temperature rise and the increase of the backup and recovery time due to the temperature fall. Therefore, the processor 300 with high reliability and low power consumption can be provided.
　機能部３１８、インターフェース部３１９等に、実施の形態２の記憶装置及び／またはフリップフロップ３４０を適用することができる。 The memory device and / or the flip flop 340 of Embodiment 2 can be applied to the functional unit 318, the interface unit 319, and the like.
　本実施の形態のプロセッサに、温度センサとしてモニタ回路１３０を設けることができる。この場合、例えば、モニタ回路１３０の出力電圧に応じて、記憶装置のリフレッシュのサイクル、又はプロセッサのパワーゲーティングのタイミングを変更することができる。 The processor of this embodiment can be provided with a monitor circuit 130 as a temperature sensor. In this case, for example, depending on the output voltage of the monitor circuit 130, the refresh cycle of the storage device or the timing of the power gating of the processor can be changed.
〔実施の形態４〕
　図１９を参照して、上記の半導体装置が組み込まれた電子機器を説明する。図１９に示す電子機器には、電子部品７０２０及び／または電子部品７０３０を有する。電子部品７０２０は、実施の形態２の記憶装置が組み込まれ、電子部品７０３０には、実施の形態３のプロセッサが組み込まれている。 Fourth Embodiment
An electronic device in which the above-described semiconductor device is incorporated will be described with reference to FIG. The electronic device illustrated in FIG. 19 includes an electronic component 7020 and / or an electronic component 7030. The electronic component 7020 incorporates the storage device of the second embodiment, and the electronic component 7030 incorporates the processor of the third embodiment.
　ロボット７１００は、照度センサ、マイクロホン、カメラ、スピーカ、ディスプレイ、各種センサ（赤外線センサ、超音波センサ、加速度センサ、ピエゾセンサ、光センサ、ジャイロセンサなど）、および移動機構などを備える。電子部品７０３０はこれら周辺機器を制御する。電子部品７０２０は例えば、センサで取得されたデータを記憶する。 The robot 7100 includes an illuminance sensor, a microphone, a camera, a speaker, a display, various sensors (an infrared sensor, an ultrasonic sensor, an acceleration sensor, a piezo sensor, an optical sensor, a gyro sensor, and the like), a moving mechanism, and the like. The electronic component 7030 controls these peripheral devices. The electronic component 7020 stores, for example, data acquired by the sensor.
　マイクロホンは、使用者の音声および環境音などの音響信号を検知する機能を有する。また、スピーカは、音声および警告音などのオーディオ信号を発する機能を有する。ロボット７１００は、マイクロホンを介して入力されたオーディオ信号を解析し、必要なオーディオ信号をスピーカから発することができる。ロボット７１００は、マイクロホン、およびスピーカを用いて、使用者とコミュニケーションをとることが可能である。 The microphone has a function of detecting an acoustic signal such as a user's voice and an environmental sound. In addition, the speaker has a function of emitting audio signals such as voice and warning sound. The robot 7100 can analyze an audio signal input through a microphone and emit a necessary audio signal from a speaker. The robot 7100 can communicate with a user using a microphone and a speaker.
　カメラは、ロボット７１００の周囲を撮像する機能を有する。また、ロボット７１００は、移動機構を用いて移動する機能を有する。ロボット７１００は、カメラを用いて周囲の画像を撮像し、画像を解析して移動する際の障害物の有無などを察知することができる。 The camera has a function of imaging the periphery of the robot 7100. In addition, the robot 7100 has a function of moving using a moving mechanism. The robot 7100 can capture an image of the surroundings using a camera and analyze the image to detect the presence or absence of an obstacle when moving.
　飛行体７１２０は、プロペラ、カメラ、およびバッテリなどを有し、自律して飛行する機能を有する。電子部品７０３０はこれら周辺機器を制御する。電子部品７０３０は、カメラで撮影した画像データを解析し、移動する際の障害物の有無などを察知する。例えば、画像データは、電子部品７０２０に記憶される。 A flying object 7120 has a propeller, a camera, a battery, and the like, and has a function to fly autonomously. The electronic component 7030 controls these peripheral devices. The electronic component 7030 analyzes image data captured by a camera and detects the presence or absence of an obstacle when moving. For example, image data is stored in the electronic component 7020.
　掃除ロボット７１４０は、上面に配置されたディスプレイ、側面に配置された複数のカメラ、ブラシ、操作ボタン、各種センサなどを有する。図示されていないが、掃除ロボット７１４０には、タイヤ、吸い込み口等が備えられている。掃除ロボット７１４０は自走し、ゴミを検知し、下面に設けられた吸い込み口からゴミを吸引することができる。例えば、電子部品７０３０は、カメラが撮影した画像を解析し、壁、家具または段差などの障害物の有無を判断する。画像解析により、配線などブラシに絡まりそうな物体を検知した場合は、ブラシの回転を停止する。 The cleaning robot 7140 has a display disposed on the top, a plurality of cameras disposed on the side, brushes, operation buttons, various sensors, and the like. Although not shown, the cleaning robot 7140 is provided with a tire, a suction port and the like. The cleaning robot 7140 can self-propelled, detect dust, and suction dust from a suction port provided on the lower surface. For example, the electronic component 7030 analyzes an image captured by a camera, and determines the presence or absence of an obstacle such as a wall, furniture, or a step. When the image analysis detects an object that is likely to be entangled in the brush, such as wiring, the rotation of the brush is stopped.
　自動車７１６０は、エンジン、タイヤ、ブレーキ、操舵装置、カメラなどを有する。例えば、電子部品７０３０は、ナビゲーション情報、速度、エンジンの状態、ギアの選択状態、ブレーキの使用頻度などのデータに基づいて、自動車７１６０の走行状態を最適化するための制御を行う。例えば、カメラで撮影した画像データは電子部品７０２０に記憶される。 The automobile 7160 has an engine, tires, brakes, a steering device, a camera and the like. For example, the electronic component 7030 performs control for optimizing the traveling state of the automobile 7160 based on data such as navigation information, speed, engine state, gear selection state, and brake use frequency. For example, image data captured by a camera is stored in the electronic component 7020.
　電子部品７０２０および／または電子部品７０３０は、ＴＶ装置（テレビジョン受像装置）７２００、スマートフォン７２１０、ＰＣ（パーソナルコンピュータ）７２２０、７２３０、ゲーム機７２４０、ゲーム機７２６０等に組み込むことができる。例えば、ＴＶ装置７２００に内蔵された電子部品７０３０は画像エンジンとして機能する。例えば、電子部品７０３０は、ノイズ除去、解像度アップコンバージョンなどの画像処理を行う。 The electronic component 7020 and / or the electronic component 7030 can be incorporated in a TV set (television receiver) 7200, a smartphone 7210, a PC (personal computer) 7220, 7230, a game console 7240, a game console 7260, and the like. For example, an electronic component 7030 incorporated in the TV set 7200 functions as an image engine. For example, the electronic component 7030 performs image processing such as noise removal and resolution upconversion.
　スマートフォン７２１０は、携帯情報端末の一例である。スマートフォン７２１０は、マイクロホン、カメラ、スピーカ、各種センサ、および表示部を有する。電子部品７０３０はこれら周辺機器を制御する。 The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display portion. The electronic component 7030 controls these peripheral devices.
　ＰＣ７２２０、ＰＣ７２３０はそれぞれノート型ＰＣ、据え置き型ＰＣの例である。ＰＣ７２３０には、キーボード７２３２、およびモニタ装置７２３３が無線または有線により接続可能である。ゲーム機７２４０は携帯型ゲーム機の例である。ゲーム機７２６０は据え置き型ゲーム機の例である。ゲーム機７２６０には、無線または有線でコントローラ７２６２が接続されている。コントローラ７２６２に、電子部品７０２０および／または電子部品７０３０を組み込むこともできる。 The PC 7220 and the PC 7230 are examples of a notebook PC and a stationary PC, respectively. A keyboard 7232 and a monitor device 7233 can be connected to the PC 7230 wirelessly or by wire. The game machine 7240 is an example of a portable game machine. The game machine 7260 is an example of a stationary game machine. A controller 7262 is connected to the game machine 7260 wirelessly or by wire. The controller 7262 can also incorporate an electronic component 7020 and / or an electronic component 7030.
〔実施の形態５〕
　本実施の形態では、ＯＳトランジスタについて説明する。 Fifth Embodiment
In this embodiment, an OS transistor is described.
＜ＯＳトランジスタ５９０＞
　図２０Ａ~図２０Ｃはそれぞれ、ＯＳトランジスタ５９０の上面図、チャネル長方向の断面図、チャネル幅方向の断面図である。図２０Ａに示すＬ１−Ｌ２線、Ｗ１−Ｗ２線は切断線である。図２０Ａは、図の明瞭化のために一部の構成要素が省略されている。 <OS transistor 590>
20A to 20C are a top view of the OS transistor 590, a cross-sectional view in the channel length direction, and a cross-sectional view in the channel width direction, respectively. The L1-L2 line and the W1-W2 line shown in FIG. 20A are cutting lines. FIG. 20A omits some components for the sake of clarity of the figure.
　図２０Ａ~図２０Ｃには、ＯＳトランジスタ５９０、絶縁層５１０、絶縁層５１２、絶縁層５１４、絶縁層５１６、絶縁層５８０、絶縁層５８２、絶縁層５８４、導電層５４６ａ、導電層５４６ｂ、および導電層５０３を示す。例えば、導電層５４６ａ、導電層５４６ｂはコンタクトクトプラグを構成し、導電層５０３は配線を構成する。 In FIGS. 20A to 20C, the OS transistor 590, the insulating layer 510, the insulating layer 512, the insulating layer 514, the insulating layer 516, the insulating layer 580, the insulating layer 582, the insulating layer 584, the conductive layer 546a, the conductive layer 546b, and the conductive layer Layer 503 is shown. For example, the conductive layer 546a and the conductive layer 546b form a contact plug, and the conductive layer 503 forms a wiring.
　ＯＳトランジスタ５９０は、ゲートとして機能する導電層５６０（導電層５６０ａ、および導電層５６０ｂ）、バックゲートとして機能する導電層５０５（導電層５０５ａ、および導電層５０５ｂ）、ゲート絶縁層として機能する絶縁層５５０と、バックゲート絶縁層として機能する絶縁層５２０、５２２、５２４と、チャネル形成領域を有する酸化物層５３０（酸化物層５３０ａ、酸化物層５３０ｂ、および酸化物層５３０ｃ）と、ソース領域またはドレイン領域として機能する導電層５４０ａ、５４０ｂと、絶縁層５７４とを有する。 The OS transistor 590 includes a conductive layer 560 functioning as a gate (a conductive layer 560a and a conductive layer 560b), a conductive layer 505 functioning as a back gate (a conductive layer 505a and a conductive layer 505b), and an insulating layer functioning as a gate insulating layer 550, an insulating layer 520, 522, 524 which functions as a back gate insulating layer, an oxide layer 530 (an oxide layer 530a, an oxide layer 530b, and an oxide layer 530c) having a channel formation region, a source region or Conductive layers 540 a and 540 b which function as drain regions and an insulating layer 574 are provided.
　酸化物層５３０ｃ、絶縁層５５０および導電層５６０は、絶縁層５８０に設けられた開口部内に、絶縁層５７４を介して配置される。酸化物層５３０ｃ、絶縁層５５０および導電層５６０は、導電層５４０ａおよび導電層５４０ｂとの間に配置される。 The oxide layer 530 c, the insulating layer 550, and the conductive layer 560 are disposed in the opening provided in the insulating layer 580 with the insulating layer 574 interposed therebetween. The oxide layer 530c, the insulating layer 550, and the conductive layer 560 are disposed between the conductive layer 540a and the conductive layer 540b.
　絶縁層５１０、５１２は層間膜として機能する。絶縁層５１２は、絶縁層５１０よりも誘電率が低いことが好ましい。誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減することができる。絶縁層５１０、５１２は単層に限定されず、積層でもよい。他の絶縁層、導電層、酸化物層も同様に単層でも積層でもよい。 The insulating layers 510 and 512 function as interlayer films. The insulating layer 512 preferably has a lower dielectric constant than the insulating layer 510. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. The insulating layers 510 and 512 are not limited to a single layer, and may be stacked. Other insulating layers, conductive layers, and oxide layers may be single-layered or stacked similarly.
　層間膜としては、酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、酸化アルミニウム、酸化ハフニウム、酸化タンタル、酸化ジルコニウム、チタン酸ジルコン酸鉛（ＰＺＴ）、チタン酸ストロンチウム（ＳｒＴｉＯ３）または（Ｂａ，Ｓｒ）ＴｉＯ３（ＢＳＴ）などの絶縁体を単層または積層で用いることができる。またはこれらの絶縁体に、例えば、酸化アルミニウム、酸化ビスマス、酸化ゲルマニウム、酸化ニオブ、酸化シリコン、酸化チタン、酸化タングステン、酸化イットリウム、酸化ジルコニウムを添加してもよい。またはこれらの絶縁体を窒化処理してもよい。上記の絶縁体に酸化シリコン、酸化窒化シリコンまたは窒化シリコンを積層してもよい。 As the interlayer film, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba, Sr) An insulator such as TiO 3 (BST) can be used in a single layer or a stack. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
　絶縁層５１０は、水または水素などの不純物が、ＯＳトランジスタ５９０に混入することを抑制するバリア性を有することが好ましい。絶縁層５１０の絶縁性材料は水素原子、水素分子、水分子、銅原子などの不純物の拡散を抑制する機能を有する（上記不純物が透過しにくい。）絶縁性材料、または、酸素（例えば、酸素原子、酸素分子などの少なくとも一）の拡散を抑制する機能を有する（上記酸素が透過しにくい。）絶縁性材料であることが好ましい。このような機能を持つ絶縁性材料としては、例えば、酸化アルミニウム、窒化シリコンなどである。 The insulating layer 510 preferably has a barrier property to suppress entry of impurities such as water or hydrogen into the OS transistor 590. The insulating material of the insulating layer 510 has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are unlikely to permeate), or oxygen (eg, oxygen) It is preferable that it is an insulating material (it is hard to permeate | transmit the said oxygen) which has a function which suppresses the spreading | diffusion of at least one, such as an atom and an oxygen molecule. Examples of the insulating material having such a function include aluminum oxide and silicon nitride.
　導電層５０３は、絶縁層５１２に埋め込まれるように形成される。導電層５０３の上面の高さと、絶縁層５１２の上面の高さは同程度にできる。導電層５０３は、タングステン、銅、またはアルミニウムを主成分とする導電性が高い導電性材料を用いることが好ましい。 The conductive layer 503 is formed to be embedded in the insulating layer 512. The height of the top surface of the conductive layer 503 and the height of the top surface of the insulating layer 512 can be approximately the same. The conductive layer 503 is preferably formed using a highly conductive conductive material containing tungsten, copper, or aluminum as a main component.
　導電層５０５と導電層５６０とを重畳して設けることで、導電層５６０、および導電層５０５に電位を印加した場合、導電層５６０から生じる電界と、導電層５０５から生じる電界とがつながり、酸化物層５３０に形成されるチャネル形成領域を覆うことができる場合がある。つまり、ゲートの電界とバックゲートの電界によって、チャネル形成領域を電気的に取り囲むことができる。本明細書において、ゲートおよびバックゲートの電界によって、チャネル形成領域を電気的に取り囲むトランジスタの構造を、ｓｕｒｒｏｕｎｄｅｄ　ｃｈａｎｎｏｌ（Ｓ−ｃｈａｎｎｅｌ）構造とよぶ。 When the conductive layer 505 and the conductive layer 560 are provided to overlap with each other, when a potential is applied to the conductive layer 560 and the conductive layer 505, the electric field generated from the conductive layer 560 and the electric field generated from the conductive layer 505 are connected to each other. In some cases, the channel formation region formed in the object layer 530 can be covered. That is, the electric field of the gate and the electric field of the back gate can electrically surround the channel formation region. In this specification, a structure of a transistor which electrically surrounds a channel formation region by an electric field of a gate and a back gate is referred to as a surrounded channol (S-channel) structure.
　絶縁層５１４、５１６は、絶縁層５１０と同様に、層間膜として機能する。水または水素などの不純物がＯＳトランジスタ５９０に混入することを抑制するため、例えば、絶縁層５１４は、不純物の拡散を抑制するバリア膜であることが好ましい。配線間に生じる寄生容量を低減するため、例えば、絶縁層５１６は、絶縁層５１４よりも誘電率が低いことが好ましい。 The insulating layers 514 and 516 function as interlayer films in the same manner as the insulating layer 510. For example, the insulating layer 514 is preferably a barrier film which suppresses diffusion of impurities, in order to suppress entry of impurities such as water or hydrogen into the OS transistor 590. For example, the insulating layer 516 preferably has a dielectric constant lower than that of the insulating layer 514 in order to reduce parasitic capacitance generated between the wirings.
　絶縁層５１４、５１６の開口の内壁に接して導電層５０５が形成されている。導電層５０５ａおよび導電層５０５ｂの上面の高さと、絶縁層５１６の上面の高さは同程度にできる。導電層５０５ａには、水素原子、水素分子、水分子、銅原子などの不純物の拡散を抑制する機能を有する導電性材料（不純物が透過しにくい導電性材料）、または、酸素（例えば、酸素原子、酸素分子など）の拡散を抑制する機能を有する（上記酸素が透過しにくい。）導電性材料（以下、酸素が透過しにくい導電性材料と呼ぶ）を用いることが好ましい。本明細書において、不純物または酸素の拡散を抑制する機能とは、上記不純物および上記酸素のうちの少なくとも１つの拡散を抑制する機能とする。例えば、導電層５０５ａが酸素の拡散を抑制する機能を持つことにより、導電層５０５ｂが酸化して導電率が低下することを抑制することができる。 A conductive layer 505 is formed in contact with the inner wall of the opening of the insulating layers 514 and 516. The heights of the top surfaces of the conductive layer 505 a and the conductive layer 505 b can be approximately the same as the height of the top surface of the insulating layer 516. The conductive layer 505 a may be a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (conductive materials to which impurities are unlikely to permeate), or oxygen (eg, oxygen atoms) It is preferable to use a conductive material (hereinafter referred to as a conductive material which hardly transmits oxygen) which has a function of suppressing the diffusion of oxygen molecules and the like (the above-mentioned oxygen is difficult to transmit). In the present specification, the function of suppressing the diffusion of the impurity or oxygen is a function of suppressing the diffusion of at least one of the impurity and the oxygen. For example, when the conductive layer 505 a has a function of suppressing the diffusion of oxygen, the conductive layer 505 b can be suppressed from being oxidized to be lowered in conductivity.
　導電層５０５が配線の機能を兼ねる場合、導電層５０５ｂは、タングステン、銅、またはアルミニウムを主成分とする導電層を有する。導電層５０５ｂは、例えば、チタン、窒化チタンと上記導電層との積層としてもよい。導電層５０５には導電性が高い導電性材料層を用いることが好ましい。その場合、導電層５０３は、必ずしも設けなくともよい。 In the case where the conductive layer 505 also functions as a wiring, the conductive layer 505 b includes a conductive layer containing tungsten, copper, or aluminum as a main component. The conductive layer 505 b may be, for example, a stack of titanium or titanium nitride and the above conductive layer. For the conductive layer 505, a conductive material layer having high conductivity is preferably used. In that case, the conductive layer 503 may not necessarily be provided.
　絶縁層５２２は、バリア性を有することが好ましい。絶縁層５２２がバリア性を有することで、ＯＳトランジスタ５９０の周辺部からＯＳトランジスタ５９０への水素等の不純物の混入を抑制する層として機能する。絶縁層５２２は、例えば、酸化アルミニウム、酸化ハフニウム、アルミニウムおよびハフニウムを含む酸化物（ハフニウムアルミネート）、酸化タンタル、酸化ジルコニウム、チタン酸ジルコン酸鉛（ＰＺＴ）、チタン酸ストロンチウム（ＳｒＴｉＯ３）または（Ｂａ，Ｓｒ）ＴｉＯ３（ＢＳＴ）などのいわゆるｈｉｇｈ−ｋ材料を含む絶縁体を単層または積層で用いることが好ましい。ＯＳトランジスタの微細化、および高集積化が進むと、ゲート絶縁層の薄膜化により、リーク電流などの問題が生じる場合がある。ゲート絶縁層にｈｉｇｈ−ｋ材料を用いることで、物理膜厚を保って、ゲート電圧の低減が可能となる。 The insulating layer 522 preferably has a barrier property. When the insulating layer 522 has a barrier property, the insulating layer 522 functions as a layer which suppresses entry of an impurity such as hydrogen from the peripheral portion of the OS transistor 590 to the OS transistor 590. The insulating layer 522 is made of, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or It is preferable to use an insulator containing a so-called high-k material such as Ba, Sr) TiO 3 (BST) in a single layer or a laminate. As the miniaturization and higher integration of the OS transistor progress, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a high-k material for the gate insulating layer, the gate voltage can be reduced while maintaining the physical thickness.
　絶縁層５２０は、熱的に安定であることが好ましい。例えば、酸化シリコンおよび酸化窒化シリコンは、熱的に安定であるため、好適である。また、ｈｉｇｈ−ｋ材料の絶縁体を絶縁層５２２と組み合わせることで、熱的に安定かつ比誘電率の高い積層構造のゲート絶縁層を得ることができる。 The insulating layer 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, by combining an insulator of a high-k material with the insulating layer 522, a gate insulating layer with a stacked structure with high thermal stability and high dielectric constant can be obtained.
〔酸化物半導体〕
　ＯＳトランジスタの酸化物半導体層は、少なくともインジウムまたは亜鉛を含む金属酸化物を有することが好ましい。金属酸化物は、特にインジウムおよび亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウムまたはスズなどが含まれていることが好ましい。また、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種、または複数種が含まれていてもよい。 [Oxide semiconductor]
The oxide semiconductor layer of the OS transistor preferably includes a metal oxide containing at least indium or zinc. The metal oxide preferably comprises, in particular, indium and zinc. In addition to them, aluminum, gallium, yttrium or tin is preferably contained. In addition, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.
　ここで、金属酸化物が、インジウム、元素Ｍおよび亜鉛を有する場合を考える。なお、元素Ｍは、アルミニウム、ガリウム、イットリウムまたはスズなどである。元素Ｍに適用可能なその他の元素として、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウムなどがある。ただし、元素Ｍとして、前述の元素を複数組み合わせても構わない場合がある。 Here, consider the case where the metal oxide contains indium, the element M and zinc. The element M is, for example, aluminum, gallium, yttrium or tin. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the aforementioned elements may be combined in some cases.
　なお、本明細書において、窒素を有する金属酸化物も金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）の範疇に含むこととする。金属酸化物と区別する場合、窒素を有する金属酸化物を、金属酸窒化物（ｍｅｔａｌ　ｏｘｙｎｉｔｒｉｄｅ）と呼称してもよい。 In the present specification, metal oxides having nitrogen are also included in the category of metal oxides. In the case of distinction from metal oxides, metal oxides having nitrogen may be referred to as metal oxynitrides.
　酸化物層５３０ａ~５３０ｃには、上掲の金属酸化物を用いることができる。酸化物層５３０において、酸化物層５３０ａ~５３０ｃが積層される領域を有する。この領域がチャネル形成領域になり、主に、酸化物層５３０ｂにチャネルが形成される。酸化物層５３０に、酸化物層５３０ａ、５３０ｃが存在することで、酸化物層５３０ｂへの不純物の拡散を抑制することができる。 For the oxide layers 530a to 530c, the above-described metal oxides can be used. The oxide layer 530 has a region where the oxide layers 530a to 530c are stacked. This region is a channel formation region, and a channel is mainly formed in the oxide layer 530b. The presence of the oxide layers 530 a and 530 c in the oxide layer 530 can suppress diffusion of impurities into the oxide layer 530 b.
　酸化物層５３０ｃは、絶縁層５８０に設けられた開口部内に、絶縁層５７４を介して設けられることが好ましい。絶縁層５７４がバリア性を有する場合、絶縁層５８０からの不純物が酸化物層５３０へと拡散することを抑制することができる。 The oxide layer 530 c is preferably provided in the opening provided in the insulating layer 580 with the insulating layer 574 interposed therebetween. When the insulating layer 574 has a barrier property, diffusion of impurities from the insulating layer 580 into the oxide layer 530 can be suppressed.
　導電層５４０ａ、５４０ｂには、アルミニウム、チタン、クロム、ニッケル、銅、イットリウム、ジルコニウム、モリブデン、銀、タンタル、またはタングステンなどの金属、またはこれを主成分とする合金を用いることができる。特に、窒化タンタルなどの金属窒化物膜は、水素または酸素に対するバリア性があり、また、耐酸化性が高いため、好ましい。例えば、導電層５４０ａ、５４０ｂを２層構造とする場合、窒化タンタル膜上にタングステン膜を積層する、チタン膜またはタングステン膜上にアルミニウム膜を積層する、銅−マグネシウム−アルミニウム合金膜、チタン膜またはタングステン膜上に銅膜を積層した積層膜を用いればよい。 For the conductive layers 540a and 540b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing any of these as a main component can be used. In particular, metal nitride films such as tantalum nitride are preferable because they have a barrier property to hydrogen or oxygen and high oxidation resistance. For example, in the case where the conductive layers 540a and 540b have a two-layer structure, a copper-magnesium-aluminium alloy film, a titanium film, or a titanium film or a tungsten film is formed by stacking a tungsten film over a tantalum nitride film. A laminated film in which a copper film is laminated on a tungsten film may be used.
　また、チタン膜または窒化チタン膜と、そのチタン膜または窒化チタン膜上に重ねてアルミニウム膜または銅膜を積層し、さらにその上にチタン膜または窒化チタン膜を形成する三層構造、モリブデン膜または窒化モリブデン膜と、そのモリブデン膜または窒化モリブデン膜上に重ねてアルミニウム膜または銅膜を積層し、さらにその上にモリブデン膜または窒化モリブデン膜を形成する三層構造等がある。なお、酸化インジウム、酸化錫または酸化亜鉛を含む透明導電材料を用いてもよい。 In addition, a three-layer structure in which a titanium film or a titanium nitride film and an aluminum film or a copper film are stacked on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is formed thereon There is a molybdenum nitride film, a three-layer structure in which an aluminum film or a copper film is stacked on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.
　導電層５４０ａ、５４０ｂ上に、酸素、または水素に対してバリア性を有するバリア層を設けてもよい。当該構成により、絶縁層５７４を成膜する際に、導電層５４０ａ、５４０ｂが酸化することを抑制することができる。バリア層には、例えば、金属酸化物を用いることができる。特に、酸素や水素に対してバリア性のある絶縁材料を用いることが好ましい。また、ＣＶＤ法で形成した窒化シリコン層を用いてもよい。バリア層を導電層５４０ａ、５４０ｂ上に設けることで、導電層５４０ａ、５４０ｂの材料選択性が向上する。例えば、導電層５４０ａ、５４０ｂに、タングステンや、アルミニウムなどの耐酸化性が低い一方で導電性が高い材料を用いることができる。また、例えば、成膜、または加工がしやすい導電体を用いることができる。 A barrier layer having a barrier property to oxygen or hydrogen may be provided over the conductive layers 540a and 540b. With this structure, when the insulating layer 574 is formed, oxidation of the conductive layers 540a and 540b can be suppressed. For the barrier layer, for example, a metal oxide can be used. In particular, an insulating material having a barrier property to oxygen and hydrogen is preferably used. Alternatively, a silicon nitride layer formed by a CVD method may be used. Providing the barrier layer over the conductive layers 540a and 540b improves the material selectivity of the conductive layers 540a and 540b. For example, for the conductive layers 540a and 540b, a material with low oxidation resistance, such as tungsten or aluminum, but high conductivity can be used. Further, for example, a conductor which can be easily formed or processed can be used.
　絶縁層５５０は、絶縁層５８０に設けられた開口部内に、酸化物層５３０ｃ、および絶縁層５７４を介して設けられることが好ましい。トランジスタの微細化、および高集積化が進むと、ゲート絶縁層の薄膜化により、リーク電流などの問題が顕在化する場合がある。絶縁層５５０はゲート絶縁層を構成し、上掲のバックゲート絶縁層と同様の構成とすることができる。 The insulating layer 550 is preferably provided in the opening provided in the insulating layer 580 with the oxide layer 530 c and the insulating layer 574 interposed therebetween. As the miniaturization and higher integration of transistors progress, problems such as leakage current may become apparent due to thinning of the gate insulating layer. The insulating layer 550 forms a gate insulating layer and can have the same structure as the above-described back gate insulating layer.
　導電層５６０ａは、導電層５０５ａと同様に、不純物または酸素の拡散を抑制する機能を有する導電性材料を用いることが好ましい。導電層５６０ａが、特に、酸素の拡散を抑制する機能を持つことで、導電層５６０ｂの酸化が抑制され、導電率が低下することを防止することができる。そのため、導電層５６０ｂの材料選択性を向上することができる。 The conductive layer 560 a is preferably formed using a conductive material having a function of suppressing diffusion of impurities or oxygen, similarly to the conductive layer 505 a. In particular, the conductive layer 560a has a function of suppressing the diffusion of oxygen, whereby oxidation of the conductive layer 560b can be suppressed and a decrease in conductivity can be prevented. Therefore, material selectivity of the conductive layer 560b can be improved.
　酸素の拡散を抑制する機能を有する導電性材料としては、例えば、タンタル、窒化タンタル、ルテニウムまたは酸化ルテニウムなどを用いることが好ましい。また、導電層５６０ａとして、酸化物層５３０として用いることができる金属酸化物を用いることができる。その場合、導電層５６０ｂをスパッタリング法で成膜することで、導電層５６０ａの電気抵抗値を低下させて導電体とすることができる。これをＯＣ（Ｏｘｉｄｅ　Ｃｏｎｄｕｃｔｏｒ）電極と呼ぶことができる。 As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide or the like is preferably used. Alternatively, a metal oxide that can be used as the oxide layer 530 can be used as the conductive layer 560a. In that case, by forming the conductive layer 560b by a sputtering method, the electric resistance value of the conductive layer 560a can be reduced to be a conductor. This can be called an OC (Oxide Conductor) electrode.
　導電層５６０は配線として機能するため、導電層５６０ｂは、導電性が高い導電体を用いることが好ましい。導電層５６０ｂには、タングステン、銅、またはアルミニウムを主成分とする導電性材料を用いることが好ましい。 Since the conductive layer 560 functions as a wiring, the conductive layer 560 b is preferably formed using a conductor with high conductivity. It is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component for the conductive layer 560b.
　絶縁層５７４は、水または水素などの不純物、および酸素の拡散を抑制するバリア性を有することが好ましい。絶縁層５７４を有することで、絶縁層５８０が有する水、および水素などの不純物が酸化物層５３０ｃ、絶縁層５５０を介して、酸化物層５３０ｂに拡散することを抑制することができる。また、絶縁層５８０が有する過剰酸素により、導電層５６０が酸化するのを抑制することができる。 The insulating layer 574 preferably has a barrier property to suppress diffusion of impurities such as water or hydrogen and oxygen. With the insulating layer 574, diffusion of impurities such as water and hydrogen included in the insulating layer 580 to the oxide layer 530b through the oxide layer 530c and the insulating layer 550 can be suppressed. Further, oxidation of the conductive layer 560 can be suppressed by excess oxygen contained in the insulating layer 580.
　絶縁層５７４には、例えば、酸化アルミニウムまたは酸化ハフニウムなどを用いることが好ましい。他にも、例えば、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジムまたは酸化タンタルなどの金属酸化物、窒化酸化シリコンまたは窒化シリコンなどを用いることができる。 For the insulating layer 574, for example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
　絶縁層５８０、５８２、５８４は、層間膜として機能する。絶縁層５８２は、絶縁層５１４と同様に、水または水素などの不純物が、外部からＯＳトランジスタ５９０に混入するのを抑制するバリア層として機能することが好ましい。絶縁層５８０、５８４は、絶縁層５１６と同様に、絶縁層５８２よりも誘電率が低いことが好ましい。誘電率が低い材料を層間膜とすることで、配線間に生じる寄生容量を低減することができる。 The insulating layers 580, 582, and 584 function as interlayer films. Like the insulating layer 514, the insulating layer 582 preferably functions as a barrier layer which prevents impurities such as water or hydrogen from entering the OS transistor 590 from the outside. Like the insulating layer 516, the insulating layers 580 and 584 preferably have a lower dielectric constant than the insulating layer 582. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
　ＯＳトランジスタ５９０は、絶縁層５８０、５８２、５８４に埋め込まれた導電層５４６ａ、導電層５４６ｂなどのプラグや配線を介して、他の構造と電気的に接続してもよい。導電層５４６ａ、導電層５４６ｂの材料は、導電層５０５のものと同様、金属材料、合金材料、金属窒化物材料、または金属酸化物材料などの導電性材料である。例えば、耐熱性と導電性を両立するタングステンやモリブデンなどの高融点材料を用いることが好ましい。または、アルミニウムや銅などの低抵抗導電性材料で形成することが好ましい。低抵抗導電性材料を用いることで配線抵抗を低くすることができる。 The OS transistor 590 may be electrically connected to another structure through a plug or a wiring such as the conductive layer 546a or the conductive layer 546b embedded in the insulating layers 580, 582, and 584. The material of the conductive layer 546 a and the conductive layer 546 b is similar to that of the conductive layer 505, and is a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material. For example, it is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity. Alternatively, it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.
　導電層５４６ａ、導電層５４６ｂは、例えば、水素、および酸素に対してバリア性を有する窒化タンタル等と、導電性が高いタングステンとの積層であることで、配線としての導電性を保持したまま、外部からの不純物の拡散を抑制することができる。 The conductive layer 546a and the conductive layer 546b are layers of, for example, tantalum nitride or the like having a barrier property to hydrogen and oxygen and tungsten having high conductivity, so that the conductivity as a wiring is maintained, Diffusion of impurities from the outside can be suppressed.
＜ＯＳトランジスタ５９２＞
　図２１Ａ~図２１Ｃはそれぞれ、ＯＳトランジスタ５９２の上面図、チャネル長方向の断面図、チャネル幅方向の断面図である。図２１Ａに示すＬ１−Ｌ２線、Ｗ１−Ｗ２線は切断線である。図２１Ａは、図の明瞭化のために一部の構成要素は省略している。 <OS transistor 592>
21A to 21C are a top view of the OS transistor 592, a cross-sectional view in the channel length direction, and a cross-sectional view in the channel width direction, respectively. The L1-L2 line and the W1-W2 line shown in FIG. 21A are cutting lines. FIG. 21A omits some components for the sake of clarity of the figure.
　ＯＳトランジスタ５９２はＯＳトランジスタ５９２の変形例であるため、主にＯＳトランジスタ５９２と異なる点について説明する。 Since the OS transistor 592 is a modification of the OS transistor 592, mainly the points different from the OS transistor 592 will be described.
　ＯＳトランジスタ５９２は、導電層５４０ａ、５４０ｂのそれぞれが、酸化物層５３０ｃ、絶縁層５５０、および導電層５６０と重畳する領域を有する。当該構造とすることで、オン電流が高いＯＳトランジスタを提供することができる。また、制御性が高いＯＳトランジスタを提供することができる。 The OS transistor 592 has a region in which each of the conductive layers 540 a and 540 b overlaps with the oxide layer 530 c, the insulating layer 550, and the conductive layer 560. With this structure, an OS transistor with high on-state current can be provided. In addition, an OS transistor with high controllability can be provided.
　導電層５６０は、導電層５６０ａ上の導電層５６０ｂを有する。導電層５６０ａは、導電層５０５ａと同様に、水素原子、水素分子、水分子、銅原子などの不純物の拡散を抑制する機能を有する導電性材料を用いることが好ましい。または、酸素（例えば、酸素原子、酸素分子などの少なくとも一）の拡散を抑制する機能を有する導電性材料を用いることが好ましい。 The conductive layer 560 includes a conductive layer 560b over the conductive layer 560a. Similarly to the conductive layer 505a, the conductive layer 560a is preferably formed using a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atom, oxygen molecule, and the like).
　導電層５６０ａが酸素の拡散を抑制する機能を持つことで、導電層５６０ｂの酸化が抑制され、導電率が低下することを防止することができる。よって、導電層５６０ｂの材料選択性を向上することができる。 With the conductive layer 560 a having a function of suppressing the diffusion of oxygen, oxidation of the conductive layer 560 b can be suppressed and a decrease in conductivity can be prevented. Thus, material selectivity of the conductive layer 560b can be improved.
　また、導電層５６０の上面および側面、絶縁層５５０の側面、および酸化物層５３０ｃの側面を覆うように、絶縁層５７４を設けることが好ましい。なお、絶縁層５７４は、水または水素などの不純物、および酸素の拡散を抑制する機能を有する絶縁性材料を用いるとよい。例えば、酸化アルミニウムまたは酸化ハフニウムなどを用いることが好ましい。また、他にも、例えば、酸化マグネシウム、酸化ガリウム、酸化ゲルマニウム、酸化イットリウム、酸化ジルコニウム、酸化ランタン、酸化ネオジムまたは酸化タンタルなどの金属酸化物、窒化酸化シリコンまたは窒化シリコンなどを用いることができる。 Further, the insulating layer 574 is preferably provided to cover the top surface and the side surfaces of the conductive layer 560, the side surface of the insulating layer 550, and the side surface of the oxide layer 530c. Note that for the insulating layer 574, an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen can be used. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
　絶縁層５７４を設けることで、導電層５６０の酸化を抑制することができる。また、絶縁層５７４を有することで、絶縁層５８０が有する水、および水素などの不純物がＯＳトランジスタ５９２へ拡散することを抑制することができる。 With the insulating layer 574, oxidation of the conductive layer 560 can be suppressed. With the insulating layer 574, diffusion of impurities such as water and hydrogen which the insulating layer 580 has into the OS transistor 592 can be suppressed.
　また、導電層５４６ａ、導電層５４６ｂと、絶縁層５８０との間に、バリア性を有する絶縁層５７６（絶縁層５７６ａ、および絶縁層５７６ｂ）を配置してもよい。絶縁層５７６を設けることで、絶縁層５８０の酸素が導電層５４６ａ、５導電層４６ｂと反応し、導電層５４６ａ、導電層５４６ｂが酸化することを抑制することができる。 Alternatively, the insulating layer 576 (the insulating layer 576a and the insulating layer 576b) having a barrier property may be provided between the conductive layer 546a and the conductive layer 546b and the insulating layer 580. With the insulating layer 576, oxygen in the insulating layer 580 can be reacted with the conductive layers 546a and 5b to suppress oxidation of the conductive layers 546a and 546b.
　また、バリア性を有する絶縁層５７６を設けることで、プラグや配線に用いられる導電体の材料選択の幅を広げることができる。例えば、導電層５４６ａ、導電層５４６ｂに、酸素を吸収する性質を持つ一方で、導電性が高い金属材料を用いることで、低消費電力の半導体装置を提供することができる。具体的には、タングステンや、アルミニウムなどの耐酸化性が低い一方で導電性が高い材料を用いることができる。また、例えば、成膜、または加工がしやすい導電体を用いることができる。 Further, by providing the insulating layer 576 having a barrier property, the range of material selection of a conductor used for a plug or a wiring can be expanded. For example, the conductive layer 546a and the conductive layer 546b have a property of absorbing oxygen, and by using a metal material with high conductivity, a semiconductor device with low power consumption can be provided. Specifically, materials having low oxidation resistance, such as tungsten and aluminum, but having high conductivity can be used. Further, for example, a conductor which can be easily formed or processed can be used.
　１０：回路、１００、１０１、１０２、１０３、１１０、１１２、１１３：半導体装置、１１４：ドライバ回路、１１４Ａ：回路、１１８：パワードメイン、１２０、１２２、１２４：電圧出力回路、１３０、１３１：モニタ回路、１３２：リセット回路、１３４：ソースフォロワ回路、１３６：オペアンプ、１３８：スイッチ回路、１４０：電圧生成部、１４３：チャージポンプ回路、１５０：電圧補正回路、１６０：電圧補正回路、１７０：電圧生成回路、１７１：制御回路、１７３：チャージポンプ回路 10: Circuit, 100, 101, 102, 103, 110, 112, 113: Semiconductor device, 114: Driver circuit, 114A: Circuit, 118: Power domain, 120, 122, 124: Voltage output circuit, 130, 131: Monitor Circuit 132: reset circuit 134: source follower circuit 136: operational amplifier 138: switch circuit 140: voltage generator 143: charge pump circuit 150: voltage correction circuit 160: voltage correction circuit 170: voltage generation Circuit 171: Control circuit 173: Charge pump circuit

Claims (13)

  1. 　第１トランジスタ、第１容量素子、第１出力端子、第１スイッチ、および第２スイッチを有し、
    　前記第１トランジスタのゲートとソースは電気的に接続され、
    　前記第１容量素子の第１端子および前記第１出力端子は、前記第１トランジスタのバックゲートに電気的に接続され、
    　前記第１容量素子の第２端子は、前記ソースに電気的に接続され、
    　前記第１スイッチは、前記バックゲートへの第１電圧の入力を制御し、
    　前記第１トランジスタのドレインは、第２電圧が入力され、
    　前記第２スイッチは、前記ソースへの第３電圧の入力を制御する半導体装置。     A first transistor, a first capacitive element, a first output terminal, a first switch, and a second switch;
    The gate and the source of the first transistor are electrically connected,
    The first terminal of the first capacitive element and the first output terminal are electrically connected to the back gate of the first transistor,
    The second terminal of the first capacitive element is electrically connected to the source,
    The first switch controls the input of a first voltage to the back gate,
    A second voltage is input to a drain of the first transistor.
    The second switch controls the input of a third voltage to the source.
  2. 　請求項１において、
    　前記第１スイッチおよび前記第２スイッチはそれぞれ、チャネル形成領域に金属酸化物を有するトランジスタである半導体装置。     In claim 1,
    Each of the first switch and the second switch is a transistor having a metal oxide in a channel formation region.
  3. 　請求項１において、
    　前記第１トランジスタはｎチャネル型トランジスタであり、
    　前記第１乃至第３電圧は定電圧であり、
    　前記第１トランジスタはノーマリオン特性を示し、かつ前記ドレインと前記ソース間の電圧は０Ｖよりも大きくなるように、前記第２電圧および前記第３電圧が設定されている半導体装置。     In claim 1,
    The first transistor is an n-channel transistor,
    The first to third voltages are constant voltages,
    The semiconductor device in which the second voltage and the third voltage are set such that the first transistor exhibits a normally on characteristic, and the voltage between the drain and the source is larger than 0V.
  4. 　請求項１において、
    　前記第１トランジスタはｐチャネル型トランジスタであり、
    　前記第１乃至第３電圧は定電圧であり、
    　前記第１トランジスタがノーマリオン特性を示し、かつ前記ドレインと前記ソース間の電圧が０Ｖよりも小さくなるように、前記第２電圧および前記第３電圧が設定されている半導体装置。     In claim 1,
    The first transistor is a p-channel transistor,
    The first to third voltages are constant voltages,
    The semiconductor device in which the second voltage and the third voltage are set such that the first transistor exhibits a normally on characteristic and the voltage between the drain and the source is smaller than 0V.
  5. 　請求項１乃至４の何れか１項において、
    　さらにバックゲートを有する第２トランジスタを有し、
    　前記第１出力端子から出力される第４電圧に応じて、前記第２トランジスタのバックゲートに入力される電圧が変化される半導体装置。     In any one of claims 1 to 4,
    And a second transistor having a back gate,
    The semiconductor device in which the voltage input to the back gate of the second transistor is changed according to the fourth voltage output from the first output terminal.
  6. 　請求項１乃至４の何れか１項において、
    　さらに第３トランジスタを有し、
    　前記第１出力端子から出力される第４電圧に応じて、前記第３トランジスタのゲートに入力される電圧が変化される半導体装置。     In any one of claims 1 to 4,
    And a third transistor,
    The semiconductor device in which the voltage inputted to the gate of the third transistor is changed according to the fourth voltage outputted from the first output terminal.
  7. 　請求項１乃至４の何れか１項において、
    　さらに、第２容量素子、電流電圧変換回路および増幅回路を有し、
    　前記第２容量素子の第１端子は、前記第１出力端子に電気的に接続され、
    　前記第２容量素子の第２端子は、前記電流電圧変換回路の入力端子に電気的に接続され、
    　前記増幅回路は、前記電流電圧変換回路から出力される第５電圧を増幅し、第６電圧を出力する半導体装置。     In any one of claims 1 to 4,
    And a second capacitance element, a current-voltage conversion circuit, and an amplification circuit,
    The first terminal of the second capacitive element is electrically connected to the first output terminal,
    The second terminal of the second capacitive element is electrically connected to the input terminal of the current-voltage conversion circuit,
    The semiconductor device amplifies the fifth voltage output from the current-voltage conversion circuit and outputs a sixth voltage.
  8. 　請求項７において、
    　前記電流電圧変換回路は、ソースフォロワ回路である半導体装置。     In claim 7,
    The semiconductor device in which the current voltage conversion circuit is a source follower circuit.
  9. 　請求項７において、
    　温度が上昇すると、前記第６電圧は減少する半導体装置。     In claim 7,
    The semiconductor device in which the sixth voltage decreases as the temperature rises.
  10. 　請求項７乃至９の何れか１項において、
    　前記増幅回路は、オペアンプである半導体装置。     In any one of claims 7 to 9,
    The amplifier circuit is a semiconductor device which is an operational amplifier.
  11. 　請求項７乃至１０の何れか１項において、
    　さらに、バックゲートを有する第４トランジスタを有し、
    　前記第６電圧に応じて、前記第４トランジスタのバックゲートに入力される電圧が変化される半導体装置。     In any one of claims 7 to 10,
    And further comprising a fourth transistor having a back gate,
    The semiconductor device wherein the voltage inputted to the back gate of the fourth transistor is changed according to the sixth voltage.
  12. 　請求項７乃至１０の何れか１項において、
    　さらに第５トランジスタを有し、
    　前記第６電圧に応じて、前記第５トランジスタのゲートに入力される電圧が変化する半導体装置。     In any one of claims 7 to 10,
    And a fifth transistor,
    The semiconductor device in which the voltage inputted into the gate of the 5th transistor changes according to the 6th voltage.
  13. 　請求項１乃至１２の何れか１項に記載の半導体装置の動作方法であり、
    　前記第１スイッチおよび前記第２スイッチをオンにすること、
    　前記第１スイッチをオンにし、かつ前記第２スイッチをオフにすること、
    　前記第１スイッチをオフにし、かつ前記第２スイッチをオフにすること、
    　前記第１スイッチをオフにし、かつ前記第２スイッチをオンにすることを含む半導体装置の動作方法。     A method of operating a semiconductor device according to any one of claims 1 to 12,
    Turning on the first switch and the second switch;
    Turning on the first switch and turning off the second switch;
    Turning off the first switch and turning off the second switch;
    A method of operating a semiconductor device, comprising turning off the first switch and turning on the second switch.
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