B7 B7 經濟部_央嘌革局員工消费合作杜印衆 五、發明説明（/ ) 詳細說明： 本發明是一種關於積體電路之閘極的製造方法，特別是 關於形成複晶矽/金屬矽化物之閘極結構的製造。 最近幾年，由於微影技術和電漿蝕刻技術的進步，積體 電路的積集密度有急劇的增加，大幅改善了電子產品的品質 與成本。目前，.應用最廣泛的積體電路是場效電晶體積體電 路（FET 1C)，無論是動態隨機存取記憶體（DRAM)、靜 態隨機存取記憶體（SRAM)、特殊應用積體電路（ASIC) 和微處理器晶片（CPU)等產品，都跟場效電晶體有關。 通常，所述場效電晶體是利用複晶矽（polysilicon)作爲 場效電晶體之閘極，然而，複晶矽即使在摻雜(doping)之後， 仍有高達500〜1200 A Ω-cm的電阻，造成電晶體連線電阻值 和電容值昇高（RC constant)，電路速度變慢。而一個改善 連線電阻值的方法是，以具有低電阻值之金屬替代複晶矽來 作爲場效電晶體之閘極，然而，後續高溫氧化層沉積（High Temperature Oxide ; HTO)等高溫製程卻不允許以金屬替代 複晶矽來作爲場效電晶體之閘極。 另一個改善區域連線電阻值的方法是以複晶矽/金屬矽 化物之複層結構來取代單層複晶矽，來作爲場效電晶體之閘 極。所述複晶矽/金屬矽化物之複層結構的金屬矽化物提供 了較低的區域連線電阻，而所述複晶矽/金屬矽化物之複層結 構的複晶矽則如傳統複晶矽閘極般，提供了良好的場效電晶 體之臨界電壓控制能力（threshold voltage control )。雖然， 用複晶矽/金屬矽化物複層結構來取代複晶矽以作爲場效電 2 (請先閲讀背面之注意事項再填寫本頁) 、1r 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 417179 經濟部中央標準局員工消費合作社印装 五、發明説明（=_ ) 晶體之閘極，可以改善電晶體區域連線電阻’但在實際製程 上卻會產生新的問題。 習用形成複晶矽/矽化鎢複層結構之矽化鎢的方式是使 六氟化鎢(WF6)和矽甲烷(SiH4)以低壓化學氣相沈積法 (LPCVD)沈積在晶片表面，但此方法所形成的矽化鎢常面臨 到的問題爲在進行褪火(annealing)後易掀起(Peeling)以及反 應中的氟原子擴散穿過底層的複晶矽’造成元件的崩潰電壓 降低。 矽化鈦(TiSix)和矽化鈷(CoSix)在金屬矽化物(X = 2到 2.6)中擁有最低的電阻率(10到15 # Ω-cm)，這二者或是由微 影製程沈積，或是由自行對準金屬矽化物製程(self-aligned silicide：)沈積。由微影製程定義複晶矽/矽化鈦閘極結構的困 難是當蝕刻複晶矽時，矽化鈦會被含氯的蝕刻氣體(Cl-based chemistry)所侵蝕，使線寬(line width)很難控制。矽化鈷則由 於缺少可產生揮發性化合物的蝕刻反應氣體，很難被蝕刻。 自行對準金屬矽化物製程是將金屬沈積在晶片表面，然後經 由高溫，藉矽化反應，形成金屬矽化物。此自行對準金屬矽 化物製程因著減去定義複層閘極結構之步驟，減去繁鎖並昂 貴的微影程序，已成爲發展的主流。但習用以自行對準金屬 矽化物製程來形成複晶矽/金屬矽化物之閘極時，會在蝕刻 源極/汲極之砂化物時造成間隙壁的損傷(spacer damage)。容 易造成閘極跟源極/汲極之間發生橋接(bridging)，電路因而 容易短路》 因此’本發明的主要目的是提供一個無橋接現象 _________3 本紙張尺度通用中國國家襟率（CNS ) A4規格（210X297公釐） (請先閱讀背由之注意事項再填寫本買) -裝· 經濟部t央標輋馬員工消費合作社印製 五、發明説明（> ) (bridging free)並具有自動對準矽化物之複晶矽/金屬矽化物 之閘極結構的製造方法。 本發明的另一目的是提供一種閘極間隙壁不受損害 (spacer damage » 本發明的另一目的是提供一種降低成本且簡化繁瑣的微 影製程之複晶矽/金屬矽化物之閘極結構的製造方法。 本發明的苒一目的是提供一種具有極低區域連線電阻和 良好的場效電晶體之臨界電壓控制能力之間極結構的製造方 法。 (―)圖示說明 圖一到圖八是本發明實施例的製程剖面示意圖。 圖一是在矽半導體基板表面形成場氧化層，定義好的複 晶矽閘極、源/汲極和間隙壁後的製程剖面圖。 圖二是沈積一層氧化層後的剖面圖。 圖三是形成一層光阻後的剖面圖。 圖四是光阻經部分顯影後的剖面圖。 圖五是複晶矽表面之氧化層被蝕刻後的剖面圖。 圖六是光阻被完全除去後的剖面圖。 圖七是沈積一層金屬之後的剖面圖。 圖八是高溫矽化步驟及反應後剩餘之金屬去除後的剖面 (二雇號說明 10半導體矽基板 12閘氧化層 11場氧化層區域 13源/汲極 本紙張尺度適用中國國家樣準（CNS ) Α4規七 ( 210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) -?τ M濟部中央嘌准苟員工消资合作社印製 417H9 五、發明说明（\L ) 14間隙壁 15複晶矽層 16氧化層 17光阻 18金屬層 19金屬矽化物層 本發明揭露之複晶矽/金屬矽化物的複層閘極結構的金 屬矽化物是指矽化鈦(TiSix)和矽化鈷(C〇Six)。以下本發明以 鈦所形成的矽化物爲實施例，鈷所形成的矽化物爲替代實施 例。 煩請參閱圖一，本發明之起始材料爲半導體的基板10， 是利用具有較低表面缺陷密度之晶格方向(100)的P型半導體 矽基板。接著，於形成隔離用的場氧化層Η之後，再連續形 成閘氧化層12、複晶矽層15和間隙壁14，並進行源極和汲 極 13 的離子植入(ion implantation)。 接下來的步驟，爲本發明之重點所在，首先形成一氧化 層16於整個晶片表面，如圖二所示》此氧化層是利用低壓化 學氣相沈積(LPCVD)形成，其厚度介於300至4006之間。 請參閱圖三，於氧化層16沈積後，形成一層光阻17於 氧化層上，此光阻的厚度爲1000到1300A 此光阻不經過曝 光(exposure)，直接顯影(development)»因爲曝光後，顯影速 度非常快，難以控制》所以本發明使光阻不經曝光，而直接 顯影，就能把顯影速度控制在380〜420 A/min之間，使顯 影劑裡的TMAH成分能緩慢地和光阻作用，直到複晶矽層15 上方的氧化層16已完全外露之後，顯影步驟才停止(如圖 四）。 接著，我們就能將複晶矽層上方的氧化層以濕式蝕刻 5 本紙涑尺度適用中國國家梯準（CNS ) A4規格（210X297公釐） , - /13 (請先閱讀背面之注意事項再填寫本頁) -ΦB7 B7 Ministry of Economic Affairs_Industrial Consumer Cooperation of Yangpu Leather Bureau Du Yinzhong 5. Description of Invention (/) Detailed description: The present invention is a method for manufacturing gates of integrated circuits, especially for the formation of polycrystalline silicon / metal silicide Fabrication of gate structure of objects. In recent years, due to advances in lithography and plasma etching technology, the accumulation density of integrated circuits has increased dramatically, which has significantly improved the quality and cost of electronic products. At present, the most widely used integrated circuit is the field effect transistor volume body circuit (FET 1C), whether it is dynamic random access memory (DRAM), static random access memory (SRAM), special application integrated circuit (ASIC) and microprocessor chip (CPU) and other products are related to field effect transistors. Generally, the field-effect transistor uses polysilicon as the gate of the field-effect transistor. However, even after doping, the poly-crystalline silicon still has a peak of 500 ~ 1200 A Ω-cm. Resistance, which causes the resistance and capacitance of the transistor connection to increase (RC constant), which slows down the circuit. One method to improve the connection resistance value is to replace the polycrystalline silicon with a metal with a low resistance value as the gate of the field effect transistor. However, subsequent high temperature processes such as high temperature oxide (HTO) deposition Metals are not allowed to be used as gates of field effect transistors in place of polycrystalline silicon. Another method to improve the resistance of the area connection is to replace the single-layer polycrystalline silicon with a multi-crystalline silicon / metal silicide multilayer structure as the gate of the field effect transistor. The metal silicide of the multi-layered silicon / metal silicide multilayer structure provides lower area connection resistance, while the multi-layered silicon of the multi-layered silicon / metal silicide multilayer structure is like a conventional multi-crystal Like a silicon gate, it provides a good threshold voltage control capability of a field effect transistor. Although, the polycrystalline silicon / metal silicide multilayer structure is used to replace the polycrystalline silicon as the field-effect power 2 (Please read the precautions on the back before filling this page), 1r This paper size applies Chinese National Standard (CNS) A4 Specification (210 X 297 mm) 417179 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (= _) The gate of the crystal can improve the connection resistance of the transistor region, but it will generate new in the actual process The problem. The conventional way to form a polycrystalline silicon / tungsten silicide multilayer structure is to deposit tungsten hexafluoride (WF6) and silicon methane (SiH4) on the wafer surface by low pressure chemical vapor deposition (LPCVD). The problems often encountered in the formation of tungsten silicide are the easy-to-rise after the annealing and the diffusion of the fluorine atoms in the reaction through the underlying polycrystalline silicon, causing the breakdown voltage of the device to decrease. Titanium silicide (TiSix) and cobalt silicide (CoSix) have the lowest resistivity (10 to 15 # Ω-cm) among metal silicides (X = 2 to 2.6), both of which are deposited by a lithography process, or It is deposited by a self-aligned silicide process. The difficulty in defining the polycrystalline silicon / titanium silicide gate structure by the lithography process is that when the polycrystalline silicon is etched, the titanium silicide will be eroded by the chlorine-based etching gas (Cl-based chemistry), making the line width very large. Difficult to control. Cobalt silicide is difficult to etch due to the lack of an etching reaction gas that can generate volatile compounds. The process of self-aligning metal silicide is to deposit metal on the surface of the wafer, and then form the metal silicide through the silicidation reaction at high temperature. This self-aligned metal silicide process has become the mainstream of development by subtracting the steps of defining the multi-layer gate structure and subtracting the complicated and expensive lithography procedures. However, it is customary to align the metal silicide process to form the gate of the polycrystalline silicon / metal silicide, which will cause spacer damage when etching the source / drain sand. It is easy to cause bridging between the gate and source / drain, and the circuit is easily short-circuited. Therefore, 'The main purpose of the present invention is to provide a bridge-free phenomenon _________3 This paper standard is generally China National Ratio (CNS) A4 Specifications (210X297 mm) (Please read the precautions before filling out this purchase)-Installed · Printed by the Ministry of Economic Affairs, Central Standards, and Printed by the Consumer Consumption Cooperative V. Description of Invention (>) (bridging free) and automatic Method for fabricating gate structure of polysilicon / metal silicide aligned silicide. Another object of the present invention is to provide a gate spacer without damage. Another object of the present invention is to provide a polycrystalline silicon / metal silicide gate structure that reduces cost and simplifies tedious photolithography processes. It is an object of the present invention to provide a method for manufacturing a pole structure having extremely low area connection resistance and good threshold voltage control ability of a field-effect transistor. Eight is a schematic cross-sectional view of the manufacturing process of the embodiment of the present invention. Figure 1 is a cross-sectional view of the process after a field oxide layer is formed on the surface of a silicon semiconductor substrate, and a defined polycrystalline silicon gate, source / drain, and spacer are defined. A cross-sectional view after an oxide layer. Figure 3 is a cross-sectional view after a photoresist is formed. Figure 4 is a cross-sectional view after a partial development of the photoresist. Figure 5 is a cross-sectional view after the oxide layer on the surface of the polycrystalline silicon is etched. Figure 6 is a cross-sectional view after the photoresist has been completely removed. Figure 7 is a cross-sectional view after a layer of metal is deposited. Figure 8 is a cross-section after the high-temperature silicidation step and the remaining metal after the reaction is removed 10 Semiconductor silicon substrate 12 Gate oxide layer 11 Field oxide layer area 13 Source / drain This paper size is applicable to China National Standard (CNS) A4 Rule VII (210 X 297 mm) (Please read the precautions on the back before filling in this Page)-? Τ M Printed by the Central Ministry of Economic Affairs, Zhungou Staff Consumer Cooperative, 417H9 V. Description of the invention (\ L) 14 Spacer wall 15 Polycrystalline silicon layer 16 Oxide layer 17 Photoresist 18 Metal layer 19 Metal silicide layer The metal silicide of the multi-layered silicon / metal silicide multi-layer gate structure disclosed in the invention refers to titanium silicide (TiSix) and cobalt silicide (CoSix). The present invention takes the silicide formed by titanium as an example. The silicide formed by cobalt is an alternative embodiment. Please refer to FIG. 1. The starting material of the present invention is a semiconductor substrate 10, which is a P-type semiconductor silicon substrate with a lattice direction (100) having a lower surface defect density. Next, after forming a field oxide layer 隔离 for isolation, a gate oxide layer 12, a polycrystalline silicon layer 15 and a spacer 14 are successively formed, and ion implantation of the source and drain electrodes 13 is performed. The steps are the focus of this invention. An oxide layer 16 is first formed on the entire wafer surface, as shown in Figure 2. "This oxide layer is formed by low pressure chemical vapor deposition (LPCVD), and its thickness is between 300 and 4006. Please refer to Figure 3, on the oxide layer After the deposition of 16, a photoresist is formed on the oxide layer. The thickness of the photoresist is 1000 to 1300A. This photoresist is developed directly without exposure »because the development speed is very fast after exposure and it is difficult to control 》 The present invention enables the photoresist to be directly developed without exposure, and the development speed can be controlled between 380 and 420 A / min, so that the TMAH component in the developer can slowly interact with the photoresist until the polycrystalline silicon layer The development step is stopped after the oxide layer 16 above 15 has been completely exposed (see Figure 4). Then, we can wet etch the oxide layer above the polycrystalline silicon layer. The paper size is suitable for China National Standard (CNS) A4 specification (210X297 mm),-/ 13 (Please read the precautions on the back first) (Fill in this page) -Φ
I I 經濟部中央樣隼局員二消費合作杜印製 五、發明説明（ί ) (wet etching)的方法去除(如圖五）。濕式餓刻是利用薄膜與特 定溶液間所進行的化學反應，來去除來被光阻覆蓋的薄膜。 它的優點是製程單純，產量速度(throughput)快以及低成本 (cost down)。本實施例使用氫氟酸(Hydrofluoric Acid)與氟化 氨(Ammonium Fluoride)的混合溶液來做氧化層16的触刻 液。蝕刻的反應式如下：I I Member of the Central Sample Bureau of the Ministry of Economic Affairs 2 Duo Printing of Consumption Cooperation V. Removal of Wet Etching (Figure 5). Wet engraving is the use of a chemical reaction between the film and a specific solution to remove the film covered by the photoresist. Its advantages are simple process, fast throughput and cost down. In this embodiment, a mixed solution of Hydrofluoric Acid and Ammonium Fluoride is used as the etching solution for the oxide layer 16. The etching reaction is as follows:
Si02(s) + 6HF(aq) - H2(g) + SiF6(g) + 2H20(g) 加入氟化氨的目的是做爲氫氟酸的緩衝劑(Buffer Agent)，以補充氟離子在溶液中因蝕刻反應的消耗 (depletion)〇 當複晶矽層15上方的氧化層經濕式蝕刻去除後，使剩餘 的光阻經由曝光和顯影而被完全剝除(如圖六），此時留在間 隙壁兩側旁的氧化層16A可以增加間隙壁的有效厚度，避免 閘極和源極/汲極之間發生橋接現象而造成短路(bridging short)。 接著厚度約在200到1000 ^的金屬鈦，將以磁控DC濺 鍍(Magnetron DC Sputtering)的方式，如圖七所示地沈積在整 個晶片的表面，包括氧化層和複晶矽。然後使整個晶片在氮 氣的環境中，加熱到600到800 °C ’進行快速熱製程(rapid thermal process ; RTP)，快速熱製程是在短時間內加高溫的 熱製程，可以使金屬矽化物成核(nucleation)和成長(growth) 爲高導電率的相態(high conductivity phase)。本實例有2階段 的快速熱製程，首先溫度範圍爲620到680 °C ’生成C49 之矽化鈦，反應式如下： 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公^ (請先閲讀背面之注意事項再填寫本頁) 訂 A 1. _6_ 經濟部中史墚隼局員工消費合作社印«. ^17 17 9 at B7 五、發明説明（/-) Ti + 2Si — TiSi2 (C-49) 由於矽化反應只會發生在鈦與複晶矽接觸的表，至於其 它各處，如源極/汲極表面因留有一氧化層，無法發生矽化 反應；於是反應剩餘或未反應的欽可藉簡單的濕式蝕刻以氧 (Ammonium)去除，無須任何光罩和後續複雜的微影製程，這 是本發明之重要特色和成就" 接著再進行第二次的快速熱製程，溫度提高至750 °C〜 900 °C，將CM9之矽化鈦進一步轉化爲更穩定(reliable)，電 阻率更低的C-54矽化鈦，反應式如下： TiSi2(C-49卜 TiSi2(C-54) 其中C-49、C-54指不同相的矽化鈦，但C-49矽化鈦的 電阻率比C-54矽化鈦的電阻率高了 3至4倍。 本發明之替代實施例爲形成矽化鈷之金屬矽化物於複晶 矽上方。快速熱製程亦以二階段完成，第一階段溫度在400 °C到500°C之間，反應如下： Co + Si — CoSi 第二階段的快速熱製程溫度則調高至650 °C到750 °C之 間，反應式如下： CoSi + Si — CoSi2 本發明在形成金屬矽化物層於原閘極之複晶矽層上方而 構成一複晶矽/金屬矽化物之閘極結構時，無須任何光罩和 後續的微影步驟，大大地簡化製程且節省成本；並且濕式蝕 刻不會造成間隙壁的損傷，而留在間隙壁兩側旁的氧化層作 爲有效間隙壁(effective spacer)進一步地保護間隙壁，以避免 _7_ 本紙張尺度適用中國固家標準（CNS ) A4規格（2IOX 297公釐） (請先閱讀背面之注意事項再填寫本頁)Si02 (s) + 6HF (aq)-H2 (g) + SiF6 (g) + 2H20 (g) The purpose of adding ammonium fluoride is to act as a buffer agent for hydrofluoric acid to supplement fluoride ion in the solution. Depletion due to the etching reaction. After the oxide layer above the polycrystalline silicon layer 15 is removed by wet etching, the remaining photoresist is completely stripped through exposure and development (see Figure 6). The oxide layers 16A on both sides of the gap wall can increase the effective thickness of the gap wall to avoid bridging shorts caused by bridging between the gate and the source / drain. Next, titanium metal with a thickness of about 200 to 1000 Å will be deposited on the surface of the entire wafer, including an oxide layer and polycrystalline silicon, by means of Magnetron DC Sputtering, as shown in FIG. 7. Then, the whole wafer is heated to 600 to 800 ° C in a nitrogen environment. The rapid thermal process (RTP) is performed. The rapid thermal process is a thermal process in which high temperature is added in a short time, which can make the metal silicide into Nucleation and growth are high conductivity phases. This example has a two-stage rapid thermal process. First, the temperature range is 620 to 680 ° C. Titanium silicide with C49 is produced. The reaction formula is as follows: The paper size is applicable to China National Standard (CNS) A4 (210X297) ^ (Please read first Note on the back, please fill out this page again) Order A 1. _6_ Printed by the Consumers' Cooperatives of the China History Bureau, Ministry of Economic Affairs ^. 17 17 9 at B7 V. Description of Invention (/-) Ti + 2Si — TiSi2 (C-49 ) Because the silicidation reaction only occurs on the surface where the titanium is in contact with the polycrystalline silicon, as for other places, such as the source / drain surface, there is an oxide layer, so the silicidation reaction cannot occur; so the remaining or unreacted reaction can be borrowed. Simple wet etching removes with oxygen (Ammonium) without any photomask and subsequent complicated lithography process. This is an important feature and achievement of the present invention. &Quot; Then a second rapid thermal process is performed, and the temperature is increased to 750. ° C ~ 900 ° C, the titanium silicide of CM9 is further transformed into a more stable (lower resistivity) C-54 titanium silicide, the reaction formula is as follows: TiSi2 (C-49, TiSi2 (C-54) where C -49, C-54 refer to different phases of titanium silicide, but C-49 is silicified The resistivity is 3 to 4 times higher than that of C-54 titanium silicide. An alternative embodiment of the present invention is to form a metal silicide of cobalt silicide on the polycrystalline silicon. The rapid thermal process is also completed in two stages, the first The stage temperature is between 400 ° C and 500 ° C. The reaction is as follows: Co + Si — CoSi The temperature of the rapid thermal process in the second stage is raised to between 650 ° C and 750 ° C. The reaction formula is as follows: CoSi + Si — CoSi2 In the present invention, when a metal silicide layer is formed on the polycrystalline silicon layer of the original gate to form a polycrystalline silicon / metal silicide gate structure, no photomask and subsequent lithography steps are required, which greatly simplifies the process. Process and save costs; and wet etching will not cause damage to the spacer, and the oxide layers left on both sides of the spacer serve as effective spacers to further protect the spacer to avoid _7_ This paper size applies China Gujia Standard (CNS) A4 specification (2IOX 297 mm) (Please read the precautions on the back before filling this page)
B7 ,經濟部中央螵龙馬員工消費合作社印製 五、發明説明（1 ) 橋接現象。此時一具有極低區域連線電阻和良好的場效電晶 體之臨界電壓控制能力的複晶矽/矽化鈦閘極結搆，於焉形 成。 本發明之替代實施例複晶矽/矽化鈷之閘極結構，除了 在快速熱製程中歷經不同的溫度，其餘製程皆同於以上所詳 述之複晶矽/矽化鈷之閘極結構的實施例。 8 (請先閡讀背面之注意事項再填寫本頁)B7, printed by the Central Longmao Employee Consumer Cooperative of the Ministry of Economic Affairs 5. Description of the invention (1) Bridging phenomenon. At this time, a polycrystalline silicon / titanium silicide gate structure with extremely low area connection resistance and good threshold voltage control ability of the field-effect electric crystal is formed. The gate structure of the polycrystalline silicon / cobalt silicide according to the alternative embodiment of the present invention is the same as the implementation of the gate structure of the polycrystalline silicon / cobalt silicide except that it undergoes different temperatures in the rapid thermal process. example. 8 (Please read the notes on the back before filling in this page)
、1T 線丨！ 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）, 1T line 丨! This paper size applies to China National Standard (CNS) Α4 specification (210X297 mm)