TW416190B - Digital receiving device - Google Patents
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- TW416190B TW416190B TW088104222A TW88104222A TW416190B TW 416190 B TW416190 B TW 416190B TW 088104222 A TW088104222 A TW 088104222A TW 88104222 A TW88104222 A TW 88104222A TW 416190 B TW416190 B TW 416190B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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Abstract
Description
416190 五、發明說明（l) ' -- 本發明是有關於-種接收裝置，且特別是有關於 數位接收裝置’其可以接收單匯流排的差動信 依 收複數匯流排的差動信號，並迅速得到其邏輯值。_人接 在現今的半導體電路中（如動態隨機存取記憶 以接收匯流排信號的數位接收裝置通常是由反相電路用 (Inverter)或緩衝電路（BuHer)所構成。在這種數位 裝置中，只要匯流排信號的電壓高於或低於某既定 (Threshold)，反相電路或緩衝電路便會輪出對應的 值（如Η或L)’進而達到資料回復的效果。另外，這 接收裝置亦具有阻抗匹配的效果，可使匯流排信號不致因 欲連接電路的輸入阻抗過小而產生不必要的失真 (Distortion) ° 不過，利用反相電路或緩衝電路所構成的數位接收裝 置卻有延遲時間（Delay)過長及信號擺幅（Swing)過大的問 題因此郤分人士便改用類比電路（如比較器）以達成數 位接收裝置。利用類比電路（如比較器）所構成的數位接收 裝置較利用反相電路或緩衝電路所構成的數位接收裝置具 有更短的延遲時間’但缺點是需要偏壓（Bi ) = 電源，且對雜訊的免役力亦相當低。 有鑑於此，本發明的主要目的便是提供一種數位接收 裝置’其採用類比式差動放大器以達成數位接收裝置，因 此延遲時間較利用反相電路或緩衝電路所構成的數位接收 裝置更短β 本發明的另一個目的就是提供一種數位接收裝置，其 ^pi mmt 第4頁 416190 五、發明說明（2) 採用電源控制手段以控制複數匯流排信號的接收，且可以 避免匯流排衝突現象（Conflict)。 本發明的又一個目的就是提供一種數位接收裝置，其 採用電源控制手段以控制複數匯流排信號的接收，因此總 體電力消耗亦可以有效地降低。 本發明的再一個目的就是提供一種數位接收裝置，其 採用差動信號的放大以判斷匯流排信號的邏輯值，因此不 需要偏壓且對雜訊的敏感度亦相當低。 為達上述及其他目的，本發明乃提供一種數位接收裝 置，用以接收匯流排的差動信號。這種數位接收襞置是由 差動放大器、輸入開關裝置、電源開關裝置所構成。其 中，輸入開關裝置連接於差動放大器的輸入端及差動信號 之間，並在數位接收裝置進行接收時導通既定時間長度， 藉以傳輸，動信號至差動放大器。而電源開關裝置則連接 差動放大器的電源端，並在輸入開關裝置導通既定時間長 度後導通，藉以由差動放大器放大差動信號以得到對應的 邏輯值。 在思種數位接收裝置中，輸入開關裝置及電源開關裝 置均可以由傳輸閘構成。 =外，本發明亦提供一種數位接收裝置，用以接收複 ^匯流排之差動信號。這種數位接收裝置是由差動放大 伽、數個輸入開關裝置、電源開關裝置所構成。其中，每 2輸入開關裝置分別連接於差動放大器的輸入端及每個匯 叫排的差動信號之間，並在數位接收裝置進行接收時導通416190 V. Description of the invention (l) '-The present invention relates to a receiving device, and in particular to a digital receiving device, which can receive differential signals from a single bus and differential signals from multiple buses, And quickly get its logical value. _People are connected to today's semiconductor circuits (such as digital random access memory to receive bus signals. Digital receiving devices are usually composed of inverter circuits or buffer circuits (BuHer). In such digital devices As long as the voltage of the bus signal is higher or lower than a certain threshold, the inverting circuit or buffer circuit will rotate the corresponding value (such as Η or L) 'to achieve the effect of data recovery. In addition, this receiving device It also has the effect of impedance matching, which can prevent the bus signal from causing unnecessary distortion due to the input impedance of the circuit to be connected being too small. However, the digital receiving device composed of an inverting circuit or a buffer circuit has a delay time. (Delay) is too long and the signal swing (Swing) is too large, so some people use analog circuits (such as comparators) to achieve digital receiving devices. Digital receiving devices using analog circuits (such as comparators) A digital receiving device using an inverting circuit or a buffer circuit has a shorter delay time ', but the disadvantage is that it requires a bias voltage (Bi) = power supply, In view of this, the main object of the present invention is to provide a digital receiving device 'which uses an analog differential amplifier to achieve the digital receiving device, so the delay time is more than using an inverting circuit or a buffer Digital receiving device constructed by circuit is shorter β Another object of the present invention is to provide a digital receiving device, which ^ pi mmt page 4 416190 V. Description of the invention (2) Use power control means to control the reception of complex bus signals It is also possible to avoid a bus conflict. Another object of the present invention is to provide a digital receiving device that uses a power control method to control the reception of a plurality of bus signals, so the overall power consumption can also be effectively reduced. Another object of the invention is to provide a digital receiving device that uses the amplification of a differential signal to determine the logic value of the bus signal, so no bias voltage is needed and the sensitivity to noise is also relatively low. To achieve the above and other objectives The present invention provides a digital receiving device for receiving a bus This type of digital receiving device is composed of a differential amplifier, an input switching device, and a power switching device. Among them, the input switching device is connected between the input terminal of the differential amplifier and the differential signal, and the digital receiving device When receiving, it is turned on for a predetermined length of time to transmit the dynamic signal to the differential amplifier. The power switching device is connected to the power terminal of the differential amplifier and is turned on after the input switching device is turned on for a predetermined length of time, so that the differential amplifier amplifies the difference. To obtain the corresponding logic value. In thinking of the digital receiving device, both the input switching device and the power switching device can be composed of transmission gates. In addition, the present invention also provides a digital receiving device for receiving a complex bus. This digital receiving device is composed of a differential amplifier, several input switching devices, and a power switching device. Among them, every 2 input switching device is respectively connected between the input terminal of the differential amplifier and the differential signal of each bus bar, and is turned on when the digital receiving device is receiving.
416190 五、發明說明（3^ ~ ' --- 每個差動信號傳輸至差動放大器。 二：η:則連接差動放大器的電源端，並在任何輪 既定時間長度後導通，藉以由差動放大器 ： '動彳5號放大，並得到對應的邏輯值。 二讓：發明之上述和其他㈣、特徵、和優點能更明 顯=，Τ文特舉一較佳實施例’並配合所附圖 細說明如下： 圖式說明 第1圖係本發明數位接收裝置的方塊圖； ㈠本發明接收單匯流排的差動信號的數位接收 裝置的電路圖；以及 本發明接收複數匯流排的差純號的數位接 收裝置的電路圖。 實施例 —明參考-第1圖，此為本發明數位接收裝置的方塊圖。 置圖2。所示=立接收裝置是由差動放大器10'輸入開 關裝置20、電源開關裝置30所構成。輸入開關裝置2〇連接 於差動放大器1〇的輸入端及欲接收的差動信號¥ 圖所示的正輸入信號η及負輸入信號ν_)之間。電 J置⑽則連接於差動放大器10的電源端及外部 ； 禾不）之間。 當數位接收裝 20首先會導通預定 放大器10的輸入端 置欲接收差動信號Vi 時間長度，藉以將差 。此時’電源開關裝 時，輸入開關裝置 動信號Vi送至差動 置3 0仍處於開路狀416190 V. Description of the invention (3 ^ ~ '--- Each differential signal is transmitted to the differential amplifier. Two: η: then the power terminal of the differential amplifier is connected and turned on after a predetermined length of time in any round, so that the differential Dynamic amplifier: 'Dynamic amplifier No. 5 is amplified, and the corresponding logic value is obtained. Second let: the above and other inventions, features, and advantages of the invention can be more obvious =, Twenty-one specific examples are provided and cooperated with the attached The detailed description of the figure is as follows: Figure 1 illustrates the block diagram of the digital receiving device of the present invention; 的 circuit diagram of the digital receiving device of the present invention that receives a single bus differential signal; and the differential number of the complex receiving bus of the present invention The circuit diagram of the digital receiving device is shown in Fig. 2. This is a block diagram of the digital receiving device according to the present invention. Refer to Figure 1. Shown in Figure 2. The = receiving device is a switching device 20, input from the differential amplifier 10 ', The power switching device 30 is composed of an input switching device 20 connected between an input terminal of the differential amplifier 10 and a differential signal to be received (positive input signal η and negative input signal ν_) shown in the figure. Electricity J is connected between the power supply terminal of the differential amplifier 10 and the outside; When the digital receiving device 20 first turns on the input terminal of the predetermined amplifier 10, it wants to receive the differential signal Vi for a length of time, so as to reduce the difference. At this time, when the power switch is installed, the input switching device motion signal Vi is sent to the differential position 30, which is still in an open circuit state.
r41619Q ~----- 五、發明說明（4) 態，因此差動放大器1 〇並不會進行任何動作。待輸入開關 裝置2 0導通預定時間長度後’電源開關裝·置3 0才會導通， 使差動放大器1 〇可以將輸入端的差動信號V i放大，進而得 到對應的邏輯值。 在這個實施例中，預定時間長度必須大於輸入信號V i 在狀態轉換時，正輸入信號V+及負輸入信號v-交會並產生 足夠電壓差所需要的時間長度。也就是，當差動信號V i由 邏輯H(L)轉換至邏輯L(H)時，預定時間長度應當大於下降 (上升）的正差動信號V+與上升（下降）的負差動信號交會， 且正差動信號V+小於（大於）負差動信號V -達足夠電壓差所 需要的時間。足夠電壓差則是指差動放大器1 〇所能辨別的 電壓差。 與本實施例比較’在利用反相電路或緩衝電路所構成 的數位接收裝置中’當匯流排信號由邏輯H ( L)轉換至邏輯 l(h)時’反相電路或緩衝電路必須在匯流排信號降低（上 升）至標準規格的邏輯L(u)之後，方能輸出對應的邏輯 值。因此’在匯流排信號的狀態轉換期間，反相電路及緩 衝電路的輸出仍然維持不變，因此會有延遲時間過長的問 題。 „ 、相反地’本實施例的數位接收裝置則是採用差動放大 S以縮短延遲時間。由於差動放大器10可以迅速放大正輸 0 3差動信號V+)及負輸入端（負差動信號V-）間的極小 ^ 〇. 數"^)’因此差動信號Vi對應的邏輯值可在正差動 W +及負差動信號v _尚未完全轉換至目的狀態時便提早r41619Q ~ ----- 5. Explanation of the invention (4) state, so the differential amplifier 10 will not perform any action. After the input switch device 20 is turned on for a predetermined length of time, the power switch device 30 will be turned on, so that the differential amplifier 10 can amplify the differential signal V i at the input terminal and obtain a corresponding logic value. In this embodiment, the predetermined time length must be longer than the time required for the positive signal V + and the negative signal v- to intersect and generate a sufficient voltage difference when the input signal V i changes state. That is, when the differential signal Vi is changed from logic H (L) to logic L (H), the predetermined time length should be greater than the positive differential signal V + falling (rising) and the negative differential signal rising (falling) meet And the time required for the positive differential signal V + to be less than (greater than) the negative differential signal V- to reach a sufficient voltage difference. Sufficient voltage difference refers to the voltage difference that the differential amplifier 10 can discern. Compared with this embodiment, 'in a digital receiving device using an inverting circuit or a buffer circuit', when the bus signal is converted from logic H (L) to logic l (h), the inverting circuit or buffer circuit must be in the bus After the row signal is reduced (rised) to the standard logic L (u), the corresponding logic value can be output. Therefore, during the state transition of the bus signal, the output of the inverter circuit and the buffer circuit remains unchanged, so there is a problem that the delay time is too long. „Conversely, the digital receiving device of this embodiment uses the differential amplifier S to shorten the delay time. Because the differential amplifier 10 can quickly amplify the positive input 0 differential signal V +) and the negative input terminal (negative differential signal The minimum value between V-) ^ 〇. The number " ^) 'Therefore, the logic value corresponding to the differential signal Vi can be early when the positive differential W + and the negative differential signal v _ have not yet completely switched to the destination state.
IIII
第7頁 416190 五、發明說明（5) 讀出，使延遲時間過長的問題獲得解決。另外，應用這種 數位接收裝置’差動信號V i的擺幅亦可以縮小（如2 〇 〇 m v) ’使匯流排或其他電路裝置的負載減輕。 第2 A圖是本發明接收單匯流排的差動信號的數位接收 裝置的電路圖；第2 B圖則是本發明接收複數匯流排的差動 信號的數位接收裝置的電路圖。 在第2A圖的例子中’數位接收裝置是由差動放大器 1 〇、傳輸閘C1〜C 2、開關S1 ~ S 2所構成。傳輸閘C1連接於正 差動信號V+及差動放大器1〇的正輸入端之間。傳輸閘㈡連 接於負差動信號V-及差動放大器1 〇的負輸入端之間。開關 S1連接於正電源Vss及差動放大器1 〇的正電源端之間。開 關S2連接於負電源Vdd及差動放大器1 〇的負電源端之間。 差動放大器10的輸出端則連接作為差動信號^(包括正差 動L號V+及負差動信號V-)對應的邏輯值◊傳輸閘ci〜C2是 由控制信號CL1及其反相信號CL1，控制開關。開關S1〜S2則 是由控制信號SEL控制開關。 當數位接收裝置欲接收差動信號v i時，控制信號CL1 首先會產生預定時間長度的脈衝，並與其反相信號CL〗，共 同導通傳輸閘C1-C2，藉以將差動信號Vi (包括正差動信號 v+及負差動信號V-)分別傳輸至差動放大器10的正輸入端 及負輸入端。此時’由於開關S1〜S2仍舊處於開路狀態， 因此外部電源並無法供應至差動放大器10，且差動放大器 10亦不會進行任何放大動作。 待傳輸閘C卜C2重新關閉後，控制信號SEL會產生脈衝Page 7 416190 V. Description of the invention (5) Read out, so that the problem of too long delay time can be solved. In addition, by using such a digital receiving device, the swing of the differential signal Vi can be reduced (eg, 2000 mv), and the load of the bus or other circuit devices can be reduced. Fig. 2A is a circuit diagram of a digital receiving device for receiving a differential signal of a single bus according to the present invention; Fig. 2B is a circuit diagram of a digital receiving device for receiving a differential signal of a complex bus according to the present invention. In the example of FIG. 2A, the 'digital receiving device' is composed of a differential amplifier 10, transmission gates C1 to C2, and switches S1 to S2. The transmission gate C1 is connected between the positive differential signal V + and the positive input terminal of the differential amplifier 10. The transmission gate is connected between the negative differential signal V- and the negative input terminal of the differential amplifier 10. The switch S1 is connected between the positive power supply Vss and the positive power supply terminal of the differential amplifier 10. The switch S2 is connected between the negative power supply Vdd and the negative power supply terminal of the differential amplifier 10. The output of the differential amplifier 10 is connected to a logic value corresponding to a differential signal ^ (including a positive differential L number V + and a negative differential signal V-). The transmission gates ci ~ C2 are controlled by the control signal CL1 and its inverted signal. CL1, control switch. The switches S1 to S2 are controlled by a control signal SEL. When the digital receiving device wants to receive the differential signal vi, the control signal CL1 first generates a pulse of a predetermined length of time, and together with its inverted signal CL, the transmission gates C1-C2 are turned on together, so that the differential signal Vi (including the positive difference) The dynamic signal v + and the negative differential signal V-) are transmitted to the positive input terminal and the negative input terminal of the differential amplifier 10, respectively. At this time ', since the switches S1 to S2 are still open, the external power cannot be supplied to the differential amplifier 10, and the differential amplifier 10 does not perform any amplification operation. After the transmission gates C2 and C2 are closed again, the control signal SEL will generate a pulse.
第8頁 416190 五、發明說明（6) 以供應外部電源至差動放大器1 〇的電源端。如此，差動放 大器10便可以放大正輸入端（正差動信號及負輸入端 (負差動信號V -)的電壓差，藉以作為差動信號v i對應的邏 輯值。 在這個例子中’傳輸閘C1〜C2的控制信號CL1 ' CL1，可 以是接收匯流排信號的指示信號。開關Si〜S2則可由電晶 體構成’其控制可由上述指示信號延遲預定時間長度以得 到。 在第2B圖的例子中’數位接收裝置是由差動放大器 1 〇、傳輸閘C1〜C 4、開關s 1 ~ S 2所構成。傳輸閘c丨連接於第 一匯流排的正差動信號V1+及差動放大器1〇的正輸入端之 間。傳輪閘C 2連接於第一匯流排的負差動信號v丨_及差動 放大器1 0的負輸入端之間。傳輸閘㈡連接於第二匯流排的 正差動信號V2+及差動放大器1 〇的正輸入端之間。傳輪閘 C4連接於第二匯流排的負差動信號V2—及差動放大器1〇的 負輸入端之間。開關S1連接於正電源vss及差動放大器1〇 的正電源端之間。開關S2連接於負電源Vdd及差動放大器 10的負電源端之間。差動放大器1〇的輸出端則連接作為差 動信號VI、V2(包括正差動信號V1+、V2 +及負差動信號 VI-、V2-)對應的邏輯值。傳輸閘以彳？是由控制信號cu 及其反相#號C L1，控制開關。傳輸閘c 3 ~ C 4是由控制信號 CL2及其反相信號CL2,控制開關d開關S1 ~S2則是由控制信 號SEL控制開關。Page 8 416190 V. Description of the invention (6) To supply external power to the power terminal of the differential amplifier 10. In this way, the differential amplifier 10 can amplify the voltage difference between the positive input terminal (positive differential signal and the negative input terminal (negative differential signal V-)) as the logical value corresponding to the differential signal vi. In this example, the transmission The control signals CL1 'CL1 of the gates C1 to C2 may be an instruction signal for receiving a bus signal. The switches Si to S2 may be constituted by transistors', and the control thereof may be obtained by delaying the above instruction signal for a predetermined time length. The example in FIG. 2B The medium 'digital receiving device is composed of a differential amplifier 10, transmission gates C1 to C4, and switches s1 to S2. The transmission gate c 丨 is connected to the positive differential signal V1 + of the first bus and the differential amplifier 1 〇 is connected between the positive input terminal of the transmission wheel C 2 is connected between the negative differential signal v 丨 _ of the first bus and the negative input terminal of the differential amplifier 10. The transmission gate is connected to the second bus The positive differential signal V2 + and the positive input terminal of the differential amplifier 10. The wheel brake C4 is connected between the negative differential signal V2 of the second bus bar and the negative input terminal of the differential amplifier 10. The switch S1 Connected to positive power supply vss and positive of differential amplifier 10 Between the source terminals. The switch S2 is connected between the negative power supply Vdd and the negative power supply terminal of the differential amplifier 10. The output terminal of the differential amplifier 10 is connected as the differential signals VI, V2 (including the positive differential signals V1 +, V2 + And negative differential signals VI-, V2-). The transmission gates are controlled by the control signal cu and its inverse # C L1 to control the switches. The transmission gates c 3 ~ C 4 are controlled by the control signals. CL2 and its inversion signal CL2, and the control switches d and switches S1 to S2 are controlled by the control signal SEL.
接收第一匯流排及第一匯流排Receive the first bus and the first bus
416190 五、發明說明¢7) 的差動信號VI、V2時，控制信號CL 1首先會產生預定時間 長度的脈衝’並與其反相信號CL1，共同導通傳輸閘 Cl ~C2 ’藉以將差動信號¥1 (包括正差動信號V1 +及負差動 信號V1-)分別傳輸至差動放大器1〇的正輸入端及負輸入 端。此時，由於開關Si ~S2仍處於開路狀態，因此外部電 源並無法供應至差動放大器的電源端，且差動放大器1〇 亦不會進行任何放大動作。待傳輸閘c丨〜C2重新關閉後， 控制信號SEL便會產生脈衝以供應外部電源至差動放大器 10的電源端。如此’差動放大器1〇便可以放大正輸入端 (正差動信號νι + )及負輪入端（負差動信號vl_)的電壓差， 藉以作為差動信號V1對應的邏輯值3 然後’控制信號CL 2會產生預定時間長度的脈衝，並 與其反相信號CL2’共同導通傳輸閘C3〜C4，藉以將差動信 號V2(包括正差動信號V2 +及負差動信號V2-)分別傳輸至差 動放大器10的正輸入端及負輸入端。此時，由於開關 S卜S2又處於開路狀態’因此外部電源亦無法供應至差動 放大益10的電源端，且差動放大器10亦不會進行任何放大 動作。待傳輸閘C3〜C4重新關閉後，控制信號SEL才會產生 脈衝以供應外部電源至差動放大器1 Q的電源端。如此，差 動放大器10便可以放大正輸入端（正差動信號V2 + )及負輸 入端（負差動信號V2-)的電壓差，藉以作為差動信號”對 應的邏輯值。 在这個例子中’傳輸閘C1〜C2的控制信號CL1、CL1’可 以是接收第一匯流排信號的指示信號。傳輸閘㈡彳彳的控416190 V. Description of the invention ¢ 7) When the differential signals VI and V2 are used, the control signal CL 1 first generates a pulse of a predetermined time period and then inverts the signal CL1 to jointly turn on the transmission gates Cl ~ C2 ', thereby converting the differential signal ¥ 1 (including the positive differential signal V1 + and the negative differential signal V1-) are transmitted to the positive input terminal and the negative input terminal of the differential amplifier 10, respectively. At this time, since the switches Si ~ S2 are still in the open state, the external power cannot be supplied to the power terminal of the differential amplifier, and the differential amplifier 10 will not perform any amplification operation. After the transmission gates c1- ~ C2 are closed again, the control signal SEL will generate pulses to supply external power to the power terminal of the differential amplifier 10. In this way, the differential amplifier 10 can amplify the voltage difference between the positive input terminal (positive differential signal v + +) and the negative wheel input terminal (negative differential signal vl_), and use it as the logical value 3 corresponding to the differential signal V1. The control signal CL 2 generates a pulse of a predetermined time length, and turns on the transmission gates C3 to C4 together with its inversion signal CL2 ′, so as to separate the differential signal V2 (including the positive differential signal V2 + and the negative differential signal V2-), respectively. It is transmitted to the positive input terminal and the negative input terminal of the differential amplifier 10. At this time, since the switches S2 and S2 are in the open state again, external power cannot be supplied to the power terminal of the differential amplifier 10, and the differential amplifier 10 does not perform any amplification operation. After the transmission gates C3 ~ C4 are closed again, the control signal SEL will generate pulses to supply external power to the power terminal of the differential amplifier 1 Q. In this way, the differential amplifier 10 can amplify the voltage difference between the positive input terminal (positive differential signal V2 +) and the negative input terminal (negative differential signal V2-), and use it as a logical value corresponding to the differential signal. Here In the example, 'the control signals CL1 and CL1 of the transmission gates C1 to C2' may be an instruction signal for receiving the first bus signal.
第10頁 416190Page 10 416190
五、發明說明（8) 制信號CL2、CL2’可以是接收第二匯流排信號的指示信 號。開關S1〜S 2則可由電晶體構成，其控制可由上述指示 信號延遲預定時間長度以得到。 綜上所述，本發明的數位接收裝置是採用類比式差動 放大器以達成數位接收裝置，因此延遲時間較利用反相電 路或缓衝電路所構成的數位接收裝置更短。 另外，本發明的數位接收裝置是採用電源控制手段以 控制複數匯流排信號的接收，因此可避免匯流排衝突現 象，並使總體電力消耗可以 再者’本發明的數位接 以判斷匯流排信號的邏輯值 敏感度亦相當低。 有效地降低。 收裝置是採用差動信號的玫大 ，因此不需要偏壓且對雜訊的 雖然本發明已以較佳實施例揭露如下，缺兑 限定本發日月，任何熟習此技藝者’在不脫離本發Μ以 和範圍内，當可做更動與潤飾，因此本發明之 ^精神 視後附之申請專利範圍所界定者為準。 ’、邊範圍當5. Description of the invention (8) The control signals CL2 and CL2 'may be instruction signals for receiving the second bus signal. The switches S1 to S2 can be composed of transistors, and their control can be obtained by delaying the above-mentioned instruction signal for a predetermined time. In summary, the digital receiving device of the present invention uses an analog differential amplifier to achieve the digital receiving device, so the delay time is shorter than that of a digital receiving device constructed using an inverting circuit or a buffer circuit. In addition, the digital receiving device of the present invention uses a power control method to control the reception of a plurality of bus signals, so it can avoid the phenomenon of bus conflicts and allow the overall power consumption to be further determined by the digital connection of the present invention to determine the bus signals. The logic value sensitivity is also quite low. Reduce effectively. The receiving device adopts the large signal of the differential signal, so it does not need bias and noise. Although the present invention has been disclosed in the preferred embodiment as follows, the lack of redemption limits the date and time of the issue. Anyone skilled in this art will not leave Within the scope and scope of the present invention, modifications and retouching can be done. Therefore, the spirit of the present invention is determined by the scope of the attached patent application. ’, The border range when
Claims (1)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW088104222A TW416190B (en) | 1999-03-18 | 1999-03-18 | Digital receiving device |
| US09/400,353 US6393510B1 (en) | 1999-03-18 | 1999-09-20 | Low power high-speed bus receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW088104222A TW416190B (en) | 1999-03-18 | 1999-03-18 | Digital receiving device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW416190B true TW416190B (en) | 2000-12-21 |
Family
ID=21639986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW088104222A TW416190B (en) | 1999-03-18 | 1999-03-18 | Digital receiving device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6393510B1 (en) |
| TW (1) | TW416190B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100743624B1 (en) * | 2004-12-29 | 2007-07-27 | 주식회사 하이닉스반도체 | Semiconductor with reduced power consumption |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3906248A (en) * | 1971-11-29 | 1975-09-16 | Texas Instruments Inc | Time delay circuit employing field effect transistor and differential operational amplifier |
| DE2315798C3 (en) * | 1973-03-29 | 1981-11-19 | Siemens AG, 1000 Berlin und 8000 München | Circuit for automatic frequency adjustment in radio and television receivers |
| JPS55118221A (en) * | 1979-03-06 | 1980-09-11 | Nec Corp | Comparison circuit |
| US5059829A (en) * | 1990-09-04 | 1991-10-22 | Motorola, Inc. | Logic level shifting circuit with minimal delay |
| US5332931A (en) * | 1991-06-24 | 1994-07-26 | Harris Corporation | High speed differential comparator |
| TW281828B (en) * | 1995-08-21 | 1996-07-21 | Thomson Consumer Electronics | Video differential bus receiver for audio/video interconnection |
-
1999
- 1999-03-18 TW TW088104222A patent/TW416190B/en not_active IP Right Cessation
- 1999-09-20 US US09/400,353 patent/US6393510B1/en not_active Expired - Lifetime
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| US6393510B1 (en) | 2002-05-21 |
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