416153 A7 B7 五、發明説明（I) 發明領域 本發明有關一種分隔閘(split gate)電氣可抹除可程式唯讀記憶體 (EEPROM) ’尤其是儲存多個準位電荷於分隔蘭(split gate)電氣可抹除 可程式唯讀記憶單元(EEPROM)的方法。 背景說明 隨著技術之進步，藉由自我收歛(Self Convergence)形式之寫入 (Programming)及抹除(Erasing)法’調整堆疊間(stacked gate)快閃記憶 單元的寫入(Programming)及抹除(Erasing)偏壓，可儲存多個準位電荷 於堆疊閘電氣可抹除可程式唯讀記憶單元或快閃記憶單元中。 例如，Min-hwa Chi 及 Albert Bergemont 發表之論文，Multi-level Flash/EPROM Memories: New Self convergent Programming Methods for Low voltage Applications, IEDM，P. 271, 1的5，就介紹了以低壓寫 入法儲存多個準位電荷於堆疊閘電氣可抹除可程式唯讀記億單元或 快閃記憶單元中。但是此自我收歛的方法由於寫入時電子來源的不 足，其寫入速率無法滿足快速寫入的需求。 另外，D. Montanari 等人發表之論文，Multi-Level Charge Storage in Source Side Injection Flash EEPROM, P. 80,1996 Int'l Nonvolatile Memory Technology Conference，就介紹了以源側注入 (Source-side Injection)法儲存多個準位電荷於堆疊鬧電氣可抹除可程 式唯讀記憶單元或快閃記億單元中。但此法僅僅由外加偏壓來控制寫 入之狀態故無法準確，且外加的檢查線路亦造成額外負荷。 另外，Shih-Jye Shen 等人發表之論文，Novel Self-Convergent Programming Scheme for Multi-Level P-Channel Flash Memory, IEDM, p. 287,1997，介紹了以同時(simultaneous)進行 Fowler-Nordheim(F-N) 隧穿抹除(erasing)及 Channel Hot Electron (CHE)注入寫入 097P068,87-115 本紙広尺度这用中界内孓枕今（CNS ) Λ4規格（21〇'Χ297公漦) (請先閱讀背面之注意事項再填寫本頁) 丁 416153 a? B7_五、發明説明（丄） (programming) >儲存多個準位電荷於P-通道堆疊閘電氣可抹除可程式 唯讀記憶單元或P-通道快閃記憶單元中。寫入速率太慢亦爲此一方法 應用於堆疊閘電氣可抹除可程式唯讀記憶單元最主要缺失。 前述自我收歛(Self Convergence)形式之寫入(Programming)及抹 除(Erasing)法之下，在寫入脈衝之時序(timing)及大小(amplitude)控制 較不嚴格之情形下，仍食自將多個準位電荷控制的很好 本發明之目的係針分隔閘(split gate)電氣可抹除可程式唯讀記憶 單元(EEPROM)，提供一方法，供於儲存多個準位電荷於分隔閘電氣 可抹除可程式唯讀記億單元。 本發明之方法之優點在，寫入電流(programming current)與源極或 基材偏壓關係展現非常好之線性關係(linear relationship)。相較於堆疊 閘電氣可抹除可程式唯讀記憶單元，本發明較佳的寫入效率、較佳的 防止被干擾能力，均提供此一多準位自我收歛寫入方式應用於分隔閘 (split gate)電氣可抹除可程式唯讀記億單元啊110_優越性。 圖示之簡要說明 第一圖爲一習知之分隔閘(split gate)電氣可抹除可程式唯讀記憶 單元(EEPROM)構造。 第二圖揭露本發明所採用之一系列寫入及抹除步驟。 第三(a)圖揭露第一實施例中之寫入及抹除週期之偏壓狀態。 第三(b)圖揭露第二實施例中之寫入及抹除週期之偏壓狀態。 第四(a)圖揭露第一實施例中之收歛過程。 第四(b)圖揭露第二實施例中之收歛過程。 ^^^1 —I- - Γ I ^^^1 1 ^^^1 — I — ^^^1 —tf-. 'V* (誚先閲讀背面之注項再填寫本頁) __097P068,87-113 ___ 本紙疚八度:標今（（_NS}A4d梠（210X297公费） 416153 A7 B7五、發明説明) 詳細說明 一習知之分隔閘(split gate)電氣可抹除可程式唯讀記憶單元 (EEPROM)構造揭露於第一圖中，如果要儲存兩種狀態於此電氣可抹 除可程式唯讀記憶單元時，可藉由表一之偏壓情形而達成。 寫入 抹除 讀出 v 一 Cg 2V 14V 4V Vd 0.6V ov 2V Vs 12V ov OV V一 sub ov ov ov 依照一較佳實施例，此單元以0.6微米CMOS製程建構於一 P型 井中。主要參數爲隧穿氧化物厚度約爲120A，控制閘氧化物厚度約 爲300A，源極接面深度約爲0.7微米，控制閘長度約爲0.6微米，浮 接閘長度約爲0.6微米。 如第二圖所示，本發明方法包含多個操作週期，每一操作週期包 含一個寫入操作(program)及一跟著的抹除操作(erase)。由第二圖可 知，經過多個操作週期後，浮接閘會向某一値收歛。此一收欽値會隨 著所設偏壓値之不同而不同。因此，藉由調整所設偏壓値，吾人可於 —記憶單元中儲存多個準位電荷。 參考第三(a)圖之第一實施例，一個操作週期約爲100微秒，其中 三分之二爲寫入，三分之一爲抹除。寫入時源極的偏壓値Vs固定約 爲10至12V，控制閘偏壓値Vg固定約爲1.5至5V。寫入時，位元 線偏壓Vd可採不同値Vd0,Vdl，Vd2，Vd3，而得到不同之浮接閘電 壓。一較佳實施例爲 Vd0=0,3V，Vdl^O.S1/，Vd2=0.7V, Vd3=0.9V。相 _____097P068, 87-115___ 本纸炫尺度进州屮PdKGUMM C'NS ) A4C格（210/2町公犮） (誚先閱讀背而之注意事項再楨寫本頁) 訂 A7 B7 五、發明説明) 對地，於抹除操作時控制閘被設定於約12至15V間。換言之，第一 實施例是使F-N隧穿電流保持於常値，然後藉由寫入操作時不同之汲 極電壓控制熱電子注入電流，幾個週期後隧穿電流及熱電子電流終於 達到穩定，一浮接閘電壓就因此被決定，如第四(a)圖之收歛過程所 示。 參考第三(b)圖之第二實施例，一個操作週期約爲〗00微秒，其中 三分之二爲寫入，三分之一爲抹除。寫入時源極的偏壓値Vs固定約 爲10至UV，汲極偏壓値Vd固定約爲0.1至1V，控制間偏壓値Vg 固定約爲1.5至5V。抹除時，源極以及汲極偏壓固定，控制閘偏壓 Vg可採不同値V_CgO,V_Cgl，V_cg2，V_Cg3，而得到不同之浮接閘電 壓。一較佳實施例爲 V_cg0=10V，V_cgl=l IV，V_cg2=12V， V„cg3=13V。換言之，第二實施例是使熱電子注入電流保持於常値， 然後藉由於抹除操作時不同之控制閘偏壓控制F-N隧穿電流，幾個週 期後隧穿電流及熱電子電流終於達到穩定，一浮接閘電壓就因此被決 定’如第四(b)圖之收欽過程所75。 由第四(a)及第四(b)圖可知，只需約五個週期，浮接閘電壓準位即 已收歛，可得到快速寫入之效果及目的》本發明寫入效率，即收欽至 某一特定値所需時間，與習知技術比較之結果如下表。 寫入效率: 本發明 Shih-Jye Shen 小於500微秒 大於100釐秒 __ 097PQ68, 87-1 15_____4 (請先閱讀背而之注意事項再填寫本頁) Λ^ ，1Τ416153 A7 B7 V. Description of the Invention (I) Field of the Invention The present invention relates to a split gate electrically erasable programmable read-only memory (EEPROM) 'especially storing multiple level charges in a split gate. ) Electrically erasable Programmable Read Only Memory Unit (EEPROM). Background Description With the advancement of technology, the programming and erasing of the stacked gate flash memory cells is adjusted through the programming and erasing methods of Self Convergence. Erasing bias can store multiple level charges in the stackable gate electrical erasable programmable read-only memory unit or flash memory unit. For example, the paper published by Min-hwa Chi and Albert Bergemont, Multi-level Flash / EPROM Memories: New Self convergent Programming Methods for Low voltage Applications, IEDM, P. 271, 1 introduces storage by low-voltage writing method. Multiple level charges are stored in the programmable gate erasable programmable read-only memory cell or flash memory cell. However, this self-convergent method cannot meet the requirements of fast writing due to insufficient electron sources during writing. In addition, a paper published by D. Montanari et al., Multi-Level Charge Storage in Source Side Injection Flash EEPROM, P. 80, 1996 Int'l Nonvolatile Memory Technology Conference, introduced the source-side injection method. Store multiple level charges in a stackable programmable erasable programmable read-only memory unit or flash memory unit. However, this method cannot control the state of writing only by applying an external bias voltage, and the additional inspection circuit also causes additional load. In addition, a paper published by Shih-Jye Shen et al., Novel Self-Convergent Programming Scheme for Multi-Level P-Channel Flash Memory, IEDM, p. 287, 1997, introduces the simultaneous (simultaneous) Fowler-Nordheim (FN) Tunnel erasing and Channel Hot Electron (CHE) injection and writing 097P068,87-115 This paper is used in this paper (CNS) Λ4 specification (21〇'297 mm) (Please read first Note on the back, please fill out this page again) Ding 416153 a? B7_V. Description of the invention (丄) (programming) > Store multiple level charges in the P-channel stack gate Electrically erasable programmable read-only memory unit or P-channel flash memory unit. The write rate is too slow and this method is also applied to the stack gate. The main erasable is the programmable erasable programmable read-only memory cell. Under the programming and erasing methods of the aforementioned Self Convergence form, under the circumstances that the timing and amplitude control of the write pulses are less stringent, the self-confidence Multiple level charges are well controlled. The object of the present invention is to electrically split a programmable gate read-only memory cell (EEPROM) of a split gate and provide a method for storing multiple level charges in the split gate. Electrically erasable, programmable, read-only, and record billion units. An advantage of the method of the present invention is that the programming current exhibits a very good linear relationship with the source or substrate bias relationship. Compared with the stackable gate electrically erasable and programmable read-only memory unit, the present invention has a better writing efficiency and a better ability to prevent interference, and provides a multi-level self-convergent writing method applied to the partition gate split gate) Electrically erasable programmable read-only memory of 100 million units 110_ superiority. Brief description of the diagram The first diagram is a conventional structure of an electrically erasable programmable read-only memory cell (EEPROM) of a split gate. The second figure discloses a series of writing and erasing steps used in the present invention. The third (a) figure shows the bias state of the write and erase cycles in the first embodiment. The third (b) figure reveals the bias state of the write and erase cycles in the second embodiment. The fourth (a) figure reveals the convergence process in the first embodiment. The fourth (b) figure reveals the convergence process in the second embodiment. ^^^ 1 —I--Γ I ^^^ 1 1 ^^^ 1 — I — ^^^ 1 —tf-. 'V * (诮 Please read the notes on the back before filling this page) __097P068,87- 113 ___ Octave guilt: Standard ((_NS) A4d 梠 (210X297) 416153 A7 B7 V. Description of the invention) Detailed description of a conventional split gate electrical erasable programmable read-only memory unit (EEPROM The structure is disclosed in the first figure. If two states are to be stored in this electrically erasable and programmable read-only memory cell, it can be achieved by the bias condition of Table 1. Write erase erase read v-Cg 2V 14V 4V Vd 0.6V ov 2V Vs 12V ov OV V_sub ov ov ov According to a preferred embodiment, this unit is built in a P-well using a 0.6 micron CMOS process. The main parameter is the thickness of the tunneling oxide is about 120A The thickness of the control gate oxide is about 300A, the depth of the source junction is about 0.7 microns, the length of the control gate is about 0.6 microns, and the length of the floating gate is about 0.6 microns. As shown in the second figure, the method of the present invention includes multiple Operation cycle, each operation cycle includes a write operation (program) and a subsequent erase operation (erase). After multiple operating cycles, the floating gate will converge to a certain threshold. This gain will vary with the bias voltage set. Therefore, by adjusting the bias voltage set, we can — A plurality of level charges are stored in the memory unit. Referring to the first embodiment of the third (a) diagram, an operation cycle is about 100 microseconds, two-thirds of which are written and one-third are erased. When writing, the source bias 値 Vs is fixed at about 10 to 12V, and the control gate bias 値 Vg is fixed at about 1.5 to 5V. During writing, the bit line bias Vd can be different 値 Vd0, Vdl, Vd2, Vd3 to get different floating gate voltages. A preferred embodiment is Vd0 = 0,3V, Vdl ^ O.S1 /, Vd2 = 0.7V, Vd3 = 0.9V. Phase __097P068, 87-115 ___ Scale into state (PdKGUMM C'NS) A4C grid (210/2 town hall) (诮 Read the precautions before writing this page) Order A7 B7 V. Description of the invention) To the ground, during the erasing operation The control brake is set between approximately 12 and 15V. In other words, in the first embodiment, the FN tunneling current is kept constant, and then the hot electron injection current is controlled by different drain voltages during the write operation. After a few cycles, the tunneling current and the hot electron current finally stabilize. As a result, the floating gate voltage is determined, as shown in the convergence process of Figure 4 (a). Referring to the second embodiment of the third (b) figure, an operation cycle is about 00 microseconds, of which two-thirds are writing and one-third are erasing. The source bias 値 Vs is fixed at about 10 to UV during writing, the drain bias 値 Vd is fixed at about 0.1 to 1V, and the inter-control bias 控制 Vg is fixed at about 1.5 to 5V. During erasing, the source and drain biases are fixed, and the control gate bias Vg can be different from V_CgO, V_Cgl, V_cg2, and V_Cg3 to obtain different floating gate voltages. A preferred embodiment is V_cg0 = 10V, V_cgl = l IV, V_cg2 = 12V, V „cg3 = 13V. In other words, the second embodiment is to keep the hot electron injection current constant, and then the difference is caused by the erasing operation. The control gate bias controls the FN tunneling current. After a few cycles, the tunneling current and the hot electron current finally reach stability. As a result, the floating gate voltage is determined 'as shown in Figure 4 (b). As can be seen from the fourth (a) and fourth (b) diagrams, it takes only about five cycles for the floating gate voltage level to converge, and the effect and purpose of fast writing can be obtained. The time required to reach a specific target is compared with the conventional technology as follows. Writing efficiency: Shih-Jye Shen of the present invention is less than 500 microseconds and greater than 100 centiseconds __ 097PQ68, 87-1 15_____4 (Please read first Note the other side to fill in this page) Λ ^ ， 1Τ