416102 五、發明說明Cl) 本發明是有關於半導體裝置（semiconductor device). 的製程’特別是有關於金屬氡化令導體（metai oxide semiconductor ;M0S)電晶體（transistor)之閑極電極 -(gate electrode)的形成方法。 通常’ M0S電晶體之閘極電極皆以複晶矽或非晶矽構 成’其中複晶矽例如為未摻入離子之複晶矽、摻雜η型或p 型離子的而未經回火處理複晶珍、亦可能是摻雜η型或ρ型 離子的而經過回火處理複晶矽’蝕刻上述不同的複晶梦以 形成閘極電極’必須調整不同的蚀刻條件，否則容易導致 閘極電極輪廓（prof ile)變窄、變形或是位於下方之閘極 氧化層的損壞- 有鑑於此’本發明的目的在於提供一種形成閘極電極 的方法，可廣泛地使用於各種材質之複晶矽或是非晶矽之 蚀刻。 根據上述目的本發明提供一種形成閘極電極的方法， 適用於形成有閘極氧化層的半導體基底，上述方法包括下 列步驟：（a)在上述半導體基底上依序形成一複晶矽層以 及第1罩幕層；（b)在欲形成閘極電極位置之上述第i罩幕 層上方形成第2罩幕層；（c)利用含氟氣體以蝕刻未被上述 第2軍幕層遮蔽之上述第！罩幕層以及上述複晶梦層，直到 去除σ卩刀厚度之複晶矽層為止；（d)去除上述第2罩幕層， =露=上述制殘留之罩幕層；（e)利用含氣氣體或含 溴轧體以蝕刻上述複晶矽層，直到露出閘極氧化層為止， 以形成閘極電極。416102 V. Description of the invention Cl) The present invention relates to the manufacturing process of semiconductor devices. In particular, it relates to the free electrode of a transistor of a metal oxide semiconductor (MOS) transistor. electrode). Generally, the gate electrodes of the M0S transistor are composed of polycrystalline silicon or amorphous silicon. Among them, the polycrystalline silicon is, for example, polycrystalline silicon not doped with ions, doped with n-type or p-type ions, and not tempered. Complex crystals may also be doped with η-type or ρ-type ions and tempered complex crystal silicon 'etches the above-mentioned different complex crystal dreams to form the gate electrode'. Different etching conditions must be adjusted, otherwise the gate electrode is likely to be caused The electrode profile narrows, deforms, or damages the gate oxide layer located below-in view of this, the object of the present invention is to provide a method for forming a gate electrode, which can be widely used for complex crystals of various materials. Etching of silicon or amorphous silicon. According to the foregoing object, the present invention provides a method for forming a gate electrode, which is suitable for forming a semiconductor substrate having a gate oxide layer. The method includes the following steps: (a) sequentially forming a polycrystalline silicon layer on the semiconductor substrate and a first 1 mask layer; (b) forming a second mask layer above the i-th mask layer where the gate electrode is to be formed; (c) using a fluorine-containing gas to etch the above which is not covered by the second military curtain layer Number! The mask layer and the above-mentioned polycrystalline dream layer, until the polycrystalline silicon layer with the thickness of σ trowel is removed; (d) The second mask layer is removed, = dew = the mask layer made by the above-mentioned residue; (e) using Gas or a bromine-containing rolled body to etch the above-mentioned polycrystalline silicon layer until the gate oxide layer is exposed to form a gate electrode.
第4頁 五、發明說明（2) 子之t f形成閘極電極的方法，其中複晶矽層俜夫放 摻雜離子且υΐ:回火處理之複晶矽層、咬ί 矽部分之複晶矽層。 ^為包含非晶 ，者，上述形成閘極電極 二氧;1層、氮氧碎化合物層、或是氮化=罩幕層係 光阻圖案形成閉極電極的方法’其中第2罩幕係含有碳之 其中含氟氣體係選自 其中步驟（c)複晶矽層 再者’上極電極的方法 cm構成之族群。 並且，形極電極的方法 被蝕刻的厚度介於1/2〜2/3之間。 含漠極電極的方法，其中含氣氣體係HC1 ’而 利用實施例並配合圖式以更詳細地說明本發明， 然而本發明不限於此。 圖式之簡單說明 ΐ卜5圖係根據本發明較佳實施例以形成閘極電極之 製造流程剖面圖。 符號之說明 100〜半導體基底。 102〜閘極氧化層。 104〜複晶矽層。 1 0 4 a〜含氟洗體姓刻後之複晶石夕層。Page 4 V. Description of the invention (2) Method for forming gate electrode by tf of the son, in which the polycrystalline silicon layer is doped with ions and υΐ: tempered polycrystalline silicon layer, bite-shaped polycrystalline silicon Silicon layer. ^ Including amorphous, the above-mentioned gate electrode is formed of oxygen; 1 layer, nitrogen oxide compound layer, or nitriding = method of forming a closed electrode with a photoresist pattern on the mask layer, wherein the second mask system The carbon-containing fluorine-containing gas system is selected from the group consisting of the method (cm) of step (c) the polycrystalline silicon layer and the 'upper electrode' method. Moreover, the thickness of the electrode electrode method is etched between 1/2 and 2/3. A method for containing a polar electrode, in which a gas-containing gas system HC1 'is used to explain the present invention in more detail using examples and drawings, but the present invention is not limited thereto. Brief Description of Drawings Fig. 5 is a sectional view of a manufacturing process for forming a gate electrode according to a preferred embodiment of the present invention. Explanation of symbols 100 to semiconductor substrate. 102 ~ gate oxide layer. 104 ~ polycrystalline silicon layer. 1 0 4 a ~ The polycrystalline stone layer after the engraved surname containing fluorine.
416102 五、發明說明（3) 1 0 4 b〜複晶石夕間極電極。 106~罩幕層（第1罩幕層）。 106a~含氣氣體敍刻後之罩幕層。 108〜光阻圖案（第2罩幕層）。 實施例。 以下請參照第1圖〜第5圖之製程剖面圖，其繪示根據 本發明實施例形成複晶矽閘極電極的流程剖面圖。 首先，清參照第1圖，其顯示形成有閘極氧化層1〇2的 半導體基底1 00，上述閘極氧化層丨〇2上依序形成有複晶矽 層1 04以及罩幕層1 06。上述複晶矽層丨04例如為未摻雜離 子（un-doped)之複晶矽層、利用離子植入形成之摻雜 (doped)複晶矽層而經過回火或未經過回火處理的複晶矽 層。當然亦可利用非晶石夕層（am〇rph〇us siiic〇n)取代複 晶矽層（polysilicon)。而罩幕層106例如為二氧化矽層 (silicon oxide)、氣氧化石夕化合物層（si]_icon oxy-nitride)、或是氮化石夕層（siiicon nitride)等。接 著，利用一般的微影製程（photolithography)以在後續欲 形成閘極電極之上述罩幕層1〇6表面形成光阻圖案1〇8。 接著’請參照第2圖，利用上述光阻圖案1 08為第1階 段钱刻罩幕，並且以含氟氣體為反應氣體，而施以非等向 性蝕刻步驟，直到蝕刻穿透罩幕層丨〇 6以及複晶矽層1 〇 4被 去除1 /2^έι3厚度為止，以留下含氟氣體蝕刻後之罩幕層 106a以晶矽層l〇4a。上述含氟氣體例如為CF4、C2F6、 或是等。 IHil IH1 41610 五、發明說明（4) 然後，請參照第3圖，利用乾蝕刻法或是溼蝕刻法剝 除光阻圖案108以及其他區域之側壁高分子（圖未顯示）。 此時，露出罩幕層l〇6a上表面。去除光阻圖案1〇8的原因 為，光阻圖案108為含有碳之有機物，碳的存在會加速氧 化物的反應而損及閘極氧化層。 其次，請參照第4圖，利用上述罩幕層1 06a為第2階段 之飯刻罩幕’並且以含氯氣體（例如H C1)或是含溴氣體（例 如Η B r)為反應氣體’施以非等向性蝕刻步驟，直到露出未 被罩幕層106a覆蓋的閘極氧化層為止，而形成複晶矽閘極 電極1 04b。此階段之蝕刻環境之中不含氟，實施方式為移 至另一反應室（chamber)或是將原有之反應室的含氟氣體 抽除。 最後’請參照第5圖’去除第2階段之罩幕層106a。 此實施例以複晶梦層為例，然而本發明之方法不限 於’亦可利用非晶發層取代複晶妙層。 此實施例第1階段以含氟碳氣體為蝕刻氣體，蝕刻 1 / 2〜2 / 3厚度的複晶矽層為例，然而本發明不以此範圍為 限，只要是蝕刻穿透罩幕層而未達到閘極氧化層的厚度皆 可。 本發明之特徵及效果 本發明的特徵在於利用2階段蝕刻複晶矽（非晶矽）的 方^式以構成閘極電極的方法。第j階段蝕刻過程使用含氟 (氟碳）氣體以蝕刻複晶矽層至既定厚度，然後去除第】階 段之光阻罩幕，而第2階段蝕刻過程不存在含氟氣體，而 416103 五、發明說明（5) 以含氣或溴氣體進行’並且以位於複晶矽上方之另一氧化 層等罩幕層為蝕刻罩幕。 根據本發明形成閘極電極的方法，可適用於各種複晶 矽材質的蝕刻，不需隨著材質不同，而調整不同的蝕刻條 件以形成閘極電極。因此’可避免閘極之輪廓變窄、變形 以及閘極氧化層受損的情形。 雖然本發明已以較佳實施例揭露如 限定本發明’任何熟習此項技藝者 ：：J非用以 ;和範圍"可作更動與潤L因此本=== 現後附之申凊專利範圍所界定者為準。 ·、416102 V. Description of the invention (3) 1 0 4 b ~ polycrystalline stone inter electrode. 106 ~ Cover layer (the first cover layer). 106a ~ Mask layer after engraving with gas. 108 ~ photoresist pattern (second cover layer). Examples. Hereinafter, please refer to the process cross-sectional views of FIG. 1 to FIG. 5, which are cross-sectional views illustrating a process of forming a polycrystalline silicon gate electrode according to an embodiment of the present invention. First, referring to FIG. 1, it shows a semiconductor substrate 100 having a gate oxide layer 102 formed thereon. A polycrystalline silicon layer 104 and a mask layer 106 are sequentially formed on the gate oxide layer 010. . The above-mentioned polycrystalline silicon layer 04 is, for example, an un-doped polycrystalline silicon layer, a doped polycrystalline silicon layer formed by ion implantation, and tempered or untempered Polycrystalline silicon layer. Of course, it is also possible to replace the polysilicon layer with an amorphous stone layer (ammorphus siiicon). The mask layer 106 is, for example, a silicon oxide layer, a silicon oxide compound layer (si) _icon oxy-nitride, or a siiicon nitride layer. Next, a general photolithography process is used to form a photoresist pattern 108 on the surface of the mask layer 10 which is to be subsequently formed with the gate electrode. Next, please refer to FIG. 2, using the photoresist pattern 108 as the first stage to etch the mask, and using a fluorine-containing gas as a reaction gas, perform an anisotropic etching step until the etching penetrates the mask layer. 〇〇6 and the polycrystalline silicon layer 104 are removed to a thickness of ½ ^^ 3, so as to leave the mask layer 106a etched by the fluorine-containing gas and the crystalline silicon layer 104a. The fluorine-containing gas is, for example, CF4, C2F6, or the like. IHil IH1 41610 V. Description of the invention (4) Then, referring to Fig. 3, use dry etching or wet etching to strip the photoresist pattern 108 and the sidewall polymers in other areas (not shown). At this time, the upper surface of the mask layer 106a is exposed. The reason for removing the photoresist pattern 108 is that the photoresist pattern 108 is an organic substance containing carbon, and the presence of carbon will accelerate the reaction of the oxide and damage the gate oxide layer. Secondly, please refer to FIG. 4, using the above-mentioned mask layer 106a as the second stage of the carved mask 'and using a chlorine-containing gas (such as H C1) or a bromine-containing gas (such as ΗB r) as the reaction gas' An anisotropic etching step is performed until the gate oxide layer that is not covered by the mask layer 106a is exposed, and a polycrystalline silicon gate electrode 104b is formed. The etching environment at this stage does not contain fluorine. The embodiment is to move to another chamber or to remove the fluorine-containing gas from the original reaction chamber. Finally, please refer to FIG. 5 to remove the mask layer 106a in the second stage. This embodiment takes the polycrystalline dream layer as an example, but the method of the present invention is not limited to the use of an amorphous hair layer instead of the polycrystalline layer. In the first stage of this embodiment, a fluorine-containing carbon gas is used as an etching gas to etch a polycrystalline silicon layer with a thickness of 1/2 to 2/3, but the present invention is not limited to this range, as long as the etching penetrates the mask layer. However, the thickness of the gate oxide layer may not be reached. Features and effects of the present invention The present invention is characterized by a method of forming a gate electrode by using a two-step etching method of polycrystalline silicon (amorphous silicon). The stage j etching process uses a fluorine (fluorocarbon) gas to etch the polycrystalline silicon layer to a predetermined thickness, and then removes the photoresist mask of the stage], while the stage 2 etching process does not include a fluorine gas, and Description of the invention (5) It is performed with a gas containing bromine or bromine gas, and a mask layer such as another oxide layer located above the polycrystalline silicon is used as an etching mask. The method for forming a gate electrode according to the present invention is applicable to etching of various polycrystalline silicon materials, and it is not necessary to adjust different etching conditions to form the gate electrode according to different materials. Therefore 'can avoid the gate's narrowing, deformation, and damage to the gate oxide. Although the present invention has been disclosed in a preferred embodiment, such as the definition of the present invention 'anyone skilled in the art :: J is not used; and the scope " can be changed and modified L therefore this === attached patent The scope defined shall prevail. ·,
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