TW415065B - Electrostatic discharge protection circuit for preventing melting of the gate structure - Google Patents

Abstract

The invention relates to the electrostatic discharge protection circuit, especially, the protection circuit that protects the gate structure from being melted to avoid the malfunction of the electrostatic discharge circuit. The feature of this invention is that the gate of every transistor is directly conducted to the source of the transistor, in which the source of every transistor is grounded. Therefore, when high voltage occurs at the pad, these transistors will turn on so as to ground the current occurring at the pad. Besides, since all the currents flow directly from gate to the source, no current will flow through the gate. In other words, current will not flow from one transistor to another transistor. Therefore, the gate voltage of every transistor is the same. That means the joule heat generated from the current flow is uniformly distributed over the entire transistors such that the gate melting caused by high joule heat can be effectively avoided. In addition, under the condition of electrostatic discharge, this electrostatic discharge protection circuit still can function normally.

Description

415065 V. Description of the invention (1) 5 _ 1 Field of the invention The present invention relates to an electrostatic discharge protection (ESD) circuit, and in particular to any kind of drain (Pad) conduction to a pad and The gate of the transistor (Oxide semiconductor; MOS) is an electrostatic discharge protection circuit that is directly conducted to the source. 5-2 Background of the Invention Integrated circuits are very sensitive to the effects of electrostatic discharge. Typical electrostatic discharges are usually short-term and transient high-voltage discharges caused by touching the pins of integrated circuits. If not prevented in advance, electrostatic discharge can damage or completely destroy the integrated circuit. Therefore, electrostatic discharge protection circuits are widely used in integrated circuits to prevent electrostatic discharge effects. Here, the ESD protection circuit is located between the pins of the integrated circuit and the die (d i e). Furthermore, a good electrostatic discharge protection device must be able to work normally under the thermal effects caused by electrostatic discharge, prevent a large amount of current from affecting the integrated circuit, and not be damaged by sudden high voltage. These capabilities mainly depend on the design and layout of the electrostatic protection device. Therefore, there are many types of electrostatic discharge protection circuits that can be used, and which type of electrostatic discharge protection circuit to use depends on the operating range of the electrostatic discharge protection device.

415065 V. Description of the invention (2) '' A useful input electrostatic discharge protection circuit is a grounded-gate transistor-type electrostatic discharge protection circuit, which includes a plurality of guard rings and is usually Turn off (turn 0ff) the transistor. The size of these transistors is significantly larger than the size of the crystals in the integrated circuit to reduce the current density and voltage. Referring to the first figure, the drain 10 of each transistor is turned on to the pad 11, and the source 12 is grounded. Among them, the pad 11 is further conducted to the pins of the integrated circuit, and the gate electrode 13 of the transistor is grounded and conducted to the contact i4. Here, the guard ring 15 is used to isolate the crystals from the crystals of the integrated circuit, and the guard ring 15 is turned on to the potential zero 16. When a high voltage is generated in the pad η, these transistors will turn on, thereby grounding the high voltage on the pad through the transistor to prevent the crystals of the integrated circuit from being affected by the high voltage. Obviously, for any transistor, the current flows directly to the source 12 via the drain 10. Obviously, these transistors can be divided into several groups. In each group, the transistors are arranged in parallel, and the voltage of any one transistor is the same as the voltage of other transistors, so the ear heat generated by the current ( joule heat) does not accumulate in any transistor. … With modern very large scale circuits (the development of very iarge scale factors: · the size of the conductor circuit is gradually shrinking, the thickness of the oxide layer of the gate is correspondingly reduced, and the thickness of the layer will significantly affect the collapse ( breakdwn) voltage, so the current will flow directly through the gate oxide layer to the gate conductor layer (as shown in the second figure, when the t high voltage is generated on the pad 20, it will flow out around the drain.

415065 V. Description of the invention (3) 'Now the depletion region 27 (depIetion region), the current will not only be affected by the lateral field (Eh) from the drain 21 to the source 22, but also subject to the vertical electric field (Vertical field, Ev); and the electrode 21 flows through the gate oxide layer 23 to the gate conductive layer 24. The current flowing through the gate includes (1) the current formed by the band-to-band tunneling hole 25 penetrating the vaporized layer and (2) the FN (Fowler-Nordheim) penetrating electron 2 6 The current formed by penetrating the oxide layer. Therefore, referring to the third figure in which the current 33 passing through the gate is represented by Ig, it can be clearly seen that all the transistors sharing the same gate form a series circuit with each other at this time. Referring to the third figure, the third figure shows a schematic circuit diagram of a current flowing from the pad 30 to the potential ground 32 (circuit ground) through the free terminal 31 of the transistor. Obviously, the voltage of each gate 31 is different from that of the other gates 31, and the farther away from the potential zero 32, the higher the voltage. Since high voltage generates high energy, and these energy systems are unevenly distributed in the gates 3, the gates 31 far from the potential zero 3 2 will be melted by a large amount of Joule heat. Obviously, when the electrostatic discharge is generated in the input protection circuit, the transistor of some input protection circuit may fail due to the melting of the gate electrode 31. In other words, when the electrostatic discharge is generated in the input protection circuit, the gate 31 of the grounded gate electrostatic discharge protection circuit may be melted, so that the input electrostatic protection circuit loses its ability to prevent the electrostatic discharge effect. σ Therefore, according to the previous summary, it is known that it is necessary to provide an electrostatic discharge protection circuit suitable for an oversized integrated circuit. In particular, there is a need to provide an input protection circuit that prevents the gate from melting, thereby ensuring the correct operation of the protection circuit.

Page 7 415065

5-3 Object and Summary of the Invention The object of the present invention is to provide an electrostatic discharge protection circuit capable of preventing the melting of the gate electrode. A preferred embodiment of the present invention is an input electrostatic discharge protection circuit, in which a protection ring surrounds a plurality of normally closed transistors, and the source of each transistor is turned on to the potential zero point, and the transistor is The drain is conductive to the pad. In addition, the source of each transistor is directly connected to the gate of the transistor via a contact. Therefore, if the thickness of the gate oxide layer is thin enough that current can flow directly from the transistor's drain to the transistor's gate, this current will also flow directly from the transistor's gate to the source through the contact. In other words, although several transistors share a long gate, the resistance of the contact is much smaller than the resistance of the gate formed by the dream, so it is caused by the current flowing along the gate. The potential difference along the gate is small and negligible. In addition, the path through which the current flows in the present invention is also much shorter than the path through which current flows in the conventional electrostatic discharge protection circuit. From the above discussion, it can be known that the present invention can effectively prevent the melting of the gate electrode to ensure the normal operation of the input electrostatic discharge protection circuit. A brief description of the 5-4 diagram: 415065 V. Description of the invention (5) The first diagram shows a schematic diagram of the electrostatic discharge protection circuit of the grounded gate transistor; The second diagram shows the electrostatic discharge protection circuit of the grounded gate transistor The cross-section of the CLP crystal is not intended; the third figure shows the equivalent circuit of a grounded gate transistor electrostatic discharge protection circuit when the gate oxide layer is thin enough to allow current to flow directly from the drain to the gate; The fourth diagram shows a schematic diagram of an embodiment of the present invention; the fifth diagram shows a schematic cross-section of a transistor according to an embodiment of the present invention; and the sixth diagram shows a gate oxide layer according to an embodiment of the present invention. An equivalent circuit diagram when thin enough to allow current to flow directly from the drain to the gate. Symbols of main parts: 10 poles 11 pads 12 sources 13 gates 14 contacts 15 guard rings 16 potential zero 20 pads 21 drain

415065 V. Description of the invention (6) 22 source 23 gate oxide layer 2 4 gate conductive layer 25 electric hole 26 electron 27 deficient area 30 塾 31 gate 32 potential zero 33 current through the closed pole 40 guard ring 41 gate 42 source 43 sink 44 pad 45 potential zero 50 gate conductive layer 51 source 52 interlayer oxide layer 53 drain 54 potential zero 55 pad 56 contact 57 ground wire

Page 415065_ V. Description of the invention (7) 60 Gate 61 Pad 62 Potential zero 5-5 Detailed description of the invention: In order to clarify the purpose of the present invention, an input electrostatic discharge protection circuit capable of preventing the melting of the gate is first proposed. This electrostatic discharge protection circuit is located between the pins of the integrated circuit and the die to prevent the die from being affected by electrostatic discharge. The main difference between the electrostatic discharge protection circuit provided by the present invention and the conventional grounded gate transistor electrostatic discharge protection circuit is that the gate of each transistor in the embodiment of the present invention is connected to the ground metal line of the source, and That is to say, any current flowing to the intermediate electrode will directly flow to the ground metal line of the source. Referring to the fourth figure, the electrostatic discharge protection circuit provided by the present invention includes a protection ring 40, a plurality of gates 41, a source 42 and a drain 43, and ^ 4, wherein the non-electrode 43 is connected to the pad 44 and the source 42 The gate 41, the source 42 and the drain 43, which are turned on to the potential zero point, constitute a plurality of protected crystals. The guard ring 40 is used to isolate these transistors from the integrated circuit, the other part, and the potential zero point conduction to the electrostatic discharge protection circuit. The material of the ring 40 includes at least a heavily doped p-type semiconductor and a heavily doped semiconductor. Type ^ Conductor. The material of the gate 41 includes at least polycrystalline silicon and metal. In addition, it is applicable to P-type transistors and N-type transistors. 415065 V. Description of the invention (8) It should be noted that the transistor is usually in the off state, and it will only turn on when high voltage appears at 塾 4 4. Another thing to note is that the size of these transistors is significantly larger than the size of the crystals in the grains. Β The reason is that large area transistors can significantly reduce the charge density, so these transistors can tolerate Large voltage range. ^ In addition to this, the detailed shape, size, and number of these transistors are determined by the working range of the ESD protection circuit provided. The typical width is about 10 ^ m to 100 in m, and the typical number is about 12 . Referring to the fifth figure, the main features of the embodiment of the present invention include that, for each transistor in the electrostatic discharge compliance circuit, the 'gate conductive layer 50' is directly conducted to the potential zero through the contact 56 and the ground metal wire 57. 54, and the resistance value between the gate conductive layer 50 and the potential zero 54 is negligible, and the resistance value includes at least the resistance value of the contact 56 (Rcontact) and the resistance value of the ground metal line 57. Therefore, when the thickness of the gate oxide layer 52 is thin enough to allow a current to flow directly from the gate 53 to the gate conductive layer 50, the current will also flow directly from the gate conductive layer 50 to the potential zero 54. In other words, the current will flow directly from the pad 55 to the potential zero 54. Even if the gate 41 is shared by several transistors as shown in the fourth figure, the current does not flow along the gate 41 but flows directly from the pad 55 to the source 51. That is, as shown in the sixth figure, the equivalent circuits of these electric crystals are arranged in a sequence. An equivalent circuit of an embodiment of the present invention is shown with reference to the sixth figure. Obviously, the gates 60 between the pad 61 and the potential zero 62 are arranged in parallel. Therefore, the voltage of any one of the gates 60 is the same as that of the other gates 60

415065 V. Description of the invention (9) House 'And the power of any gate 60 is the same as the power of other gates. So 'not only the Joule heat caused by the current is evenly distributed across the gates', but because the resistance value (RC0ntact) of contact 56 approaches zero, the power of the current (the product of voltage and resistance value) also approaches zero, so Joule The effect of heat is negligible in the present invention. It is apparent that the spirit of the present invention is that the gate system of any transistor is connected to the source of the transistor, and the resistance between the gate and the source is negligible. So even if the gates of adjacent transistors are adjacent, no current will flow through them. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 13

Claims (1)

415065 6. Application patent scope 1. An electrostatic discharge protection circuit for integrated circuit, comprising: a pad for input and output; a plurality of transistors, wherein a plurality of drains of the plurality of transistors are connected to the pad, And the source of each transistor is directly connected to the gate of the transistor, and the plurality of sources of the plurality of transistors are conducted to a potential zero point; and a guard ring, the guard ring surrounds the Most transistors. 2. The circuit described in item 1 of the scope of patent application, wherein each of the transistors described above has a width of about 10 # m to 1 0 0 // m. 3. The circuit according to item 1 of the scope of patent application, wherein the number of the plurality of transistors mentioned above is about 12. 4. The circuit according to item 1 of the scope of patent application, wherein the plurality of transistors mentioned above include P-type transistors and N-type transistors. 5. The circuit described in item 1 of the scope of patent application, wherein the plurality of transistors described above are normally off, and when a high voltage appears on the pad, the plurality of transistors are on. This allows current to flow from the pad to the potential zero. 6. The circuit according to item 1 of the scope of patent application, wherein the above-mentioned protection ring is conducted to the potential zero point, and the material of the protection ring includes heavily doped P Page 5050 "" Patented semiconductors and heavily doped N-type semiconductors η 'V The circuit described in item 1 of the patented scope, the crystalline silicon gate is melted, and the material covering the gate includes at least polycrystalline silicon and metal. Most of the above 8. A round of electrostatic discharge protection circuit is used to prevent • isC- < Έ. Semiconductor substrate;-塾 is used for input and output; miscellaneous; = doping protection ring is located on the semiconductor substrate, and the P-type concentrated The doped guard ring system is turned on to a potential zero point; and most of the transistors are surrounded by the p-type heavily doped guard ring, and two of the two = body drains are turned on to this, and each-the majority The transistor is connected to the plurality of sources of the plurality of transistors, and each of the plurality of transistors is connected to the potential point. "Like 9. The circuit described above, wherein the majority of the transistors described above are normally off, and when a high voltage appears at the voltage, the majority of the transistors are in an on state so that current can flow from the pad to the Potential zero 10. The application circuit of patentable scope of item 8, wherein the thickness of each of said transistor 5 Hai about 1 ν ^ m to 1 billion from the square. Page 15 415065 6. Scope of patent application 11. The circuit described in item 8 of the scope of patent application, wherein the material of most of the above gates includes at least polycrystalline silicon. Page 1111