TW415009B - Two-stage fabrication method of void free dielectrics - Google Patents

Abstract

This invention relates to a two-stage fabrication method of void free dielectrics. The present invention is different from the prior art, which directly forms a dielectric layer on a surface with semiconductor structures, in that two dielectric layers are employed to cover on the surface of the semiconductor structures. The two dielectric layers, i.e., the upper dielectric layer and the lower dielectric layer are used to cover a substrate having a plurality of structures formed thereon. The lower dielectric layer is substantially uniform to cover the structures. The deposition rate of the upper dielectric layer on the surface and the sidewall of the structures is relatively low to prevent the formation of overhang such that a void can be not be produced. With such a process, the lower and the upper dielectric layers are void-free dielectric layers.

Description

415009 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for forming a dielectric layer, and more particularly to the use of two-stage formation to generate a void free dielectric layer. Method 0 5-2 Background of the Invention: In the manufacturing process of integrated circuits, a dielectric material is a material with a wide range of uses, at least for covering semiconductor structures, forming protective layers, and forming interlayer dielectric (interlayer dielectric, ILD). Of course, the dielectric material used in each dielectric layer depends on the use of the dielectric. The dielectric material is shaped like a semiconductor and at least flattened. This has a gap of 1 3 15 Most of the electrical quality is used to include the gate, electricity, and lithography on the substrate 10 of the semiconductor body. Since it may be at a dielectric position in some parts, the other surface is 1, and the stable layer is usually a layer of 15. 10 The semiconducting electrode and the semiconducting layer 15 of the inner and outer procedures are semi-flat, as shown on the surface 11 of the first figure, and the body structure 12. Can be connected. When the dielectric will be applied to form a void between the body structure 12 and the conductor substrate 10, the semi-massive layer to confirm and cover the energy 15 physical dielectric will appear 'special surface 11 semi-conducting dielectric After the electro-mass layer 15 is formed, all the existing conductor structures 12 are formed, and the photo-mass layer 15 is formed. The apparent gap 1 3 is because it corresponds to lj and the dielectric layer structure 12 and 415009. V. Description of the invention (2) Since the material and the forming method of the dielectric layer 15 depend on the purpose of the dielectric layer 15 Therefore, the pores 14 cannot be eliminated by changing the material and forming method of the dielectric layer 15. An important example is the inter-level dielectric (ILD). Generally, the step-coverage of tetraethyl-〇rthossilicate (TEOS) is better than that of silane (SiH4). Moreover, the incorporation of boron, phosphorus, etc. can effectively reduce the glass transition temperature. Therefore, the internal dielectric layer is usually boron phosphorus tetraoxyethyl silicon (orthossi 1 icate, BPTE0S). ). However, due to the thermal fluidity of the tetraoxoethoxylate, pores 14 are often formed between the semiconductor structures 12, especially when the aspect ratio of the gap 13 is large. In the subsequent contact process, the existence of the pores 14 may cause defects such as abnormal short circuits between different contacts. According to the above discussion, how to form a non-porous dielectric layer is an important issue in the fabrication of integrated circuits. In particular, an inner dielectric layer such as is used to prevent abnormal shortness caused by pores ... pores 5-3 Purpose and Summary of the Invention: The main purpose of the present invention is to propose a method. A further purpose of this method is to provide a method for forming a non-porous dielectric layer--a method for forming a non-porous dielectric layer--a method using a two-stage formation process

415009 V. Description of the invention (3) In addition, a special purpose of this method is to propose a method for forming a butterfly phosphate glass layer and a tetraoxoethyl stone layer by two-stage deposition, thereby forming a non-porous dielectric layer . Yoda explained the purpose of the present invention, and a method for manufacturing a non-porous dielectric layer by two-stage formation was proposed. The tH method includes at least the following steps: Continuously seeding some semiconductor elements in a semiconductor substrate, the surface of the semiconductor substrate is usually flattened. ^ First, forming a plurality of semiconductor structures above the surface of the semiconductor substrate ′ There are a plurality of gaps between the semiconductor structures. Ancient foundations form the first dielectric layer on the semiconductor substrate and cover the entire assembly: the junction and the thickness of the first dielectric layer must be adjusted to form a uniformly covered dielectric. Stratum. 28th thought: the second dielectric layer is formed on the dielectric layer. The pores ^ i t above the Zr semiconductor structure and the sidewalls of the semiconductor structure are so low that they do not form any pores. Thus formed

Lit is effectively eliminated to form a non-porous dielectric layer. The special purpose of the example to + spoon L is the sun and moon described in the following embodiment. This embodiment includes at least the following steps: U and a half U body = *: semiconductor substrate, in which there are most and most semiconductors. The structure has a plurality of gaps between Yoshihiro conductor structures above the surface of the semiconductor substrate. (3) using electrochemical chemical vapor deposition (plasraa enhanced

Page 6 415009 V. Description of the invention (4) Chemical vapor deposition (PECVD) forms a tetraoxyethyl dream layer with a thickness of about 1500 angstroms to 4000 on this semiconductor substrate and covers all semiconductor structures β (4) Use Atmospheric pressure chemical vapor deposition (APCVD) forms a borophosphotetraoxyethyl silicon layer with a thickness of about 8000 angstroms to 12,000 angstroms on the tetraoxyethyl silicon layer. 5-4 Schematic illustration: Section 1 shows the formation of 'in the mesogenic layer' in the conventional technique? L I5 Song mechanism; Figures A to B show cross-sections of one embodiment of the present invention; and Figures A to C show cross-sections of another embodiment of the present invention Illustration. Symbols of main parts: 10 semiconductor substrate 11 surface 12 semiconductor structure 13 gap 14 pore

V. Description of the invention

15 16 20 21 22 23 24 25 30 31 32 33 34 35 36 Dielectric layer upper surface semiconductor substrate surface semiconductor structure first dielectric layer gap second dielectric layer semiconductor substrate surface semiconductor structure gap tetraoxane The top surface of the base silicon layer borophosphosilicate glass ionospheric layer is 5-5 inventions § Sheep details p spoon: 11 The second A picture shows the majority of semiconductor structures 22 is formed on the semiconductor substrate that already contains the majority of semiconductor elements 20 There are also a plurality of gaps 24 between the semiconductor structures 22. A possible semiconductor element includes at least a gate, an isolation layer, a source, and a drain, and a possible semiconductor structure 22 includes at least an interconnect, an electrode, and a metal-oxide semiconductor transistor. In addition, semiconducting

Page 8 415009 V. Description of the invention (6) The surface 2 1 of the body substrate 20 is usually planarized to ensure the stability of the semiconductor structure 2 2 ′, especially in a multilayer structure, it must be planarized. Next, a first dielectric layer 23 is formed on the surface 21 of the semiconductor substrate 20, where the first dielectric layer 23 also covers all the semiconductor structures 2 2. It must be noted that the thickness of the first dielectric layer 23 must be sufficiently thin to effectively prevent the formation of overhangs. The upper limit of this thickness depends on the aspect ratio of the gap 24. Therefore, the first dielectric layer 23 is usually a uniformly covered dielectric layer 'and is generally formed by a chemical vapor deposition method. Then referring to the second B diagram, a second dielectric layer 25 is formed on the first dielectric layer 23 'and fills all the gaps 24. The material and process of the second dielectric layer 25 must be such that the ratio of the deposition rate of the second dielectric layer 25 above the semiconductor structure 22 to the sidewalls of the semiconductor structure 22 is sufficiently low to not form any pores. Therefore, the 'gap 24 is completely filled with the first dielectric layer 22 and the second dielectric layer 25, and a non-porous dielectric layer is also formed on the semiconductor substrate 20. Of course, in most cases, the second dielectric layer 25 is formed by a chemical vapor deposition method. An important and particular application of the present invention is an internal dielectric layer. In the conventional process, the internal dielectric layer is usually formed by using boron phosphorus tetraoxoethane and silicon which can reduce the glass transition temperature. In any case, when the borophosphotetraoxyethyl silicon layer is used to cover an uneven surface, pores are often formed in the borophosphotetraoxyethyl silicon layer, which causes defects such as short circuits in subsequent processes such as metal plugs. . In order to eliminate these defects', the present invention is applied to form a void-free inner dielectric layer in two stages of deposition. First, as shown in FIG. 3A, a plurality of semiconductor structures 32 are formed.

Page 9 415008

On the semiconductor substrate 30 which already includes a plurality of semiconductor elements, there are also a plurality of gaps 33 between the semiconductor structures 32. The possible semiconductor elements ^ rarely include a gate, an isolation layer, a source, and a drain, and the possible semiconductor structure 32 includes at least interconnects, electrodes, and metal-oxide semiconductors. In addition, the surface 31 of the semiconductor substrate 30 is usually planarized, thereby ensuring the stability of the semiconductor structure 32. First, as shown in FIG. 2B, a tetraoxyethyl silicon layer 34 is formed on the surface 31 and covers all the semiconductor structures 32. The tetraoxyethyl silicon layer 34 is formed by a plasma chemical vapor deposition method at a pressure of 2-2 Torr and a temperature of 4100 t, and has a thickness of about 15,000 angstroms to 4,000 angstroms. It is worth noting that because the thickness of the tetraoxyethyl silicon layer 34 is thin enough to effectively reduce the formation of overhangs, there will not be any pores in the tetraoxyethyl silicon layer 34. Of course, the thickness of the tetraoxyethyl yarn layer 34 is basically determined by the aspect ratio of the gap 33. The third 'as shown in the third C figure' forms a borophosphosilicate glass separation layer 35 in the tetraoxyethyl stone layer. Above 3 4, the thickness of the cut-off layer 30 5 must be higher than the height of each semiconductor structure 32. In this embodiment, the borophosphosilicate glass delamination layer 35 is formed by atmospheric pressure chemical vapor deposition method at a pressure of 1 atmosphere and a temperature of 4 300 ° C to 4 5 0 t: Approximately 8000 angstroms to 12,000 angstroms. Furthermore, the weight percentage of rotten borosilicate glass layer 35 is about 4.4% to 5%, and the percentage of phosphorus is about 3.4% to 3.6%. It is worth noting that the deposition rate ratio of the borophosphosilicate glass layer 35 above the semiconductor structure 32 and the sidewalls of the semiconductor structure 32 must be smaller than the deposition rate ratio of the shed-filled tetraoxetane layer of the same thickness. So although in the conventional inner dielectric layer

Page 10 415009 V. Description of the invention (8) In the process t, the borophosphosilicate glass layer 35 which is suspended in the borophosphotetraoxyethyl silicon layer phosphosilicate glass layer 35 to form the gap 33 is all tetraoxyethyl silicon The layer 34 and the borophospho oxyethyl silicon layer 34 and the inner dielectric layer of the borophosphosilicate glass. In addition, because of the inner space, the borophosphosilicate glass layer 3 5 is treated in a frank manner. The above description is only an example of the present invention and is only used for illustration and not for implementation without departing from the substance of the present invention. 'These changes should still belong to the scope of this invention. And voids, but in the butterfly can effectively stop and then fill the non-porosity. Therefore, the gap 3 3 is filled with the silica glass layer 35, and the four layers 3 5 can form a non-porosity together. The dielectric layer is located on the top surface 36 of the two adjacent structures. Usually, the two preferred embodiments are only flat, which really limits the scope of the patent application of the present invention. The scope of the scope can still be clarified. Therefore, the scope of the present invention is defined.

Claims (1)

415009 VI. Scope of patent application 1. A two-stage method for forming a non-porous dielectric layer, the method at least comprises: providing a semiconductor substrate; forming a plurality of semiconductor structures on the surface of the semiconductor substrate, here There are a plurality of gaps between the semiconductor structures; a first dielectric layer is formed on the semiconductor substrate and covers all the semiconductor structures; the thickness of the first dielectric layer is thin enough that the first dielectric layer There is no void in a dielectric layer; and a first dielectric layer is formed on the first dielectric layer, so that the plurality of gaps are both by the first dielectric layer and the second dielectric The dielectric layer is filled 2. As in the method of claim 1 of the patent application, the deposition rate of the second dielectric layer above the semiconductor structure and the sidewall of the semiconductor structure must be low enough so that it does not form any pores . 3. A method for forming a non-porous inner dielectric layer by two-stage deposition, the method at least comprising: providing a semiconductor substrate; forming a plurality of semiconductor structures on the surface of the semiconductor substrate, and having a plurality of gaps Interposed between each semiconductor structure; a tetraoxyethyl silicon layer is deposited on the semiconductor substrate and covers all of the semiconductor structure, the tetraoxyethyl silicon layer is a uniformly covered dielectric layer, and Page 12 415009 VI. The scope of the patent application forms a borophosphosilicate glass layer on the tetraoxyethyl silicon layer, so that the majority of the gaps are covered by the tetraoxyethyl silicon layer and the borophosphosilicate glass layer. Fill up. 4. The method according to item 3 of the patent application, wherein the above-mentioned tetraoxyethyl silicon layer is formed by a plasma chemical vapor deposition method at a pressure of 2.2 Torr and a temperature of 41 0 ° C. 5. The method according to item 3 of the patent application, wherein the thickness of the above-mentioned tetraoxyethyl silicon layer is about 15 Angstroms to 4 Angstroms. 6. The method according to item 3 of the patent application, wherein the borophosphosilicate glass layer is formed by atmospheric pressure chemical vapor deposition at a pressure of 1 atmosphere and a temperature of 4300c to 450 ° C. . 7. The method of claim 3, wherein the weight percentage of the butterfly in the above borophosphosilicate glass is about 4,4% to 5%, and the percentage of phosphorus is about 34% to 3. 6%. 8. The method of claim 3, wherein the thickness of the above borophosphosilicate glass layer is about 8000 angstroms to 12,000 angstroms. • The method of applying for item 3 of the patent scope, the ratio of the deposition rate of the borosilicate glass layer above the semiconductor structure to the sidewall of the semiconductor structure must be Page 13 415009 Page 14