TW414949B - Non-symmetrical transistor structure and its manufacturing method - Google Patents

Abstract

The present invention is related to a structure of a non-symmetrical transistor and its manufacturing method. The structure of a non-symmetrical transistor is featured by: first, lightly doped drain is formed by the side of the drain only by which the resistance of the source can be reduced and the operating voltage of the non-symmetrical transistor is lowered; second, the pocket implant is formed under the source only by which the capacitance of drain is lowered to decrease the delay of transmission and the possibility of short channel effect is reduced. The manufacturing method of this non-symmetrical transistor divides the manufacturing process of the transistor, especially the process of lightly doped drain and pocket implant, into sections which are processed separately in the source and the drain to make the lightly doped drain formed by the side of the drain only and the pocket implant formed under the source only by which the non-symmetrical structure is formed.

Description

414949

5 _1 Field of the invention: The present and the Ming are related to the structure and manufacturing method of an asymmetric transistor, and particularly to a light doped drain. The light doped drain is formed only on and / or extremely heterogeneous. Pocket impiant is formed only in the asymmetric transistor structure under the source, and the manufacturing method of segmenting the transistor process between the source and the drain. 5-2 Invention Background: 々, its basic structure is as shown in the first figure

At this time, the structures of the lightly doped drain 15 and the conventionally used transistor are symmetrical, as shown. The gate electrode 11 is formed on the substrate 11 and is usually covered by the spacer 12 so that the source electrode 13 and the drain electrode 14 are located on the surface of the substrate 10, 414949 V. Description of the invention ( 2) Quality miscellaneous bags 16 are not necessary. However, when the short channel effect is important, in order to prevent the performance of the transistor from being degraded due to hot carrier effect, punch through, and threshold voltage lowering, etc., it is lightly mixed. Both the drain 15 and the impurity doping bag I 6 are indispensable. In any case, lightly doped A produces some non-negligible auxiliary miscellaneous bags 16 which will increase the electrical transient time of the drain) Extend # of lightly doped drain 15 pairs to prevent lowering at source 1 3 and drain 1 4 mixed bags 1 6 Although the source resistance can be prevented from increasing, so that according to the above discussion can be improved a lot. Low operating voltage and high response speed must also be improved. It is also necessary to develop a new electric power source. First of all, in the capacitance value, the carrier conduction between the thermal carrier effect is reduced while the reaction speed is reduced by half. (The working electricity of the punch conductor is known, especially when the accumulation rate is known. Of course, the square wave of crystal manufacture The turn rate of the conductor under the pole 14; the second effect is not the concentration; through) the pressure rises. A new method for the development of the power of the transistor circuit is to use the impurity conversion time (, which is large at the source 13, but it will be the third, the impurity, but also the structure that can increase gradually. Transistor structure 5 ~ 3 Purpose and summary of the invention: The main purpose of the present invention is a body structure; the second type of asymmetric transistor. First, the system of the present invention is proposed. Lightly mixed

$ 5 pages 5,, and, Ming ⑶ _ ', 戍 极 二 go to 3 coffee. In other words, although bran glutinous rice and Feng Li are asymmetric T 'called', but lightly mixed with the drain and impurity impurity bag: clothed in the source region to wash the drain electrode. By the process of the drain electrode and impurity impurity bag, Separate processes. With shape = proceed. #Changed by J in different regions to form asymmetric transistors.

Q 5 4 diagram brief explanation = Γ diagram shows the conventional transistor structure; structure; diagram shows according to the present invention-embodiment, #symmetric transistor junction diagram A to D — Schematic diagrams of cross-sections of different stages of the manufacturing method of symmetrical transistors. Examples of non-main parts are: 10 substrate 11 gate 12 gap 13 source 14 and 15 light disturbances and poles

V. Description of the invention (4) 16 Impurity impurity bag 20 Substrate 21 Intermediate electrode 22 Spacer 23 Source electrode 24 Drain electrode 25 Light impurity electrode 26 Impurity impurity bag 30 Substrate 31 Gate 32 Photoresist 33 First impurity 34 impurity Miscellaneous bag 35 Second impurity 36 Source electrode 37 L and electrode 38 Third impurity 39 Partition wall 40 Fourth impurity 41 Light doped wave pole-5 Detailed description of the invention

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5. Description of the invention (5) --- The second figure is a schematic cross-sectional view of the first embodiment of the present invention, showing the structure of an asymmetric transistor. The asymmetric transistor includes at least the following cells: a gate electrode 21, a spacer 22, a source electrode 23, a drain electrode 24, a lightly doped drain electrode 25, and a doped impurity bag 26. It must be noted that the second figure is only a schematic cross-sectional view of the present invention '. Therefore, the outline and relative position of each unit need not be the same as the second figure', but only need to comply with the restrictions mentioned in the following description. The gate electrode 21 is formed on the substrate 20 and includes an oxide layer and a conductive layer. The partition wall 22 is located on the side wall of the gate electrode 21, and is used to protect the side wall of the gate 21 from being damaged in the subsequent semiconductor process. The possible types of the substrate 20 include at least a P-type substrate and a [^ -type substrate, and the gate electrode 2_ 丨 includes at least an oxide layer and a conductive layer, and the material type of the conductive layer includes at least polycrystalline stone. Evening, gold layers and metal dreams. The source electrode 23 and the drain electrode 24 are both located on the surface of the substrate 20, while the source electrode 23 and the sink electrode 24 are located on both sides of the region of the substrate 20 covered by the gate electrode 21. The lightly doped drain electrode 25 is located only on the surface of the substrate 20 near the drain electrode 25 and below the spacer wall 22. The lightly doped drain electrode 25 does not appear on the surface of the substrate near the source electrode 23. In other words, the distribution of the lightly doped drain electrodes 25 is not symmetrical. The impurity impurity bag 26 is located below the source electrode 23, and the outline of the impurity impurity bag 26 projects below the gate electrode 21. However, the impurity impurity bag 26 does not contact the gate electrode 21, the light impurity electrode 25, and the drain electrode 24. The impurity doping bag has the same polarity as the substrate 20 ', but has a higher concentration than the substrate 20'. When the substrate 20 is a P-type substrate, the impurity type of the impurity impurity bag 26 includes at least boron; when the substrate 20 is an N plastic substrate, the impurity type of the impurity impurity bag 26 includes at least

V. Description of the invention (6) * " ---- Including scales. Only W ΐ ΐ ground 'due to the asymmetric transistor structure' lightly doped drain 25 / formed next to the asymmetric transistor's drain 24 and the impurity doped bag "is also only shaped at the source 23 of the asymmetric transistor This is why the asymmetric transistor structure: in addition to saving the materials forming the lightly doped drain electrode 25 and impurity doped bag 26, at least! There are several advantages: First, because there is no lightly doped impurity beside the source electrode 23 The drain 25, so the carriers moving from the source 23 to the drain 24 are directly from the source 23, and the number will not be reduced by the influence of the light clutter 25, that is, the source 23 and the drain The resistance value between 2 and 4 can be reduced. Second, because there is no impurity impurity bag 26 beside the drain electrode 24, no capacitance is generated between the impurity impurity bag 26 and the electrode 24, so that the reaction rate of the transistor will not be reduced. It is reduced due to the increase of the capacitance-induced conversion time (1: ransien1: time). It can be seen that when the transistor is used in high-speed components, this asymmetric transistor structure is quite valuable β Second, because the source 23 and the The resistance between the drain 2 and the 4 can be reduced, and the current value It is proportional to the strength of the transistor's output signal, so the 'transistor's operating voltage can be effectively reduced at the same signal strength. It can be seen that in a low operating voltage integrated circuit', this asymmetric transistor structure is quite valuable. Fourthly, because the impurity doping bag 26 is not only located below the source electrode 23, but also its profile protrudes below the gate electrode 21, the asymmetric transistor structure can effectively prevent the empty region (deple1; i〇n regi〇n ) And penetration happen

Page 9 V. Description of the invention (7) The second circle A to the third circle D are schematic cross-sectional views of different stages in the manufacturing method of the asymmetric transistor. This manufacturing method includes at least the following steps: First, as shown in FIG. 3A, the gate electrode 31 is formed on the substrate 30, and then a photoresist 32 is formed on the substrate 30, and the photoresist 32 covers at least the substrate 30. Corresponding to the region of the drain electrode, the substrate 30 is then subjected to a first impurity 33 implantation procedure to form an impurity doping bag 34. It must be noted that in the implantation procedure of the first impurity 33, the first impurity 33 is not incident perpendicularly to the substrate 30, but incident to the substrate 30 in a direction biased to the drain, so the impurity impurity bag 34 is roughly located Outside the region corresponding to the source in the substrate 30, it also protrudes below the gate 31, but the impurity impurity bag 34 does not come into contact with the gate 31. It must be noted that the polarity of the first impurity 33 is the same as that of the substrate 30. When the substrate 30 is a P-type substrate, the type of the first impurity 33 includes at least boron, and when the substrate 30 is an N-type substrate, the type of the first impurity 33 includes at least = it must be noted that the impurity impurity bag 34 The concentration of the first- impurity f 33 is higher than the impurity concentration of the substrate 30. It is also important to note that the contour of the impurity doping bag 34 depends at least on the energy and incident direction of the incident -th impurity 33. Average quality

The angle of injection into the base material 30 is about 15 degrees to 45 degrees. The miscellaneous negative W is about 3 per cubic centimeter-the concentration of impurities 33 and the amount is about 30 to 80.

Ke ", when M's exact angle, roll, and performance of the transistor need to be related to the details of the process. Focus on the asymmetry and then, as shown in the third B picture, the substrate 30 is implanted, so that the first 30 The second impurity 35 is implanted into the source 36 .: The area is still covered by the photoresist 32, so the second impurity 35 is not covered by

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The implantation process performed when the photoresist 32 is removed before entering the substrate 30 is the second drain electrode 37. Here, the concentration of the second impurity 35, and the concentration of the second impurity 35 is higher than the ion concentration of the source electrode 36, and the third impurity 38 is used later. Therefore, the energy of the third impurity 38 is usually the depth to which it is incident. Firstly, the implantation process of the impurity 40 of the spacer 39 on the gate 31 is completed to complete the drain region covered by the spacer 39 and the polarity of the fourth impurity 40 and the concentration of the third impurity are lower than the concentration of the third impurity 35. The ion concentration of the pole 36. In the crystal process, the source region and the drain region are a mask and lithography of the asymmetric transistor process order. 5. Description of the invention (8) The electrode region. Next, as shown in FIG. 3C, a third impurity implantation procedure is performed. The three impurities 3 8 are simultaneously implanted in the source 36 and have the same polarity as the third impurity 38. The concentration of the third impurity 38 is high because the ion concentration of 37 is low. At the same time, a light-doped drain is formed in the process, which has a lower energy than the second impurity 35 to reduce the final amount. As shown in Figure 3D, on the side wall, the substrate 30 is subjected to the fourth electrode 37 and the source. In the process of pole 36, lightly doped drain 41 is formed at this time. Here the 35th polarity is the same, but the fourth impurity 3g is high, so that the drain 37 and the source can be adjusted. Obviously, because the impurity impurity bag in the conventional electrode area is separately manufactured, the transistor sequence can be saved. It is worth noting that although in the third A picture, the photoresist 3 2 covers not only the drain region of the substrate 30 but also part of the gate 3 丨. However, the only limitation on the photoresist 32 covered area is that during the implantation process of the first impurity 33, the first impurity 33 will not be implanted in the drain region of the substrate 30 to ensure that the impurity impurity bag 34 will not The drain 37 is in contact with the lightly doped drain 41. Therefore, the photoresist

Page 11 sfenp V. Description of the invention (9) 3 2 extends to the source area of the substrate 30, and can even cover part of the source area, thereby changing the area where the first impurity 3 3 can be implanted to adjust Contours of impurities mixed with sacks 3 4. The above description is only two preferred embodiments of the present invention, and these embodiments are only used for illustration and not for limiting the scope of patent application of the present invention. Such changes can be implemented without departing from the essence of the present invention, and such changes should still fall within the scope of the present invention. Therefore, the scope of the present invention is defined by the following patent applications.

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Claims (1)

'Asymmetric transistor structure, the asymmetric transistor has at least two gates, and the gates include at least an oxide layer and a conductive layer formed on a substrate; a gap wall, which is located at The side wall of the gate; ~ the source, the source is located on the substrate; the wide-no pole, the drain is located on the substrate; and the material of the gate is located on the drain and the Between the source electrodes; the light impurity light electrode, which is located in the 's portion of the substrate, and is located below the gap; and M—the impurity impurity bag, the impurity impurity bag is located in the Under the source and throat. The opening includes: ‘the two materials covered by the gate near the part = t asymmetrical transistor of the patent scope item 1, including: P-type substrate or N-type substrate. The above-mentioned guide: the asymmetric transistor in item 1 of the patent scope, where the above "" material types include at least polycrystalline silicon, metal and metal silicidation. ^ The asymmetric transistor of the second shell, where the polarity of the coat is the same as that of the substrate, but the concentration, the height of the substrate =: The type of impurities in the upper and lower bags of the asymmetric transistor of the range 1 At least butterflies and dishes. The biography. Miscellaneous 6. Scope of patent application-The asymmetric transistor π of item 1 of the 6-quality patent scope, in which the above mentioned miscellaneous and miscellaneous clothes are not in contact with the lightly doped drain and the drain. Among them, the above-mentioned miscellaneous substance i τ, please apply for the asymmetric transistor in the first item of the patent scope, and the miscellaneous bag does not come into contact with the gate. 8. A manufacturing method for forming an asymmetric transistor, the method includes at least the following steps: forming a gate on a substrate; forming a photoresist on the substrate, the photoresist covering at least the substrate corresponding to A drain region; a first impurity implantation process is performed on the substrate to form an impurity impurity bag, and the first impurity impurity incorporated in the implantation process is not perpendicular to the substrate; and the impurity impurity bag It is generally located in a region corresponding to a source in the substrate; a second impurity implantation process is performed on the substrate to implant the second impurity into the source; remove the photoresist; A third impurity implantation procedure is performed on the substrate, the implantation procedure is to implant a third impurity onto the substrate at the same time as the region corresponding to the source electrode and the drain electrode; forming a gap wall on the side wall of the gate electrode "The non-electrode area covered by the gap wall is a lightly doped light electrode; and a fourth impurity implantation process is performed on the substrate to form the drain electrode and Page 14 6. Scope of patent application The source. 9. The manufacturing method of claim 8 in which the polarity of the first impurity is the same as that of the substrate, and the possible types of the first impurity include at least boron and phosphorus. 10. The manufacturing method according to item 8 of the scope of patent application, wherein the angle at which the first impurity is injected into the substrate is about 15 to 45 degrees. 1 1 · The manufacturing method according to item 8 of the scope of patent application, wherein the concentration of the above-mentioned first impurity is approximately 1 E1 4 to 1E1 per cubic centimeter, and the concentration of the first impurity must be such that the impurity is mixed with impurities in the bag The concentration is higher than the impurity concentration of the substrate. 1 2. The manufacturing method according to item 8 of the scope of patent application, wherein the energy of the first impurity is about 30 to 80 K ev. 1 3. The manufacturing method according to item 8 of the scope of patent application, wherein the profile of the impurity impurity bag described above depends on the incident angle and energy of the first impurity, and also depends on the area covered by the photoresist. 1 4. The manufacturing method according to item 8 of the scope of patent application, wherein the aforementioned impurity bag is not in contact with the gate. Page 15 β ^ βρτρ 6. Scope of Patent Application 1 5. The manufacturing method according to item 8 of the scope of patent application, wherein the polarity of the second impurity is the same as that of the third impurity. 16. The manufacturing method according to item 8 of the application, wherein the concentration of the second impurity is higher than the concentration of the third impurity. 17. The manufacturing method according to item 8 of the application, wherein the polarity of the fourth impurity is the same as the polarity of the third impurity. 18. The manufacturing method according to item 8 of the application, wherein the concentration of the fourth impurity is higher than the concentration of the third impurity. 19. The manufacturing method according to item 8 of the scope of patent application, wherein the lightly doped drain electrode and the drain electrode are not in contact with the impurity doped bag. Page 16