經濟部中央標準局員工消費合作社印製 413940 Λ7 ___B7 五、發明説明（1 ) 本發明係Μ於一種積體電路電容元件的製造方法， 特別是關於一種應用化合反應原理，以簡化製程進而提 高產品良率的動態隨機存取記憶體記憶單元之儲存電容 製造方法。 發明背景 近年來，在積體電路的設計上，電容器的地位日趨 重要’且已經成為一無可替換之電路元件。例如目前廣 泛使用電容器之動態隨機存取記憶體（DRAM : dynamic random access memory)、震盪器（osciiiat〇r)、時間延遲電 路（time delay circuitry)、類比/數位或數位/類比轉換器 (AD/DA converter)及許多其他應用電路。 電谷器基本上是由隔著一絕緣物質之兩導電層表面 (即電極板）構成，由於電容器電容量C=e d/A，其中ε 為絕緣物質之介電常數’ d為絕緣物質之厚度，a為電 極板表面積’因此電容器儲存電荷之能力係由前述三種 物理特徵決定，即（1)絕緣物質之厚度；（2)電極板之表 面積；及（3)與絕緣物質介電常數相關之電子或機械性 質。 以動態隨機存取記憶趙為例，其中每一記憶單元的 儲存機構乃由_電容器所組成，為了在有限的基底面積 上增加記憶體的儲存容量，必須提高基底上記憶單元的 密度’亦即使記憶體電路能包含更大量之記愧單元，因 此每一記憶單元於基底上所佔的投影面積必須不斷減 少；而同時’記憶單元儲存機構之電容部份則仍必須有 本紙張尺度適用中國國家標準（CNS )以規格（2! 0X297公楚 {請先閱讀背面之注意事項再填疼本頁) 訂Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 413940 Λ7 ___B7 V. Description of the Invention (1) The present invention relates to a method for manufacturing integrated circuit capacitor elements, and in particular, it relates to an application of the chemical reaction principle to simplify the process and improve the product. Method for manufacturing storage capacitor of dynamic random access memory memory cell with good yield. BACKGROUND OF THE INVENTION In recent years, in the design of integrated circuits, the status of capacitors has become increasingly important 'and has become an irreplaceable circuit element. For example, dynamic random access memory (DRAM: dynamic random access memory), oscillator (osciiiat〇r), time delay circuitry, analog / digital or digital / analog converter (AD / DA converter) and many other application circuits. The electric valley device is basically composed of the surfaces of two conductive layers (ie, electrode plates) separated by an insulating substance. Since the capacitance of the capacitor is C = ed / A, where ε is the dielectric constant of the insulating substance, and d is the thickness of the insulating substance. , A is the surface area of the electrode plate ', so the capacity of the capacitor to store charge is determined by the aforementioned three physical characteristics, namely (1) the thickness of the insulating material; (2) the surface area of the electrode plate; and (3) the dielectric constant related to the insulating material. Electronic or mechanical properties. Taking dynamic random access memory Zhao as an example, the storage mechanism of each memory unit is composed of capacitors. In order to increase the memory storage capacity on a limited substrate area, the density of the memory cells on the substrate must be increased. The memory circuit can contain a larger number of shame cells, so the projection area occupied by each memory cell on the substrate must continue to decrease; at the same time, the capacitance part of the memory cell storage mechanism must still have this paper standard applicable to the Chinese country Standard (CNS) Order (2! 0X297 Gongchu {Please read the precautions on the back before filling this page)
C 413940 M濟部中央橾準局負工消贽合作社印«. A7 B7 五、發明説明（2) 儲存足夠充分之電荷量的能力，以防止電路操作中寄生 電容和雜訊對儲存訊號所造成的影響β _為能達成上述減小每一記憶單元於基底上所佔的投 影面積，同時仍保有足夠電容儲存能力的要求，則必須 從前述之絕緣物質之厚度、電極板之表面積及絕緣物質 介電常數相關之電子或機械性質來進行研究；其中在增 加電極板之表面積上，一種三維（Three-dimension)之堆疊 式電容（STC : stacked capacitor cell)被發展出來，其乃 利用立體結構來形成電容電極板，因此於較小的基底投 影面積下即可產生足夠的電容表面積，來達到更高的储 存容量，以減低軟錯記率（SER : softerrorrate)等訊號的 錯誤。 而傳統的堆疊式電容結構製造方法，如美國專利第 548801 1所述之皇冠狀（crown)電容結構製造方法或是台 灣專利公告第0311256號之立體堆疊式電容結構製造方 法，其均利用一層稱為犧牲層（Sacrificial Layer)的方式來 保護部分導電層，而以蝕刻或化學機械研磨法（CMP ; Chemical Mechanical Polish)來除去未為犧牲層所保護的 其餘導電層後，再將犧牲層去除以構成電容之電極板， 而此方法的缺點乃在於因為犧牲層深陷於容器狀的電容 電極板中，常造成犧牲層去除不完全而殘留的問題，或 以過蝕刻方式（Over Etch)來完全去除犧牲層卻造成電極 板層的損傷<= 因此，本發明的目的是提供一種不需沉積犧牲層而 本紙張尺度適用中國國家標準（CNS ) Λ4現格（210X297公釐）C 413940 M Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Consumer Affairs and Cooperatives «. A7 B7 V. Description of the invention (2) The ability to store a sufficient amount of charge to prevent parasitic capacitance and noise from causing circuit signals during operation In order to achieve the above-mentioned requirements to reduce the projected area of each memory cell on the substrate while still maintaining sufficient capacitance storage capacity, the thickness of the foregoing insulating material, the surface area of the electrode plate, and the insulating material must be achieved To study the electronic or mechanical properties related to the dielectric constant; Among them, in order to increase the surface area of the electrode plate, a three-dimensional (Three-dimension) stacked capacitor cell (STC) has been developed, which uses a three-dimensional structure to The capacitor electrode plate is formed, so that a sufficient capacitor surface area can be generated with a small substrate projection area to achieve a higher storage capacity and reduce signal errors such as soft error rate (SER: softerrorrate). The traditional manufacturing method of stacked capacitor structures, such as the crown capacitor structure manufacturing method described in U.S. Patent No. 5,480,801 or the three-dimensional stacked capacitor structure manufacturing method of Taiwan Patent Publication No. 0311256, both use a layer The sacrificial layer is used to protect part of the conductive layer, and the remaining conductive layers that are not protected by the sacrificial layer are removed by etching or chemical mechanical polishing (CMP; Chemical Mechanical Polish), and then the sacrificial layer is removed to The electrode plate of the capacitor is formed, and the disadvantage of this method is that the sacrificial layer is deeply trapped in the container-shaped capacitor electrode plate, which often causes the problem of incomplete removal of the sacrificial layer and residue, or it is completely over-etched. Damage to the electrode plate layer caused by removal of the sacrificial layer < = Therefore, the object of the present invention is to provide a Chinese paper standard (CNS) Λ4 (210X297 mm), which does not require the deposition of a sacrificial layer.
Bn·— fll· flilt n (請先閲讀背面之注意事項再填寫本頁) -Φ. 413940 A7 _________B7 五、發明説明（3) 完成立體堆疊式電容結構的製造方法。 本發明的另一目的是提供一種不需沉積犧牲層而完 成皇冠狀（Crown type)電容結構的製造方法。 (靖先聞讀背面之注意事項再填寫本頁) 本發明的另一目的是提供一種利用化合反應和選擇 性蝕刻的方式而完成立體堆疊式電容結構的製造方法。 本發明的另一目的是提供一種利用化合反應和選擇 性餘刻的方式而完成皇冠狀（Crown type)電容結構的製 造方法。 本發明的主要製程包括下列步輝：於半導體基底上 形成複數個場氧化層、複數條字元線、複數個擴散區及 複數條位元線；然後覆蓋上一平坦化層和一蚀刻阻絕 層；再形成複數個底端和該複數個擴散區互相接觸之掺 雜多晶珍插检。 接著沉積上一電容容器層和一反應層；然後利用微 影、蝕刻方式部分留下該電容容器層和該反應層，定義 出複數個電容容器區，該複數個插栓的頂端顯露於該複 數個電容容器區的底部區域；再沉積一順應性覆蓋於該 複數個電容容器區及該反應層上之下電極板層。 經濟部中央標隼局貝工消费合作社印裝 接著進行本發明的重點，進行一化合反應步驟，使 得該部分留下之反應層與該下電極板層之疊接部份發生 反應’產生一化合層；接著進行選擇性的蝕刻步驟，將該 化合層去除，之後視所製造之電容結構為立體堆疊式電容 結構或是皇冠狀電容結構，而將部分留下之電容容器層留 下或去除；接著連續沉積上一介電層及一上電極板層。 枣紙浪尺度適用中國國家標隼（CNS ) A4規格{ 210X297公釐> 413940 經濟部中央棣準局貝工消费合作社印製 Λ7 發明説明（4) 圈式之簡單說明 第1圖係為本發明在製作晶圓基底之剖面圖，其顯 示一元成場氧化層（Field Oxide)、主動區（Active Area)、 字元線、擴散區、插栓、平坦化層和蝕刻阻絕層的堆疊 結構的步驟； 第2圖係為本發明在製作晶圓基底之剖面圖，其顯 示一依據第1圖定義一電容容器區後，接著沉積一下電 極板層的步驟； 第3圖係為本發明在製作晶圓基底之剖面圖，其顯 示一依據第2圖進行一使得反應層與下電極板層疊接部 份發生化合反應而成為化合層的升溫悴火步驟 (Annealing Process)步驟； 第4圖係為本發明在製作晶圓基底之剖面圖，其顯 示一依據第3圖進行高選擇比的蝕刻，去除化合層及電 容容器層的步驟； 第5圖係為本發明在製作晶圓基底之剖面圈，其顯 示一依據第4圖進行連續沉積儲存電容介電層及上電極 板的步驟。 第6圖係為本發明依據另一實施例製作晶園基底之 剖面圖，其顯示一完成場氧化層（Field Oxide)、主動區 (Active Area)、字元線、擴散區、平坦化層、蝕刻阻絕層、 插拴區圖形、電容容器層及反應層的堆疊結構的步驟； 第7圖係為本發明依據另一實施例製作晶圓基底之 剖面圖’其顯示一依據第6圊形成一電容容器區及插拴 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ί^-------訂------I (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 413940 A7 _____B7 五、發明説明（5) 區的步驟。 第8圖係為本發明依據另一實施例製作晶圓基底之 剖面圖’其顯示一依據第7圖形成一下電極板層及同時 形成插拴的步驟。 第9圖係為本發明依據另一實施例製作晶圓基底之 剖面圖’其顯示一依據第8圖於去除化合層後，進行連 續沉積儲存電容介電層及上電極板的步驟。 發明詳細說明 本發明係關於一積體電路電容添件的製造方法，為 方便說明，特別以動態隨機存取記憶體記憶單元的製造 為實施例。 請參閱第1圖，其顯示本發明之起始步驟。首先在 半導體基板8上形成一由場氧化層（Field 〇xicle)9所阻隔 之主動區（Active Area)10 ，接著形成二相鄰的字元線 12、擴散區11及位元線（未顯示）後，然後覆蓋上一平坦 化層14和餘刻阻絕層16，此二層之材料分別可為二氧 化矽和氮化矽。接著使用傳統的方法形成一摻雜的多晶 矽插栓13於二相鄰的字元線12之間，該插栓π的底端 和該擴散區11互相接觸。然後連續沉積上一電容容器層 18和反應層20，其中該電容容器層18可為二氧化矽材 質’該反應層20材質則選自於與後續下電極板材質會發 生化合反應者’若後續下電極板材質為矽材質時，則該 反應層材質可為金屬鈦（Τί)、鈷（Co)等材質，此處以金屬 鈦（Ti)為例。此時半導體基板已完成了製造儲存電容陣 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ 297公釐} (請先聞讀背面之注意事項再填寫本頁) 訂 B7 五、發明説明（6) 列的準備，緊接著可進行儲存電容的製造。 記憶單元通常由二個儲存電容所組成，儲存電容藉 由該插栓13而與基板中的該擴散區11導通。該擴散區 U藉由該字元線12所形成的場效電晶體而與位元線互 相連接。記憶單元之間則是以一厚的場氧化層9來區隔 開。擴散區11的主要功能為活化（Active)場效電晶體， 其可視設計上的需要摻雜為N型或P型的場效電晶體。 經濟部中央榡準局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 請參閱第2圖，以傳統曝光、顯影、蝕刻的方法留 下部分該反應層20’和該電容容器層18’，來定義一電容 容器區22，該插栓13的頂端則顯露於該電容容器區22 的底部區域，以使後續之儲存電容能經由該插栓13而與 該擴散區11導通。其中該電容容器層18’的厚度決定於 所需的該電容容器區22高度，而該電容容器區22的高 度則決定於所需的儲存電容值大小，於是藉由設計上所 要求的電容值大小，便可決定該電容容器層18’的厚度。 接著以低溫化學氣相沉積法（CVD)沉積一下電極板層 24，使其可順應性的覆蓋於該電容容器區22及該反應層 20’上。該下電極板層24可採用同步摻雜沉積（In-situ Doped deposition)或是沉積完成後再播雜，例如擴散 (Diffusion)、離子植入（Ion Implanted)等的方式所沉積的 非晶梦層（Amorphous Silicon)或多晶石夕廣（Ploy Silicon)。 請參閲第3囷，進行一升溫淬火步驟（Annealing Process)，升溫至該反應層20’與該下電極板層24疊接的 部份發生化.合反應的溫度以上，使得該二層發生化合反 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央橾牟局貝工消费合作社印製 413940 Λ7 B7 五'發明説明（7) — 應而成為化合層32，於此該化合反應溫度為6001^以 上，而生成之該化合層為二矽化鈦材質（TiSi2)，且該下 電極板層均將完全結晶為多晶石夕（Ploy Silicon)材質。而若 是前述沉積步驟採用高溫化學氣相法沉積下電極板層24 時，其沉積之溫度若已足以使該反應層20’與該下電極板 層24(第2圖）疊接部份直接發生化合反應時，如此則可 省略該升溫淬火步驟（Annealing Process)。 請參閱第4圖’使用一於二矽化鈦材質與多晶砂材 質間具有高選擇比的蝕刻步驟來進行蝕刻，此處以氣氣 酸為例’氫氟酸可蝕刻二氧化矽與二氧化鈦材質，而幾 乎不會蝕刻多晶矽材質及氮化矽材質；將前述第3 驟所完成之基底以氫氟酸蝕刻，去除該二矽化妖層32& 該電容容器層18’，於是形成了容器狀多晶矽儲存電容之 下電極板42。 請參閱第5圖’於已形成之該容器狀多晶石夕储存電 容之下電極板42上連續沉積儲存電容介電層52及上電 極板54 ，其中該電容介電層52之可為氧化矽/氮化石夕〆 氧化梦（ΟΝΟ ； Oxide/Nitride/Oxide)、氧化石夕/氮化石夕 (ON ； Oxide/Nitride)或氧化组（Ta2〇5)等高介電係數材 料’該上電極板54則為同步摻雜沉積（in_situ D〇ped deposition)之多晶矽材料’如此便完成了動態隨機存取記 憶體記憶單元之皇冠狀（Crown type)結構儲存電容的製 造。 本發明的另一實施例可將上述實施例中之插栓13於 本紙張尺度適用中國國冬榡準（CNS )六4说格（210X297公釐） -ί衣— {諳先閲讀背面之注意事項再填寫本頁 訂- * 413940 A7 B7 五、發明説明（8) 形成電容容器區及沈積下電極板層時同時形成，而不需 如前述第1圖般預先完成’其餘步驟則與上述實施例相 同；詳細步驟請參閱第6囷，其顯示如前述第1圖般於 半導體基板8上形成一由場氧化層（Field Oxide)9所阻隔 之主動區（Active Area)10 ’接著形成二相鄰的字元線 12、擴散區11及位元線（未顯示）後，覆蓋上一平坦化層 14和蝕刻阻絕層16，而與前述第1圖步驟所不同者為此 時並不預先完成插拾13 ’而僅用傳統的方式，將插拴區 圊形61預先完成於該餘刻阻絕層16上，然後連續沉積 上一電容容器層18和反應層20。 請參閱第7圖，以傳統曝光、顯影、蝕刻的方法來 製成一電容容器區71，此時繼續該蝕刻步驟，由於姓刻 阻絕層16阻絕的緣故’因此該蝕刻步驟將依該插栓區圖 形61所定義的區域内繼續蝕刻該平坦化層至該擴散 區11表面，而形成一插拾區72。 經濟部中央標準局負工消费合作杜印製 (請先閲讀背面之注意事項再填寫本頁) 請參閱第8圖，以化學氣相沉積法（CVD)沉積一下電 極板層81，使其可順應性的覆蓋於該電容容器區71、 該反應層20及該插拴區72上；若該後拾區71之寬度小 於該下電極板層81沈積厚度的二倍時，該插拴區71將 完全為該下電極板層81所填滿，形成插栓82 ;而若該 插拴區71之寬度大於該下電極板層81沈積厚度的二倍 時’該插拴區71將無法為該下電極板層81所填滿，於 是形成一中空插拴（未顯示）；但無論該插拴是否完全填 滿，其均可確保儲存電容與基板中的該擴散區11導通。 本紙張尺度適用中國國家標準（CNS ) A4現格< 210X2?7公釐） 413940 Α7 Β7 五、發明説明（9) 接著進行相同於第3圖至第5圖之步驟，使該反應層與 該下電極板疊接部份發生化合反應形成化合層，去除該 化合層及該電容容器層’接著沈積電容介電層及上電極 層以完成動態隨機存取記憶體記憶單元之皇冠狀（Crown type)結構儲存電容的製造，為簡化起見於此不再重複贅 述。 請參閱第9圈’其為本發明之另一實施例_立體堆疊 式電容結構-之製程結果，相同於前述之二實施例中的所 有步驟’其中所不同者為於該化合層^2(第3圖）形成後， 並不將該化合層及該部分留下之電容容器層18,一同去 除’僅以選擇性蝕刻方式去除該化合層32，而仍留下該 部分留下之電容容器層18，，接著連續沉積電容介電層及 上電極層’如此所完成者為立體堆疊式電容結構。 雖然本發明已揭露實施例如上，然其並非用以限定 本發明，任何熟悉此技藝者，在不脫離本發明之精神和 範圍内’當可做些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 ----------------1Τ------Γ— (請先閩讀背而之；逆意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 本紙張尺度適用中國國家標隼（CNS ) Α4規格（210X297公釐）Bn · — fll · flilt n (Please read the notes on the back before filling this page) -Φ. 413940 A7 _________B7 V. Description of the invention (3) Complete the manufacturing method of the three-dimensional stacked capacitor structure. Another object of the present invention is to provide a method for manufacturing a Crown type capacitor structure without depositing a sacrificial layer. (Jingxian first read the notes on the back and then fill out this page) Another object of the present invention is to provide a method for manufacturing a three-dimensional stacked capacitor structure using a combination reaction and selective etching. Another object of the present invention is to provide a method for manufacturing a Crown type capacitor structure by using a combination reaction and a selective remainder. The main process of the present invention includes the following steps: forming a plurality of field oxide layers, a plurality of word lines, a plurality of diffusion regions, and a plurality of bit lines on a semiconductor substrate; and then covering a planarization layer and an etch stop layer And forming a plurality of doped polycrystalline silicon inserts that are in contact with each other at the bottom and the plurality of diffusion regions. Next, a capacitor container layer and a reaction layer are deposited. Then, the capacitor container layer and the reaction layer are partially left by lithography and etching to define a plurality of capacitor container areas, and the tops of the plurality of plugs are exposed in the plurality. A bottom area of each capacitor container area; and a compliance layer is deposited on the plurality of capacitor container areas and the electrode layer above and below the reaction layer. Printed by the Central Bureau of Standards of the Ministry of Economic Affairs of the Bayer Consumer Cooperative, the focus of the present invention is then carried out, and a compounding reaction step is performed so that the reaction layer left in this part reacts with the overlapping part of the lower electrode plate layer to produce a compound A selective etching step is followed by removing the compound layer, and then depending on whether the capacitor structure is a three-dimensional stacked capacitor structure or a crown-like capacitor structure, leaving or removing part of the remaining capacitor container layer; Then, a dielectric layer and an upper electrode plate layer are successively deposited. The jujube paper wave scale is applicable to the Chinese National Standard (CNS) A4 specification {210X297 mm > 413940 Printed by the Central Laboratories Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, Λ7 Description of the invention (4) A simple description of the circle type Figure 1 is for this The invention is a cross-sectional view of a wafer substrate, which shows a stacked structure of a field oxide layer (Field Oxide), an active area, a word line, a diffusion area, a plug, a planarization layer, and an etch stop layer. Step 2 is a cross-sectional view of a wafer substrate in the present invention, which shows a step of depositing an electrode plate layer after a capacitor container area is defined according to FIG. 1; A cross-sectional view of a wafer substrate, which shows an Annealing Process step performed in accordance with FIG. 2 to make a reaction between the reaction layer and the lower electrode plate laminate portion to become a combined layer; FIG. 4 is The present invention is a cross-sectional view of a wafer substrate, which shows a step of etching with a high selectivity according to FIG. 3 to remove the compound layer and the capacitor container layer. The bezel shows a step of continuously depositing a storage capacitor dielectric layer and an upper electrode plate according to FIG. 4. FIG. 6 is a cross-sectional view of a crystal substrate according to another embodiment of the present invention, which shows a completed field oxide layer, an active area, a word line, a diffusion area, a planarization layer, Steps of etching a stacked structure of a barrier layer, a plug region pattern, a capacitor container layer, and a reaction layer; FIG. 7 is a cross-sectional view of a wafer substrate made according to another embodiment of the present invention, which shows that a The size of the capacitor container area and the plug are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ί ^ ------- Order ------ I (Please read the precautions on the back before filling (This page) Printed by 413940 A7 _____B7, Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. The steps in the description of the invention (5). FIG. 8 is a cross-sectional view of a wafer substrate according to another embodiment of the present invention. It shows a step of forming a lower electrode plate layer and forming plugs at the same time according to FIG. 7. FIG. 9 is a cross-sectional view of a wafer substrate according to another embodiment of the present invention. It shows a step of continuously depositing a storage capacitor dielectric layer and an upper electrode plate after removing the compound layer according to FIG. 8. Detailed Description of the Invention The present invention relates to a method for manufacturing an integrated circuit capacitor add-on. For convenience of explanation, the manufacture of a dynamic random access memory memory cell is taken as an example. Please refer to Fig. 1, which shows the initial steps of the present invention. First, an active area 10 blocked by a field oxide layer 9 is formed on the semiconductor substrate 8, and then two adjacent word lines 12, diffusion areas 11, and bit lines (not shown) are formed. ), And then cover the planarization layer 14 and the remaining resist layer 16, the materials of these two layers may be silicon dioxide and silicon nitride, respectively. Then, a doped polysilicon plug 13 is formed by using a conventional method between two adjacent word lines 12, and the bottom end of the plug π and the diffusion region 11 are in contact with each other. Then, a capacitor container layer 18 and a reaction layer 20 are successively deposited. The capacitor container layer 18 may be made of silicon dioxide. The material of the reaction layer 20 is selected from those who will react with the material of the subsequent lower electrode plate. When the material of the lower electrode plate is made of silicon, the material of the reaction layer may be made of titanium (T), cobalt (Co), or the like. Here, titanium (Ti) is used as an example. At this time, the semiconductor substrate has completed the manufacture of the storage capacitor array. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) (please read the precautions on the back before filling this page). Order B7 V. Description of the invention ( 6) The preparation of the column can be followed by the manufacture of the storage capacitor. The memory unit is usually composed of two storage capacitors, and the storage capacitor is connected to the diffusion region 11 in the substrate through the plug 13. The diffusion region U borrows The field effect transistor formed by the word line 12 is connected to the bit line. The memory cells are separated by a thick field oxide layer 9. The main function of the diffusion region 11 is active (Active ) Field-effect transistor, which can be doped with N-type or P-type field-effect transistor according to the design requirements. ) Please refer to FIG. 2, a portion of the reaction layer 20 ′ and the capacitor container layer 18 ′ is left by conventional exposure, development, and etching methods to define a capacitor container region 22, and the top of the plug 13 is exposed in the capacitor container region 22 ′. Capacitor container area 22 bottom Region, so that subsequent storage capacitors can communicate with the diffusion region 11 through the plug 13. The thickness of the capacitor container layer 18 'is determined by the required height of the capacitor container region 22, and the The height is determined by the required storage capacitance value, so the thickness of the capacitor container layer 18 'can be determined by the required capacitance value in the design. Next, the electrode is deposited by low temperature chemical vapor deposition (CVD). The plate layer 24 allows it to conformably cover the capacitor container region 22 and the reaction layer 20 '. The lower electrode plate layer 24 may be deposited by synchronous doping (In-situ Doped deposition) or after the deposition is completed. Dopant, such as Amorphous Silicon or Polyoy Silicon deposited by means of diffusion, Ion Implanted, etc. Please refer to Section 3, for a Annealing process, the temperature rises to the part where the reaction layer 20 'overlaps with the lower electrode plate layer 24. The temperature of the reaction is above the temperature of the reaction, so that the two layers are combined. Standard (CNS) A4 (210X297 mm) Printed by the Central Labor Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 413940 Λ7 B7 Five 'Invention Description (7) — It should become the compound layer 32, where the reaction temperature is 6001 ^ Above, the resulting compound layer is made of titanium disilicide (TiSi2), and the lower electrode plate layer will be completely crystallized into polycrystalline silicon (Ploy Silicon) material. If the foregoing deposition step is performed by high temperature chemical vapor deposition When the lower electrode plate layer 24 is deposited at a temperature sufficient to cause the reaction reaction between the reaction layer 20 'and the overlapping portion of the lower electrode plate layer 24 (Figure 2) directly, the heating and quenching step may be omitted. (Annealing Process). Please refer to Fig. 4 'Etching using an etching step with a high selectivity ratio between titanium disilicide material and polycrystalline sand material. Here, taking gas acid as an example', hydrofluoric acid can etch silicon dioxide and titanium dioxide materials. Polycrystalline silicon and silicon nitride materials are hardly etched; the substrate completed in the third step is etched with hydrofluoric acid to remove the disilicide layer 32 & the capacitor container layer 18 ', and a container-like polycrystalline silicon storage is formed. Electrode plate 42 under the capacitor. Please refer to FIG. 5 'continuously depositing a storage capacitor dielectric layer 52 and an upper electrode plate 54 on the electrode plate 42 of the container-shaped polycrystalline silicon storage capacitor that has been formed. The capacitor dielectric layer 52 may be oxidized. Oxide / Nitride / Oxide, Oxide / Nitride, or Oxide / Nitride or Ta205, etc. The plate 54 is a polycrystalline silicon material of in-situ doped deposition. This completes the manufacture of a Crown type storage capacitor for a dynamic random access memory memory cell. In another embodiment of the present invention, the plug 13 in the above embodiment can be applied to the standard of Chinese National Winter Criterion (CNS) 64 (210X297 mm) at this paper scale-衣衣-{谙 Read the note on the back first Please fill in this page to order-* 413940 A7 B7 V. Description of the invention (8) It is formed at the same time when the capacitor container area and the lower electrode plate layer are formed, and it does not need to be completed in advance as in the first figure above. The remaining steps are the same as the above implementation. The example is the same; see step 6 for detailed steps. It shows that an active area 10 'blocked by a field oxide layer 9 is formed on the semiconductor substrate 8 as shown in the first figure, and then a two-phase is formed. After the adjacent word line 12, the diffusion area 11, and the bit line (not shown), the planarization layer 14 and the etch stop layer 16 are covered, and the difference from the step in the first figure above is not completed at this time. The plug 13 ′ is completed in a conventional manner only by inserting the plug region 圊 61 on the remaining resist layer 16 in advance, and then continuously depositing a capacitor container layer 18 and a reaction layer 20. Please refer to FIG. 7, a capacitor container region 71 is made by the conventional exposure, development, and etching methods. At this time, the etching step is continued. Because the resist layer 16 is blocked by the last name, the etching step will follow the plug. In the area defined by the area pattern 61, the planarization layer is continuously etched to the surface of the diffusion area 11 to form an insertion area 72. Du printed by the Central Bureau of Standards, Ministry of Economic Affairs and Consumer Cooperation (please read the notes on the back before filling this page) Please refer to Figure 8 to deposit the electrode plate layer 81 by chemical vapor deposition (CVD) so that it can be used. Compliantly covers the capacitor container area 71, the reaction layer 20, and the plug area 72; if the width of the back pick-up area 71 is less than twice the thickness of the lower electrode plate layer 81, the plug area 71 Will be completely filled with the lower electrode plate layer 81 to form a plug 82; and if the width of the plug region 71 is greater than twice the thickness of the lower electrode plate layer 81, the plug region 71 will not be the The lower electrode plate layer 81 is filled, so a hollow plug (not shown) is formed; however, whether the plug is completely filled or not, it can ensure that the storage capacitor is electrically connected to the diffusion region 11 in the substrate. This paper scale applies Chinese National Standard (CNS) A4 now <210X2? 7 mm) 413940 Α7 Β7 V. Description of the invention (9) Then follow the same steps as in Figures 3 to 5 to make the reaction layer and A compounding reaction occurs in the overlapping portion of the lower electrode plate to form a compounding layer. The compounding layer and the capacitor container layer are removed, and then a capacitor dielectric layer and an upper electrode layer are deposited to complete the crown shape of the dynamic random access memory memory unit. The manufacturing of a type) structure storage capacitor is not repeated here for the sake of simplicity. Please refer to the ninth circle, 'This is another embodiment of the present invention _ three-dimensional stacked capacitor structure-process results, the same as all the steps in the previous two embodiments' where the difference is in the compound layer ^ 2 ( (Figure 3) After the formation, the compound layer and the capacitor container layer 18 left in the part are not removed together, and the compound layer 32 is only removed by selective etching, while the capacitor container left in the part is still left. Layer 18, and then successively depositing a capacitor dielectric layer and an upper electrode layer. Thus, the completed structure is a three-dimensional stacked capacitor structure. Although the embodiments of the present invention have been disclosed above, they are not intended to limit the present invention. Anyone familiar with the art can do some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention It shall be subject to the definition in the appended patent application scope. ---------------- 1Τ ------ Γ— (please read it first; fill in this page if you are against it) The paper size printed by the cooperative is applicable to China National Standard (CNS) Α4 specification (210X297 mm)