TW413900B - Method for forming conductive structure capable of decreasing the resistance - Google Patents

Abstract

There is disclosed a method for forming conductive structure on a semiconductor substrate and decreasing the resistance thereof. The method comprises the steps of: forming a dielectric layer on the semiconductor substrate and etching the dielectric layer to form a contact hole, wherein the contact hole exposes the upper surface of the semiconductor substrate; forming conductive structure in the contact hole; removing part of the dielectric layer to increase the exposed surface area of the conductive structure on the dielectric layer.

Description

413900 A7 ________B7_ V. Description of the invention () Field of the invention: The present invention relates to a semiconductor device, especially a method for manufacturing a low-resistance conductive structural element. Background of the Invention: With the continuous development of semiconductor technology, wafer fabrication The technology has a trend towards high density. And by reducing the size of various components in the wafer, a semiconductor 1C device with a high integration density is also effectively completed. However, in this 1C manufacturing process, it also faces many difficulties and challenges. Generally speaking, in the internal structure of the integrated circuit, millions of components are often connected to perform the specific function required. Therefore, the performance of the integrated circuit depends on the performance and reliability of various components in its structure. For each component, an interconnect structure is required to exchange the electronic signal β between the components. What's more important is that as the integration degree of the semiconductor manufacturing process continues to increase, the current design of integrated circuits is moving toward The trend of multiple interconnections. In this multiple interconnect structure, a large number of conductive vias are used between the conductive plugs (contact) and the dielectric layer. Please refer to the first figure. In the prior art, the process of interconnect structure was often formed by forming a halide-like dielectric layer 102 on the semiconductor substrate 100 to achieve isolation β. Then, by using a conventional lithography Technology, a contact layer is formed on the dielectric layer 102, and then a conductive layer is formed. This paper is applicable to the national standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page ) Order-1 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 413900 Α7 Β7 V. Description of the invention (110) on the dielectric layer ι02 'and filled in the formed contact hole. Then, the conductive layer 110 is polished by a chemical mechanical polishing (CMP) process using a well-known technology until it reaches the dielectric layer 102. In this way, a desired interconnect structure can be formed, in which the interconnect structure Ho is the residual conductive layer in the contact hole. It is worth noting that in order to meet the requirements of reducing the size of the component to improve the accumulation, the width of this contact hole is often smaller than before.4 However, this also makes the subsequent formation of interconnecting structures (ie, conductive plugs). (Or the connection between dielectric layers), 'often unable to effectively control its yield, and the resulting interconnect structure has a great resistance value', which reduces the efficiency of the electrical connection and reduces the "Performance has a bad effect" "Especially when the component size has fallen below the sub-Hui meter, the operating voltage of various components has also decreased. How to reduce the resistance value of the interconnect structure becomes the problem when manufacturing integrated circuits A big challenge. OBJECT AND SUMMARY OF THE INVENTION The object of the present invention is to provide a method for making a conductive structure with low resistance on the side. The manufacturing method can make the conductive structure to be manufactured have a larger surface area than that formed by the conventional technology. By increasing the surface area above the conductive structure, the resistance value of the conductive structure can be effectively reduced. A kind of low-resistance conductive structure made on a semiconductor substrate. This paper U is suitable for China National Standards (CNS) Congxie (2IGX297 public celebration) (Please read the precautions on the back before filling out this page. Order ψ *- The Ministry of Economic Affairs Zhizhi Property Bureau 8 工 消 # Cooperative print 413900 A7 B7 V. The method of the invention description includes the following steps. First, a dielectric layer is formed on a semiconducting hip substrate, and the dielectric layer is etched to A contact bar is formed, wherein the contact hole exposes the upper surface of the semiconductor substrate. Then, a conductive layer is formed on the dielectric layer and filled in the contact hole. Then, a chemical mechanical polishing process is performed to grind the dielectric layer. A conductive layer on the surface; a chemical mechanical polishing process is performed on the dielectric layer to remove a portion of the dielectric layer and form a conductive structure with a dome-shaped upper surface; thus, by increasing the upper surface area of the conductive structure, It can effectively reduce its resistance value. Brief description of the formula By the following detailed description combined with the attached drawings, the above content and the many advantages of this invention can be easily understood, of which: One image is a cross-sectional view of a semiconducting wafer, showing the steps for forming a conductive structure on a semiconducting heterosubstrate according to conventional techniques. The second image is a cross-sectional view of a semiconducting wafer, showing the definition of a dielectric layer according to the present invention. The step of exiting the contact hole; the third figure shows the step of forming a conductive layer on the substrate of Fengdao Zhao according to the present invention; the fourth circle shows the cross section of the semiconductor wafer according to the present invention. Steps for forming a conductive structure on the substrate of the ship; and the fifth figure is a data circle showing the comparison of the resistance value of the conductive plug formed according to the present invention and the conductive plug formed by the conventional technology. This paper Compensation system CNS) MY Secret (Training \ 297) and (please read the notes on the back before filling this page) Order the Intellectual Property Bureau of the Ministry of Economic Affairs to print 413900 A7 B7 V. Description of invention () Invention Detailed description: The present invention provides a new method for manufacturing a conductive plug with a rounded upper surface. Increasing the surface area of the conductive plug by grinding the dielectric layer can effectively reduce the upper surface resistance value (RtQp); and because the dielectric layer is polished, the thickness of the dielectric layer is reduced. The resistance value (RpUg) of the conductive plug formed below will also decrease accordingly, which can effectively reduce the resistance value of the interconnect structure formed. A detailed description of the present invention is as follows. Referring to the second figure, in a preferred embodiment, a single crystal silicon substrate 100 with < 100 > crystal orientation is provided. Next, a dielectric layer 102 is formed on the semiconductor substrate 100 to generate an insulation effect β. What is to be explained here is that before the formation of the dielectric layer 102, the various types required for manufacturing integrated circuits have been formed on the surface of the semiconductor substrate 100. Active components, passive components, and peripheral circuits. In a preferred embodiment, the dielectric layer 102 may be formed of silicon oxide or silicon nitride. In general, using chemical vapor deposition (CVD) with tetraethyl oxalate (TEOS) can form silicon oxide at a temperature of about 600 to 800 ° C and a pressure of about 1 1 0 rr; or Thermal oxidation is used to form silicon oxide. As for silicon nitride, it is about 400 to 450. It is formed in the furnace of C, and the reaction gases in the process are SiH4, N2O and NH3. In addition, tetraethyl silicate (TEOS) can also be used as a reaction material, and boron and phosphorus atoms can be added to form borophosphine dream glass (BPS G) by low pressure chemical vapor deposition (LPCVD) as the above medium. Electrical layer 102. It is worth noting that all paper sizes are in use ® Bacteria Standard (CMS) Α4 grid (210X29 "? mm) (Please read the notes on the back before filling out this page to order-1 Printed by the Bureau of Industrial and Consumer Cooperatives 413900 A7 ____B7 V. Description of the invention () The dielectric layer 102 formed has a thickness of about 4,000 angstroms to 6500 angstroms, and in a preferred embodiment, the dielectric layer 102 is formed. The thickness is 5500 Angstroms β. Next, the contact hole 103 can be defined on the dielectric layer 102 by conventional lithography and etching techniques to expose the semiconductor substrate 100 above. First, 'a photoresist can be formed on the dielectric layer 102 to define the contact hole pattern' and used as a single screen for the subsequent etching process * then the dielectric layer 102 is subjected to a engraving process to form a contact hole. 103 on the semiconductor substrate 100 ^ In the preferred embodiment, plasma holes can be used to form contact holes 103, where CC12F2, CHF3 / CF4 can be selected as the etch agent for removing the oxide dream. , CHF3 / 0 :, CH ^ CHF :, CF4 / 〇2. As for the etchant used to remove silicon nitride, you can choose CF4 / H, CHF, or CH CHF. Please refer to the third figure. A conductive layer 104 is formed on the dielectric layer 102 and the semiconductor substrate 100, and is filled in the contact hole 103. The formation of the conductive layer 104 can be well known. Technology, such as physical vapor deposition (PVD), sputtering, and other similar processes are deposited on the semiconductor substrate 100. In addition, the material of the conductive layer 104 can be aluminum, titanium, tungsten, copper, gold, platinum, alloy Or polycrystalline silicon, etc. "In a preferred embodiment, a chemical vapor deposition (CVD) method can be used to form a tungsten metal layer with WF6 and H2 as the reaction gas at a temperature of about 400 to 500 ° C as the conductivity. Layer 104. Subsequently, a portion of the conductive layer 104 'is removed to expose the upper surface β of the dielectric layer 102. In a preferred embodiment, chemical mechanical polishing can be used. CNS Α4 Specification (2 丨 0X297mm> (Please read the precautions on the back before filling out this page)-Ordered by the Intellectual Property Bureau Employee Consumption Cooperative of the Ministry of Economy 413900 Employee Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printing A 7 ____B7 V. Description of Invention () (CMP) The conductive layer 104 is polished until it reaches the dielectric layer 102. Then, a 'chemical mechanical polishing process is performed on the dielectric layer 102 to remove a portion of the dielectric layer 102', so as to obtain the fourth figure The conductive plug 106 and the residual dielectric layer 102 are shown. The thickness of the residual dielectric layer is about 3000 angstroms to 4500 angstroms, and 3685 angstroms in a preferred embodiment. It is worth noting that grinding After the procedure, the top surface 108 of the conductive plug 106 will be at least 700 angstroms higher than the upper surface of the dielectric layer 102. It is worth noting that during the polishing process for the dielectric layer 102, the conductive plug 106 located in the contact hole is also ground away. However, the speed of removing the conductive plug 106 is less than that of removing the dielectric. The speed of the layer 102 is such that after the grinding process is completed, the conductive plug formed will have a dome-shaped upper surface 108. In this way, since the dome-shaped upper surface 108 has a larger contact area, the resistance value of the conductive plug 106 can be effectively reduced. Please refer to the first section, which shows the conductive plug 110 formed by the conventional method. The contact area of the horizontal upper surface is obviously smaller than the conductive plug 106 formed by the method of the present invention. It is based on the conventional technology that the conductive plug 110 has a higher resistance value. Generally speaking, the total resistance value (Rc) of the conductive plug is equal to the surface resistance value (Rbntt.) And the upper surface resistance value of the conductive plug. The sum of the resistance value (Rlep) and the resistance value of the conductive plug itself (Rplug), where the resistance value of the conductive plug itself (RPue) and the length of the conductive plug are different. Please refer to the fifth figure, which shows the resistance value of the conductive plug 106 formed by using the present invention (Please read the precautions on the back before filling this page) 1C. Order

I C This paper size is applicable to the Chinese National Standard (CNS) A4 washing grid (210X297)

Claims (1)

413900 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs of the Bayer Consumer Cooperative Association 3 !. AS B8 C8 D8々, patent application scope 1. A method for manufacturing a conductive structure with low resistance on a semiconductor substrate, the method includes at least the following steps: forming A dielectric layer on the semiconductor substrate; etching the dielectric layer to form an opening in the dielectric layer, wherein the opening is used to expose the upper surface of the semiconductor substrate; forming a conductive structure in the opening; and moving Excluding part of the dielectric layer to increase the surface area of the conductive structure exposed on the upper surface of the dielectric layer, and the upper surface of the conductive structure is at least about 700 angstroms higher than the upper surface of the dielectric layer. 2. The method according to item 1 of the scope of patent application, wherein the above-mentioned dielectric layer is composed of silicon oxide. 3. The method of claim 1 in which the above-mentioned dielectric layer is composed of silicon nitride. 4. The method according to item 1 of the patent application, wherein the above-mentioned dielectric layer is composed of borophosphosilicate glass. 5. The method according to item 1 of the patent application group, wherein the above-mentioned conductive structure is a conductive plug (plug ) »6. If the method of the first item of the scope of patent application, the material of the above conductive structure can choose aluminum, titanium, tungsten, copper 'gold' platinum, alloy, polycrystalline * Xi (Please read the precautions on the back before (Fill in this page) 10 This paper is used in China's National Standard (CNS) A4 specification (210X297 mm) 4139〇〇 Patent application scope or any combination thereof. 7. For the method of applying for item I of the patent scope, wherein the above-mentioned conductive structure is a dielectric interlayer connection (via). 8. The method according to item 1 of the scope of patent application, in which the step of removing the dielectric layer described above is performed using a chemical mechanical polishing method. 9 The method according to item 丨 of the Patent Application Group, wherein the process of removing part of the dielectric layer can increase the surface area of the conductive structure and reduce the surface resistance value of the conductive structure. 10. The method according to item 1 of the patent application scope, wherein after removing a part of the dielectric layer, the residual dielectric layer has a thickness of about 300 angstroms to 4500 angstroms. 11. The method according to item 1 of the scope of patent application, wherein the conductive structure has a do-me-shaped upper surface after removing a part of the dielectric layer. Printed by a cooperative 12. A method of manufacturing a conductive plug with low resistance on a semi-conductive substrate, the method includes at least the following steps: forming a dielectric layer on the semiconductor substrate; etching the dielectric layer to form A contact hole is formed on the dielectric layer, wherein the contact hole is used to expose the upper surface of the semi-conductor substrate; a conductive plug is formed in the contact hole; and the scale of this paper is in accordance with the Chinese Standard for Crisis (CNS) M Specification (210 × 297 male shame) 413900 b | D8 Sixth, the patent application process is performed to remove part of the dielectric layer and form a conductive plug with a dome-shaped upper surface, where the ffl The top table above shows that the central government of the Ministry of Economic Affairs, the Central Bureau of the Bureau of the Male Workers Consumer Cooperatives, printed electricity and electricity plugged in the Ministry of Electricity to obtain the transfer of the dielectric dielectric crystals with a lower percentage. Describing the description, the description α · 0 divided and up, up, up, up, down, up, down, up, down, up, down, up, down, up, down, up, up, up, up, up, up, up, up, up, down, up, up, up, up, up, up, up either continuously, long, long, long, long, long, long, long, long, long, long, long, long, long, long, long, long, long, long, long, long, long, long, long, long, long. The beginning, the law, the law, the law, the law, the law, the law, the law, the law, the law, the law, the law, the science of the items, the items, the copper items, the machine, the plug 2 2 2 2 2 2 Learn 2 Insert 1111 111. No. No. No. Tungsten No.) · No. No. Electric surface surrounding. Fan, Fan, Fan, Fan, Fan, Fan, Fan, Ti, Fan (V Fan, Fan Fan should be good. Lee. Profit structure, profit line profit is Leica's Concession College, Is, Special Speed, Special Training Please add a layer, please construct the glass, please choose. Please step by step, please apply for the application of the application, and apply for the application of the application, such as silicon, silicon, silicon, silicon, can be assembled, such as electricity, such as the process. .Chemical.Phosphorus.Dielectric is expected to be 13 oxygen, 14 nitrogen, 15 boron, 16 materials, any 17 is 18 medium, and 19 layers are high. You can plug the electric surface layer or plug (see the back of the first Note: Please fill in this tile again.) This paper size is not used in China's National Standard (CNS) A4 specification (210X 29? Mm) The scope of patent application fl39G〇 The surface resistance value on the conductive plug. ^ 20. The method according to item 12 of the scope of patent application, wherein after removing part of the dielectric layer, the remaining dielectric layer has a thickness of about 3000 angstroms to 4500 angstroms. 21. The method of claim 12 in which the dome-shaped upper surface of the conductive plug is at least about 700 angstroms higher than the upper surface of the dielectric layer. 22. —A method of manufacturing a conductive plug with low resistance on a semiconductor substrate, the method including at least the following steps: forming a dielectric layer on the semiconductor substrate; engraving the dielectric layer to form a contact hole On the dielectric layer, the contact hole is used to expose the upper surface of the semiconductor substrate; a conductive layer is formed on the dielectric layer and filled in the contact hole, and a part of the conductive layer is removed until it reaches Up to the upper surface of the dielectric layer; and removing a portion of the dielectric layer to form a conductive layer having a dome-shaped upper surface, and the dome-shaped upper surface of the conductive layer is higher than the dielectric layer On the surface. 23. For the method of claim 22 in the scope of patent application, the material of the conductive layer can be selected from the group consisting of inscription, defect, medium, copper, gold, diamond, alloy, polycrystalline dream, or any combination thereof. 24. If you apply for the method in item 22 of the patent scope, in which the above-mentioned removal section is 13 paper scales freely using the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) Ordered by the Ministry of Economic Affairs, Shaoyang, Quasi-Bureau, Industrial and Consumer Cooperatives, 413900 n C8 D8. 6. The scope of patent application for this conductive layer is performed by chemical mechanical polishing. 25. For the method of applying for the scope of patent application No. 22, in which the step of removing the dielectric layer described above is performed using chemical mechanical polishing method β. 26. For the method of applying for the scope of patent application No. 22, where the removal The process of copying the dielectric layer can increase the surface area of the conductive plug and reduce the surface resistance value of the conductive plug. 27. The method of claim 22, wherein after removing part of the dielectric layer, the residual dielectric layer has a thickness of about 3000 angstroms to 4500 angstroms. 28. The method according to item 22 of the scope of patent application, wherein the dome-shaped upper surface of the above-mentioned conductive plug is at least about 700 angstroms higher than the upper surface of the dielectric layer (please read the precautions on the back before filling this page) Order! Printed by the Central Bureau of Standards, the Ministry of Economic Affairs, Shellfish Consumer Cooperative, S- This paper is standard in the use of a® home ladder standard (CNS) is 4 gauge ice (2 丨 0 × 297 mm)