TW413893B - Method for eliminating etching microloading effect by etching and depositing at the same location - Google Patents

Abstract

The present invention relates to a method for eliminating etching microloading effect by etching and depositing at the same location. The spirit of the present invention is to use a capping layer to cover both the substrate and the photoresist on the substrate before etching of the substrate in which the capping layer may be made of dielectric layer or polymer layer. Because the aspect ratio of the trench will limit the step coverage capability of the capping layer, and that of the photoresist is limited by the opening width, the depth of the capping layer at the bottom of narrow trench is smaller than the depth of the capping layer at the bottom of wide trench. Therefore, in the subsequent etching process, although the microloading effect will cause the etching speed in the wide trench to be faster than the etching speed in the narrow trench, the thick capping layer at the bottom of the wide trench may need more time to be etched. Accordingly, it is obvious that the etching microloading effect will be cancelled by the deposited capping layer, so as to make the wide trench and the narrow trench formed by etching to have the same depth.

Description

413893

The present invention relates to a method for eliminating etch microloading effect, and more particularly to a method for simultaneously forming a plurality of trenches having the same depth but different widths. 5-2 Background of the Invention: In most practical semiconductor manufacturing processes, there are many components on the ^ layer on the integrated circuit. When these components are formed by an etching process, the manufacturing process of these components includes at least the following Procedure: ^ First, 'a photoresist is formed on the surface of this layer, and the photoresist has many openings', where each opening has its own shape and size. Secondly, an etching process is performed on this layer to form a plurality of channels. Each channel corresponds to a specific opening. Then, the related subsequent processes are performed to form the required components. It must be noted that in integrated circuits with multi-layer structures, the distance between the corresponding two layers is fixed. Therefore, the depth of each trench must be trenched: the depth of other trenches is the same, otherwise the components that are not at the bottom are damaged by this trench (soil. == foot 24. There are some components in the first layer that have insufficient depth to damage the trench. "2 ' This is the basic limitation of the trench formation process. There is no conflict between this basic limitation and the basic technology of the plasma etching process. The etching microload effect conflicts with each other. The etching microload

413893 V. Description of the invention (2) ----- f should mean that when not all ions are incident perpendicularly to a substrate, the probability of the wide channel trench hitting the substrate is lower than that of the narrow channel trench. The mechanism of "Knowledge" further leads to a faster etching rate in the wide trench and a deeper depth in the wide trench. In the example shown in Figure 1A, the mechanism of the etch microload effect is briefly discussed. As shown in FIG. 1A, the dielectric layer is located on the substrate j ', and the substrate π includes at least a metal-oxide semiconductor and an isolation (isolati), and the integrated circuit is a In the case of an integrated circuit of a multilayer structure, the 'substrate π' further includes how many dielectric layers, a plurality of contacts (conntact), and a plurality of interconnects (interconnect). Moreover, a photoresist 112 is formed on the surface of the dielectric layer 10. The photoresist 12 has a first opening 13 and a first opening 14. The width of the first opening 13 is greater than the width of the second opening 14. Big. Since all the plasma reactors provided by the prior art cannot make all the plasmas, all the ions 15 in the reactor are perpendicularly incident on the dielectric layer. Therefore, the "second opening" 4 has a wider area, which effectively increases the probability of the collision reaction between the obliquely incident ions j 5 and the dielectric layer 10, which in turn leads to an etching rate of the second opening 14 that is higher than that of the first opening 13. The etch rate comes fast. This is the so-called micro-load effect. The effect of the recording micro-load effect can be illustrated with the first B diagram. Obviously, the first trench 16 corresponding to the first opening 13 is a shallow trench, and the second trench 17 corresponding to the second opening 14 is a deep trench. Therefore, instead of the second channel 1β7 just touching the substrate 11 and the first channel 16 has not yet touched the substrate 11, the first channel 16 just touches the substrate 11 and the second channel 17

Page 5 413893 V. Description of the invention (3) It has penetrated into the inside of the substrate 11 to increase the danger of the internal structure of the substrate being damaged. From the previous discussion, we can know that the micro-loading effect of etching will cause the adverse effects of strict species, so it must be developed-a method that can form many trenches with the same depth but different widths at the same time. 5-3 Purpose and Summary of the Invention: The main object of the present invention is to provide an efficient and feasible method for simultaneously forming a wide trench and a narrow trench with the same depth. Another object of the invention is to provide a method for forming a plurality of different trenches having the same depth by first forming a cover layer 'on the photoresist. Another object of the present invention is to provide a method that can not only eliminate the lack of etching micro-load response, but also maintain a high throughput. In order to achieve the purposes of the present invention, a method capable of eliminating the lack of etching micro-load effect The method is proposed. In this method, before the etching process is performed, a cover layer is used to cover the substrate and the photoresist on the substrate simultaneously. Since the trench aspect ratio will limit the step coverage that the cover layer can achieve: in terms of photoresistance, the width of the opening is limited, so the thickness of the overlay layer at the bottom of the narrow opening will be smaller than that at the bottom of the wide opening The thickness of the layer. Therefore, in the process, although the micro-load effect of the last name will cause the etching rate seen in the opening to be faster than the etching rate in the narrow opening, but this

$ 6 pages 413893 V. Description of the invention (4) The thick cover layer at the bottom of the wide opening also requires more time to etch. Therefore, the micro-load effect of the etching will be significantly offset by the deposited cover layer, so that the depth of the wide trench and the narrow trench formed by the etching is the same.

413893 V. Description of the invention (5) 203 Drain 204 Closed pole 21 Dielectric layer 22 Photoresist 23 First opening 24 Second opening 25 Narrow contact hole complex 26 Wide trench groove 27 Cover layer 28 Narrow contact hole 29 Wide Detailed description of the trench 5 invention: In order to explain in detail in the following paragraphs, an integrated circuit manufacturing process will be described in which the narrow contact hole is separated from the first, such as the second A containing isolation 201 and gold oxide 204. A dielectric layer 21 is then formed. In addition, the 'substrate 20' further has a plurality of interconnects. In the present invention, as shown in the drawings where the wide trench is formed at the same time, the semi-transistor material layer 21 is out of the bottom. When the product includes the steps of one of the preferred embodiments, it will be explained. In this embodiment, the methods of narrow contact holes and wide trenches have the same depth. For the substrate 20, the substrate 20 includes at least the source electrode 20, the drain electrode 203, and the gate electrode 20 to form a photoresist 22. The bulk circuit is a multilayer integrated circuit dielectric layer. Contact with

Page 8 413893 V. Description of the invention (6) Second, as shown in the second figure B, a photolithographic etching process is performed on the photoresist 22 to form the first opening 23 and the second opening 24 in the photoresist 22 'Where the width of the first opening is W3 and the width of the second opening is W4, and the width of the second opening W4 is larger than the width of the first opening ff3. Incidentally, the thickness of the photoresist 22 is about several angstroms to several micrometers. Third, as shown in FIG. 2C and referring to FIG. 2B, a partial etching process is performed on the dielectric layer 21 to etch a portion of the dielectric layer 21 to form a narrow contact hole. It is formed below the first opening 23 and the wide trench groove prototype 26 is below the second opening 24. It is worth noting that due to the effect of the etching micro-load effect, the depth of both the narrow contact hole deflection 2 5 and the wide channel trench prototype 2 6 is equal to (= the same ° here). The role of this part of the etching process is by etching The dielectric layer 21 under the first opening 23 and the second opening 24 increases the aspect ratio of both the first opening 23 and the second opening 24. The fourth 'formation layer 27 is formed as shown by the second circle D' On the photoresist 22, = is also filled into the narrow contact hole release 25 and the wide channel groove release 26. The aspect ratio of the contact hole release 25 is larger than that of the wide channel groove prototype 26. Γ is smaller than the thickness of the cover layer 27 on the bottom of the narrow contact hole prototype 25. The thickness of the cover layer 27 on the bottom of the channel trench 26 is smaller than that of the second test. The thickness difference is proportional to the aspect ratio thickness difference between the two, and then, the part # engraving procedure performed will increase this cover layer 27 (, and the possible types of cover 2 layer 27 are at least the dielectric layer and the Polymer laminate ^, possible materials for the composite layer are at least fluorocarbons, hydrocarbons " f slave compounds. In addition, the cover layer 27 The formation method includes at least a pre-rolling phase deposition method.

413893 V. Description of the invention (7) Fifthly, an etching process is performed as shown in the second E diagram, so that the narrow contact hole prototype 25 and the wide channel trench prototype 26 are etched at the same time, and a dielectric layer 21 is simultaneously formed. The narrow contact hole 28 and a wide channel groove 29 ′ both of the narrow contact hole 28 and the wide channel groove 29 directly touch the substrate 20. Finally 'remove the remaining photoresist 2 2. Obviously, the difference in etching rate between the narrow contact hole prototype 25 and the wide channel trench prototype 26 due to the etching micro-load effect is the bottom of the narrow contact hole prototype 25 and the bottom of the wide channel trench prototype 26. The difference in thickness of the cover layer 27 between them is offset, so the depth of both the narrow contact hole 28 and the wide trench 29 is the same. Therefore, it can be said that the key of the present invention is to appropriately adjust the thickness difference of the cover layer 27 between the narrow contact hole complex 25 and the wide trench groove prototype 26, so that the difference in etching rate due to the micro-load effect is effectively offset. In addition, the difference in thickness of the cover layer 27 between the narrow contact hole relief 25 and the wide channel trench relief 26 can be increased by the aforementioned part of the single-engraving procedure. The following paragraphs will explain one application of the present invention: a method for eliminating etch micro-load effects in a semiconductor process by co-site etching and deposition. Since most of the content and steps of this application are the same as the previous examples, only the different parts are described in the following paragraphs: (1) The substrate is a semiconductor substrate, and the cover layer is a polymer layer . (2) After the semiconductor substrate is covered by a dielectric layer, the semiconductor substrate is placed in a plasma reactor having at least two independent energy sources. A first energy source is used to generate a plasma in the plasma reactor, and a second energy source is used to generate a DC bias near the surface of the semiconductor substrate.

Claims (1)

413893 VI. Scope of patent application 1. A method for forming a narrow contact hole and a wide trench at the same time in an integrated circuit manufacturing process, wherein the narrow contact hole has the same depth as the wide trench, and the method includes at least the following steps: providing a A substrate; forming a dielectric layer on the substrate; forming a photoresist on the dielectric layer; performing a lithographic etching process to form a first opening and a second opening in the photoresist, The width of the first opening is smaller than the width of the second opening. A part of the etching process is performed to etch a part of the dielectric layer, so that a narrow contact hole is formed under the first opening. And a wide channel trench prototype is formed under the second opening; a covering layer is formed on the photoresist and filled into the narrow contact hole relief and the wide channel trench prototype, and in the narrow contact The thickness of the cover layer on the bottom of the hole shape is smaller than the thickness of the cover layer on the bottom of the wide channel groove. An etching process is performed to make the narrow contact hole shape and the wide channel groove. The prototype is etched at the same time, and A narrow contact hole and a wide trench are simultaneously formed in the dielectric layer, and the narrow contact hole and the wide trench are in direct contact with the substrate. Here, the narrow contact hole is out of shape with the wide trench trench. The difference in etching rate due to the etching micro-load effect is offset by the difference in the thickness of the cover layer between the bottom of the narrow contact hole prototype and the wide channel trench bottom. Therefore, the narrow contact hole The same depth as the wide trench; and removing the remaining photoresist. Page 12 413893 VI. Application for Patent Scope 2. The method described in the application for stupid items, wherein the above-mentioned substrate contains at least metal-oxide semiconductors and isolation 3. The method described in item 1 of the application, when the integrated body When the circuit is a multilayer integrated circuit, the substrate further includes a plurality of dielectric layers, a plurality of contacts, and a plurality of interconnects. The thickness of the light-resistance effect is slightly etched on the person who is not in the same degree. The interest is specifically requested to apply as described in 6 Cheng Chengfen βί. The deeper of the mouth two opening two open the second and the second and the mouth opening one open the first and the first place in the bit plus etched by the 'borrowing system' Page 13 413893 [Applicable patent model. If the application is specially adjusted ^ 6 of which the above-mentioned cover layer shape 8 · The method described in item 1 _ of Jiachai Guisi Plant at least includes a chemical vapor deposition method 9. A A method for removing etching micro-load effects in a semiconductor process by in-situ etching and deposition. The method at least includes: providing a semiconductor substrate, the semiconductor substrate is covered by a dielectric layer, and a photoresist is formed on the semiconductor substrate. A dielectric etching process is performed on the dielectric layer to form a wide opening and a narrow opening in the photoresist, wherein the wide opening and the narrow opening are directly in contact with the dielectric layer; the semiconductor substrate Placed in an electropolymerization reactor, a first energy source in the energy source 1 of the electropolymerization reactor is used to generate a plasma on the conductor, and a second energy source is used to A direct current bias is generated near the surface of the semiconductor substrate; a narrow opening is formed: a polymer layer is on the photoresist and filled into the opening; the second part is: due to the characteristics of the deposition process' in the narrow polymer layer Thickness; "of: degree Than on the bottom of the wide opening, so that "L: J resistance is formed with the dielectric layer at the same time-a narrow channel is formed at the same time as the etching process, and then a narrow channel is formed under the dielectric opening D The trench is under the opening and a wide trench is on the wide body substrate. Bu: The narrow trench in the middle and the wide trench are in direct contact with the semiconducting conductor. The etching process is performed by Time and the polymer 413893 6. The thickness of the patent application layer is adjusted so that the depth of both the narrow trench and the wide trench is the same 10. The method as described in the application, wherein the semiconductor substrate includes at least a gold-oxygen semi-transistor and isolation. 11. The method according to the application, wherein the semiconductor substrate described above may further include a multi-layered structure ', the multi-layered structure includes at least a plurality of dielectric layers, a plurality of contacts, and a plurality of interconnects. 1 2. The method according to item 9 of the application, wherein the thickness of the photoresist is about several angstroms to several micrometers. Si £ 1 3. The method according to the application, wherein the possible materials of the polymer layer include carbon I compounds, dehydrogen compounds, and carbon compounds. Very ill 1 4 · The method as described in the application for patent,%, wherein the type of the first energy source includes at least the RF energy generated by the inductor coil and the RF energy generated by the capacitor electrode plate. I belongs to # rS9 '1 5. The method as described in the application section, wherein the type of the above-mentioned second energy source has at least the radio frequency energy generated by the cathode. 1 6. The method described in the application may further include Page 15 413893 6. Application for patent scope Before the deposition process, a part of the etching process is performed. The part of the etching process is performed by etching the dielectric layer located under the wide opening and the narrow opening to increase the | Aspect ratio of flexion, mouth, and the narrow opening. 1 7. The method described in the application \ ^^ 9, wherein the types of semiconductor processes mentioned above include at least an interconnect process and a dual damascene process. Both semiconductor processes need to form small contact holes and large contacts with the same depth. region. ί 1 8. The method as described in the application, wherein the typical width of the narrow opening described above is less than about 0.3 microns. 19 9. The method as described in the application, wherein the typical width of the wide openings above is approximately greater than 1 micron. Page 16