TW412833B - Method of forming contact via - Google Patents

Abstract

A method of forming a contact via comprises two parts: forming a first contact plug in a first dielectric layer; forming a second dielectric layer; forming a second contact plug in the second dielectric layer connecting the first contact plug. The invented method can be applied on the production of contact via in the peripheral circuit region of a DRAM or the logic circuit region of an embedded DRAM.

Description

412833 4 1 27twf.d〇c / 006 A? _ B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing a contact window, and more particularly, to a dynamic random access memory (DRAM) device. The peripheral circuit area of the structure 'or a method of forming a contact window in an embedded dynamic random access memory (Embeded DRAM) logic circuit area. In the semiconductor process, the contact window is responsible for the electrical connection between the upper metal interconnect and the lower component area. In the DRAM or embedded DRAM element structure, there is often a considerable height difference between the memory cell (ceU) area and the peripheral circuit area or logic circuit area. This is because the capacitor in the DRAM structure is responsible for data storage. In order to make the capacitor large enough to keep the minimum requirements of the capacitor, the surface area of the lower electrode in the dram cell must often be increased. Inevitably, the volume and height of the lower electrode will be larger than other components. In this way, when making a contact window in a peripheral circuit area or a logic circuit area, it faces a challenge of a larger aspect ratio. The following uses embedded DRAM as an example. Figures 1A to 1C show cross-sectional views of a conventional manufacturing process of a contact window of an embedded DRAM logic circuit area. Referring to FIG. 1A, first, a substrate 100 is provided. The substrate 100 has a memory cell region 102 and a logic circuit region 104. Transistors 106, 108, and word lines are formed in the memory cell area 102 and the logic circuit area 104 (not shown). An oxide layer is then formed. 10 is covered on the transistors 106 and 108 to isolate it from other components. Then, a DRAM capacitor 112 is fabricated in the memory region 102, including a lower electrode 114, a dielectric film layer 115, and Upper electrode 116. The transistors 106, 108, oxide layer 10 and capacitor 112 are made by any applicable traditional method. Those skilled in this art should be able to easily reach 3 •-II | 1... _ · * ··濞 1-.-一 ____ The inverse rule of this paper ^ 丨 rape: ㈣ ((, NS) Λ 视 姑 (2) 〇'Χ 297 ^ # _) (For the precautions for reading first, then continue writing Page) Installation * Α7 Β7 412833 4] 27twf.doc / 〇〇ό 5. The invention is described, and will not be described in detail here. Then 'Please refer to FIG. 1B, using the chemical vapor deposition method, in the oxide layer ιαο An additional oxide layer 118 is formed thereon and covers the capacitors. 2. Then, a portion of the dielectric layer U8 is removed by a chemical mechanical honing method to obtain a flat upper surface. Then, a conventional lithographic etching technique is used for uranium Oxide layers 118 and 112 'are etched to form contact opening 120, and a source / drain region 113 of transistor 108 is exposed. Referring to FIG. 1C, a chemical vapor deposition method is used in A titanium nitride layer 122 is formed on the oxide layer h8 as a glue layer, and covers the inner surface of the contact window opening 120. Then, A sputtering method or a chemical vapor deposition method forms a tungsten metal layer 124 on the titanium nitride layer 122 and fills the contact window opening 122. Finally, using the oxide layer 118 as the honing end point, a chemical mechanical honing method is used. The contact window process is completed by removing the tungsten metal layer 124 and the adhesive layer 122 outside the contact window opening 120. In the above process, because the height of the capacitor 112 is quite large, the aspect ratio of the contact window opening 120 is also quite high. Not only during etching At the same time, the formed by-products are easy to accumulate at the bottom, and it is easier to cause holes in the plug when the plug is inserted. Therefore, the object of the present invention is to provide a method for manufacturing a contact window, which can reduce the contact. The aspect ratio of the window opening makes the process of etching the opening of the contact window easy to operate, and no holes will occur when the metal conductor layer is penetrated. According to the above purpose, the present invention proposes a method for manufacturing a contact window, which will form a contact window The steps are divided into two parts. After the capacitor structure of the DRAM cell is formed, 'a first contact window insert is first formed in the first dielectric layer (" Trilobata clever page) i installed.

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Print V. Description of the invention (i) Plug, and then form a second dielectric layer, and then form a second contact window plug in the second dielectric layer to connect the first contact window plug. Thus, the aspect ratios of the first and second contact window plugs are smaller than the conventional method. According to the above object, the present invention proposes a method for manufacturing a contact window plug, which includes the following steps: First, a substrate is provided, a memory area and a non-memory circuit area are defined on the substrate, and a non-memory circuit area has a Gold Oxygen Semitransistor. Next, a first dielectric layer is formed on the substrate. After that, a capacitor is formed in the memory area, and a dram cell is completed. Then, a first dielectric layer is defined to form a first contact window opening in a non-memory circuit region, exposing a source / drain region of a metal-oxide semiconductor. Thereafter, a first adhesive layer is formed on the first dielectric layer and covers the inner surface of the opening of the first contact window. Next, a first metal layer is formed on the first adhesive layer and fills the first contact window opening. Then, the first metal layer and the first adhesive layer outside the first contact window opening are removed to form a first contact window plug in the first contact window opening. Thereafter, a second dielectric layer is formed on the entire substrate and covers the first contact plug and the capacitor. Then, the second dielectric layer is planarized and defined to form a second contact window opening at a position relative to the first contact window plug. Then, a second adhesive layer is formed on the second dielectric layer and covers the inner surface of the opening of the second contact window. Next, a second metal layer is formed on the second adhesive layer and fills the second contact window opening. Finally, the second metal layer and the second adhesive layer outside the second contact window opening are removed to form a second contact window plug in the second contact window opening, wherein the second contact window plug and the first contact window plug. Plugged electrical connection. Because the step of using the contact window is divided into two steps. (&Quot; Read the precautions before writing this page)

、 1T Bianchuan ten Kl'Mm of this paper scale) ΛΊ gauge cypress (210X 297g t) 412833 4 1 27t wt \ doc / 006 A7 B7 「， 一. — 1 j 1 'V. Description of the invention (4) a The depth of the contact window and the second contact window is smaller than that of the contact window formed at one time, and the aspect ratio is also small. Therefore, the disadvantage of excessively high aspect ratio can be avoided. It can be more clearly and easily understood. A preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings: Figures 1A to 1C show a conventional embedded DRAM logic circuit. A cross-sectional view of the manufacturing process of the contact window of the area; and FIGS. 2A to 2F show cross-sectional views of the manufacturing process of the contact window of the embedded DRAM logic circuit area according to a preferred embodiment of the present invention. Description: 100, 200: substrates 102, 202: memory regions 104, 204: non-memory regions 106, 108, 206, 208: transistors 110, U8, 210, 224: dielectric layers 112, 212: capacitors 113, 213: Contact window plug 114: lower electrodes 115, 215: dielectric film layer 116: upper electrodes 120, 218, 230 240: contact window openings 122, 232, 242: adhesive layers 124, 234, 244: metal layer 6 丨 丨 丨, one by one one by one — _ _ _ one Page).

* 1T A7 4] 27twf.d〇c / 0 (} 6 B7 · ————————. —......... 5. Description of the invention (t) 236, 246 · Contact window plug 2A to 2F show cross-sectional views of a manufacturing process of a contact window of an embedded DRAM logic circuit area according to a preferred embodiment of the present invention. Referring to FIG. 2A, first, a substrate 200 is provided. The substrate 100 has a memory cell region 202 and a non-memory circuit region 204. If it is a DRAM element, the non-memory circuit region 204 is a peripheral circuit region; if it is an embedded DRAM element, the non-memory circuit region 204 is a logic circuit region. Metal-oxide semiconductors 206 and 208 are formed in the memorization area 202 and the non-memory circuit area 204, respectively. Thereafter, a dielectric layer 210 having a thickness of about 10,000 (M3, 0000 angstroms) is formed to cover the electrical On the crystals 206 and 208, the material of the dielectric layer is, for example, silicon oxide, and a typical formation method is, for example, chemical vapor deposition. Another line is usually formed in the dielectric layer 21 on the crystals 206 and 208. $ ， 'Cannot be displayed in this figure, and is not the focus of the present invention, so I will not go into details. Then, please refer to Figure 2B. A DRAM capacitor structure 212 is formed in the memory area 202, and includes a lower electrode 214, a dielectric film layer 215, and a power-up electrode 216. For example, a conventional lithographic etching method is first used to define a dielectric 餍 21G 'to form a contact window opening therein. 218, exposing the substrate 200, and then 'forming a polycrystalline silicon layer on the dielectric layer 210, filling the contact window opening 218' and electrically connecting the substrate. The polycrystalline silicon layer is then defined to form 220. Next, outside the lower electrode 214 A dielectric film layer 215 is formed on the surface. For example, a layer of hafnium oxide 215 ° is formed on the surface of the lower electrode 214 by thermal oxidation. Next, another polycrystalline silicon layer is formed on the dielectric film layer 215 and this layer is defined to form an upper electrode. 216. After the stomach is formed on the surface of the upper electrode 216%, read the back, and then install it!

'.t Part A ten times it and b Γΐ .1 A ί Talent I ιΊ > V This paper size this state ten (ϋΤϋ 石 Τ210χ 297 public dream) 412833 4 127twf', doc / 006 A 7 The chemical layer 224 is typically formed by, for example, atmospheric pressure chemical vapor deposition (APCVD). Referring to FIG. 2C ', the dielectric layer 210 is defined to form a contact window opening 230 in the non-memory circuit region 204, and the source / drain region 213 is exposed. A typical method is, for example, a dry etching method to form a contact window opening 230 'in the dielectric layer 210 to expose the source / drain region 213 of the transistor 208. Thereafter, an adhesive layer 232 is formed on the dielectric layer 210 and covers the inner surface of the opening 230 of the contact window. The material of the adhesive layer is, for example, Chin, Titanium Nitride, Crane, Tungsten Nitride, Giant, Nitrided Giant, and the like. The formation method is, for example, a chemical vapor deposition method. Next, a metal layer 234 is formed on the adhesive layer 232 and fills the contact window opening 230. The material of the metal layer 234 is, for example, tungsten, aluminum, or the like, and a method of forming the metal layer 234 is, for example, a chemical vapor deposition method. Then, referring to FIG. 2D, the metal layer 234 and the adhesive layer 232 other than the contact window opening 232 are removed to form within the contact window opening 230—the contact window plug 236, wherein the first contact window plug 236 and the source / sink The pole region 213 is electrically connected. A typical method of removing a portion of the metal layer 234 and the adhesive layer 232 is, for example, an etch-back method using the dielectric layer 20 as an end point. Referring to FIG. 2E, another dielectric layer 238 having a thickness of about 9000-12000 angstroms is formed on the dielectric layer 210 and covers the capacitor 212 and the contact plug 236. The material of the dielectric layer 238 is, for example, silicon oxide, and a typical formation method is, for example, a chemical vapor deposition method. Then, the dielectric layer 238 is planarized. For example, a portion of the dielectric layer 238 is removed by chemical mechanical honing to obtain a flat upper surface. Next, a dielectric layer 238 is defined to form a contact window opening 240 at a position corresponding to the contact window plug 236. For example, using the traditional 8 secret ruler materials () ^ ΰΓ (2 \ 〇Χ29Τ ^ · §) ~~ --- (" Read the precautions for the back and then " {" This page) Install '

-1T 412833 4 l 27twf, doo / 006 V. Description of the Invention (, ·)) Lithographic etching technology etches the dielectric layer 238, forms a contact window opening 240 therein, and exposes the upper surface of the contact plug 236. Then, an adhesive layer 242 is formed on the dielectric layer 238 by a chemical vapor deposition method, and covers the inner surface of the contact window opening 240. Next, a metal layer 244 is formed on the adhesive layer 242, and the contact window is opened 240. The material of the adhesive layer 242 is, for example, titanium, titanium nitride, tungsten, tungsten nitride, giant, molybdenum nitride, etc., and the material of the metal layer 244 is, for example, tungsten, aluminum, or copper. A typical formation method is, for example, chemical vapor phase. Deposition method. Finally, referring to 2F, the metal layer 244 and the adhesive layer 242 other than the contact window opening 240 are removed to form a contact window plug 246. For example, with the dielectric layer 238 as an end point, a part of the metal layer 244 and the adhesive layer 242 are removed by using a chemical mechanical honing method or an engraving method. Among them, if the material of the metal layer 244 is copper, it is only applicable to the chemical mechanical honing method. It can be known from the above-mentioned preferred embodiments of the present invention that the application of the present invention is performed by dividing the step of forming a contact window into two parts. After the capacitor structure of the DRAM cell is formed, a first contact window plug is first formed in the first dielectric layer, then a second dielectric layer is formed, and then a second contact window plug is formed in the second dielectric layer. The plug is connected to the first contact window plug. The depth of the first contact window and the second contact window obtained in this way is smaller than that of the contact window formed once, and the aspect ratio is also small. Therefore, the shortcomings of high quotient width can be avoided. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. Duper Chuanyu KRiU ((210X297 mm)

Claims (1)

Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 412833 as 4! 27twf.doc / 006 L / o 6. Application for Patent Scope 1. A method for manufacturing a contact window, which defines a memory area and a non-memory on a substrate A circuit region having a first metal-oxide semiconductor transistor in the non-memory circuit region has a first dielectric layer formed on the substrate, and a capacitor has been formed in the memory region. The method includes: defining the A first dielectric layer 'to form a first contact window opening in the non-memory circuit area, exposing a source / drain region of the metal-oxide semiconductor; and forming a first contact window opening in the first contact window Contact window plug; forming a second dielectric layer on the first dielectric layer and covering the first contact window plug; planarizing the second dielectric layer; defining the second dielectric layer to Forming a second contact window opening at a position corresponding to the first contact window plug; and forming a second contact window plug in the second contact window opening, wherein the second contact window plug and the first contact window plug The contact window plug is electrically g. 2. The method for manufacturing a contact window | _ as described in item 1 of the scope of the patent application, wherein the non-memory region is selected from the logic circuit region # decay circuit region among-. j ::: > 3. The method for manufacturing a contact window as described in item 1 of the patent application scope, wherein the method of forming the first contact window plug includes: forming a first adhesive layer on the first dielectric Forming a first metal layer on the first adhesive layer and covering the first contact window opening; and removing the first contact window opening other than the first contact window opening; A metal layer and the first 10 (please read the precautions on the back before filling in this), va This paper size applies the Chinese National Standard (CNS) Α4 specification (210X297 mm) Printed by the Offshore Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Policy 412833 ABl4l27tWfd0C / 〇06 __D8 patent application adhesive layer to form a first contact window plug in the first contact window opening, wherein the first contact window plug. In: \ 4. Contact the manufacturer as described in item 3 of the gfg patent scope, where the material of the first metal layer includes tungsten. 5 'The manufacturer of the contact window ^^ as described in item 3 of the patent application range', wherein the method of removing the first layer and the first adhesive layer outside the opening of the first contact window includes an etch-back method. 6. The manufacturing method of contact as described in item 3 of the scope of the patent application, wherein the material of the first adhesive layer is selected from the group consisting of titanium, nitrogen myrtle, giant, nitrided giant, and combinations thereof.丨, ^ 7. The method for manufacturing the contact window g described in item 1 of the scope of the patent application, wherein the method for forming the second contact window plug includes: forming a second adhesive layer on the second dielectric layer, and Covering the inner surface of the second contact window opening; forming a second metal layer on the second adhesive layer, and filling the second contact window opening: removing the second metal layer and the second contact window opening except the second contact window opening and The second adhesive layer is used to form a second plug in the second contact window opening. 8. The method for manufacturing a contact window according to item 7 in the scope of the patent application, wherein the material of the second metal layer includes tungsten D: 9. The contact window method according to item 7 in the scope of the patent application, wherein the first The two adhesive layers are selected from the group consisting of titanium, titanium nitride, and molybdenum. 10. Contact plug as described in item 7 of the scope of patent application: The manufacturer of molybdenum nitride and the manufacturer (please read the note $ on the back before filling this page) The paper size is not applicable to the country of the country (CNS) A4 size (2IOX2 !? 7 mm) 412833 I 27twf .doc / 〇〇6 A8 B8 C8 D8 VI. Patent application scope method, in which the second metal layer and the first metal layer are removed Manufacturer 11. The contact method described in item 7 of the scope of patent application, wherein the method of removing the second layer and the second adhesive layer outside the opening of the second contact window includes a chemical mechanical honing method. 12. The method for manufacturing a contact window as described in item 8 of the patent application, wherein the material of the second metal layer includes copper. Q13. The method for manufacturing the contact as described in item 1 of the patent application, wherein the first The thickness of a dielectric layer is about 1000-liotlQ '; 1 '\ 14. The manufacturing method of contact reading as described in item 1 of the scope of the patent application, wherein the thickness of the first dielectric layer is about 90,000-12 × § # · | 矣. 15. The manufacturing method of contact as described in item 1 of the scope of patent application, wherein the materials of the first dielectric layer and the second dielectric layer include oxide sand. —; Order Bing (Please read the precautions on the back before filling out this page) Printing Policy of Employees' Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs 12 This paper size applies to China National Standard (CNS) Α4 specification (210 × 297 mm)