TW410291B - A data processing system integrating basic input/output system and system memories - Google Patents

Abstract

The present invention discloses a data processing system integrating basic input/output system (BIOS) and system memories. The system includes a read/write nonvolatile memory for storing the system data in the first bank, the third bank and the fourth bank as well as the BIOS in the second bank of the nonvolatile memory, in which the addresses of the first bank, the third bank and the fourth bank are defined to be continuous and the addresses of the third bank and the second bank are defined to be identical; an address bus used to transmit the accessing address issued by the system; and a decoding device electrically connecting with the read/write nonvolatile memory and the address bus. The decoding device maps the second bank of the read/write nonvolatile memory in response to the BIOS selection signal as the first logical index and its accessing address, the third bank of the nonvolatile memory in response to the accessing address as the second bank address and the BIOS selection signal as the second logical index, maps the first bank of the nonvolatile memory in response to the accessing address as the first bank address, and map the fourth bank of the nonvolatile memory in response to the accessing address as the fourth bank address. The above-mentioned mapping is used for the system to access the mapped bank.

Description

410291 V. Description of the invention (l) Field of the invention: The present invention relates to the basic input / output system of electronic products. The system "especially refers to the system for storing basic input / output systems in system memory in electronic products." · Background of the invention:

Q. With the rapid progress of technology, notebook computers and handheld digital electronic products are widely used. For general data processing systems, such as personal computers or other consumer electronics products, a basic input / output system (Basic Inp.ut / Output System, BIOS) is usually required to manage the boot time when booting. Some programs, such as power-on self-test when the computer starts up, and low-level settings such as drives, keyboards, screens, etc. ϋ Provide some software support boards for various devices connected to the computer. In addition, 'the system still needs various forms of storage devices (such as hard disks, etc.) to store the operating system (0s) and other application software, as a reference to the specific function of the system c ...' · For consumer Electronic products, Zhu Zhenglei 1. j ancient, because its communication only messes up like a shoulder TV or a satellite TV receiver ° because its communication only performs a specific work force: can ', so there is no need to Generally, it only needs the seal of Little Zedan, and the Kappa disk can store Xu Xi's huge applications. m i Brix 4 = two sets of software programs used to store specific purposes i.e. α consumer electronics usually use some access speed

410291 V. Description of the invention (2) Faster non-volatile memory (N ο nv ο 1 a't i 1 emem 〇ry>), such as flash memory, etc. as a memory device. In addition, due to consumer The architecture of electronic products is simpler than general purpose computer systems, so the conventional ISAUndustry Standard Architecture architecture is sufficient. However, because the ISA address bus (Addressbus) is 24 bits, it can support To 1 6MB of memory. Please refer to the first diagram 'The diagram shows the memory access block diagram used by the conventional consumer electronics' sub-product, which is in 16 MB of memory, using j DRAM as the address 0 0 0 0 0 p ~ 7FFFFF storage place, and the address ^ 8 0 0 0 0 0 ~ FFFFFF storage place uses four. Flash memory memory chip 1 0 2, 1 0 4, 1 0 6, 1 0 8 to make up. In the second figure, the memory chip 10, 102, 104, 106, 108 is used for data transmission with the central processing unit via the ISA data cable, and the decoding device 100 is separately connected to the memory chip. 1 0 2, 1 0 4, 1 0 6, 1 0 8 'The four chip selection signals (R0MCS1 # ~ R0MCS4 #) are connected. The decoding device 100 includes a decoder 110 'which corresponds to four decoding areas (because there are four memory chips), and uses the selected chip selection signal-No. 5 to specify the memory-the body chip 1 Selected persons in 0 2, 1 0.4, 10 6 and 108. The basic output system is ^! The system has 12.0 memory, which is routed through the I SA address. Enter the designated address, and use the * XD cable to do the input and output operations. It should be noted that the basic I / O system memory 12 is controlled by a basic I / O chip selection signal 1 (BI0SCS #) 'and activated when BI0SCS # is 0' for the basic I / O system's capture. Take operation. . 乂

41G291

Page 6 4-10.291 V. Explanation of the invention (4) Access address; a decoding device electrically connected to the readable and writable non-volatile memory and the address bus. The decoding device is based on a basic The input / output system selects the signal as the first logic level and the access address, and maps the second sector of the readable and writable non-volatile memory, so that the access address is the second sector address. And when the basic input / output system selects the signal as the second logic level, the third sector of the readable and writable non-volatile memory is mapped, so that when the access address is the first sector address, The first sector of the readable and writable non-volatile memory is mapped. When the access address is the fourth sector address, the fourth sector of the writable non-volatile memory is executed. Mapping; the above-mentioned mapping system is used to make the system access to the mapping section. Brief description of the drawings: The above-mentioned content and the many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, of which: The first picture shows the memory used in conventional consumer electronic products. Body Access-Fang Xian [Net. The memory of this system is separate from the system that Kedong loses and enters the life system; ». / / The second diagram shows the memory access block diagram of the first preferred embodiment of the present invention, The system memory 艟 is combined with the basic input / output system memory system;, The third figure shows the internal structure of the memory when the basic input / output system is stored in the system memory of the present invention;

410291 V. Description of the invention (5) _ The fourth picture does not show the second preferred embodiment disclosed by the invention; the fifth picture Λ does not show the result of the first preferred embodiment of the invention Corresponding result list; and the fifth β figure shows the corresponding result list generated by the second preferred embodiment of the present invention; the illustrated part: 1 0 0 '21 0, 41 0: decoding device; 1 0 2 , 104, 106, 108: memory chips;

110, 225, 425: decoder; 'W 1 2 0: basic input / output system memory_; 202, 204, 206, 208: memory chip; 215, 415: combinational logic device; and 230, 430: address Conversion logic device. Detailed description of the invention: Please refer to the second figure s. It depicts the memory access block diagram of the first preferred embodiment of the present invention. In the first comparative embodiment of the second figure, it also uses 'DRAM as a storage location of addresses 00000-00 ~ 7FFFFF' in the memory of 16 MB3 and addresses 800000 ~ FFFFFF. The storage location uses four flash memory chips 20, 20, 2, 4, 6, 0.8, and a 128KB BIOS as an example. The BIOS is also the same as BIOSCS #. It is started when it is 0. In fact, the sum of DRAM and flash memory is 16 MB, but two

410291 Five 'Invention Note ¢ 6) The number of use and the number of chips can be adjusted according to the application. In the first preferred embodiment of the present invention in the second figure, the memory chips 202, 20 4, 206, and 20 08 are connected to the decoding device 21 〇, and are also carried out through the I SA data cable and the central processing unit. Data transfer. Take β I Os as 1 2 8KB as an example (the actual application can be increased or decreased due to different needs), and store BI0.s in the memory .. chip 20 2 address 9E0 0 0 0 '9FFFFF, so the memory The remaining storage space of the wafer 202 is only 2.M-128KΈ. For the decoding device and device 210, four chip selection signal lines (R0MCS1 # ~ R0MCS4 #) are respectively connected with the above four memory chips '2, 2, 2, q, 4;: ,,', 2 0, and 2 phases. Then, the memory chip that will be accessed by ._squeeze drive. The decoding device 2 10 includes a decoder 2 25, a combination logic device 2 1 5 and a bit address conversion logic device 2 3 0. The decoder 2 2 5 includes five decoding areas (D1, D2, D3, D4, and DB) for decoding the ISA address to know which decoding area the I A A address corresponds to. The corresponding results MB #, Ml #, and M2 # generated by the decoding areas DB, D1, and D2 of the decoder 2 2 5 will be sent to the combinational logic device 2 1 5 for further comparison, and the decoding area D3. D4 corresponds to D4. As a result, the signal lines R 0 MCS 3 # and R 〇MCS 4 # are directly fed into the memory through the chip selection signal lines R 0 MCS 3 # and R 0 MCS 4 #, respectively. In addition, in addition to the corresponding input results MB #, Ml #, and M2 #, the combinational logic device 215 is also controlled by the basic given input crystals, “irmTOSCS #”, which is used to produce peak total soil and Yuxin lose R0MCS1 # and R0MCS2 #, and feed them into the memory chips 202 and 204, respectively, to determine whether the memory chips 202 and 204 are selected.

Page 9 410291 V. Description of the invention (7) Please refer to the fifth chart A, which depicts the output correspondence table MB #, Ml #, M2 # according to the input IS A address and BI 0 SCS #; In addition, in the chart of the fifth: A chart, 'RoMCSl #, ROMCS2 #' is also listed in accordance with the logical level of the corresponding results. When the I SA address points to 80,000 ~ 9 swellings stored in the memory chip 202?系统 's system data area, and] ^ 1〇 $ (: When ^ is 1', the corresponding one will be 'Decoding area D1 and M1 # will be 0, and both μb # and .M2 # will be 1; this When R0MCS1 # and R0MCS2 # will be 0 and 1, respectively, so that the memory chip 2 0 2 can be driven to read out the system data only. When the I $ a address falls in the range of = AOOOOO-BDFFFF, and BI0SCS When # is 1, because at this time, the stored year is the D2 area that does not overlap with the decoding area DB, so M2 # will be reduced to 0, and MB # and Ml # will be 1 '. At the same time, RMCS1 # will be 1. And R0MCS2 # is 0, which is used to start the memory chip 2 0 4 to read the system data. When the ISA address falls within the range of 9E 0 0 0 0 ~ 9FFFFF, and BI0SCS # is 1, because the access at this time Is the D 2 area that overlaps with the decoding area DB, but because it corresponds to both the decoding area DB and D2 ′, 〇 # and M2 # will be reduced to 0 at the same time, and M1 # will be 1, while R0MCS1 # will be 1, and R0MCS2 # is 0, which is used to start the memory chip 2 04 to continue the system data. Furthermore, 'When is a bit-address is corresponding to the decoding area, and when B I 0SCS # is 0', it means B I 〇S data Will be accessed, but so send L to decode 225's ISA address has only 20 address lines (the other 4 highest address f lines are all Bit 0), so the decoder 225 can't actually solve any results, so MB #, Ml #, M2 # are all Is 1. However, because BI0SCS # is 0, ROMCS1 # is also 0 'to drive the memory chip 202 to read the BIOS data. Finally, when the ISA address corresponds to the decoding area D3 or D4, and

Page 10 410291 V. Description of the invention (8) BTOSCS # is! When deleting, M1 #, M2 #, _⑶ #, and cs2 # are all because the memory chips 202, 204, 206, and 2008 each contain 2MB addresses, so only 21 address lines can be used to point to all Address. Therefore, the address conversion logic 'devices 2,30 only need to output 21 address lines when receiving the ISA address. However, because there are only 20 BIOS addresses, from 21 to 24 bits, they are all 0. If the BIOS address is transferred to the memory crystal 002 according to this, it will always only be sent to addresses below 1 MB. In this embodiment, Bi0s is placed at an address of 1 MB to 2 MB in the memory chip 202. Therefore, in the first preferred embodiment, the address conversion logic device 230 will set the BIOSCS # to 0 when BI0SCS # is 0. The value of the 21st bit of the entered ISA address is converted from 0 to 1 (but if β 丨 〇s is placed in the 0MB -1 MB address in the memory chip 202, it is not necessary to convert) Point to B 丨 〇s data storage. Moreover, when BI0SCS # is 1, the address conversion logic device 230 will judge whether the access address needs to be added to 20000h (丨 2 8 KB) according to the IS A address to point to the system. . Data storage. For example, when the ISA address corresponds to the decoding area D 丨, the bit-rack conversion logic device 230 sends the 21-bit I s A address (remove the leftmost 3 bits) to the memory chip 202; When the ISA address is included in the decoding areas D2, D3, and D4, the address conversion logic device 230 adds a 2 0000 address to the 21-bit ISA address (200K of BIOS capacity) to generate After accessing the address, it is sent to the memory chip to access the system data.

^ 10291 V. Description of the invention (9) In fact, the address of B 10 S stored in the memory chip from the private M + month may depend on the actual planning. For example, in the third picture, you can see that the region C below 1 MB is used to represent the addresses OOOOOO ~ FFFFFF in the 1MB interval, and the region D 'below 2Mβ represents the 1MB to 2MB area. 21E〇〇〇〇〇 ～ 1FFFFF entity address. In the first preferred embodiment of the second figure +, the area D is an area for storing m0s, which is stored using M28KB. Because the area in the second figure is occupied by area D ', the data stored outside area D is used to store the data system. However, the system data cannot be discontinuous when it is accessed (for example, when accessing software programs). (Code) 'So it is necessary to use the position conversion logic 230 and the combination logic device 215 to eliminate this problem. Furthermore, although the above-mentioned embodiment is explained using four 2MB flash memories, it is practically available in other capacities. Flash memory, for example, uses two 4Mβ flash memories. To implement the content disclosed in the present invention by the chip, however, the address conversion logic device 230 needs to convert the 22nd and 21st bits of the ISA address (such as 0〇a〇MB— 1Mβ, '01alMB-2MB, 10a2MB-3MB, 11a3MB-4MB), to point to the location of the technical content disclosed by BIOS. Obviously, those skilled in the art can use more high-capacity flash memory: chip-', I would like to enumerate an example for further explanation. When you want to access the system data pointed to by the address 9E0 000, the system data pointed to 9E0 000 is actually stored in the first memory chip 303 because the BIOS is stored between 9E0 0 0 0-9FFFFF. Cells. However, the BIOS data stored at the 9E000 address is also pointed out using the 9E000OO address, so it occurs at

410291 V. Description of the invention (10) The ISA address between 9EOOOO ~ 9FFFFF will point to the BIOS and system data at the same time. In the second picture, the above problem can be eliminated after the B10SCS # signal is used. Because when the ISA address 9EOOOO-9FFFFF and BI0SCS # are 0, it is used to indicate that the accessed data will be BIOS, so the address translation logic device 230 is also driven by BI0SCS # which is 0 at this time. In order to convert the 21st bit of the biqs address to generate an access address of 1E0000-1 FFFFF, it is sent to the area D of the memory chip 202 to read out the BIOS data. Therefore, system data with the same ISA address as 9E0 0.0 0-9FFFFF will not be read out, that is, system data stored in the first cell of the memory chip 204. On the other hand, when the ISA address 9E00 00-9FFFFF is used to read out the system data, the address conversion logic device 23 at this time adds the ISA address 9EOOOO plus 20000h shift (the large i128KB of the BIOS ) a, ρ form the address of A00 0 0 0, and then take 21 bits' to form ⑽⑽ = access address to point to the first cell of memory crystal 20 4, and then read out Stored system data too. In addition, the example depicted in Figure 3 may vary depending on the actual cheek condition. For example, if the BIOS is stored in section C, but the entire memory is left, you can take a few changes. Please refer to the fourth figure, which depicts the b ^ 5 memory chip 2 0 2 of the present invention, a preferred embodiment, which is the same as the first embodiment, and the second one: the first money also uses DRAM as 0 0 0 0 0 0 ~ 7FFFFF storage place —— Car Father's Best Example. Ting 'and 800 000 ~ FFFFFF also uses four flash memories > k ^

410291 V. Statement (11) --- 2 0 4, 2 0 6, 2 0 8. Since the basic input / output system is stored in the 8EOOOO ~ 8FFFFF section of the memory chip 202 (that is, stored in the area C of the fourth ^) *, the decoding device 425 is generated by the decoding area D2 (9EOOOO ~ BDFFFF). The corresponding result can be fed directly to the memory chip 204 via ROMCS2 # without further judgment by the combinational logic device 415. Because the physical addresses before and after 8EOOOO ~ 8FFFFF (respectively 8 liver? Factory and 9 0 0 0 0 0) are all in the memory crystal 2.0. 2 / different from the embodiment shown in the second figure 'However The values shown in the five decoding areas of the decoder 2 2 5 are still ISA addresses. 'Please refer to the fifth diagram B', which depicts the corresponding results mb, # and ΜΓ #, and BI.OSCS # 'The round-robin correspondence table generated according to the input ISA address, when the ISA address points to the decoding area D1 When the system data area does not overlap with the decoding area DB, BI0SCS # will be 1 at this time, so, # · will be 0, and MB '# will be 1; but R〇MCSl # will be 0, used to start the memory chip 202 to read out the required system data. When [§ A address points to the system data area of 8E0 000 ~ 8FFFFF, because it corresponds to the decoding area D1 'which overlaps with the solution and area DB, but because Β ί 0 SCS # is 1, so μ 1, # And MB '# are both 0' and R〇μCS1 # is also 0, which is used to start the memory chip '202 to read and output the required system data. Furthermore, when the ISA address points to the BIOS data area of 8EOOOO ~ eFFl ^ FF, because the address input to the decoder 425 is only 20 bits (the remaining 21-24th bits are 0), the decoder 425 can not find the corresponding decoding area, so we '# and mb' # are both j; but because BI0SCS # is 0, so RMCSl # will also be 0, used to start recording

410291 V. Description of the invention (12) Membrane chip 2 0 2 to read out the required B 10S data. Finally, when the ISA address corresponds to the decoding area D2, D3, or D4, because BiosCS #, MB, #, and ΜΓ # are all 1, romCSI # is also 1. The same 'the above embodiment can also use two 4MB to implement the content disclosed in the present invention, but the address conversion logic device 4 3 0 needs to convert the 2nd bit of the Isa address according to the address where BI 0S is located. And the 21st bit (such as OOaOMB-IMB, 01alMB-2MB, 10a2MB-3MB, 1: ia 3MB-4MB) to point to the address where bIOS is located. In fact, politicians can also use more high-capacity flash memory chips based on the technical content disclosed in this publication, and can be based on the techniques disclosed in the present invention. All logic circuit structures. The advantages of Cheng and Zhiduo: By using this basic output into the system memory, you can avoid extra memory to store the extra space of the readable and writable memory. Although the present invention is explained in the above with a better example, it is not the spirit of the invention and the actual invention of the ship. "," "Is not intended to limit the invention." ] For example, in this article: For the basic input and output program storage address area to learn about the artisans in this field, what magnetic zone. Therefore, familiar with the method and device of the present invention can be easily 410291

Claims (1)

410291 Scope of patent application 1. A kind of information that combines ^., Processing system, v access system (β 1 os) and system memory. The system includes: read and write non-17 volatile write & non-j memory, which is used to store system data in the first part of the memory that can store the memory; the third section and the fourth section, the section, of which Each time the system enters the system, the second segment address of the non-volatile memory can be read and written. The first segment address, the third segment address and the fourth segment address are set as continuous addresses, and the first The three-segment address is the same address as the second self; = = stream, used to transmit the access address issued by the system; A. Ma Lingzhi, electrically connected to the readable and writable non-volatile information office B The 4 address converges bismuth, & 'Knowledge 丨 King 5 Carcass and this number is the first i green decoding device in response to-basic input and output win system selection news ", editing level and the access address. Map the readable non-amplifier & — £ 饫, corresponding to the access address and address. The basic round-in / out system selects the signal as the second logical bit and two sectors. The non-volatile can be written. The third segment of the memory is mapped. Because of this, when the address is the first segment, the read-write nonvolatile peak is The first segment of the memory is mapped, so when the access address is the 1st memory of the 4th region, the fourth segment of the readable and writable non-volatile memory is also mapped. The antipodal system is used to make the system access the antipodal, 1 2 3 4 '. Heart segment Page U 1 The data processing system as described in the first item of the patent application scope, wherein the .2 unit further includes a bit conversion device 'responds to the basic round in' and '3' when the signal is at the first logical level. ^ System selection of the address bus 4 卄 Get the address to 410291 6. The address range of the second section of the patent application is mapped. Proceed to the second section of the readable and writable non-volatile memory. 3. If you apply for the data processing system of the first and benefit range, the readable and writable volatile memory is a flash memory. tIf the data processing system of item 1. of the patent scope is declared, the address bus is the ISA (. Industry Standard Architecture) address bus. 5 · The data processing system of the first item of the patent scope, wherein the readable and writable non-volatile memory of the first sector address, the third sector address, and the fourth sector address are a continuous bit site. Test: Γ combines the basic input / output system (BI0S) with the data processing system of the system memory. The system includes:, Noisy selling and writing non-volatile memory, used to store system data in the .. ', "The first area of the volatile memory is stored in the volatile memory L1'r ... 丞 + John access system is the second section of the volatile memory that can be narrowed ¥ 2, where the second area Paragraph '·' One. Write and write non-volatile memory: the highest segment of the hidden body; two = address bus, used to transmit the access address issued by the system; the address collection / electrical connection to the readable and writable non-volatile memory and The number is the first-logic short: the device responds to a basic input / output system selection signal, position level, and the access address, and is non-volatile to the read / write P.18 410291 The second area of the memory of the six-patent application is mapped to _ ^ / Λ branch. Therefore, when the access address is the Chu k address, the first area mapping is expected; f Continue to write the first sector of the non-volatile memory to access it. The above-mentioned mapping is used to enable the system to perform 7-to-2 mapping on the patent application scope of the 6th data processing system, where the decoding equipment beep ^ contains a bit conversion device ' The basic input / output system selects the & for a logic level, converts the access address of the address bus to ^ second sector address' to the second sector of the writable non-volatile memory Reflection. 8. The data processing system according to item 6 of the patent application scope, wherein the readable and writable non-volatile memory is a flash memory. 9. If the data processing system of item 6 of the patent application scope, the address bus is an iSA (Industry standard Architecture) address bus option-. — 10. — The post-decoding device maps the system data of the non-volatile memory 10 that can be read and written to the basic input system (BIOS) according to the access address issued by the address bus transmission system. The read-write non-volatile memory 2 is used to store the system data in the first region & 'the third region and the fourth region of the writable non-volatile memory, storing the basic input / output system in the accessible 410291 VI. Patent application scope Read and write the second sector of non-volatile memory, where the definition of the first sector address, the second sector address and the fourth sector address are continuous addresses, and The third sector address is defined as the same address as the second sector address, and the solution device is electrically connected to the readable and writable non-volatile memory and the address bus. It is characterized in that the decoding device responds to In a basic I / O system, the signal is selected as the first logic level and the access address, and the second section of the readable and writable non-volatile memory is mapped. When the sector address and the basic round access system select the signal as the second logical level, the third sector of the readable bird ^ volatile memory is mapped, so the access address is equal to the first sector address To the first sector of the readable and writable non-volatile memory: when the access address is the fourth sector address, the fourth sector of the read-write non-volatile memory Antipodal; which of the above is Tian Tian access. 1 Use u to make the system perform the mapping of the mapped section. If the scope of the patent application includes ... Bit M conversion device 'Λ When the decoding split number is the first logical level, she should use the basic input and output system. Select the address of the second segment of the message. It is expected that the access address of the address bus to the mapping. Read and write the second section of non-volatile memory 1 2 • As the decoding device on page 1 of the patent application, the readable memory is a flash memory. Dan f and! Jing Jingfei 410291, Chinese patent application range 2. You ^ apply for a decoding device in the 10th patent scope, which makes the address confluence = an ISAUndustry Standard Architecture) address exchange = · if the scope of patent application Paragraph (ii). The solution of the item. The code device, wherein: the first sector address and the third sector address of the :: sex memory are read; the non- & segment address is a continuous address. Music four = a private decoding device that responds to the storage of a single address bus transmission system. It outputs a mapping of the system data in the non-volatile memory that can be read and written to the basic input and output system (BIO). Wherein the readable and writable non-volatile IS storage system data is -t second f I of the readable and writable non-volatile memory, and the basic input / output system is paper-based in the writable and non-volatile memory. The second section is the = section of the readable and writable non-volatile memory, and the decoding device is electrically connected to the address bus of the readable and writable non-volatile memory at 1 address, which is characterized by: The 1st sema device responds to the basic input system by selecting the signal as the first zone fish and the access address, and speaking to the readable and volatile non-volatile memory the second lecture ^ ^ 仃. When the address is the address of the first sector, the first sector of the non-volatile memory is read and written for mapping; access is performed. The above-mentioned map is used for the system to perform the mapping of the mapped section. Page 21 VI. Application for patent scope __ 1 more 6. Λ application ^ ^ Li Si range of the 26th decoding device, where the decoding device word W.r upgrades the device, according to the basic output. Input system selection Blind as the first logical position is on time, 媸 w otL 一一 &#; address, and this can be all #k opposite. Item T writes the second section of non-volatile memory for 1 7. For example, the scope of the patent application 1st $ jg Xigu & Furnace $ ^ r, ^ _ currency coin 13 'decoding device' where the read-write non- Volatile memory is a flash memory. 18. The decoding device according to item 15 of the patent application scope, wherein the address bus is an IS A (Industry Standard Architecture) address bus. 1 9. One% of the readable and writable access maps are stored in the system section and the address field. The address sections include: (a) Non-volatile storage of the basic round-trip system (B 〖〇s) and system data. The memory is mapped in response to an address issued by an address bus transmission system. The mapping is used to allow the system to access the pair of segments. The non-volatile memory is used for storing Data is stored in the first section of the readable and writable non-volatile memory, and the third and fourth sections are used to store the basic input / output system in the second section of the readable and writable non-volatile memory, wherein the first section The segment address, the definition of the third zone and the fourth zone address are consecutive addresses, and the third address is defined as the same address as the first zone address of Suan, this method package is based on the input and output of Jifeng The system selects the signal as the first logic level Page 22 410291 ____ VI. Scope of patent application-and the access address, mapping of the second section of the readable and writable non-volatile memory;. (B) The address corresponding to the access address is the When the address of the second sector and the basic input / output system select tfl as the second logical level, the third sector of the readable and writable non-volatile memory is mapped; (c) corresponding to the access address is When the first sector is located at the address, the first sector of the readable and writable non-volatile memory is mapped; and (d) when the access address is the fourth sector address, The fourth segment of non-volatile memory can be read and written for mapping. 20. The method according to item 19 of the scope of patent application, which further includes a step before step (a): when the signal selected by the basic input / output system is the first logical level, the address bus is converted. Access the address to the second sector address. 2 1. The method according to item 19 of the scope of patent application, wherein the readable and writable non-volatile memory is a flash memory. 2 2. If the method of item 19 of the scope of patent application, the address bus is an ISA (Industry Standard Architecture) address bus · Row 0 2 3. If the method of item 19 of the scope of patent application, The first sector address, the third sector address, and the fourth sector of the read-write nonvolatile memory Page 23 410291 VI. Scope of Patent Application The address is a continuous address. 2 4 .—A method for mapping the readable and writable non-volatile memory that stores the basic input / output system (B 10S) and system data according to the access address issued by a one-bit bus transmission system. Mapping is used for the system to access the mapped section. The readable and writable non-volatile memory is used to store the system data in the first section of the writable non-volatile memory. The basic input / output system is stored in a second section of the readable and writable non-volatile memory, wherein the second section is the highest section of the readable and writable non-volatile memory. The method includes:-( a) Map the second sector of the readable and writable non-volatile memory based on the first logical input timing and the access address selected by a basic input / output system; (b) Based on the memory When the address is the first sector address, the first region_segment of the writable non-volatile memory is mapped. 25. The method according to item 24 of the scope of patent application, which further includes a step before step (a): when the signal is selected as the first logical level by the basic input / output system, the address bus is converted. Access address to the second sector address. 26. The method of claim 24, wherein the readable and writable non-volatile memory is a flash memory. Page 24 Page 25