KR101165966B1 - Memory system being accessed as a synchronous mode or an asynchronous mode by command - Google Patents

Abstract

A memory system accessible by a command in synchronous or asynchronous mode is disclosed. A memory system is a memory system connected to a host processor and accessed in a synchronous or asynchronous mode, the memory system comprising: a nonvolatile memory, a nonvolatile memory controller for accessing the nonvolatile memory, a first memory area dedicated to the host processor, and a nonvolatile memory system. By including a second memory area dedicated to the volatile memory controller and a shared memory area accessible by both the host processor and the nonvolatile memory controller, performance of the memory system can be improved.

Description

MEMORY SYSTEM BEING ACCESSED AS A SYNCHRONOUS MODE OR AN ASYNCHRONOUS MODE BY COMMAND}

TECHNICAL FIELD The present invention relates to flash memory, and more particularly, to a memory system accessible in synchronous mode or asynchronous mode according to a command from a file system.

Flash memory is a non-volatile memory device that can erase and rewrite data electronically. Unlike EEPROM, it is used when a large amount of volatile and solid state storage such as digital music player, digital camera and mobile phone is needed. In addition, the flash memory is also used as a USB driver, which is a temporary storage medium for transferring data between computers, and recently, a SD (Secure Digital) card, a multimedia card (MMC) including a flash memory, and the like are widely used.

Memory systems such as SD cards and multimedia cards with built-in flash memory incorporate small amounts of SDRAM in the flash memory controller to temporarily store data transferred from the host processor. In addition, the method of writing data to the flash memory is a synchronous mode method, that is, the host processor transmits the next data to the memory system only after receiving a return signal from the memory system in which the flash memory has been written to the flash memory. I'm using

However, in such a conventional system, since the capacity of the SDRAM used as a temporary buffer is small, the host processor has to split the data to be written to the flash memory into small sizes and deliver it to the memory system several times. There is a problem that the speed is too high to improve the performance of the memory system.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a memory system that can improve the performance of the memory system.

In order to achieve the above object, a memory system according to the present invention is a memory system connected to a host processor and accessed in a synchronous mode or an asynchronous mode, comprising: a nonvolatile memory, a nonvolatile memory controller for accessing a nonvolatile memory, An internal memory may include a first memory area dedicated to a host processor, a second memory area dedicated to a nonvolatile memory controller, and a shared memory area accessible by both the host processor and the nonvolatile memory controller.

In addition, the memory system is accessed in either synchronous mode or asynchronous mode based on commands from the file system of the host processor.

The nonvolatile memory may be a NAND flash memory having a NAND type memory cell structure, and the internal memory may be one DRAM. In addition, the memory system may be integrated into a single chip.

The file system may also be comprised of a first file system for accessing data in a synchronous mode and a second file system for accessing data in an asynchronous mode.

According to a second embodiment of the present invention, a memory system is provided, which is a memory system connected to a host processor and accessed in a synchronous mode or an asynchronous mode, the memory system being a nonvolatile memory and a nonvolatile memory for accessing the nonvolatile memory. It may include a memory controller and an internal memory connected to the flash memory controller for temporarily storing data.

In addition, the memory system is accessed in either synchronous mode or asynchronous mode based on commands from the file system of the host processor.

The nonvolatile memory may be a NAND flash memory having a NAND type memory cell structure, and the internal memory may be a DRAM. In addition, the memory system may be integrated into a single chip.

The file system may also be comprised of a first file system for accessing data in a synchronous mode and a second file system for accessing data in an asynchronous mode.

According to the present invention, the performance of the memory system can be improved by accessing data from the synchronous mode to the asynchronous mode or from the asynchronous mode to the synchronous mode by software commands from the file system.

1 is a hardware structure of a memory system according to an embodiment of the present invention.
2 is a hardware structure of a memory system according to another embodiment of the present invention.
3 is a software structure of the memory system according to FIGS. 1 and 2.
4 is a flowchart illustrating a method of operating a synchronous mode of the memory system according to FIG. 2.
5 is a flowchart illustrating a method of operating an asynchronous mode of the memory system according to FIG. 2.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

1 is a hardware structure of a memory system according to an embodiment of the present invention, in which a memory system 100 connected to a host processor 110 includes a flash memory 101, a flash memory controller 102, and a DRAM 103. can do.

The DRAMs 111 and 103 have a characteristic of being periodically reproduced since information stored as one type of RAM is extinguished with time, and is used as a large-capacity temporary memory device because of its simple structure and easy integration. Volatile memory. Unlike the prior art, in the present invention, a separate large capacity DRAM 103 is added to the flash memory controller 102. Therefore, the host processor 110 does not need to send data in small pieces, thereby improving performance of the memory system. Can be improved.

The flash memory 101 is a nonvolatile memory device that does not require power to maintain information in a memory chip. Preferably, the flash memory 101 is a NAND flash memory having a NAND structure in a cell array configuration, but is not limited thereto. (Read Only Memory), Static Random Access Momoey (SRAM), or the like.

The flash memory controller 102 accesses data in the flash memory 101 in the same operation mode as that of the host processor 110, and internally converts a logical address into a physical address to provide the flash memory 101 to the flash memory 101. It includes a Flash Translation Layer (FTL). The memory system 100 may be integrated into a single chip.

In the memory system having the above configuration, the process of writing data to the flash memory 101 is as follows.

In the synchronous mode, the host processor 110 reads data from the DRAM 111 and temporarily stores the data in the DRAM 103 in the memory system 100. Thereafter, the flash memory controller 102 writes data temporarily stored in the DRAM 103 to the flash memory 101. Thereafter, when writing is completed, the flash memory controller 102 transmits a return signal indicating completion to the host processor 110. After receiving the return signal, the host processor 110 may perform an operation other than accessing the flash memory 101.

In the asynchronous mode, the host processor 110 reads data from the DRAM 111 and temporarily stores the data in the DRAM 103. The flash memory controller 102 then transfers the fake return signal to the host processor 110. The host processor 110 receiving the fake return signal may perform another operation. Meanwhile, the data temporarily stored in the DRAM 103 is then written to the flash memory by the flash memory controller 102. As described above, in the asynchronous mode, the flash memory 101 transmits a fake return signal to the host processor 110 as long as the data is written to the temporary memory DRAM 103 even before data is completely written to the host processor 110. ) To perform different operations to improve the performance of the overall memory system. However, since the DRAM 103 as a temporary buffer is a volatile memory, if the power is turned off before being written to the flash memory 101, data may be erased.

2 is a hardware structure of a memory system according to another exemplary embodiment of the present invention. The memory system 200 connected to the host processor 210 may include a flash memory 201, a flash memory controller 202, and one DRAM 203. It may include. In FIG. 2, unlike FIG. 1, two DRAMs 111 and 103 are integrated into one RAM 203.

The flash memory 121 is a nonvolatile memory device that does not require power to maintain information in a memory chip. The flash memory 121 is preferably a NAND flash memory having a NAND structure in a cell array configuration, but is not limited thereto. (Read Only Memory), Static Random Access Momoey (SRAM), or the like.

The flash memory controller 202 accesses data in the flash memory 201 in the same operation mode as that of the host processor 210, and internally converts a logical address into a physical address to provide the flash memory 201. It includes a Flash Translation Layer (FTL). The memory system 200 may be integrated into a single chip.

On the other hand, the one DRAM 203 is also referred to as a dual port memory, and has a memory area # 1 dedicated to the host processor 210, a memory area # 2 dedicated to the flash memory controller 202, and a host processor. And a shared memory area # 3 accessible by both 210 and flash memory controller 202. In order for the host processor 210 and the flash memory controller 202 to access the shared memory area # 3, the host processor 210 and the flash memory controller 202 must access the shared memory area # 3 after obtaining an access right from the original DRAM 203. The memory system 200 may be integrated into a single chip.

3 is a software structure of the memory system of FIGS. 1 and 2, which includes a file system 301 that operates in the host processor 210, a host processor driver 302, and a memory system driver 303 that operates in the memory system 200. ) In addition, as shown, the file system 301 is composed of a file system 1 (301a) operating in a synchronous mode and a file system 2 (301b) operating in an asynchronous mode, the host processor driver 302 is also in a synchronous mode The driver 302a operates in an asynchronous mode and the driver 302a operates in an asynchronous mode. The memory system driver 303 also includes a driver 303a operating in a synchronous mode and a driver 303b operating in an asynchronous mode.

As shown in FIG. 3, the memory system driver 303 operating on the memory system 200 operates in conjunction with the host processor driver 302, and the operation of the synchronous mode and the asynchronous mode is a file of the host processor 210. Distinguished by commands from system 301. As described above, the present invention can operate by dividing the operation mode into the synchronous mode and the asynchronous mode by a software method, the operation mode can be easily changed by a simple command, and the performance of the memory system can be improved over the hardware method. The software structure shown in FIG. 3 may also be applied to the memory system of FIG. 1.

4 is a flowchart illustrating a method of operating a synchronous mode of the memory system according to FIG. 2.

Referring to FIG. 4, in step 400, the host processor 210 obtains an access right to the shared memory area # 3 from the original DRAM 203 and then writes to the unique dedicated memory area # 1. The existing data is written to the shared memory area # 3.

When writing is complete, in step 401, the flash memory controller 202 acquires access right to the shared memory area # 3, and writes data recorded in the shared memory area # 3 to the flash memory 201. do.

Thereafter, in step 402, the original DRAM 203 transmits a return signal to the host processor 210 indicating that data writing is completed. The host processor 210 receiving the return signal may perform an operation other than accessing the flash memory 201.

5 is a flowchart illustrating a method of operating an asynchronous mode of the memory system according to FIG. 2.

Referring to FIG. 5, in step 500, the host processor 210 acquires an access right to the shared memory area # 3 from the original DRAM 203, and then writes to the unique dedicated memory area # 1. The existing data is written to the shared memory area # 3.

When writing is complete, in step 501, the one DRAM 203 transmits a fake return signal to the host processor 210 indicating that data writing is completed. The host processor 210 receiving the fake signal may perform an operation other than accessing the flash memory 201.

Thereafter, in step 501, the flash memory controller 202 acquires an access right to the shared memory area # 3, and writes data recorded in the shared memory area # 3 to the flash memory 201.

The present invention can also be embodied as computer-readable codes on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, and the like. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

100, 200: hardware structure of the memory system
110, 210: host processor
111, 103: DRAM
101, 201: flash memory
102, 202; Flash memory controller
203: One DRAM
301: file system
302: host processor driver
303: memory system driver

Claims (12)

delete A memory system connected to a host processor and accessed in synchronous or asynchronous mode,
Nonvolatile memory;
A nonvolatile memory controller for accessing the nonvolatile memory; And
An internal memory including a first memory area dedicated to the host processor, a second memory area dedicated to the nonvolatile memory controller, and a shared memory area accessible by both the host processor and the nonvolatile memory controller,
The memory system,
Based on a command from a file system of the host processor, the memory system being accessed in either a synchronous mode or an asynchronous mode. The method of claim 2,
The nonvolatile memory,
A NAND flash memory having a NAND type memory cell structure. The method of claim 2,
The memory system,
Memory system characterized in that integrated into a single chip. The method of claim 2,
The file system,
A first file system for accessing data in a synchronous mode; And
And a second file system for accessing data in asynchronous mode. The method of claim 2,
The internal memory,
The memory system, characterized in that the one DRAM. delete A memory system connected to a host processor and accessed in synchronous or asynchronous mode,
Nonvolatile memory;
A nonvolatile memory controller for accessing the nonvolatile memory; And
An internal memory connected to the nonvolatile memory controller for temporarily storing data;
The memory system,
And access data in either a synchronous mode or an asynchronous mode based on a command from a file system of the host processor. The method of claim 8,
The nonvolatile memory,
A NAND flash memory having a NAND type memory cell structure. The method of claim 8,
The memory system,
Memory system characterized in that integrated into a single chip. The method of claim 8,
The file system,
A first file system for accessing data in a synchronous mode; And
And a second file system for accessing data in asynchronous mode. The method of claim 8,
The internal memory,
Memory system, characterized in that the DRAM (DRAM).

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