409360 A7 B7_—— 五、發明説明（f ) 發明領域： 本發明係關於一種積體電路製程中之消弭導電層結構 間介電層中鎖孔(key hole)問題的方法，特別是關於一種 於導電層結構間以自行對準接觸窗(self-aligned contact; SAC)方式製作電容器時，消弭導電層結構間介電層中因鎖 孔問題而造成兩個分離之電容器短路的方法。 發明背景： 一般而言，關於半導體產業的製程技術中，元件 (曲vice)及晶粒(die)尺寸極小化與高積集度，一直是積體 電路製作上極爲重要的發展方向之一。爲因應積體電路之 線寬逐漸縮小的趨勢，積體電路之自動對準(s e 1 f - a 1 i gned) 已廣泛的被利用了，以期能同時達到對準與尺寸縮小的目 的，其中自動對準接觸窗(self-aligned contact; $AC)製 程，已應用於皇冠型電容器(crown capacitor)之製作。 經濟部智愍財產局員工消費合作社印製 在積體電路後段製程的應用中，於位元線（bit line) 間以自行對準接觸窗製程製作皇冠型電容器，請參考圖一 之結構上視圖，係爲積體電路中導電層結構(即複晶矽位元 線BL)間的介電層（interpoly oxide; ΙΡ0)中，以自行對 準接觸窗方式形成皇冠型電容器Q，在該傳統製程技術中， 發現因ΙΡ0沉積時產生的鎖孔(key hole)K問題，會造成後 續電容器下層電極板之複晶矽材質塡入所述鎖孔K之中，而 造成兩個分離之電容器短路，產生元件電性不良及良率降 低的問題。 2_ 本紙張尺度通用中國國家標準（CNS ) ( 210X297公釐） 409360 A7 B7_____ 五、發明説明（» ，請參照圖二所示之習知技藝製程結構示意圖，其中圖 二A、B及C分別爲沿圖一中Μ’、BB’及CC’方向剖面之示意 圖，以方便進一步說明鎖孔問題。請先參考圖二A、B，提 供一已完成前段製程的半導體基板10，該基板10的表面已 形成有一層導電層11及其上之介電層12，製作有複晶矽20 與矽化金屬（si licide)30所組成的複晶矽化金屬 (polycide)導線結構，以及其上之硬式護罩（hard mask)40，然後製作導線結構之間隙壁(spacer)50a，由於 是屬於積體電路之後段製程階段，爲保護已製作完成之電 性元件，故必須選用製程溫度較低的電漿輔助式化學氣相 沉積法（Plasma-Enhanced chemical vapor deposition; PECVD)來形成氮化矽(ShN4)之間隙壁介電質，但因PECVD-ShN4本身特性的原因’會造成間隙壁上端過寬(over-head) 的形狀，因此增加了導線結構間的深寬比(aspect ratio)， 所以當氧化矽介電層60塡入導線結構之間時，其滲塡能力 將無法完全塡滿高深寬比的凹溝，因而產生了鎖孔K，在開 啓自動對準接觸窗後(圖二B所示），沉積電容器下層電極板 之複晶矽層70時，由於通常所使用的同步摻雜複晶矽（in-situ doped poly-Si)具有極佳的階梯覆蓋能力（step coverage)，所以極易塡滿所述鎖孔K所形成之細小通道之 中，而會造成兩個分離之電容器短路，如圖二C中所示。 本發明即是針對上述之問題提出解決方法，以避免因 鎖孔通道造成電容器間短路的問題。 發明之槪述： __3____ 张尺度適用中國國家標準（CNS ) A4規招「（ 210X 297公疫")~~ ---------装— 一 一 ， N)/- (請先閲讀背面之注意事項寫本頁) i- —訂409360 A7 B7 _—— V. Description of the invention (f) Field of the invention: The present invention relates to a method for eliminating key hole problems in a dielectric layer between conductive layer structures in an integrated circuit manufacturing process, and more particularly to a method for When the capacitors are fabricated by self-aligned contact (SAC) between conductive layer structures, a method for eliminating short circuits between two separated capacitors due to a keyhole problem in the dielectric layer between conductive layer structures is eliminated. BACKGROUND OF THE INVENTION Generally speaking, in the process technology of the semiconductor industry, the miniaturization and high integration of component and die sizes have always been one of the most important development directions in the fabrication of integrated circuits. In order to respond to the trend of decreasing the line width of integrated circuits, the automatic alignment of integrated circuits (se 1 f-a 1 i gned) has been widely used in order to achieve the purpose of alignment and size reduction at the same time, of which The self-aligned contact ($ AC) process has been applied to the production of crown capacitors. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the application of the back-end process of the integrated circuit. The crown-type capacitors are manufactured by self-aligning the contact window process between the bit lines. Please refer to the top view of the structure in Figure 1. Is a crown-shaped capacitor Q formed by a self-aligned contact window in a dielectric layer (interpoly oxide; IP0) between conductive layer structures (ie, polycrystalline silicon bit line BL) in a integrated circuit. In this traditional process, In the technology, it was found that the problem of the key hole K generated during the IP0 deposition would cause the polycrystalline silicon material of the subsequent electrode plate of the capacitor to penetrate into the key hole K, resulting in a short circuit between the two separated capacitors. Problems such as poor electrical properties of the device and reduced yield occur. 2_ The paper size is in accordance with the Chinese National Standard (CNX) (210X297 mm) 409360 A7 B7_____ 5. Description of the invention (», please refer to the schematic diagram of the conventional technology process structure shown in Figure 2, where Figures A, B and C are respectively Schematic cross-sections along the directions M ', BB' and CC 'in Figure 1 to facilitate further explanation of the keyhole problem. Please refer to Figures 2A and B first to provide a semiconductor substrate 10 that has completed the previous process. The surface of the substrate 10 A conductive layer 11 and a dielectric layer 12 thereon have been formed, and a polycide wire structure composed of a polycrystalline silicon 20 and a silicide 30 has been fabricated, and a hard cover thereon (Hard mask) 40, and then the spacer 50a of the wire structure is produced. Since it belongs to the later stage of the integrated circuit, in order to protect the completed electrical components, a plasma processing aid with a lower process temperature must be selected. -Chemical chemical vapor deposition (PECVD) to form the spacer dielectric of silicon nitride (ShN4), but due to the characteristics of PECVD-ShN4 itself, (over-head) shape, thus increasing the aspect ratio between the lead structures, so when the silicon oxide dielectric layer 60 penetrates between the lead structures, its permeability will not fully fill the height, width and width Compared with the recess, a keyhole K is generated. After the automatic alignment contact window is opened (shown in FIG. 2B), when the polycrystalline silicon layer 70 of the lower electrode plate of the capacitor is deposited, due to the commonly used synchronous doping compound, In-situ doped poly-Si has excellent step coverage, so it is easy to fill the small channels formed by the keyhole K, which will cause short circuit between two separate capacitors. As shown in Figure 2C. The present invention proposes a solution to the above problems to avoid the problem of short circuit between capacitors caused by the keyhole channel. Description of the invention: __3____ The scale is applicable to the Chinese National Standard (CNS) A4 Regulations ((210X 297 public epidemic ") ~~ --------- install — one by one, N) /-(Please read the precautions on the back to write this page) i- —Order
Tt 經濟部智態財產笱員工消費合作社印製 409360 A7 B7 五、發明説明（)） 本發明之主要目的是提供一種消弭導電層結構間介電 層中鎖孔問題的方法，可於導電層結構間以自行對準接觸 窗方式製作電容器時，防止二分離之電容器間短路的現 象，以提昇產品之良率。 本發明的另一目的是提供一種消弭導電層結構間介電 層中鎖孔問題的方法，以二步驟沉積電容器之複晶矽下層 電極，來避免二分離之電容器間短路的現象，使製程易於 整合。 本發明是利用下列技術手段來達到上述之各項目的:首 先，依一般製程步驟形成導電層結構間之自行對準接觸 窗，而該接觸窗之間的介電層中已生成鎖孔管道；接著， 以二步驟分別沉積電容器之複晶矽下層電極，先沉積一層 高溫薄膜(HTF)複晶矽，藉由其較差的階梯覆蓋能力將鎖孔 口封住，再沉積一層同步摻雜(in-situ doped)複晶矽，即 可解決二分離之電容器間短路的問題。 圖式簡要說明： 圖一爲積體電路中導電層結構間以自行對準接觸窗方 式形成電容器之結構上視圖。 ’ 圖二A〜C爲習知技藝中於導電層結構間以自行對準接 觸窗方式製作電容器時，導電層結構間介電層中因鎖孔問 題而造成兩個分離之電容器短路之剖面示意圖。其中圖二A 係爲沿圖一AA’剖面，圖二B係爲沿圖一BB’剖面，圖二C 係爲沿圖一 CC’剖面。 圖三A~B爲本發明實施例中於基板上沉積氮化矽層之 ____4______ 本紙張尺度適用中國國家系準（CNS ) A4規格（210X297公釐） ' -----------裝-- (請先閱讀背面之注意事t填寫本頁) 訂 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明説明（^ ) 剖面示意圖。其中圖三A係爲沿圖一 Μ’剖面，圖三B係爲 沿圖一 ΒΒ’剖面。 圖四Α〜Β爲本發明實施例中於基板上形成氮化矽間隙 壁之剖面示意圖。其中圖四A係爲沿圖一 M’剖面，圖四B .係爲沿圖一 BB’剖面。 圖五A~B爲本發明實施例中於基板上沉積氧化矽層之 剖面示意圖。其中圖五A係爲沿圖一 M’剖面，圖五B係爲 沿圖一 BB剖面。 圖六A~C爲本發明實施例中形成自行對準接觸窗，並留 有鎖孔之剖面示意圖。其中圖六A係爲沿圖一 M’剖面，圖 六B係爲沿圖一 BB’剖面，圖六C係爲沿圖一 CC’剖面。 圖七爲爲本發明實施例中於自行對準接觸窗內沉積第 一步驟之HTF複晶矽層，並封住鎖孔不致造成短路之沿圖 一 CCT之剖面示意圖。 圖八爲本發明實施例中於自： 步驟之複晶矽層之沿圖一 CC’之剖面示意圖 圖號說明： 請 閱 讀 意 事 5裝Printed by Tt Intellectual Property of the Ministry of Economic Affairs and printed by employee consumer cooperatives 409360 A7 B7 V. Description of the invention ()) The main purpose of the present invention is to provide a method for eliminating the problem of pinholes in the dielectric layer between conductive layer structures. When self-aligning contact windows are used to make capacitors, the short circuit between two separated capacitors is prevented to improve the yield of the product. Another object of the present invention is to provide a method for eliminating the problem of pinholes in the dielectric layer between the conductive layer structures. The two-step deposition of the polycrystalline silicon lower electrode of the capacitor is used to avoid the short circuit between the two separated capacitors, and the process is easy Integration. The present invention uses the following technical means to achieve the above-mentioned objects: first, according to the general process steps, self-aligned contact windows between conductive layer structures are formed, and keyhole pipes have been generated in the dielectric layer between the contact windows; Next, the capacitor ’s polycrystalline silicon lower electrode is deposited in two steps. First, a layer of high temperature thin film (HTF) polycrystalline silicon is deposited. The keyhole is sealed by its poor step coverage ability, and then a layer of synchronous doping (in -situ doped) Polycrystalline silicon can solve the problem of short circuit between two separated capacitors. Brief description of the drawings: Figure 1 is a top view of a structure in which capacitors are formed by self-aligning contact windows between conductive layer structures in a integrated circuit. '' Figure 2A ~ C are cross-sectional schematic diagrams of short circuits between two separated capacitors due to keyholes in the dielectric layer between the conductive layer structures when the capacitors are manufactured by self-aligning contact windows between the conductive layer structures in the conventional art. . Among them, Fig. 2A is along the section AA 'in Fig. 1, Fig. 2B is along the section BB', and Fig. 2C is along section CC '. Figure 3A ~ B are ____4______ of the silicon nitride layer deposited on the substrate in the embodiment of the present invention. This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) '--------- --Equipment-(Please read the notice on the back t to fill out this page) Order A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention (^) Sectional schematic diagram. Among them, FIG. 3A is a section along FIG. 1M ′, and FIG. 3B is a section along FIG. 1B ′. FIG. 4 is a schematic cross-sectional view of a silicon nitride spacer formed on a substrate according to an embodiment of the present invention. Among them, Fig. 4A is a cross section taken along the line M 'in Fig. 1, and Fig. 4B is a cross section taken along the line BB' in Fig. 1. 5A to 5B are schematic cross-sectional views of a silicon oxide layer deposited on a substrate according to an embodiment of the present invention. Among them, Fig. 5A is a cross section taken along the line M 'in Fig. 1, and Fig. 5B is a cross section taken along the line BB in Fig. 1. 6A to 6C are schematic cross-sectional views of forming self-aligning contact windows and leaving lock holes in the embodiment of the present invention. Among them, FIG. 6A is along the section M ′ of FIG. 1, FIG. 6B is along the section BB ′, and FIG. 6C is along the section CC ′. FIG. 7 is a schematic cross-sectional view of FIG. 1 CCT in which the HTF polycrystalline silicon layer of the first step is deposited in the self-aligned contact window and the lock hole is not caused to cause a short circuit in the embodiment of the present invention. Fig. 8 is a schematic cross-sectional view of the step of the polycrystalline silicon layer in Fig. 1 CC 'in the embodiment of the present invention. Figure No. Description: Please read
1T 經濟部智慧財產局0H;工消費合作社印製 BL-位元線 IPO-複晶矽層間介電層 SAC-自行對準接觸窗 11-導電層 20-複晶砂層 40-硬式護罩 60-複晶砍層間介電層 K-鎖孔 Q-皇冠型電容器 10-半導體基板 12-介電層 30-金屬矽化物 50,50a-氮化矽層 70-複晶矽下層電極 本紙張尺度適用中國國家標準（CNS ) A4規格（21 ο X 297公釐） A7 B7 409360 五、發明説明（/) …80- HTF複晶矽層 90-摻雜複晶矽層 發明詳細說明： 以下係以一應用於積體電路後段製程，於導線結構間之 自行對準接觸窗中製作電容器之製程爲實施例，來說明本 /發明。仍請參照圖一之導電層結構間以自行對準接觸窗方 式形成電容器之結構上視圖，圖三至圖八中係顯示本實施 例沿圖一中Μ’、BB’及CC’剖面之製程示意圖。首先，請參 考圖三，其中圖三A係顯示沿圖一 M’剖面，圖三B係顯示 沿圖一 BB’剖面，提供一已完成前段製程之半導體基板10， 該基板10的表面已形成有一層導電層丨1(通常爲製程中之 第二複晶矽層poly-2)及其上之介電層12，並以習用技術 在上述半導體基板結構的表面上形成導電層結構，所述導 電層結構係作爲位元線(Bit Line)，一般來說，可採用複 晶矽層爲位元線導電層結構，而本實施例係採用複晶矽層 20及矽化金屬（s i 1 i c i de)層30所形成之阻値較低的複晶矽 化金屬複層結構(polycide)，該複晶砂化金屬層上方具有 一層硬式護罩(hard mask)40，通常該硬式護罩係爲氮化矽 材質。 經濟部智慧財產局員工消費合作社印製 接著，爲製作導電結構之間隙壁(spacer) ’而先以製程 溫度較低（約400〜500°C)的電漿輔助式化學氣相沉積法 (Plasma-Enhanced Chemical Vapor Deposition; PECVD) 沉積一氮化矽層50於所述基板上，然後利用垂直方向之非 均向性電漿蝕刻方式蝕刻所述氮化矽層50，以形成氮化矽 間隙壁50a。由於屬於積體電路之後段製程階段，爲保護已 本紙張尺度適用中國國家標準（CNS > A4規格（210X297公瘦） 409360 經濟部智慧財產局員工消費合作钍印製 A7 _B7_ 五、發明説明（i ) 製作完成之電性元件，故必須選用製程溫度較低的方式來 形成氮化矽之間隙壁介電質，但因PECVD-Si3N4本身特性的 原因，會造成間隙壁上端過寬(over-head)的形狀，如圖四 .A(沿圖一 M’剖面)及圖四B(沿圖一 BB’剖面)所示。 .接著，請參考圖五，其中圖五A係爲沿圖一 M’剖面， 圖五B係爲沿圖一 BB’剖面，於表面沉積一層複晶砂導線層 間介電層(intepoly oxide; IP0)60，由於氮化砂間隙壁50a 之上端過寬的形狀，因此增加了導線結構間的深寬比，所 以當IP0層60塡入導線結構之間時，其滲塡能力將無法完 全塡滿高深寬比的凹溝，而產生了鎖孔K。 再接著，請參考圖六，其中圖六A係爲沿圖一 M’剖面、 圖六B係爲沿圖一BB’剖面、圖六C係爲沿圖一 CC’剖面， 利用習用微影蝕刻方式於所述導電層結構之間的IP0層60 中開啓自行對準接觸窗(SAC)，如圖六B及C中所示。由於 鎖孔K的存在，圖六C中顯示出二分離之自行對準接觸窗 SAC之間，將藉由該鎖孔所形成之細小管道而彼此相通。 隨後，開始製作電容器，先形成電容器複晶矽下層電極 板，此步驟係爲本發明之重點，以兩階段分別沉積複晶矽 層，請參考圖七之沿圖一 CC’之剖面示意圖，首先沉積一薄 層之第一複晶矽層80，所述第一複晶矽層80係採用具有較 差階梯覆蓋能力（step coverage)的複晶砂材質，藉由此一 特性，可將所述鎖孔口封住，而不致使複晶矽完全滲入鎖 孔通道產生兩電容器之短路，本實施例係採用具有較差階 梯覆蓋能力的高溫薄膜(High temperature Film; HTF)複1T Intellectual Property Bureau of the Ministry of Economic Affairs 0H; Industrial and consumer cooperatives printed BL-bit line IPO- polycrystalline silicon interlayer dielectric layer SAC- self-aligned contact window 11- conductive layer 20- polycrystalline sand layer 40- hard cover 60- Interlayer dielectric layer K-keyhole Q-crown type capacitor 10-semiconductor substrate 12-dielectric layer 30-metal silicide 50,50a-silicon nitride layer 70-polycrystalline silicon lower electrode This paper is applicable to China National Standard (CNS) A4 specification (21 ο X 297 mm) A7 B7 409360 V. Description of the invention (/)… 80- HTF polycrystalline silicon layer 90-doped polycrystalline silicon layer Detailed description of the invention: The following is an application The process of making a capacitor in the self-aligned contact window between the lead structures at the latter stage of the integrated circuit is an example to illustrate the present invention. Please still refer to the top view of the structure of the capacitor formed by the self-aligned contact window between the conductive layer structures in Fig. 1. Figs. 3 to 8 show the process of this embodiment along the M ', BB' and CC 'sections in Fig. 1. schematic diagram. First, please refer to FIG. 3, wherein FIG. 3A shows a cross section along FIG. 1M, and FIG. 3B shows a cross section along FIG. 1B ′. A semiconductor substrate 10 having completed the previous process is provided. The surface of the substrate 10 has been formed. There is a conductive layer 丨 1 (usually the second polycrystalline silicon layer poly-2 in the process) and the dielectric layer 12 thereon, and a conductive layer structure is formed on the surface of the above-mentioned semiconductor substrate structure by conventional techniques. The conductive layer structure is used as a bit line. Generally speaking, a polycrystalline silicon layer can be used as the bit line conductive layer structure. In this embodiment, the polycrystalline silicon layer 20 and a silicided metal (si 1 ici de ) Layer 30 has a low-impedance polycrystalline silicidated metal polycide structure (polycide). The polycrystalline sanded metal layer has a hard mask 40 above it, which is usually nitrided. Silicon material. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Next, in order to make the spacers of the conductive structure, the plasma-assisted chemical vapor deposition method (Plasma) with a lower process temperature (about 400 ~ 500 ° C) was first used. -Enhanced Chemical Vapor Deposition; PECVD) deposits a silicon nitride layer 50 on the substrate, and then etches the silicon nitride layer 50 using a vertical non-uniform plasma etching method to form a silicon nitride spacer 50a. Since it belongs to the later stage of the integrated circuit, to protect the paper size, the Chinese national standard (CNS > A4 specification (210X297 male thin)) is applied. 409360 Employees ’cooperation with the Intellectual Property Bureau of the Ministry of Economic Affairs printed A7 _B7_ V. Description of the invention ( i) The finished electrical component must be formed at a lower process temperature to form the silicon nitride spacer dielectric. However, due to the characteristics of PECVD-Si3N4, the upper end of the spacer will be too wide (over- head), as shown in Figure IV. A (along the M 'cross section of Figure 1) and Figure B (along the BB' cross section of Figure 1). Then, please refer to Figure 5, where Figure 5A is along Figure 1. M 'section, Figure 5B is a section along the BB' section of Figure 1, depositing a layer of polycrystalline sand interlayer dielectric layer (intepoly oxide; IP0) 60 on the surface. Because the upper end of the nitrided sand barrier 50a is too wide, Therefore, the aspect ratio between the lead structures is increased, so when the IP0 layer 60 penetrates between the lead structures, its penetration ability will not completely fill the grooves of the high aspect ratio, and a keyhole K is generated. Then, Please refer to FIG. 6, where A of FIG. 6 is along M ′ of FIG. The cross section, FIG. 6B is along the BB ′ section of FIG. 1, and FIG. 6C is the CC ′ section of FIG. 1. The self-aligned contact is opened in the IP0 layer 60 between the conductive layer structures by a conventional lithographic etching method. The window (SAC) is shown in Figures 6B and C. Due to the existence of the keyhole K, Figure 6C shows two separate self-aligning contact windows SAC, which will be formed by the keyhole. The pipelines are in communication with each other. Then, the capacitor production is started, and the capacitor polycrystalline silicon lower electrode plate is first formed. This step is the focus of the present invention. The polycrystalline silicon layer is deposited in two stages, please refer to Figure 7 along Figure 1 CC ' In a schematic cross-sectional view, a thin first polycrystalline silicon layer 80 is first deposited. The first polycrystalline silicon layer 80 is made of a polycrystalline sand material with poor step coverage. With this characteristic, The keyhole opening can be sealed without causing the polycrystalline silicon to completely penetrate into the keyhole channel to cause a short circuit between the two capacitors. This embodiment uses a high temperature film (HTF) with poor step coverage.
孝 P 裝 訂 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 409360 A7 _B7_____ 五、發明説明（^/ ) 晶砂，該HTF複晶砂亦可爲同步摻雜（in-situ doped)複晶 矽，所述第一複晶矽層之厚度係約介於200~400A之間；接 著，請參考圖八之沿圖一 CC’之剖面示意圖，進行第二階段 .沉積一層第二複晶矽層90，該第二複晶矽層90係以習用技 術所沉積的同步摻雜(i η - s i t u doped)複晶政，其厚度係/約 介於500~150〇A之間，目前習知技藝中做爲電容器下層電 極的複晶矽表面沉積有一層半球形晶粒砂(Hemispherical Grain Silicon; HSG-Si)，可增加下層電極表面積以提昇 電容量，故本實施例之所述第二複晶矽層的表面係亦可沉 積一層HSG-Si，該第一及第二複晶砂層80、90即形成電 容器下層電極板。後續將再依序形成電容器介電質層及電 容器複晶矽上層電極板，以完成電容器之製作。 由上所述，本發明的特徵在於兩階段沉積複晶矽層於 ΙΡ0的SAC之中，其中最主要的是第一階段利用具有較差階 梯覆蓋能力的複晶矽薄層，如高溫薄膜(HTF)複晶矽，將鎖 孔口封住，而不致使複晶矽完全滲入鎖孔通道產生兩電容 器之短路。 以上所述係利用較佳實施例詳細說明本發明，而非限 制本發明的範圍，因此熟知此技藝的人士應能明瞭，適當 而作些微的改變與調整，仍將不失本發明之要義所在，亦 不脫離本發明之精神和範圍’故都應視爲本發明的進一步 實施狀況。謹請貴審查委員明鑑’並祈惠准，是所至禱。 本紙張尺度適用中國國家標準（CNS ) A4規格（21 〇 X撕公釐）Xiao P binding line The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 409360 A7 _B7_____ 5. Description of the invention (^ /) Crystal sand, the HTF complex crystal sand can also be doped synchronously (in-situ doped) polycrystalline silicon, the thickness of the first polycrystalline silicon layer is between about 200 and 400A; then, please refer to the cross-sectional schematic diagram along CC 'of FIG. 8 for the second stage. A second polycrystalline silicon layer 90, which is a synchronous doped (i η-situ doped) compound crystal deposited by conventional techniques, and has a thickness of about 500 to 150 Å. A layer of Hemispherical Grain Silicon (HSG-Si) is deposited on the surface of the polycrystalline silicon used as the lower electrode of the capacitor in the conventional art, which can increase the surface area of the lower electrode to increase the capacitance. A layer of HSG-Si can also be deposited on the surface of the second polycrystalline silicon layer, and the first and second polycrystalline sand layers 80 and 90 form a capacitor lower electrode plate. Subsequently, the capacitor dielectric layer and the capacitor polycrystalline silicon upper electrode plate will be sequentially formed to complete the production of the capacitor. From the above, the present invention is characterized in that the polycrystalline silicon layer is deposited in the SAC of IP0 in two stages, the most important of which is the use of a thin layer of polycrystalline silicon with poor step coverage in the first stage, such as a high temperature film (HTF ) Polycrystalline silicon, sealing the keyhole, so that the polycrystalline silicon does not completely penetrate into the keyhole channel, resulting in a short circuit between the two capacitors. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention. Therefore, those skilled in the art should be able to understand that making appropriate changes and adjustments will still not lose the essence of the present invention. Without departing from the spirit and scope of the present invention, it should be regarded as a further implementation of the present invention. I would like to ask your reviewer ’s clear reference, ’and to pray for your sincere prayer. This paper size applies to China National Standard (CNS) A4 (21 〇 Tear mm)