Α7 經濟部中央標準局貝工消費合作社印製 五、發明说明（/ ) 本發明是有關於一種半導體元件的閘極結構與製造方 法，且特別是有關於一種無附加物（Lateral)的閘極結構之-半導體元件與製造方法，其可應用於自行對準金屬矽化物 (Salicide)製程。 自行對準金屬矽化物的形成方式是先在半導體晶片上 形成一層金屬層，其中，最常使用的金屬材料是鈦、白金、 鈷或鎢。之後，將晶片送進高溫的環境，使覆蓋於閘極電 極或源極/汲極的上方之金屬層，因爲與矽接觸而在高溫的 環境下形成金屬矽化物，並且在高溫的環境下進行相位結 構的轉換，而得到電阻値較小的金屬矽化物。在晶片的其 他部分上，金屬層並沒有與矽接觸，因此雖然經過高溫， 也不會產生金屬矽化物，由於這個特性，使得在形成金屬 矽化物時不必經過微影製程的步驟，因此以這種方式所形 成之金屬矽化物稱爲自行對準金屬矽化物。 隨著半導體元件的尺寸變小，亦即當閘極長度（Gate Length)縮小時，在形成自行對準金屬砂化物的技術中也遭 遇到一些問題，例如在形成金屬層後進行高溫反應，使金 屬與矽形成金屬矽化物的過程中，過高的溫度，會使得矽 的成分向旁邊擴散，造成金屬與矽在不預期的位置進行反 應而形成金屬矽化物，這個情形，常會造成元件之間發生 不預期橋接(Bndge)的現象。在習知技藝中，爲了避.免橋 接的問題，在進行高溫製程步驟時須降低溫度，但是如果 溫度太低則很容易使得所形成的金屬矽化物，因爲品質不 佳而無法有效的降低接點間的接觸電阻。 3 3!J—^ .' I!J n I n —1 I I- n n n K K n n ^ (請先閲讀背面之注意事^t填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4祝格（210X297公釐） 經濟部中央標準局貝工消費合作社印製 4305twf.doc/006 A7 _ B7 五、發明説明（Z) 以下請參照第1A圖至第1H圖，來說明習知一種半導 體元件之閘極結構之製造方法。 首先，請參照第1A圖’提供一半導體基底1〇〇，此半 導體基底100具一淺溝渠隔離區（Shallow Trench Isolation)101和一主動區域（Active Area)103。在半導體基 底100上，依序形成一閘極氧化層（Gate Oxide)102、多晶 砂層（Polysilicon)104 和反反光射層(Anti-Reflection Coating，ARC)106。 接著，請參照第1B圖，定義反反光射層106、多晶矽 層104和閘極氧化層102，並去除反反光射層106，以在半 導體基底100的主動區域103上，形成一閘極結構（Gate Structure)105。其中，此閘極結構105包括閘極氧化層102 和閘極電極104a。 然後，請參照第1C圖，以閘極結構105爲罩幕，進 行一低濃度離子植入(Implant)，形成一輕摻雜源極/汲極結 構（Lightly Doped Source/Drain Structure)l 15，例如塡入 N-型離子的輕摻雜源極/汲極結構。 其後，請參照第1D圖，在半導體基底100上，形成 一観氧化層(Liner Oxide)108。然後，在襯氧化層1Q8上， 形成一氮化矽層（SiN Layer)110。 接著，請參照第1E圖，回蝕刻(Etching Back)去除部 分的氮化砂層110及襯氧化層108，以形成一間隙壁 (Spacer)l 10a。 然後，請參照第IF圖，以間隙壁110a和閘極結構105 11111 if ti 11 n I n li ^ - (讀先聞讀背面之注意事产ί填寫本頁) 409298 4305twf.doc/006 A7 B7 經清部中央搮準扃員工消费合作社印裝 五、發明説明（3 ) 爲罩幕，進行高濃度離子植入，以形成一源極/汲極區^ (Source/Drain)112，例如塡入N+型離子的源極/汲極區112。- 其後’請參照第1G圖，形成一鈦金屬層116，覆蓋半 導體基底100、閘極結構105、源極/汲極區112及間隙壁 110a。 接著，請參照第1H圖，進行一高溫製程步驟，使得 在閘極105及源極/汲極區112上的金屬層116與矽反應形 成一自行對準金屬矽化物(Salicide)118。之後，去除未轉變 成金屬矽化物之剩餘的鈦金屬層116。無法避免的，在間 隙壁110a J;會產生自行對準金屬矽化物附加物（Salicide LateiiU120 生成。 在上述製程中，在閘極長度(Gate Length)縮小時，亦 即半導體兀件尺寸變小，閘極線(Gate Line)上的自行對準 金屬砂化物形成（Salicide Formation)的品質變差，使得閘極 電阻變咼，而影響產品的效能（Performance)。因此緣故， 形成自行對準金屬矽化物之快速加熱回火（Rapid Thermal Annealing，RTP)的溫度及時間均需作調整，以得到較佳之 閘極電阻。一般均將快速加熱回火溫度調高或反應時間增 長’以得到較好的自行對準金屬矽化物形成，此做法的副 作用是更容易在間隙壁上形成自行對準金屬矽化物附加 物’而導致閘極與源極/汲極的接觸(Contact)，造成半導體 元件發生短路或橋接現象。尤其是當閘極長度縮小時，此 情形將更爲嚴重。 本發明提出一種半導體元件之閘極結構的製造方法， 5 — 1 J ^-- U3. (請先閱讀背面之注意事W冉填寫本頁) -J§Α7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (/) The present invention relates to a gate structure and a manufacturing method of a semiconductor element, and in particular, to a gate without additional materials (Lateral) Structure-Semiconductor element and manufacturing method, which can be applied to self-aligned metal silicide (Salicide) process. Self-aligned metal silicide is formed by first forming a metal layer on a semiconductor wafer. The most commonly used metal material is titanium, platinum, cobalt, or tungsten. After that, the wafer is sent into a high-temperature environment, so that the metal layer covering the gate electrode or the source / drain electrode is formed in a high-temperature environment due to contact with silicon, and is performed in a high-temperature environment. The phase structure is changed to obtain a metal silicide with a smaller resistance. On the other parts of the chip, the metal layer does not contact the silicon, so no metal silicide will be generated even after high temperature. Because of this characteristic, it is not necessary to go through the lithography process step when forming the metal silicide. The metal silicide formed in this way is called self-aligned metal silicide. As the size of semiconductor elements becomes smaller, that is, when the gate length is reduced, there are also some problems in the technology of forming self-aligned metal sands, such as performing a high temperature reaction after forming a metal layer, so that During the process of metal and silicon forming metal silicide, excessive temperature will cause the components of silicon to diffuse to the side, causing the metal and silicon to react at unexpected locations to form metal silicide. This situation often causes Unexpected bridging occurs. In the conventional art, in order to avoid the problem of bridging, the temperature must be reduced when performing high-temperature process steps, but if the temperature is too low, it is easy to make the formed metal silicide because of poor quality and cannot effectively reduce the connection. Contact resistance between points. 3 3! J— ^. 'I! J n I n —1 I I- nnn KK nn ^ (Please read the notes on the back ^ t to fill out this page) This paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm) Printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4305twf.doc / 006 A7 _ B7 V. Description of the Invention (Z) Please refer to Figures 1A to 1H to explain how to learn a semiconductor device. Manufacturing method of gate structure. First, referring to FIG. 1A, a semiconductor substrate 100 is provided. The semiconductor substrate 100 has a shallow trench isolation area 101 and an active area 103. A gate oxide 102, a polysilicon 104, and an anti-reflective coating (ARC) 106 are sequentially formed on the semiconductor substrate 100. Next, referring to FIG. 1B, the retroreflective reflective layer 106, the polycrystalline silicon layer 104, and the gate oxide layer 102 are defined, and the retroreflective reflective layer 106 is removed to form a gate structure on the active region 103 of the semiconductor substrate 100 ( Gate Structure) 105. The gate structure 105 includes a gate oxide layer 102 and a gate electrode 104a. Then, referring to FIG. 1C, the gate structure 105 is used as a mask to perform a low-concentration ion implantation (Implant) to form a lightly doped source / drain structure 15. For example, lightly doped source / drain structures doped with N-type ions. Thereafter, referring to FIG. 1D, a linear oxide layer 108 is formed on the semiconductor substrate 100. Then, a silicon nitride layer (SiN Layer) 110 is formed on the liner oxide layer 1Q8. Next, referring to FIG. 1E, a part of the nitrided sand layer 110 and the liner oxide layer 108 are removed by Etching Back to form a spacer 10a. Then, please refer to Figure IF, with the partition wall 110a and the gate structure 105 11111 if ti 11 n I n li ^-(Read the first notice on the back and fill in this page) 409298 4305twf.doc / 006 A7 B7 Printed by the Central Government Department of the Ministry of Education and the Consumers ’Cooperatives. V. Invention Description (3) The mask is used for high-concentration ion implantation to form a source / drain region. Source / drain regions 112 of N + type ions. -Hereafter, please refer to FIG. 1G, and a titanium metal layer 116 is formed to cover the semiconductor substrate 100, the gate structure 105, the source / drain region 112, and the spacer 110a. Next, referring to FIG. 1H, a high-temperature process step is performed, so that the metal layer 116 on the gate 105 and the source / drain region 112 reacts with silicon to form a self-aligned metal silicide (Salicide) 118. Thereafter, the remaining titanium metal layer 116 which has not been converted into a metal silicide is removed. It is unavoidable that self-aligned metal silicide addition (Salicide LateiiU120) will be generated in the gap 110a J. In the above process, when the gate length is reduced, that is, the size of the semiconductor element becomes smaller, The quality of the self-aligned metal salicide formation on the gate line becomes worse, which makes the gate resistance worse and affects the performance of the product. Therefore, the self-aligned metal silicide is formed. The temperature and time of Rapid Thermal Annealing (RTP) of materials need to be adjusted to obtain better gate resistance. Generally, the rapid heating and tempering temperature is increased or the reaction time is increased to obtain better Self-aligned metal silicide is formed. The side effect of this method is that it is easier to form self-aligned metal silicide additions on the gap wall, which results in the contact between the gate and the source / drain, causing a short circuit in the semiconductor device. Or bridging phenomenon. Especially when the gate length is reduced, this situation will be more serious. The present invention provides a method for manufacturing a gate structure of a semiconductor element. Method, 5 - 1 J ^ - U3 (Read precautions W Ran fill in the back of this page) -J§.
T % 本纸張尺度適用中国國家揉準（CNS ) A4祝格（210X297公釐） 經濟部中央標準局貝工消費合作社印装 409298 43 05twr.doc/〇〇6 ρ^η B7 五、發明説明（¥ ) 可以避免自行對準金屬矽化物附加物生成，並可提高半導 體元件的良率。 本發明提出一種半導體元件之閘極結構的製造方法， 此方法包括：首先，提供一基底，在基底上，依序形成一 閘極氧化層、導電層、帽蓋層和反反光射層。接著，定義 反反光射層、帽蓋層、導電層和閘極氧化層，並去除反反 光射層’以在基底上形成一閘極結構，且在閘極結構上覆 蓋有帽蓋層。然後，進行一低濃度離子植入，形成一輕摻 雜源極/汲極結構。其後，在基底上，形成一襯氧化層。接 著，在襯氧化層上，形成一氮化矽層。其後，回蝕刻去除 « 部分的氮化矽層及襯氧化層，以形成一間隙壁。然後，以 間隙壁、帽蓋層和閘極結構爲罩幕，進行高濃度離子植入， 以形成一源極/汲極區。其後，去除帽蓋層，裸露出閘極結 構，使間隙壁的頂端高於閘極結構的頂端，以形成一凹槽 結構。接著，形成一金屬層，覆蓋基底、凹槽結構及間隙 壁。然後，進行一高溫製程步驟，使得該凹槽結構內之金 屬層轉變爲一自行對準金屬矽化物。最後，去除剩餘之金 屬層。 本發明同時提出一種半導體元件之閘極結構，應用於 自行對準金屬矽化物製程，此半導體元件包括：（υ.—半 導體基底。（2).—閘極結構，位於半導體基底上，其中閘 極結構包括：一閘極氧化層和一閘極電極，依序形成於半 導體基底上。（3).—襯氧化層，鄰接於閘極結構之側邊。（4). 一間隙壁，鄰接襯氧化層的另一側邊，且間隙壁的頂端高 6 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） 11.-------Ί---裝-------訂------線 V (請先閣讀背面之注意事^:填寫本覓) 409298 4305twi'doc/0 0 6 經濟部中央標準局負工消費合作社印製 五、發明説明（彡） 於閘極結構的頂端，以在間隙壁與閘極結構形成一凹槽結’ 構。（5).—自行對準金屬矽化物層，位於閘極結構上，並-塡入凹槽結構，其中自行對準金屬矽化物層的厚度小於或 等於凹槽結構的深度。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1H是繪示習知一種半導體元件之閛極結 構之製造流程的剖面示意圖；以及 第2A圖至第21圖是繪示本發明一較佳實施例之一種 半導體元件之閘極結構的製造流程的剖面示意圖。 圖式之標記說明： 100，200 :半導體基底 101，201 :淺溝渠隔離區 102，202 :閘極氧化層 103，203 :主動區域 104 :多晶矽層 l〇4a，204a :閘極電極 105，205 :閘極結構 106，208 :反反光射層 108，211 :襯氧化層 110，210 :氮化矽層 110a，210a :間隙壁 ' 7 J . 〔 I 訂 線 (諳先閱讀背面之注意事爷再填寫本頁) 本紙法尺度適用中国國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局負工消費合作社印製 409298 - 4305tw1.doc/006 A 7 _B7 _ 五、發明説明（g ) 112 :源極/汲極區 115，207 :輕摻雜源極/汲極結構 116 :鈦金屬層 118，218 :自行對準金屬矽化物 120:自行對準金屬矽化物附加物 204 :導電層 206 :帽蓋層 209 :凹槽結構 216 :金屬層 實施例 本發明係提出一種半導體元件之閘極結構的製造方 法，以下請參照第2A圖至第21圖說明本發明之實施例。 首先，請參照第2A圖’提供一半導體基底200，此半 導體基底200具一淺溝渠隔離區201和一主動區域203。 在半導體基底200上，依序形成一閘極氧化層202、導電 層204、帽蓋層(Cap Layer)206和反反光射層208。其中形 成導電層204的材質例如爲多晶矽，其形成的方法例如爲 化學氣相沉積法(CVD);形成帽蓋層206的材質例如爲氧 化矽，其形成的方法例如以四乙基-鄰-矽酸酯(Tetra-Ethyl-Ortho-Silicate，TEOS)爲氣體源的低壓化學氣相沉積法 (LPCVD)，帽蓋層206(亦即氧化矽層)的厚度約爲300 A左 右；形成反反光射層208的材質例如爲氮氧化矽（SiO-xNy)，其形成的方法例如爲電漿加強式化學氣相沉積法 (Plasma Enhanced CVD，PECVD)。 8 本紙法尺度逍用中國國家標準（CNS ) A4規格（210X297公釐) (請先閱讀背面之注意事項再填寫本頁) •裝· 訂 409298 4305twf. doc/006 A7 B7 五、發明説明（9) 然後，請參照第2 B圖，定義反反光射層208 '帽蓋^ 層206、導電層204和閘極氧化層202，並去除反反光射層-208，以在半導體基底200的主動區域203上，形成一閘極 結構205 ’且在閘極結構205上覆蓋有帽蓋層206。其中， 此閘極結構205包括閘極氧化層202和閘極電極204a。 接著，請參照第2 C圖，以閘極結構205和帽蓋層206 爲罩幕’進行一低濃度離子植入，形成一輕摻雜源極/汲極 結構207,例如塡入N_型離子的輕摻雜源極/汲極結構207。 其後，請參照第2 D圖，在半導體基底200上，形成 一襯氧化層211。然後，在襯氧化層211上，形成一氮化 矽層(SiN Layer)210。其中形成襯氧化層211的方法例如爲 低壓化學氣相沉積法(LPCVD);形成氮化矽層210的方法 例如爲化學氣相沉積法(CVD)-。 然後，請參照第2 E圖，以回蝕刻(Etching Back)法， 例如爲非等向性蝕刻法，去除部分的氮化矽層210及襯氧 化層211，以形成一間隙壁210a。其中間隙壁210a的材質 例如爲氮化矽。 接著，請參照第2F圖，以間隙壁210a、帽蓋層206 和閘極結構205爲罩幕，進行高濃度離子植入，以形成一 源極/汲極區212，例如塡入N+型離子的源極/汲極區212。 其後，請參照第2G圖，去除帽蓋層206，裸露出閘極 結構204a，使間隙壁210a的頂端高於該閘極結構205的 頂端，以形成一凹槽結構209。其中，此凹槽結構209的 深度Η約爲300 A左右。這個凹槽結構209爲本發明之一 9 本紙張尺度適用中國囷家揉準（CNS ) A4規格（210X297公釐} J------^----------1T------0 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印製 經濟部中央標準局貝工消費合作社印製 409298 4305twt*. doc/006 A 7 B7 五、發明説明（o ) 重要特徵，在後續的高溫製程步驟中，間隙壁210a與閘 極結構205所形成的此一凹槽結構209，可以使得在後續 的步驟中形成的金屬層216(繪示於第2H圖中）在凹槽結構 209中形成較厚的自行對準金屬矽化物(繪示於第21圖中）1 並且避免閘極電極204的矽擴散出來，在間隙壁210a的表 面形成金屬矽化物的附加物，而造成閘極電極204與源極/ 汲極區212之間發生橋接的問題。 然後*請參照第2H圖，形成一金屬層216，覆蓋半導 體基底200、凹槽結構209及間隙壁210a。此金屬層216 的材質例如爲鈦、白金、鈷或鎢，而形成此金屬層216的 方法例如以磁控DC濺鍍的方式。 接著，請參照第21圖，進行一高溫製程步驟，使得 凹槽結構209內之金屬層216轉變爲一自行對準金屬矽化 物218。其中，高溫製程步驟例如以750°C至850t左右的 高溫進行；形成自行對準金屬矽化物218的材質例如爲 TiSi2。之後，去除未轉變成金屬矽化物之剩餘的金屬層 216，移除剩餘的金屬層之方法例如爲以濕蝕刻的方法進 行。 本發明係另外提出一種半導體元件的閘極結構，以下 請參照第21圖說明本發明之實施例。 一種半導體元件之閘極結構，應用於自行對準金屬矽 化物製程中，此半導體元件之閘極結構包括： (1).一半導體基底200，此半導體基底200具一淺溝渠隔離 區201和一主動區域203。 本紙張尺度逋用中國國家榡準（CNS ) A4洗格（210X297公釐） ----11---_----裝------訂一------線 (請先閱讀背面之注$巩再填寫本頁) 43 05twf.doc/006 A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（） (2) ·—閘極結構205，位於半導體基底200之主動區域203 上，其中鬧極結構205包括：一聞極氧化層202和一閘極 電極204a，依序形成於半導體基底200上。其中，形成閘 極電極的材質例如爲一多晶石夕。 (3) ,—襯氧化層211，鄰接於閘極結構205之一側邊。 (4) .—間隙壁210a，鄰接襯氧化層211的另一側邊，且間 隙壁210a的頂端高於閘極結構205的頂端，使得間隙壁210a 與閘極結構205形成一凹槽結構209(如第2G圖所示，以 Η表示）。此間隙壁210a的頂端高於閘極結構205的頂端， 以在間隙壁210a與閘極結構205形成一凹槽結構209，其 爲本發明的特徵之一。其中，間隙壁210a的頂端高於閘 極結構205的頂端之凹槽結構209的深度Η約爲300A左 右。 (5) .—自行對準金屬矽化物層218，位於閘極結構205上， 並塡入凹槽結構209中，其中自行對準金屬矽化物層218 的厚度小於或等於凹槽結構209的深度Η。其中，自行對 準金屬矽化物層218的材質例如矽化鈦。. 綜上所述，本發明的一個重要特徵爲在自行對準金屬 矽化物形成之前，間隙壁的頂端高於閘極結構的頂端，利 用此高出的間隙壁做屏障，將自行對準金屬矽化物形成並 固定在閘極結構上，當在自行對準金屬矽化物製程中，調 高快速加熱回火溫度或時間加長時，自行對準金屬矽化物 不會因附加物生成而跨過此屏障而形成到間隙壁上，形成 閘極和源極/汲極之間的橋接現象，而發生短路。又因爲快 ▼ 0¾ (請先聞讀背面之注意事項再填寫本页) ，νβ 本紙張尺度適用中國國家標準（CMS ) Α4規格（210X297公釐) 409298 4305ivvf.dot:/006 A7 五、發明説明（ί。） 速加熱回火溫度或時間均有調高的空間，對自行對準金屬 矽化物形成有正面助益。 由上述本發明較佳實施例可知，應用本發明具有下列 優點：（1).當在自行對準金屬矽化物製程中，調高快速加 熱回火溫度或時間加長時，自行對準金屬矽化物不會因附 加物生成，可提高半導體元件良率。（2).因爲快速加熱回 火溫度或時間均有調高的空間，對自行對準金屬矽化物形 成有幫助，可提高自行對準金屬矽化物的品質。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 ----ί Γ--^----裝---丨^--訂------線 (#先聞讀背面之注意事項再填寫本頁) 經濟部卡央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）T% This paper size is applicable to China National Standards (CNS) A4 (210X297 mm) Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 409298 43 05twr.doc / 〇〇6 ρ ^ η B7 V. Description of the invention (¥) It can avoid the formation of self-aligned metal silicide additions, and can improve the yield of semiconductor devices. The invention provides a method for manufacturing a gate structure of a semiconductor element. The method includes: first, providing a substrate, and sequentially forming a gate oxide layer, a conductive layer, a cap layer, and a reflective reflective layer on the substrate. Next, define a retroreflective layer, a cap layer, a conductive layer, and a gate oxide layer, and remove the retroreflective layer 'to form a gate structure on the substrate, and cover the gate structure with a cap layer. Then, a low concentration ion implantation is performed to form a lightly doped source / drain structure. Thereafter, an oxide layer is formed on the substrate. Next, a silicon nitride layer is formed on the liner oxide layer. After that, etch-back removes the «part of the silicon nitride layer and the liner oxide layer to form a spacer. Then, the spacer, the cap layer and the gate structure are used as a mask to perform high-concentration ion implantation to form a source / drain region. Thereafter, the cap layer is removed, and the gate structure is exposed, so that the top of the gap wall is higher than the top of the gate structure to form a groove structure. Next, a metal layer is formed to cover the base, the groove structure and the spacer. Then, a high-temperature process step is performed to transform the metal layer in the groove structure into a self-aligned metal silicide. Finally, the remaining metal layers are removed. The invention also proposes a gate structure of a semiconductor element, which is applied to a self-aligned metal silicide process. The semiconductor element includes: (υ.—semiconductor substrate. (2) .— a gate structure located on the semiconductor substrate, wherein the gate The gate structure includes: a gate oxide layer and a gate electrode, which are sequentially formed on a semiconductor substrate. (3).-A lining oxide layer adjacent to the side of the gate structure. (4) a gap wall, adjacent The other side of the oxide layer is lined, and the top of the gap wall is 6 inches higher. This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 11 .------- Ί ----- ----- Order ------ line V (please read the notice on the back ^: fill in this search) 409298 4305twi'doc / 0 0 6 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Description of the invention (彡) At the top of the gate structure to form a groove structure between the gap wall and the gate structure. (5).-Self-aligned metal silicide layer, located on the gate structure, and-塡Into the groove structure, wherein the thickness of the self-aligned metal silicide layer is less than or equal to the depth of the groove structure. The above and other objects, features, and advantages can be more clearly understood. The following is a detailed description of a preferred embodiment and the accompanying drawings, as follows: Brief description of the drawings: Figures 1A to 1H are FIG. 2A to FIG. 21 are cross-sectional schematic diagrams showing a manufacturing process of a gate structure of a semiconductor device according to a preferred embodiment of the present invention. Explanation of the symbols of the drawings: 100, 200: semiconductor substrate 101, 201: shallow trench isolation region 102, 202: gate oxide layer 103, 203: active region 104: polycrystalline silicon layer 104a, 204a: gate electrode 105, 205: Gate structure 106, 208: Reflective reflective layer 108, 211: Oxide lining layer 110, 210: Silicon nitride layer 110a, 210a: Spacer wall '7 J. [I Thread (read the precautions on the back first) Master fills in this page again) This paper method applies the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed by the Central Consumers Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 409298-4305tw1.doc / 006 A 7 _B7 _ V. Description of the invention ( g) 112: source / drain Regions 115, 207: lightly doped source / drain structure 116: titanium metal layer 118, 218: self-aligned metal silicide 120: self-aligned metal silicide 204: conductive layer 206: capping layer 209: Groove structure 216: Embodiment of metal layer The present invention proposes a method for manufacturing a gate structure of a semiconductor device. Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 2A to 21. First, referring to FIG. 2A, a semiconductor substrate 200 is provided. The semiconductor substrate 200 has a shallow trench isolation region 201 and an active region 203. On the semiconductor substrate 200, a gate oxide layer 202, a conductive layer 204, a cap layer 206, and a reflective reflective layer 208 are sequentially formed. The material for forming the conductive layer 204 is, for example, polycrystalline silicon, and the method for forming it is, for example, chemical vapor deposition (CVD); the material for forming the capping layer 206 is, for example, silicon oxide, and the method for forming it is, for example, tetraethyl-o- Tetra-Ethyl-Ortho-Silicate (TEOS) is a low-pressure chemical vapor deposition (LPCVD) method using a gas source. The thickness of the cap layer 206 (that is, the silicon oxide layer) is about 300 A; reflective reflection is formed. The material of the emitter layer 208 is, for example, silicon oxynitride (SiO-xNy), and the method for forming the emitter layer 208 is, for example, Plasma Enhanced Chemical Vapor Deposition (PECVD). 8 Chinese paper standard (CNS) A4 specification (210X297 mm) (Please read the notes on the back before filling in this page) • Binding and ordering 409298 4305twf. Doc / 006 A7 B7 V. Description of the invention (9 ) Then, referring to FIG. 2B, define the retroreflective layer 208 'cap ^ layer 206, the conductive layer 204 and the gate oxide layer 202, and remove the retroreflective layer -208 to cover the active area of the semiconductor substrate 200. On 203, a gate structure 205 ′ is formed, and the gate structure 205 is covered with a capping layer 206. The gate structure 205 includes a gate oxide layer 202 and a gate electrode 204a. Next, referring to FIG. 2C, a low-concentration ion implantation is performed using the gate structure 205 and the capping layer 206 as a mask to form a lightly doped source / drain structure 207, such as a doped N_ type. The lightly doped source / drain structure 207 of the ions. Thereafter, referring to FIG. 2D, an oxide liner 211 is formed on the semiconductor substrate 200. Then, a silicon nitride layer (SiN Layer) 210 is formed on the liner oxide layer 211. The method for forming the liner oxide layer 211 is, for example, a low-pressure chemical vapor deposition (LPCVD) method; the method for forming the silicon nitride layer 210 is, for example, a chemical vapor deposition (CVD) method. Then, referring to FIG. 2E, an Etching Back method, such as an anisotropic etching method, is used to remove a portion of the silicon nitride layer 210 and the lining oxide layer 211 to form a spacer 210a. The material of the spacer 210a is, for example, silicon nitride. Next, referring to FIG. 2F, the spacer 210a, the capping layer 206, and the gate structure 205 are used as a mask to perform high-concentration ion implantation to form a source / drain region 212, for example, N + ion Source / drain region 212. Thereafter, referring to FIG. 2G, the cap layer 206 is removed, and the gate structure 204a is exposed, so that the top of the spacer 210a is higher than the top of the gate structure 205 to form a groove structure 209. The depth 此 of the groove structure 209 is about 300 A. This groove structure 209 is one of the present invention. 9 The paper size is applicable to the Chinese family standard (CNS) A4 (210X297 mm) J ------ ^ --------- 1T- ----- 0 (Please read the notes on the back before filling in this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by the Shellfish Consumer Cooperatives Printed by the Central Standards Bureau of the Ministry of Economics, printed by the Shellfish Consumer Cooperatives 409298 4305twt *. Doc / 006 A 7 B7 V. Description of the invention (o) Important feature: In the subsequent high-temperature process step, the groove structure 209 formed by the partition wall 210a and the gate structure 205 can make the metal layer 216 ( (Shown in FIG. 2H) a thick self-aligned metal silicide is formed in the groove structure 209 (shown in FIG. 21) 1 and the silicon of the gate electrode 204 is prevented from diffusing out of the gap 210a. Additions of metal silicides are formed on the surface, causing bridging between the gate electrode 204 and the source / drain region 212. Then * Please refer to FIG. 2H to form a metal layer 216 to cover the semiconductor substrate 200 and the recess The groove structure 209 and the partition wall 210a. The material of the metal layer 216 is, for example, titanium, platinum, cobalt, or Tungsten, and the method for forming the metal layer 216 is, for example, magnetron DC sputtering. Next, referring to FIG. 21, a high temperature process step is performed so that the metal layer 216 in the groove structure 209 is transformed into a self-alignment. Metal silicide 218. Among them, the high-temperature process step is performed at a high temperature of about 750 ° C to 850t, for example; the material for forming the self-aligned metal silicide 218 is, for example, TiSi2. After that, the remaining metal layer that is not converted into the metal silicide is removed. 216, the method of removing the remaining metal layer is performed by, for example, a wet etching method. The present invention proposes a gate structure of a semiconductor element, and an embodiment of the present invention is described below with reference to FIG. 21. A gate of a semiconductor element The electrode structure is used in a self-aligned metal silicide process. The gate structure of the semiconductor device includes: (1) a semiconductor substrate 200 having a shallow trench isolation region 201 and an active region 203. Paper size: China National Standards (CNS) A4 washing grid (210X297 mm) ---- 11 ---_---- installation ------ order one ------ line (please First read the note on the back. (Fill in this page) 43 05twf.doc / 006 A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () (2)-Gate structure 205 is located on the active area 203 of the semiconductor substrate 200, of which The anode structure 205 includes: an oxide layer 202 and a gate electrode 204a, which are sequentially formed on the semiconductor substrate 200. The material forming the gate electrode is, for example, a polycrystalline stone. (3),-the lining oxide layer 211 is adjacent to one side of the gate structure 205. (4).-The spacer 210a is adjacent to the other side of the lining oxide layer 211, and the top of the spacer 210a is higher than the top of the gate structure 205, so that the spacer 210a and the gate structure 205 form a groove structure 209 (As shown in Figure 2G, indicated by Η). The top end of the spacer wall 210a is higher than the top end of the gate structure 205 to form a groove structure 209 in the gap wall 210a and the gate structure 205, which is one of the features of the present invention. The depth of the groove structure 209 at the top of the spacer 210a is higher than that of the gate structure 205, which is about 300A. (5) .— Self-aligned metal silicide layer 218 is located on the gate structure 205 and is inserted into the groove structure 209, wherein the thickness of the self-aligned metal silicide layer 218 is less than or equal to the depth of the groove structure 209 Alas. Among them, the material of the self-aligned metal silicide layer 218 is, for example, titanium silicide. In summary, an important feature of the present invention is that before the self-aligned metal silicide is formed, the top of the gap wall is higher than the top of the gate structure. Using this higher gap wall as a barrier, the self-aligned metal will be aligned. The silicide is formed and fixed on the gate structure. When the self-aligned metal silicide process is adjusted to increase the rapid heating and tempering temperature or the time is prolonged, the self-aligned metal silicide will not cross this due to the formation of additional substances. A barrier is formed on the gap wall, forming a bridge between the gate and the source / drain, and a short circuit occurs. Because of the fast ▼ 0¾ (please read the precautions on the back before filling in this page), νβ This paper size applies the Chinese National Standard (CMS) Α4 specification (210X297 mm) 409298 4305ivvf.dot:/006 A7 V. Description of the invention (Ί.) There is room to increase the temperature or time of the rapid heating and tempering, which has a positive effect on the formation of self-aligned metal silicide. It can be known from the above-mentioned preferred embodiments of the present invention that the application of the present invention has the following advantages: (1). In the self-aligned metal silicide process, when the rapid heating tempering temperature is increased or the time is lengthened, the metal silicide is self-aligned. Since no additive is generated, the yield of the semiconductor device can be improved. (2). Because the rapid heating and tempering temperature or time can be adjusted, it is helpful for the formation of self-aligned metal silicide, which can improve the quality of self-aligned metal silicide. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. ---- ί Γ-^ ---- install --- 丨 ^-order ------ line (#First read the notes on the back and fill out this page) Employees of Card Central Standards Bureau, Ministry of Economic Affairs The paper size printed by the consumer cooperative is applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm)