TW408456B - Ceramic chip form semiconductor diode - Google Patents

Abstract

The present invention provides a new packaging form of a semiconductor diode, which is fabricated by using low-temperature cofired ceramic (LTCC) technology. The fabrication method is low-cost and the resulting chip form semiconductor diode has good hermeticity and high reliability. The fabrication method includes the steps of: (a) providing a ceramic green tape having a through hole for positioning a diode die; (b) positioning a diode die in the through hole; (c) sandwiching the diode die between two ceramic green tapes having printed conductive layers facing the electrode surfaces of the diode die; (d) laminating the ceramic tapes into a compact such that the conductive layers connect to the electrodes of the diode die; (e) firing the laminated parts to form a monolithic sintered body; and (f) forming end terminals, and solder-plating the end terminals to finish a ceramic chip of the semiconductor diode.

Description

408456 V. Description of the invention (1) [Field of the invention] The present invention provides an innovative package design for silicon semiconductor rectifier diodes, which is related to the multilayer ceramic packaging technology. In particular, low-temperature co-fired ceramics are used to make a polar core chip. Superimposed, degreased, and co-mingled with ceramic raw embryo thin menstruation, wafer-type diode elements. This new type of diode package can be used. The diode packaging process improves the air-tightness of the diode element and relies on [Background of the Invention] A common silicon semiconductor diode package can be used for packaging. Forms of coarse type Ⅱ: (1) metal or ceramic carrier packaging, plastic mold sealing: ,, = (3) glass polymer rotating ㈣ packaging. In the first type of package, the dipoles are placed in the recesses of metal or ceramic pre-digging, and then the upper and lower surfaces of the dipole cores are connected by brazing. Because the diode domain or the material cannot be completely tightly sealed, this package is poor in airtightness and low in reliability. The second type of plastic mold packaging is to first connect the diodes; they can be soldered or hard-bonded, and then sealed with a plastic material to ensure that there is no gap between the wire electrode f and the packaging material.装 材料。 Loading materials. As for the third type of glass slurry spin-coating package, the sealing temperature of molybdenum or tungsten is bonded to the diode core. The glass is: high. The coating method covers the entire diode to form a polymer-resistant material = good. Packaged components; but the disadvantage is the complexity of m material aeration = process' and the obtained diode components are: Ma Yongfan, page 5 C '\ Prógraro Files \ Patent \ 0582-3796-E. Ptd 408456 V. Description of the invention (2) In response to the demand for miniaturization of electronic products, the development of chip-type diode devices has become increasingly important . The two main technologies for making wafer-type components include (1) thin film method-plating and photoetching (2) thick film method-to knife forming. The thin film process should be used for the production of diode chips, while the thick film method is used for the packaging of the diode chips. Due to the maturity of low-temperature co-firing technology in multilayer ceramic packages, it can greatly simplify the process steps of wafer-type diodes, and at the same time have the inherent high air-tightness and high reliability of ceramic packages. Therefore, the new form of diode packaging design described in the present invention is to use this low-temperature co-firing technology to make the diode core chip and ceramic research embryo sheet through the steps of lamination, degreasing, and co-firing to form a wafer type. Diode element. [Prior art] a Semiconductor component package proposed in US Patent No. 4,540,603 ^ It is connected to an external copper bearing by lead-tin soldering, and then protected by an external package. This package is mainly composed of high molecular weight :: prefabricated =, not resistant to high temperature environment, poor air tightness, and because of the use of wire bearing squares' application range is limited. Enclosed. The semiconductor element seal proposed in US Patent No. 49421 39 is similar to Patent No. 454G6Q3. It is also packaged with a polymer '= axis method, but with different materials such as aluminum, conductor axis, and semiconductor wafer. Metallized connection layer. At first, it was also proposed in S. U.S. Patent No. 5 1 66098; Ϊ ;: two polymers were used as barrel-shaped outer layers. A was proposed in U.S. Patent No. 50 1 9535.

408456 V. Description of the invention (3) ~ · $ Replace the original metal connection method of the conductor layer with the thermoplastic molecule P I (Polyimide) and the substrate followed by '. This method incorporates the chip into the circuit design of the entire integrated circuit. Although it can effectively reduce the package size, it also reduces the variability in circuit design. U.S. Patent No. 5,372,721 proposes a miniaturized appearance integrated circuit seal (S0ICP) method, which is connected to a lead frame by semiconductor wafer metallization and wire bonding and then encapsulated with epoxy resin. Compared with ceramic packaging, it still has poor air tightness and reliability. The chip-type diode packaging method proposed in U.S. Patent No. 5550086 is to place a diode core chip in a groove of a ceramic plate that has been densely sintered and screen-printed with external electrodes, and the diode is sealed with a glass gel. The body core sheet is fixed to the pottery groove groove, and the positive and negative surfaces of the core sheet are covered with a conductor layer, and the outer electrode is connected to the outer electrode. Finally, a glass shaft is covered to complete the overall package. [Objective of the Invention] It is known from the foregoing prior art that wafer-type diodes are urgently needed in electronic products to achieve light, thin, short, and small product design requirements. Considering the reliability, functionality, and simplification of manufacturing processes, the application of low-temperature co-fired ceramic packaging technology to the fabrication of wafer-type diodes is becoming increasingly important. The purpose of the present invention is to provide an innovative package design for a silicon semiconductor rectifier diode, and to use a low-temperature co-fired ceramic technology to make a new type ceramic wafer type diode element. An object of the present invention is to provide a method for manufacturing a ceramic wafer type silicon semiconductor rectifier diode, which can effectively simplify the manufacturing process and reduce the manufacturing cost.

C: \ Prograoi Files \ Patent \ 0582_3796-E.pt (i page 7 408 ^ 56 V. Description of the invention (4) Another object of the present invention is to provide a polar element, which has a good airtightness. Porcelain and component reliable ceramic wafer type [Brief description of the invention] The new method disclosed in the present invention is to use a low-temperature co-firing ceramic method to make ceramic green sheets, and set the hole size of the diode core to Facilitate the subsequent stacking and pressing of the green embryos in the degreasing and co-firing steps of the diode core sheet; finally, the diode core sheet is packaged. The following steps are detailed: (a) Provide a ceramic green sheet-sized hole ; (B) placing a diode core (c) on the layer of the ceramic core of the diode chip and making contact with the surface; the encapsulation technology of the semiconductor chip diode is used for packaging steps: first on the ceramic green embryo; Through punching shape, the thickness of this raw embryo needs to be slightly larger; the upper and lower surfaces of the screened wire layer are laminated and laminated to attach the terminal electrode and electroplating. The "manufacturing sheet of the present invention" has a placeable sheet In the hole; the upper and lower surfaces are covered with a layer of printed overlay Make the conductor layer and core sheet (d) sinter and compact the above-mentioned ceramic multilayer green body to form one (e), attach the terminal electrode and electroplating tin to complete the fabrication of the chip-type surface-adhesive component; The core can be placed two pieces of Taoman, cut, and tin, and the finished method includes the anode and cathode body of the diode core brushed with a conductor; and the diode surface [simple description of the diagram]

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^ 〇845β V. Description of the invention (5) Method flow 1 The diagram is not made of the new form of the crystal moon type silicon semiconductor diode f, the solid diagram of the present invention shows the new form of the wafer type silicon semiconductor diode Figure 2B shows the side view of the various layers of ceramics before the superimposed embryos are packaged. Packages for the steps of post firing, upper electrode, and electric ore etc. [Symbols] Bulbs; 2 ~ Ceramic raw materials Embryo; L conductor layer; 4 ~ terminal electrode and electroplating layer. [Detailed description of the invention], the new type of wafer type silicon semiconductor diode packaging method of the present invention, the finished diode core chip is made and co-fired at low temperature Multi-layer ceramic packaging = encapsulation, can be obtained according to the steps of doctor blade forming, punching, screen printing, lamination, co-firing, adhesion of terminal electrodes, tin plating, etc. The following describes the chip with Figure 1. The manufacturing process of the type diode. First, the rectifying diode wafer with PN layer diffusion completed is prepared in (101) first, and the positive and negative electrode coating process is performed on the rectifying diode wafer in (10 2). Among them, The metallization coating on the positive and negative electrode surfaces can be aluminum, , Silver plated or gold plated secondary 'to meet different needs. In (1〇3) the completion of the metal plating film of the wafer, cutting or chemical etching, sand-blasting, etc. made Ruipian

ΐΗΗΗΙΙ 11H C: \ Program Files \ Patent \ 0582-3796-E.ptd page 9 40S456 V. ‘Explanation (6) Continue with chemical etching and oxidation treatment. In order to package and protect the diode core chip, select the diode core that can be used. Sheet of low temperature co-firing glass-ceramic material (sintering and densification temperature needs to be lower than 800C), mixed with solvent and organic molecules, and prepared into a slurry (201) with proper rheological behavior for doctor blade forming to produce ceramic raw materials Embryo (202). After drying, the green embryo flakes are subjected to green embryo punching and wire screen printing according to the traditional thick film manufacturing method (203). In step (104) ', the diode core piece is placed in the cavity of the ceramic green embryo that has been punched. It should be noted that the thickness of the ceramic green embryo should be slightly larger than the thickness of the diode core piece. The positive and negative surfaces of the diode core sheet are covered with a layer of ceramic green embryos printed with a conductor layer on each side, and the alignment of the core sheet and the conductor layer is performed at (105). Combination, (丨 07) element cutting, (108) degreasing and co-firing treatment, and finally (丨 09) attaching the terminal electrode and electroplating tin to complete the new form of wafer type silicon semiconductor of the present invention. Production of polar bodies. In the above, the stacked ceramic green sheets of (106) can be uniaxially laminated or hot-pressed to align the ceramic green sheets that have been positioned; and the degreasing and co-firing treatment of (108) can be performed at 500 After staying at ° C for 1 hour to complete degreasing, the temperature is then raised to a higher temperature (not more than 800 ° C) to sinter and compact. Figures 2A and 2B are side views of each layer of ceramic green embryos before and after stacking between the diode core and the ceramic packaging material. With the production process described in Figure 1, the wafer type II can be clearly described. The overall design and manufacturing method of the polar body. The numbers 1 to 4 marked in the figure represent (1) diode core pieces, (2) ceramic green embryos, (3) conductor layers, and (4) terminal electrodes and plating layers. Because the manufacturing method of this new type of wafer type diode is low temperature

C: \ ProgramFiles \ Patent \ 0582-3796-E.ptd page 10 408456 V. Description of the invention (7) Ceramic = f packaging technology 'The materials used to package the diode chip include: $ IM KL, and the conductor layer Must be co-fired with the diode core chip at low temperature, shape; 0 ,, gas-tight wafer-type ceramic diode element. It is worth noting that the heat treatment temperature of general diode core pieces cannot be higher than 800 t. ^ = Diode core pieces are destroyed. Therefore, the choice of packaging materials, especially the second 34, whether the powder can be as low as 1 to 800,000 (the following sintering is 'dense,' owning enough is the primary consideration for this type of packaging. * 于 陶 兖 生 = ^ 共The amount of shrinkage in the XY direction during firing will affect the diode core chip and the ceramic material 1 B, the degree of adhesion, the punching size of the ceramic green embryo, and the lamination condition of T caused by the stacking step, which is the key to the overall packaging technology. In addition, because the a-chip monopolar element needs to be fixed to the circuit board using surface adhesion technology, the thermal expansion coefficient between the polar chip and the ceramic packaging material must be similar to avoid excessive soldering during the solder heat treatment process. Thermal stress causes cracks and damage to the element. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention. Various modifications and retouching can be made, so the protection scope of the present invention shall be determined by the scope of the attached patent application.

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Claims (1)

Gongmeng ----------- 2 "26. Patent application scope 1. A method for manufacturing a ceramic wafer type silicon semiconductor diode, including the following steps: (a) providing a ceramic green sheet It has a hole the size of a diode core piece, (b) A diode core piece is placed in the hole; (c) A conductor layer is printed on the upper and lower surfaces of the diode core piece. The ceramic green sheet is laminated, and the conductor layer is brought into contact with the positive and negative surfaces of the core sheet after lamination; (d) the ceramic laminated green sheet is sintered and compacted to form one body; and (e) the end electrodes are attached and Tin electroplating to complete the fabrication of wafer-type diode surface adhesive components. 2. The manufacturing method as described in item 1 of the scope of patent application, wherein the thickness of the green sheet in step (a) is slightly greater than the thickness of the diode core sheet 3. The manufacturing method according to item 1 of the scope of patent application, wherein the conductor layer is made by a thick film screen printing method. 4. The manufacturing method according to item 1 of the scope of patent application, wherein step (c) is Thin ceramic ceramics that have been positioned by uniaxial lamination or hot equalization Lamination./ 5. The manufacturing method described in item 1 of the scope of patent application, wherein step (c) further comprises: cutting the laminated ceramic green embryo. 6. As described in item 1 of the scope of patent application Manufacturing method, wherein step (d) is sintered at a temperature lower than 800 ° C. 7. A ceramic wafer-type dicing semiconductor diode made according to the manufacturing method described in item 1 of the scope of patent application body., C: \ ProgramFiles \ Patent \ 0582-3796-E, ptd page 12