本發明4μ 锸拎盖古〜有關於一種半導體製程’且特別是有關於一 t a声 电浆積層之線—線電容值一致性的方法。 介電；；；電製程⑽P-CVD)所製作的内金屬 芬古贫♦ 11如同役度電漿未摻雜矽玻璃（HDP-USG)以 漿磷矽玻璃（HDP-FSG)，其根據報導顯示具有 一杜真特性’且特別在次微米超大型積體電路（ULS I) 兀仵。 #间密度電漿化學氣相沉積製程主要是先利用電漿化學 氣相沉積法沉益_ ^ Μ . ，、 儿積一内金屬介電層於含金屬内連線之基底表 =制並且部分溝填之金屬内連線間的溝渠。然後’再以濺 二衣程削掉部分位在金屬内連線邊緣以及溝渠間的内金屬 介電層’使得内金屬介電層可再繼續填入溝渠内。重複上 述的/儿積、減鍍製程便可形成—溝填良好的内金屬介電 f ’而重複的次數則依線寬以及元件的積集度而定，其中 若線寬窄且積集度密的話’則可增加沉積、濺鍍的重複次 數。 然而’由於高密度電漿氣相沉積過程的離子具有極高 的轟擊能量，因此在沉積到基底表面後，往往會造成基底 表面溫度不均勻’使得所獲得之高密度電漿化學氣相沉積 層的線-線電容值不一致，此結果將使得後續形成之電路 性能產生極大的差異性。 有鑑於此’本發明乃揭示一種改善高密度電漿沉積層 之線-線電容值一致性的方法’其特徵為在高密度電漿沉 積層形成於一基底表面時’增加該基底背面之散熱氣體的The present invention relates to a method for manufacturing a semiconductor process, and more particularly to a method for coherent line-line capacitance values of a t a acoustic plasma laminate. Dielectric ;;; In-process metal (P-CVD) produced by the metal fengal lean ♦ 11 As the active plasma non-doped silica glass (HDP-USG) and plasma phosphorous silicon glass (HDP-FSG), according to the report The display has a true-duty characteristic, and is particularly in the sub-micron ultra large integrated circuit (ULS I) vulture. The #density plasma chemical vapor deposition process mainly uses the plasma chemical vapor deposition method Shen Yi _ ^ Μ, and the inner layer of a metal dielectric layer on a substrate containing metal interconnects is manufactured and partially Trench between metal interconnects in a trench. Then, “the inner metal dielectric layer located at the edge of the metal interconnect line and between the trenches is cut off again in a sputtering process” so that the inner metal dielectric layer can continue to fill the trench. It can be formed by repeating the above-mentioned process, reducing the plating process-the internal metal dielectric f 'with a good trench filling, and the number of repetitions depends on the line width and the degree of accumulation of the components, where the line width is narrow and the degree of accumulation is dense If you use it, you can increase the number of repetitions of deposition and sputtering. However, because the ions of the high-density plasma vapor deposition process have extremely high bombardment energy, after deposition on the substrate surface, the temperature of the substrate surface is often uneven, which makes the obtained high-density plasma chemical vapor deposition layer. The line-to-line capacitance values are inconsistent. This result will cause great differences in the performance of subsequent circuits. In view of this, the present invention discloses a method for improving the line-line capacitance value consistency of a high-density plasma deposition layer, which is characterized by 'increasing heat dissipation on the back of the substrate when the high-density plasma deposition layer is formed on a substrate surface Gas
第4頁 40837η 五、發明說明（2) 流量分佈及大小，以期有效的增加基底溫度分佈的均勻度 和降低基底的沉積溫度，亦即用以改善該高密度電漿沉積 層的溫度一致性。其中，該散熱氣體包為氮氣、氦氣、氬 氣或其他惰性氣體。至於基底背面之散熱方式，則可分為 内圈散熱氣體及一外圈散熱氣體。藉由調整内、外圈散熱 氣體的壓力大小及相對比率，可使晶圓溫度被有效地控 制。 為使本發明之優點及特徵更清楚可見，玆將以根據本 發明之較佳實施例，並配合相關圖式詳細說明如下。 圖式之簡單說明： 第1圖顯示的是在0.18#m製程中比較根據本發明以及 習知製程製備的高密度電漿氟摻雜矽玻璃的線-線電容值 (L-L capacitance)。 實施例： 首先，提供四片晶圓，編號分別為W1〜W4。接著，利 用0. 1 8 // m製程，於此四片晶圓上分別形成高密度電漿化 學氣相沉積層，然後再測量不同位置的線〜線電容值。以 下將描述此四片晶圓上之高密度電漿化學氣相沉積層之形 成步驟。 W1 :利用高密度電漿沉積法於編號W1的晶圓表面形成 一厚度約18K埃之高密度電漿化學氣相沉積的未摻雜矽玻 璃層（USG )，且晶圓背面散熱用的内、外圈氦氣的流量分Page 4 40837η 5. Description of the invention (2) The flow distribution and size, in order to effectively increase the uniformity of the substrate temperature distribution and reduce the deposition temperature of the substrate, that is, to improve the temperature consistency of the high-density plasma deposition layer. The heat-dissipating gas package is nitrogen, helium, argon or other inert gas. As for the heat dissipation method on the back of the substrate, it can be divided into inner ring heat dissipation gas and an outer ring heat dissipation gas. By adjusting the pressure and relative ratio of the heat dissipation gas in the inner and outer rings, the wafer temperature can be effectively controlled. In order to make the advantages and features of the present invention more clearly visible, a preferred embodiment according to the present invention will be described in detail below in conjunction with related drawings. Brief description of the figure: Figure 1 shows the comparison of the line-line capacitance (L-L capacitance) of the high-density plasma fluorine-doped silica glass prepared according to the present invention and the conventional process in a 0.18 # m process. Embodiment: First, four wafers are provided, and the numbers are W1 to W4. Next, a high density plasma chemical vapor deposition layer was formed on the four wafers using a 0.18 // m process, and then the line-line capacitance values at different positions were measured. The formation steps of the high-density plasma chemical vapor deposition layer on the four wafers will be described below. W1: A high-density plasma chemical vapor deposition undoped silica glass layer (USG) with a thickness of about 18K is formed on the surface of the wafer No. W1 by a high-density plasma deposition method. The flow of helium in the outer ring
第5頁 40837η 五、發明說明（3) 別為4 torr以及8 torr，沉積完畢後，再以化學機械研磨 法進行平坦化處理。 W2 :利用高密度電漿沉積法於編號W1的晶圓表面形成 一厚度約1 8K埃之高密度電漿化學氣相沉積的氟摻雜石夕玻 璃層（FSG )，且晶圓背面散熱用的内、外圈氦氣的流量分 別為4 torr以及8 torr，沉積完畢後，再以化學機械研磨 法進行平坦化處理。 W 3 :利用高密度電漿沉積法於編號W1的晶圓表面形成 一厚度約17K埃之高密度電漿化學氣相沉積的氟摻雜石夕玻 璃層（FSG)，經化學機械研磨處理後，再以高密度電聚沉 積法形成一厚度1 0 00埃之高密度電漿化學氣相沉積的未摻 雜係玻璃層（USG)於平坦的氟摻雜矽玻璃層（FSG)上。利用 高密度電漿化學氣相沉積法形成氟摻雜矽玻璃以及未摻雜 石夕玻璃時’晶圓背面散熱用的内、外圈氦氣的流量分別為 4 torr 以及8 torr。 W 4 :此晶圓將利用習知的反應條件進行高密度電聚沉 積法。利用高密度電漿沉積法於編號W4的晶圓表$形成― 厚度約1 8 K埃之高密度電聚化學氣相沉積的氟摻雜矽玻璃 層（FSG) ’其中晶圓背面散熱用的内、外圈氦氣的流量分 別為2 · 5 t 〇 r r以及8 t 〇 r r ’ ί儿積元畢後，再以化學機械研 磨法進行平坦化處理。 接著，再分別檢測此四片晶圓之高密度電漿沉積層在 不同位置的線-線電容值，其結果如第1圖所示。 第1圖之橫座標是檢測到的電容值，而縱座標則是在Page 5 40837η V. Description of the invention (3) Different from 4 torr and 8 torr, after the deposition is completed, the chemical mechanical polishing method is used for planarization. W2: A high-density plasma chemical vapor deposition (FSG) glass layer (FSG) with a thickness of about 18K angstroms is formed on the surface of the wafer No. W1 by a high-density plasma deposition method. The flow rates of the helium gas in the inner and outer rings are 4 torr and 8 torr, respectively. After the deposition is completed, the chemical mechanical polishing method is used for planarization. W 3: A high-density plasma chemical vapor deposition fluorine-doped stone layer (FSG) with a thickness of about 17K is formed on the surface of the wafer No. W1 by a high-density plasma deposition method. After chemical mechanical polishing Then, a high-density plasma chemical vapor deposition undoped glass layer (USG) with a thickness of 1,000 angstroms is formed by a high-density electrodeposition method on a flat fluorine-doped silica glass layer (FSG). When the high-density plasma chemical vapor deposition method is used to form fluorine-doped silica glass and undoped stone glass, the flow of helium in the inner and outer rings for heat dissipation on the wafer backside is 4 torr and 8 torr, respectively. W 4: This wafer will be subjected to high-density electrolytic deposition using conventional reaction conditions. Formed by high-density plasma deposition method on wafer number W4 ― Fluorine-doped silica glass layer (FSG) with a high-density electropolymer chemical vapor deposition thickness of about 18 K Angstroms, where the backside of the wafer is for After the flow of helium in the inner and outer rings is 2.5 t 〇rr and 8 t 〇rr ', the planarization treatment is performed by chemical mechanical polishing. Next, the line-to-line capacitance values of the high-density plasma deposition layers of the four wafers at different positions were tested separately. The results are shown in Figure 1. The horizontal coordinate in Figure 1 is the detected capacitance value, while the vertical coordinate is in
第6頁 4〇83V〇 五、發明說明（4) 晶圓上的位置。如圖所示，於晶圓4 (符號△)不同位置所 測得之線-線電容值差異極大，而根據本發明之製程所製 備的晶圓1 (符號# )、晶圓2 (符號〇）以及晶圓3 (符號# )， 在不同位置上所測得之線-線電容值差異明顯比晶圓1來得 /J、 〇 因此，根據本發明所揭示之方法，於形成高密度電漿 化學氣相沉積層時，增加基底背面散熱氣體之流量以拉近 内、外散熱氣體的壓力，可有效降低該基底的溫度及改善 該高密度電漿沉積層的溫度一致性，進而改善高密度電漿 化學氣相沉積層之線-線電容值的一致性。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，所作之各種更動與潤飾，均落在本發明的專利 範圍内。此外，本發明之保護範圍當視後附之申請專利範 圍所界定者為準。Page 6 4〇83V〇 5. Description of the invention (4) Position on the wafer. As shown in the figure, the line-line capacitance values measured at different positions of wafer 4 (symbol △) are extremely different, and wafer 1 (symbol #) and wafer 2 (symbol 0) prepared according to the process of the present invention. ) And wafer 3 (symbol #), the difference in measured line-to-line capacitance values at different positions is significantly better than wafer 1 / J, 〇 Therefore, according to the method disclosed in the present invention, a high-density plasma is formed In the chemical vapor deposition layer, increasing the flow of heat radiation gas on the back surface of the substrate to reduce the pressure of the inner and outer heat radiation gas can effectively reduce the temperature of the substrate and improve the temperature consistency of the high-density plasma deposition layer, thereby improving the high density. Consistency of Line-to-Line Capacitance of Plasma Chemical Vapor Deposition. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Range of patents. In addition, the scope of protection of the present invention shall be determined by the scope of the appended patent application.
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