407356 五、發明說明（1) 本發明係提供一種用於半導體晶片之薄膜電阻以及其 製作方法。 用於半導體晶片上的薄膜電阻是用來提供穩定的電p且 值，但是當薄膜電阻的電阻層厚度不均勻時，在電阻層厚 度較小的區域會產生較大的電阻值，而在電阻層厚度較大 的區域則會產生較小的電阻值，使得電阻值不穩定，而I 響薄膜電阻的功能。 請參考圖一，圖一所示為習知用於半導體晶片10之薄 膜電阻2 0的剖面示意圖。習知設於一半導體晶片丨〇表面之 薄膜電阻20包含有一第一介電層12設於半導體晶片之表 面上’二導電層14設於第一介電層丨2之一預定區域上，一 第二介電層16設於二導電層14之上，其中並分別於二導電 層1 4上側設一孔洞，以及一電阻層丨8設於第二介電層丨6表 面之一預定區域内，並分別填滿二導電層1 4上側之二孔 洞。由於二導電層1 4之一端分別與電阻層1 8互相接觸’因 此當半導體晶片10與外界電連接時，二導電層14可以用來 作為電阻層1 8之電連接線。 在習知薄膜電阻20的製作過程中，由於二導電層14會 先被設=第一介電層12之一預定區域上，而使半導體晶片 10表面南度不一，因此當第二介電層16與電阻層18依序被 沈積於半導體晶片10表面上時，便會產生階梯覆蓋（step407356 V. Description of the invention (1) The present invention provides a thin film resistor for a semiconductor wafer and a manufacturing method thereof. Thin film resistors used on semiconductor wafers are used to provide stable electrical p and values, but when the thickness of the resistance layer of the thin film resistor is not uniform, a larger resistance value will be generated in a region with a smaller thickness of the resistance layer, and Regions with a larger layer thickness will produce a smaller resistance value, making the resistance value unstable, and I will function as a thin film resistor. Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional view of a conventional thin film resistor 20 for a semiconductor wafer 10. It is known that the thin film resistor 20 provided on the surface of a semiconductor wafer includes a first dielectric layer 12 provided on the surface of the semiconductor wafer. The two conductive layers 14 are provided on a predetermined area of the first dielectric layer. The second dielectric layer 16 is disposed on the two conductive layers 14, and a hole is respectively provided on the upper side of the two conductive layers 14, and a resistance layer 8 is disposed in a predetermined area on the surface of the second dielectric layer 6. And fill two holes on the upper side of the two conductive layers 14 respectively. Since one end of the two conductive layers 14 and the resistance layer 18 are in contact with each other ', when the semiconductor wafer 10 is electrically connected to the outside, the two conductive layers 14 can be used as electrical connection lines of the resistance layer 18. In the manufacturing process of the conventional thin film resistor 20, since the two conductive layers 14 are first set on a predetermined area of the first dielectric layer 12, and the surface of the semiconductor wafer 10 is different, the second dielectric When the layer 16 and the resistance layer 18 are sequentially deposited on the surface of the semiconductor wafer 10, a step coverage is generated.
_407356 五、發明說明（2) - coverage)的問題，使電阻層18的沈積厚度不均勻而影響 製程的品質。由於電阻層18的沈積厚度不均句，當二^電 層14與電阻層18互相電連接時，在電阻層18之厚度較小的 區域會產生較大的電阻值，而在電阻層18之厚度$大的區 域則會產生較小的電阻值，使電阻層〗8之電阻值 不均勻而不穩定。 '又 因此本發明之主要目的在於提供一種用於半導體晶片 之薄膜電阻以及其製作方法，可以避免薄膜電阻之電阻值 因其厚度不均勻而不穩定的情形。 圖示之簡單說明 圖一為習知設於半導體晶片之薄膜電阻的剖面示意圖。 圖二為本發明設於半導體晶片之薄膜電阻的剖面示意圖。 圖三至圖八為圖二所示用設於半導體晶片之薄膜電阻製 方法的示意圖》 圖示之符號說明 30 半導體晶片 32 介電層 34 電阻層 36 絕緣層 38 導電層 40 薄膜電阻 42 接觸洞 44 孔洞 請參考圖二’圖二為本發明設於半導體晶片30之薄嗅_407356 V. Description of the invention (2)-The problem of coverage) makes the deposition thickness of the resistive layer 18 uneven and affects the quality of the process. Due to the uneven deposition thickness of the resistance layer 18, when the electrical layer 14 and the resistance layer 18 are electrically connected to each other, a larger resistance value will be generated in a region with a smaller thickness of the resistance layer 18, and The area with a large thickness of $ will produce a smaller resistance value, making the resistance value of the resistance layer uneven and unstable. 'And therefore, the main object of the present invention is to provide a thin film resistor for a semiconductor wafer and a manufacturing method thereof, which can avoid a situation where the resistance value of the thin film resistor is unstable due to uneven thickness. Brief Description of the Drawings Figure 1 is a schematic cross-sectional view of a conventional thin film resistor provided on a semiconductor wafer. FIG. 2 is a schematic cross-sectional view of a thin film resistor provided on a semiconductor wafer according to the present invention. Figures 3 to 8 are schematic diagrams of the method for manufacturing a thin film resistor provided on a semiconductor wafer shown in FIG. 2 "Symbols for illustration 30 Semiconductor wafer 32 Dielectric layer 34 Resistive layer 36 Insulating layer 38 Conductive layer 40 Thin film resistor 42 Contact hole 44 holes, please refer to FIG. 2 'FIG.
月說明（f~^^^6 > 電阻40的剖面示意圖。本發明設於一半導體晶片3〇上的薄 膜電阻40包含有—以硼磷矽玻璃（BPSG)所構成的介電層 32 ’設於半導體晶片30表面，一以鉻化矽（SiCr)所構成的 電阻層34 ’設於介電層32表面之一預定區域内，一以二氧 化石夕所構成的絕緣層36，設於電阻層34之上，其中並於電 随層3 4上側之兩端各設有一孔洞，以及以鋁為主要成分之 金屬合金所構成的二導電層38，分別設於電阻層34上側之 二孔洞内並凸出於絕緣層3 6之表面。二導電層3 8分別與電 阻層34之兩端相互電連接’可以用來做為電阻層34之電連 接線。 請參考圖三至圖八，圖三至圖八為圖二所示設於半導 體晶片3 0之薄膜電阻4 0的製作方法的示意圖。如圖三所 示，本發明薄膜電阻40是製作於半導體晶片3〇表面之介電 層3 2上進行。在製作薄膜電阻4〇時，先於介電層32表面形 成電阻層34，再以化學氣相沈積法（chemical vap〇r deposition)於電阻層34表面形成絕緣層36，如圖四所 不。接著進行一非等向性乾蝕刻製程，以去除介電層32之 預疋區域外之電阻層34及絕緣層36，如圖五所示。 隨後再進行一第一蝕刻製程，用來去除位於電阻層34 上側兩端之絕緣層3 6部分以形成二孔洞4 4，如圖六所示。 第一蝕刻製程是以緩衝式氧化層蝕刻液（buffered 〇xide etcher，簡稱B0E)作為蝕刻溶液的濕蝕刻製程。接下來於(F ~ ^^^ 6 > A schematic cross-sectional view of a resistor 40. The thin film resistor 40 provided on a semiconductor wafer 30 of the present invention includes a dielectric layer 32 'made of borophosphosilicate glass (BPSG) Provided on the surface of the semiconductor wafer 30, a resistive layer 34 'composed of silicon chrome (SiCr) is provided in a predetermined area of the surface of the dielectric layer 32, and an insulating layer 36 composed of silica is provided on Above the resistance layer 34, a hole is provided at each of the two ends on the upper side of the electrical layer 34, and two conductive layers 38 made of a metal alloy containing aluminum as a main component are respectively provided in the two holes on the upper side of the resistance layer 34 And protrudes from the surface of the insulating layer 36. The two conductive layers 38 and the two ends of the resistance layer 34 are electrically connected to each other, and can be used as electrical connection lines of the resistance layer 34. Please refer to FIG. 3 to FIG. 3 to 8 are schematic diagrams of a method for manufacturing the thin film resistor 40 provided on the semiconductor wafer 30 shown in FIG. 2. As shown in FIG. 3, the thin film resistor 40 of the present invention is a dielectric layer manufactured on the surface of the semiconductor wafer 30. 3 to 2. In the production of the thin film resistor 40, before the surface of the dielectric layer 32 A resistive layer 34 is formed, and then an insulating layer 36 is formed on the surface of the resistive layer 34 by a chemical vapor deposition method, as shown in Figure 4. Then, an anisotropic dry etching process is performed to remove the dielectric. The resistive layer 34 and the insulating layer 36 outside the pre-etched area of the layer 32 are shown in Fig. 5. Subsequently, a first etching process is performed to remove portions of the insulating layer 36 located on both ends of the resistive layer 34 to form two layers. The holes 44 are shown in Figure 6. The first etching process is a wet etching process using buffered oxide etcher (B0E) as an etching solution. Next,
半導體晶片30表面上形成一導電層38，將電阻層34上侧兩 端之二孔洞4 4填滿’如圖七所示。最後進行一第二蝕刻製 程’用來去除電阻層34外圍之導電層38部份以及絕緣層36 表面上之部份導電層38，以於二孔洞44之上形成二不相連 之導電層38，使二導電層38可以分別經由二孔洞44與電阻 層34之兩端相互電連接，如圖八所示，便完成薄膜電阻4〇 的製作。 本發明在形成導電層38之前，可以利用乾蝕刻方法進 行一接觸洞蝕刻製程’用來在介電層32之預定區域外形成 至少一接觸洞（<:〇1^3〇1:11〇16)42(圖六）。而形成導電層 38時，同時將電阻層34上側兩端之二孔洞44與介電層32之 接觸洞42填滿（圖七）。並且進行第二蝕刻製程時，也去 除介電層32表面上之部份導電層38，以於每個接觸洞42上 形成互不相連之導電層39 (圖八），使每個導電層39可以 分別經由每個接觸洞42與半導體晶片30上的元件相互電連 接。由於位於介電層32上的接觸洞42是利用乾蝕刻所製 成，而位於絕緣層36的孔洞44是利用濕蝕刻所製成，可以 避免利用乾蝕刻同時製作接觸洞42與孔洞44而對電阻層34 造成電漿損害（plasma damage)。而且接觸洞42與孔洞44 分別製作，可以分別對不同的蝕刻區域設定適當的製程參 數’來控制蝕刻時間以準確地蝕刻至預定的深度。 本發明之薄膜電阻40中，由於電阻層34是設於平坦的A conductive layer 38 is formed on the surface of the semiconductor wafer 30, and two holes 44 at both ends of the upper side of the resistance layer 34 are filled 'as shown in FIG. Finally, a second etching process is performed to remove a portion of the conductive layer 38 on the periphery of the resistance layer 34 and a portion of the conductive layer 38 on the surface of the insulating layer 36 to form two disconnected conductive layers 38 on the two holes 44. The two conductive layers 38 can be electrically connected to two ends of the resistive layer 34 through the two holes 44 respectively, and as shown in FIG. 8, the production of the thin film resistor 40 is completed. Before the conductive layer 38 is formed in the present invention, a contact hole etching process can be performed by using a dry etching method to form at least one contact hole (<: 〇1 ^ 3〇1: 11〇) outside a predetermined area of the dielectric layer 32. 16) 42 (Figure 6). When the conductive layer 38 is formed, at the same time, the two holes 44 at both ends of the upper side of the resistance layer 34 and the contact holes 42 of the dielectric layer 32 are filled (Fig. 7). And during the second etching process, a part of the conductive layer 38 on the surface of the dielectric layer 32 is also removed, so as to form a non-connected conductive layer 39 on each contact hole 42 (FIG. 8), so that each conductive layer 39 The components on the semiconductor wafer 30 may be electrically connected to each other via each of the contact holes 42. Since the contact hole 42 on the dielectric layer 32 is made by dry etching, and the hole 44 on the insulating layer 36 is made by wet etching, it is possible to avoid making contact holes 42 and holes 44 at the same time by dry etching. The resistive layer 34 causes plasma damage. Moreover, the contact holes 42 and the holes 44 are made separately, and appropriate process parameters' can be set for different etching regions to control the etching time to accurately etch to a predetermined depth. In the thin film resistor 40 of the present invention, since the resistance layer 34 is provided on a flat surface,
第7頁 介電層32表面上，因此 、 於電阻層34上側的二薄二_厚度均勻的電阻層34。設 兩端相互電連接時，ώ 曰、里由—孔洞4 4與電阻層3 4之 電一發生電4:穩電厚度均勻’因此薄膜 薄膜ίΠ用於半“晶片3。之 庚泊h ΛΑ # /、製作方法，疋於介電層32表面上形成厚 ::勻的電阻層34 ’而且將二導電層38分別設於電阻層34 貝:之絕緣層36的二孔洞44内，使二導電層38分別與電阻 曰之兩端相互電連接以形成薄膜電阻4〇，因此薄膜電阻 的厚度均勻之電阻層34，可以避免發生電阻值不穩定 以上所述僅為本發明之較佳實施例，凡依本發明申請 #和範圍所做之均等變化與修飾’皆應屬本發明專之 盍範圍。Page 7 On the surface of the dielectric layer 32, two thin, two-thick resistive layers 34 on the upper side of the resistive layer 34 are uniform. It is assumed that when the two ends are electrically connected to each other, the electric power of the hole 4 4 and the resistance layer 3 4 is generated. 4: The thickness of the stable electricity is uniform. Therefore, the thin film thin film is used for a semi- "wafer 3. Heppodium ΛΑ # / 、 Production method, forming a thick :: uniform resistive layer 34 ′ on the surface of the dielectric layer 32, and placing two conductive layers 38 in the resistive layer 34, respectively, in the two holes 44 of the insulating layer 36, so that The conductive layer 38 and the two ends of the resistor are electrically connected to each other to form a thin-film resistor 40. Therefore, the resistance layer 34 having a uniform thickness of the thin-film resistor can avoid the instability of the resistance value. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications according to the application # and scope of the present invention should fall within the scope of the present invention.