__4JMu 五、發明説明（） 5-1發明磔域： 本發明係有闞於一種半導體元件隔離區之製程，特别 是一種以多晶矽緩衝之區域氧化隔離製程。 5-2發明背景： 爲了獲致所需求的積體電路晶片功能，必須在單一半 導體晶圓上建立如電阻、電容、電晶體等許多不同種類與 功能的王動π件。在晶片上的每個元件都必需在電性上加 以隔離，以確保它們操作之獨立性，而不會影響其它元 件。於是，分隔不同元件或不同功能區域之半導體元件痛 離方法就成爲現代金屬氧化物半導體（1^〇3)與雙載子積 Μ電路製程中的一個重要技術》對於高積集度之半導雄積 禮電路來説，元件間不適當之隔離會產生漏電流，且漏電 流會消耗大量的功率。不適當之隔離也會加重閉鎖現象， 並會造成暫時性甚至永久性的電路損壞。另外，不適當之 隔離會產生雜訊容限（noisemargin)退化，電壓遷移以及 串擾訊號（crosstalk}。 經濟部中央標準局貝工消費合作杜印製 (請先閲讀背面之注意事項再填寫本頁) 區域氧化隔離法（L0C0S)乃最爲人所熟知的隔離技 術。L0C0S藉由氧化矽基板的方式在主動式元件或功能 區域之間產生二氧化矽而提供了隔離》由於矽基板很容易 氧化成二氧化矽，L0C0S具有方法簡單及成本低廉之優 點，而在超大型積體電路（VLSI)中成爲廣泛使用之隔離技 本紙張尺度適用中國國家揉率（CNS ) A4规格（210X297公着） 經濟部中央標準局負工消費合作杜印製 <έ052ΐ1五、發明説明（ 術。然而，由於半導體積體電路之製造趨向高封裝密度， LOCOS逯遇到尺寸難以随之調降的瓶薄。 1 994年A. Bryant等人在IEDM技術刊物的671頁 上發表其論文"Characteristics 〇f CMOS Device Isolation f0r the ULSI Age"，其中回顧了區域氧化隔離 法與渠溝隔離法兩種不同的隔離技術的特點。在隔離深 度、隔離平坦性以及主動區域與隔離區域間的轉換各方 面，作者討論了 LOCOS與STI如何加以改進以符合其調 降尺寸之需求。對於深次微米CMOS之製程來説，傳統 的LOCOS隔離遭遇到許多困難’例如烏喙效應的側向延 伸過大，平坦性不足，區域場氡化層稀薄效應，及應力產 生之基板缺陷等》其中，在尺寸缩小時絶緣髏變薄，烏喙 結構’以及場植入侵害等爲LOCOS在調降尺寸上的主 要的挑戰》對於未來的CMOS技術而言，最有效的元件 隔離方法不但要能提供主動區域與隔離區域間的轉換，對 元件特性或形態所產生的衝擊也必須最小。 在以氮化矽爲軍幕進行氧化製程時，於矽基板上的氧 化效應將會向側邊延伸’所生成氧化層之邊緣形狀類似烏 嘴’稱爲烏喙效應》由於烏喙效應的發生，主動區域將因 而變窄，這是LOCOS技術最主要的癥結所在。要抑制烏 喙效應’減少氧化現象的側向擴散，則必須將緩衝軍幕應 力作用之垫氧化層的厚度減至最低。而爲了在顧及減輕氣 化矽革幕層之應力作用的情形下，又能減少垫氧化層的厚 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公羞 (請先閲讀背面之注意事項再填寫本頁) -裝· 訂一7 .I涑 經濟部中央梂準局貞工消费合作社印製 ^05211_B7____五、發明説明（） 度，於是在薄墊氧化層上增加一多晶矽層作爲緩衝，以取 得最佳的效果，囡此發展出多晶矽緩衝之區域氧化隔離法 {polysilicon-buffered LOCOS, PBLOCOS}以改進傳统的 區域氧化隔離法，降低烏喙效應。如同T.Nishihara等人 在其論文"A 0.5 a m Isolation Technology Using Advanced Poly Silicon Pad LOCOS (APPL) w {IEDM Tech. Dig., p.100, 1988}中所述，PBLOCOS 以多晶發 層取代垫氧化層的缓衝功用，鳥喙效應將因垫氧化層的厚 度減少而受到抑制》 然而根據 J· Nage丨等人在論文"Stress -Induced Void Formation in Interlevel Polysilicon Film during Poly buff ered Local Oxidation of Siliconw (J. Electrochem. Soc., vol. 140, p.2356, 1993}提及，雖 然 PBL0C0S可以減輕烏喙效應，但卻會產生針孔結構 {pitting formation)。由於以熱鱗酸對氛化梦軍幕層進行 濕蝕刻時，蝕刻劑也會侵蝕場氧化層附近的多晶矽層，终 導致基板損傷。而在濕氧化過程中，水、氨氣與矽會產生 化學反應，稱爲帶狀白化效應（White Ribbon Effect}。 由於此一效應的作用，在氮化矽軍幕去除後，在多晶矽層 上會出現針孔結構，而在多晶矽層去除後，則基板上也會 出現針孔結構。帶狀白化效應的化學反應機制在T.T. Sheng 等人的論文"From White Ribbon to Black Belt: A Direct Observation of the Kooi Effect Masking Film by Transmission Electron Microscopy ”（J. (請先閲讀背面之注意事項再填寫本頁) •裝· 訂 本纸張尺度適用中B國家揉率（CNS ) A4规格（210X297公釐） 經濟部中央標準局貝工消费合作社印製 A7 --4052η______ 五、發明说明（） EI e c t r 〇 c h e m. S 〇 c.，v ο 1. 1 4 Ο, p L 1 6 3, 1 9 9 3}中有詳細 的介紹》此帶狀白化效應的機制將會造成基板損傷，使反 率降低，影響深次微米製程甚鉅。 5-3發明目的及抵述： 爲了改善上述帶狀白化效應所產生的針孔結構，本發 明提出了一個改進的多晶矽缓衝之區域氡化法以製造場 氧化隔離區域。採用多晶矽層以減輊烏味效應，並於多 晶矽層上形成氧化層以防止針孔結構發生。 首先形成一垫氧化層與一矽層，接著在〇2、Ν2〇或 NO環境中實施熱氡化法形成另一墊氡化層，並將發層轉 化成多晶石夕層’以完成氧化層、多晶石夕層以及氧化層之 緩衝堆*。形成氮化矽層於缓衝堆疊層之上，然後以標 準微影製程及非等向性蝕刻法將氮化矽層圈案化，以定 義主動區域。接著以氮化梦層爲軍幕蝕刻此緩衝堆要 層，然後實施熱氧化法以形成場氡化隔離區《去除氣化 矽層與緩衝堆4層後’在半導體基板上以標準的方法製 造MOS元件，本發明於焉完成。 5-4圈式簡單説明： 本發明之前述的情況及其許多伴隨的優點將由下面 詳細的叙述並結合附圈而更爲容易瞭解，其中： -----：----^裝 I.-----訂 __^--„---ΐ i (請先聞讀背面之注意事項再填寫本頁v->__4JMu 5. Description of the Invention (5) 5-1 Invention Field: The present invention relates to a process of isolating a semiconductor device, especially a process of isolating and isolating a region buffered by polycrystalline silicon. 5-2 Background of the Invention: In order to achieve the required integrated circuit chip functions, many different types and functions of king π components such as resistors, capacitors, transistors, etc. must be established on a single half-conductor wafer. Each component on the wafer must be electrically isolated to ensure that they operate independently without affecting other components. Therefore, the method of separating semiconductor devices from different components or different functional areas has become an important technology in the process of modern metal oxide semiconductor (1 ^ 03) and bipolar product M circuits. For the male-greater circuit, improper isolation between components will cause leakage current, and the leakage current will consume a lot of power. Improper isolation can also exacerbate latch-up and cause temporary or even permanent circuit damage. In addition, improper isolation will result in noise margin degradation, voltage migration, and crosstalk. Printed by the Consumer Product Cooperation Department of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) ) Area Oxidation Isolation (L0C0S) is the most well-known isolation technology. L0C0S provides isolation by generating silicon dioxide between active components or functional areas by means of a silicon oxide substrate.Since the silicon substrate is easily oxidized As a silicon dioxide, L0C0S has the advantages of simple method and low cost, and has become a widely used isolation technology in very large scale integrated circuit (VLSI). The paper size is applicable to the Chinese National Kneading Rate (CNS) A4 specification (210X297) Du printed by the Central Bureau of Standards of the Ministry of Economic Affairs and printed by the consumer. <0522> V. Invention Description (However, as semiconductor integrated circuit manufacturing tends to high packaging density, LOCOS 逯 encounters thinner bottles that are difficult to reduce in size.) 1 994 A. Bryant et al. Published his paper on 671 pages of IEDM technical journal " Characteristics 〇f CMOS Device Isolation f0r the ULSI Ag e ", which reviewed the characteristics of two different isolation technologies, the area oxidation isolation method and the trench isolation method. In terms of isolation depth, isolation flatness, and conversion between the active area and the isolation area, the author discussed how LOCOS and STI It has been improved to meet the requirements of downsizing. For deep sub-micron CMOS processes, traditional LOCOS isolation has encountered many difficulties. For example, the lateral extension of the black beak effect is too large, the flatness is insufficient, and the thinned field field layer is thin. "Effects, substrate defects caused by stress, etc." Among them, the reduction of the size of the insulating cross section when the size is reduced, the black beak structure, and the field plant invasion are the main challenges for LOCOS to reduce the size. For future CMOS technology, The most effective method of component isolation must not only provide the conversion between the active area and the isolation area, but also have the least impact on the characteristics or morphology of the component. During the oxidation process with silicon nitride as the military curtain, on the silicon substrate The oxidation effect will extend to the side. The edge of the generated oxide layer is similar to a black mouth. It is called the black beak effect. The active region will be narrowed as a result of this, which is the main sticking point of the LOCOS technology. To suppress the black beak effect and reduce the lateral diffusion of the oxidation phenomenon, the thickness of the oxide layer of the cushion that buffers the stress of the curtain must be reduced. To the minimum. In order to reduce the thickness of the oxidized silicon leather curtain layer, and reduce the thickness of the pad oxide layer, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297) (please read the back first) Please note this page, please fill in this page)-Binding · Order 7. Printed by Zhenong Consumer Cooperative, Central Government Bureau of Standards, Ministry of Economic Affairs ^ 05211_B7____ 5. Description of the invention (), so a polycrystalline silicon is added on the thin oxide layer The layer acts as a buffer to achieve the best results. Therefore, polysilicon-buffered LOCOS (PBLOCOS) has been developed to improve the traditional regional oxidation isolation method and reduce the black beak effect. As described by T. Nishihara et al. In their paper " A 0.5 am Isolation Technology Using Advanced Poly Silicon Pad LOCOS (APPL) w {IEDM Tech. Dig., P. 100, 1988}, PBLOCOS is replaced with a polycrystalline layer The cushion function of the pad oxide layer, the bird's beak effect will be suppressed due to the reduction of the thickness of the pad oxide layer. However, according to J. Nage 丨 et al. In the paper " Stress -Induced Void Formation in Interlevel Polysilicon Film during Poly buff ered Local Oxidation of Siliconw (J. Electrochem. Soc., vol. 140, p. 2356, 1993) mentioned that although PBL0C0S can reduce the black beak effect, it will produce a {pitting formation). When the wet dream etch is performed on the curtain layer of the atmospheric dream army, the etchant will also erode the polycrystalline silicon layer near the field oxide layer, eventually causing damage to the substrate. During the wet oxidation process, water, ammonia gas and silicon will have a chemical reaction, which is called the white ribbon effect. Because of this effect, after the silicon nitride military curtain is removed, it is on the polycrystalline silicon layer. The pinhole structure will appear, and after the polycrystalline silicon layer is removed, the pinhole structure will also appear on the substrate. The chemical reaction mechanism of the band whitening effect is described in the paper by TT Sheng et al. "From White Ribbon to Black Belt: A Direct Observation" of the Kooi Effect Masking Film by Transmission Electron Microscopy ”(J. (Please read the precautions on the back before filling out this page) • Binding and binding paper size applicable for country B kneading rate (CNS) A4 size (210X297 mm ) Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 --4052η ______ 5. Description of the invention () EI ectr 〇che m. S 〇c., V ο 1. 1 4 〇, p L 1 6 3, 1 9 9 There is a detailed introduction in 3} "The mechanism of the band whitening effect will cause damage to the substrate, reduce the reflectance, and affect the deep sub-micron process. 5-3 Purpose of the invention and refutation: In order to improve the above band whitening effect In the resulting pinhole structure, the present invention proposes an improved polycrystalline silicon buffered region sulfonation method to manufacture field oxidation isolation regions. A polycrystalline silicon layer is used to reduce the effect of odor, and an oxide layer is formed on the polycrystalline silicon layer to prevent needles. The pore structure occurs. First, a pad oxide layer and a silicon layer are formed, and then a thermal padding method is performed in a 02, N2O, or NO environment to form another padding layer, and the hair layer is converted into a polycrystalline layer. 'To complete the buffer layer of the oxide layer, polycrystalline silicon layer and oxide layer *. A silicon nitride layer is formed on the buffer stack layer, and then the silicon nitride layer is formed by a standard lithography process and anisotropic etching method. Circled to define the active area. Then the main layer of this buffer stack was etched with the nitrided dream layer as a military curtain, and then a thermal oxidation method was performed to form a field-isolated isolation zone "After removing the gasified silicon layer and the buffer stack 4 layers' The MOS device is manufactured by a standard method on a semiconductor substrate, and the present invention is completed in 焉. 5-4 Loop Brief Description: The foregoing situation of the present invention and its many accompanying advantages will be further detailed by the following detailed description in conjunction with the attached circle Easy to understand , Of which: -----: ---- ^ 装 I .----- Order __ ^-„--- ΐ i (Please read the notes on the back before filling in this page v- >
__ 4052 五、發明説明（） 第一圈爲依照本發明在基板上形成垫氧化層之半導 體晶圓之截面圈； 第二圈爲依照本發明在墊氧化層上形成非晶矽層之 半導體晶圓之截面圖； 第二圈爲依照本發明在非晶矽層上形成第二墊氧化 層之半導«晶圓之截面圈； 第四圖爲依照本發明在第二墊氧化層上形成氮化矽 層並定義主動區域之半導體晶圓之截面圈； 第五圈爲依照本發明在基板上實行熱氧化以形成場 氧化區之半導體晶圓之截面圈；及 第六圃爲依照本發明在基板上製造MOSFET之半導 體晶圓之截面圈。 5-5發明詳細説明： 本發明提出了一個改進的多晶矽缓衝之區域氧化法 以製造場氧化隔離區域。其中應用到許多在傳统技藝中 已廣爲熟知的技術如微影、蝕刻、以及化學氣相沈積法 (Chemical Vapor Deposition, CVD}等，在此將不詳述其 内容。此外，本發明採用氧化層、多晶矽層以及氧化層 組成之堆疊層作爲氧化緩衝層，其中多晶矽層可減輕鳥 喙效應，而形成於多晶矽層上之氧化層可防止針孔結構 發生。 參閲第一圖，基板2爲晶格方位< 1 00 >之單晶矽。 本紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐） β0 ^ Γ-裝一Γ -----訂一Γ--.--- I 線 4 丨 {請先閲讀背面之注f項再壤寫本頁} 經濟部中央標準局貝工消费合作社印裝 __e； 五、發明説明（） -薄氧化妙層4形成於基板2的表面上作爲整氧化層 此墊氧化層4具有大约5 0-2〇〇埃之厚度，且可以 度大約800-1 1 00¾的乾式或濕式氧氣環境下利用熱 氧化法形成於半導體基板2上β此外，此氧化矽層4亦 可在溫度大約400-750¾時利用低壓化學氣相沉積法 (LPCVD)加以沉積。 接著如第二圈中所顯示，一未摻雜之非晶矽層6沉 積在墊氧化層4之上。此非晶矽層6之厚度大約爲 300-1 000埃’可以在攝氏大约4〇〇至575.c之溫度時 以低恩化學氣相沉積法或是電漿增強式化學氣相沉積法 (plasma enhanced CVD, PECVD}形成。 經濟部中央橾準局貝工消費合作社印製 接著參考第三圖’在〇2、N20或是NO的環境中實 施一高溫氧化法，形成另一墊氧化層8於矽層6之上。 當所選擇的氧化環境爲〇2時，此第二垫氧化層8將由氧 化石夕所構成；若所選擇的氧化環境爲N2〇或是NO，則 此第二墊氧化層8將由氮氧化矽所構成。此外，於此步 裸中，其餘未被氧化的非晶矽薄膜6也將形成結晶而轉 化成多晶矽層。在傳统的多晶矽緩衝之區域氧化法中， 此多晶矽層6可取代墊氧化層的緩衝作用，以減少應力 作用及鳥喙效應。而在本發明中，則採用墊氧化層4、多 晶矽層6以及第二垫氡化層8形成堆疊以作爲缓衝層。 此熱氧化所使用之溫度大約爲攝氏800-1100 ·〇!。 本紙張ΛΑ適用中國國家揉準（CNS ) μ胁（210x297公羡） 經濟部t央樣準局貝工消費合作社印製 __4〇52li ^ 五、發明説明（） 於緩衝堆疊層4、6、8形成後，採用低壓化學氣相 沉積法沈積一氮化矽層10於第二垫氧化層8之上，作 爲場氧化層生成時的氧化軍幕，如同第四«中所颟示。 此步驟適當的沈積溫度約爲攝氏600至800TC，形成的 氮化矽層10厚度大約爲1 000-4000埃。此外，氮化石夕 層10也可以採用電漿增強式化學氣相沉積法，於構氏 溫度约300至5001C之下形成。在墊氧化層4、多晶石夕 層6以及第二墊氧化層8的堆疊缓衝作用下，比之於一 般以單一墊氧化層緩衝的情形，氮化矽層10可以具有 的更大的厚度。 採用光阻塗佈，曝光，及顯影等傳統微影方法形成光 阻於氮化矽層10之上，以定義主動區域之圖案，並暴露 出非主動區域的部份。接著以此光阻爲革幕，採乾式蝕刻 方法蝕刻氮化矽層1 0。此非等向蝕刻製程可以採用反應 性離子蝕刻法（RIE)來進行，其適當之蝕刻電漿源爲含氟 之電衆氣雜如CF4/02、CF2/H2、CHF3或是NF3e然後， 同樣採用非等向蝕刻製程，以相同的革幕圖樣，蝕刻包含 整氧化層4、多晶矽層6以及第二垫氧化層8的缓衝堆 4層。OF*、CHF3、Cd6或是C3F8等可作爲蝕刻氧化矽 層的独刻電漿源’而Cl2、BCI3、HBr、SF6或是SiCI4則 可作爲蝕刻多晶矽層的蝕刻電漿源β 在去除光阻並實施濕式清潔法之後，以氮化矽層1 〇 爲軍幕，對矽基板2進行高溫氧化製程，場氧化隔離區 本纸張適財國國家榡率YCNS )从胁（〉------ -----„---,I--裝 J-----訂—--,----線 1 (請先聞讀背面之注意事項再填寫本頁〕 經濟部中央樣準局員工消费合作社印掣 五、發明説明（） 12於焉形成於基板2上未被氧化革幕遮蓋的區域❶此熱 氧化温度大约爲攝氏800-11 00·<〇,因爲在氮化矽軍幕層 1〇與多晶矽層6之間的第二墊氧化層8的隔離作用，由 水、氨氣輿矽進行化學反應所產生的帶狀白化效應將被降 至最低’對基板2所產生的針孔結構損傷也囡而大爲減 少。此一步樣之結果可參考第五圈。 接著’以熱磷酸溶液爲濕蝕刻劑，去除氮化矽軍幕層 1〇。於此濕蝕刻過程中，第二墊氧化層8可以阻擋蝕刻 劑向下侵襲多晶矽層6,以避免最终造成基板的損傷。接 著，墊氧化層4、多晶矽層6以及第二垫氧化層8被依 次去除。其中，可利用緩衝氣化蚀刻溶液（b u f f e r e d oxide-etching solution, BOE solution}或是氫氟酸⑴F} 稀釋溶液作爲蝕刻劑，以濕蝕刻法去除垫氧化層4以及 第二垫氧化層8。而多晶矽層6則可以採用硝酸（ΗΝ03) 與氮氣酸（HF)的混合溶液作爲濕姓刻劑加以去除。此外， 含有氫氧化鉀（K0H)的濕蝕刻劑也可以用來清除多晶矽 層。 最後，參考第六圈，閘極氧化層在半導體基板2上 再度生長。然後，在主動區域上形成由閘極，源極與汲 極所組成之主動元件以完成CMOS電晶體之製造》 根據上述之方法，場氧化隔離區12形成於半導髏基 板2之上，以提供主動元件之間的隔雜區域。由於多晶 -----.--^--.^:1-1 (請先閲讀背面之注意事項再填寫本頁) 訂 線 本紙張尺度通用中國國家標牟（CNS > Α4规格（2丨〇Χ297公釐） h , Ά w ^ Α7 Β7 i、發明説明（ 矽廣6的採用，可以減輊鳥喙效應；而形成於多晶矽層 上之第二墊氧化層8,則可以防止由帶狀白化效應在基板 2上所產生的針孔結構，以及以熱磷酸溶液蝕刻氣化珍革 w時產生的基板損m了這些來自傳统場氧化隔 離技術之問題後，半導體製造之整合積集度可以有效的 增加，且本發明之方法可應用在深次微米元件製程，而 達成較高的製程良率。 以上所述僅爲本發明之較佳實施例而已，並非用以限 定本發明之申請專利範团；凡其它未脱離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範囲内。 -----L--.——γ裝-----訂—--^--·Γ線丨 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印製 本纸張尺度適用中國困家揉準（CNS ) Α4规格（210Χ297公釐）__ 4052 V. Description of the invention (1) The first circle is a cross-sectional circle of a semiconductor wafer that forms a pad oxide layer on a substrate according to the present invention; the second circle is a semiconductor crystal that forms an amorphous silicon layer on the pad oxide layer according to the present invention A cross section of a circle; The second circle is a cross-section circle of a semiconductor «wafer which forms a second pad oxide layer on an amorphous silicon layer according to the present invention; The fourth diagram is a nitrogen pad formed on the second pad oxide layer according to the present invention The fifth circle is a cross-sectional circle of a semiconductor wafer that is thermally oxidized on a substrate to form a field oxide region according to the present invention; and the sixth circle is a cross-sectional circle according to the present invention. A cross-section circle of a semiconductor wafer on which a MOSFET is manufactured on a substrate. 5-5 Detailed Description of the Invention: The present invention proposes an improved polycrystalline silicon buffered region oxidation method to fabricate field oxidation isolation regions. Among them, many techniques that are widely known in traditional techniques such as lithography, etching, and chemical vapor deposition (CVD) are not described in detail here. In addition, the present invention uses oxidation The polycrystalline silicon layer and an oxide layer are used as an oxidation buffer layer. The polycrystalline silicon layer can reduce the bird's beak effect, and the oxide layer formed on the polycrystalline silicon layer can prevent the pinhole structure from occurring. See the first figure, substrate 2 is Monocrystalline silicon with lattice orientation < 1 00 > The paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) β0 ^ Γ-packed Γ ----- order one Γ--. --- I line 4 丨 {Please read the note f on the back first and then write this page} Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs __e; 5. Description of the invention ()-Thin oxide layer 4 is formed on The surface of the substrate 2 serves as a whole oxide layer. The pad oxide layer 4 has a thickness of about 50 to 200 angstroms, and can be formed on a semiconductor by thermal oxidation in a dry or wet oxygen environment at a degree of about 800 to 1 00 ¾. On the substrate 2 In addition, the silicon oxide layer 4 can also be It is deposited by low pressure chemical vapor deposition (LPCVD) at about 400-750 ° C. Then, as shown in the second circle, an undoped amorphous silicon layer 6 is deposited on the pad oxide layer 4. This amorphous silicon The thickness of layer 6 is about 300-1 000 angstroms. It can be formed by low-En chemical vapor deposition or plasma enhanced CVD at a temperature of about 400 to 575.c. PECVD} is formed. Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards, the Ministry of Economic Affairs, and then referring to the third figure, a high-temperature oxidation method is performed in an environment of 0, N20, or NO to form another pad oxide layer 8 on the silicon layer 6 When the selected oxidation environment is 0 2, the second pad oxide layer 8 will be composed of oxidized stone; if the selected oxidation environment is N 2 0 or NO, the second pad oxide layer 8 will be formed by It is composed of silicon oxynitride. In addition, in this step, the remaining non-oxidized amorphous silicon film 6 will also form crystals and be converted into a polycrystalline silicon layer. In the conventional polycrystalline silicon buffered area oxidation method, this polycrystalline silicon layer 6 can Replace the cushioning effect of the pad oxide layer to reduce the stress effect and The beak effect. In the present invention, a pad oxide layer 4, a polycrystalline silicon layer 6, and a second pad siliconized layer 8 are used to form a stack as a buffer layer. The temperature used for this thermal oxidation is approximately 800-1100 ° C. This paper ΛΑ is suitable for China National Standards (CNS) μ threats (210x297 public envy) Printed by the Central Bureau of the Ministry of Economic Affairs of the Central Bureau of Spectacles Consumer Cooperative __4〇52li ^ V. Description of the invention () In the buffer stacking layer 4, After the formation of 6, 8, a low-pressure chemical vapor deposition method is used to deposit a silicon nitride layer 10 on the second pad oxide layer 8 as an oxidizing military curtain when the field oxide layer is generated, as shown in the fourth «. A suitable deposition temperature in this step is about 600 to 800 ° C, and the thickness of the silicon nitride layer 10 formed is about 1 000-4000 Angstroms. In addition, the nitrided layer 10 can also be formed by plasma enhanced chemical vapor deposition at a temperature of about 300 to 5001C. Under the cushioning effect of the pad oxide layer 4, the polycrystalline silicon layer 6, and the second pad oxide layer 8, the silicon nitride layer 10 may have a larger thickness. A photoresist is formed on the silicon nitride layer 10 by using conventional photolithography methods such as photoresist coating, exposure, and development to define the pattern of the active area and expose portions of the non-active area. Then, using the photoresist as a leather curtain, a dry etching method is used to etch the silicon nitride layer 10. This anisotropic etching process can be performed by reactive ion etching (RIE). The appropriate etching plasma source is a fluorine-containing gas such as CF4 / 02, CF2 / H2, CHF3 or NF3e. Then, the same A non-isotropic etching process is used to etch the buffer stack 4 layer including the entire oxide layer 4, the polycrystalline silicon layer 6, and the second pad oxide layer 8 with the same leather screen pattern. OF *, CHF3, Cd6, or C3F8 can be used as a plasma source for etching silicon oxide layers, while Cl2, BCI3, HBr, SF6, or SiCI4 can be used as an etching plasma source for etching polycrystalline silicon layers. After the wet cleaning method is implemented, the silicon substrate 2 is used as a military curtain, and the silicon substrate 2 is subjected to a high-temperature oxidation process. The field oxidation isolation zone is suitable for the country and the country ’s rate YCNS.) (> ----- ------ „---, I--install J ----- order ---, ---- line 1 (please read the precautions on the back before filling this page) Probationary Staff Consumer Cooperatives Co., Ltd. V. Description of the Invention (12) Yu is formed on the substrate 2 and is not covered by the oxidized leather curtain. The thermal oxidation temperature is about 800-11 00 ° C. The isolation effect of the second pad oxide layer 8 between the silicon army curtain layer 10 and the polycrystalline silicon layer 6 and the band-like whitening effect produced by the chemical reaction of water and ammonia gas with silicon will be minimized. The damage to the pinhole structure is also greatly reduced. The results of this step can be referred to the fifth circle. Then 'the hot phosphoric acid solution is used as a wet etchant to remove nitrogen The silicon army curtain layer 10. During the wet etching process, the second pad oxide layer 8 can prevent the etchant from invading the polycrystalline silicon layer 6 downward to avoid eventually damaging the substrate. Then, the pad oxide layer 4, the polycrystalline silicon layer 6 and The second pad oxide layer 8 is sequentially removed. Among them, a buffered oxide-etching solution (BOE solution) or a hydrofluoric acid} F} diluted solution can be used as an etchant to remove the pad oxide layer by wet etching. 4 and the second pad oxide layer 8. The polycrystalline silicon layer 6 can be removed by using a mixed solution of nitric acid (ΗΝ03) and nitrogen acid (HF) as a wet etching agent. In addition, a wet etchant containing potassium hydroxide (K0H) It can also be used to clear the polycrystalline silicon layer. Finally, referring to the sixth circle, the gate oxide layer grows again on the semiconductor substrate 2. Then, an active element composed of a gate, a source, and a drain is formed on the active area to complete Manufacture of CMOS Transistor》 According to the method described above, the field oxidation isolation region 12 is formed on the semiconductor substrate 2 to provide a region for impurity isolation between active elements. Because of polycrystalline -----.-- ^- - . ^: 1-1 (Please read the notes on the back before filling in this page) The size of the booklet is in accordance with the national standard of China (CNS > Α4 size (2 丨 〇 × 297mm) h, Ά w ^ Α7 Β7 i. Description of the invention (Silicon 6 can reduce the bird's beak effect; and the second pad oxide layer 8 formed on the polycrystalline silicon layer can prevent the pinhole structure on the substrate 2 caused by the band-like whitening effect. After the substrate damage caused by etching the gasified leather w with a hot phosphoric acid solution, these problems from the traditional field oxidation isolation technology can effectively increase the integration concentration of semiconductor manufacturing, and the method of the present invention can be applied to Deep sub-micron device manufacturing process to achieve higher process yield. The above is only a preferred embodiment of the present invention, and is not intended to limit the patent application scope of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall include Within the scope of the patent application below. ----- L --.—— γ installed ----- ordered --- ^-· Γ line 丨 (Please read the precautions on the back before filling this page) Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumption The paper size printed by the cooperative is applicable to China ’s poor families (CNS) Α4 size (210 × 297 mm)