.¾1¾‘部中夾ir:卒^Jh-Τ消於合作ii印fi 405195 A7 B7 五、發明説明（1 ) 發明領域 本發明涉及一種以銅/無電鍍鎳/焊錫組合之覆晶接合 焊錫隆點及其製法。此焊錫隆點可製作於以鋁爲電極或以 銅爲電極之矽晶半導體積體電路。 發明背景 半導體技術步入次微米時代之後，矽晶片的信號輸出 入點（Input/Output Connection)大幅增加，砂晶片的尺寸也 維持一貫以1.13倍年增率成長（如，；ί. H. Lau and Y. H. Pao, Solder Joint Reliability of BGA, CSP, Flip, and Fine Pitch SMT Assemblies，Chapter 1，McGraw-Hill, 1997所描述）， 但是電子產品卻朝輕薄短小目標邁進，這使得過去近二十 年來，電子構裝技術配合著發展高集積度構裝技術；1985 年之前所應用的插排腳技術（Insertion Mount Technology) 的接腳數（Pin Count)多爲五十以下，1985年之後所發展成 熟的表面黏著技術（Surface Mount Technology)不但使元件 模組（Component Module)變薄，也更進一步大幅增加接腳 數，現今的PQFP (Plastic Quad Flat Package)常見達 208 或是 256，其甚至可達300以上，以接腳數而言，例如PQFP這種 週邊（Peripheral)接合技術所能達到的接腳術似已到了飽和 程度，此一方面受限於有限的週邊長度，亦即有限的週邊 空間，另一方面模具加工以及沖壓造成之應力問題都不易 克服，因此已多改爲以蝕刻方式製作且以鐵鎳合金取代銅 合金。 本紙張尺度適州中囤國家樣牟（CNS ) A4規格（210X297公釐） -----^------^------1T------^ (請先閲讀背面之注意事項再填寫本頁) ίί浐部中央il'^'-^.h工消拎合作.=t.l印5! 405195 a7 _B7__ 五、發明説明（2 ) 導線架週邊接合的表面黏著技術，其接腳數已不易再 增加，同時接腳數增加所伴隨的腳距縮小，將影響電性， 近五年來以陣列式（Area Array)構裝接合的BGA (Ball Grid Array)，以錫球取代導線架，縮短電訊傳輸距離，加大腳 距或接腳數，同時其製程較傳統的導線架接合容易，因此 已逐漸取代部份導線架構裝市場，BGA技術的基板與矽晶 片間的電性通路（Electrical Connection)目前多以打線接 合，隨著正發展之中的晶片尺寸構裝（Chip Scale Packaging ; CSP)槪念的引進，未來於高接腳數之元件模組 將亟需以覆晶接合（Flip Chip Bonding)配合BGA技術，製作 所謂的Flip Chip BGA(或C4BGA)，甚至以覆晶接合進行直 接晶片接合（Direct Chip Attachment ; DCA)的方式，製作早 被提出的晶片接合基板（Chip on Board ; COB)結合，由於覆 晶接合是目前所有三種晶片接合技術（另兩種爲打線接合 以及捲帶式晶片自動接合）中，唯一能以陣列構裝者，其 最能符合高腳數構裝需求，因此電子構裝產業已逐漸建立 此產業結構。 覆晶接合技術的晶片與基板接合方式，可藉導電膠 (Electrical Conductive Adhesive)或焊錫隆點（Solder Bump) 接合，導電膠技術尙在硏發階段，受限於導電膠的電性較 差，短時間內尙不易普及。焊錫隆點接合技術通常需於晶 片上製作焊錫隆點，再將此晶片覆蓋接合於基板的接墊 上，焊錫隆點製作及其品質好壞是影響覆晶接合技術成敗 之關鍵。 本紙乐尺度適用中國國家標率（CNS ) A4規格（210X297公釐） ; 裝------訂------線--1 (請先閲讀背面之注意事項再填讀本頁) 405195 五、發明説明（3 ) 覆晶接合技術特點在於可充份利用晶片表面積以爲 I/O位置，使構裝效率大幅提昇，此技術（如，H. Lau, Flip Chip Technologies, Chapter 1，McGraw-Hill, 1996所描述）晶 片與基板必須分別製作I/0(Input/0utput)焊錫隆點（Solder Bump)與焊錫墊（Bump Pad)，藉黏晶機（Die Bonder) 將晶片對位覆接於基板之焊錫墊，再加熱使焊錫重熔聚成 球狀以與焊錫墊接合，焊錫重新熔融，熔融時藉焊錫液之 表面張力作用，進一步輔助晶片與基板之對位，此步驟稱 爲重流（Reflow)，重流之後，晶片即與基板接合，接合 之後，晶片與基板之間的空隙可塡以適當之塡充膠 (Underfill)以保護接點，提升可靠度（Reliability)。覆 晶接合之晶片先行製作的焊錫隆點，是製作於晶片線路的 電極（Electrode )上，是晶片與基板間訊號的輸出入（I/O ) 點，功能與傳統打線接合的金線相同，焊錫隆點的整體高 度大約100 μιη (微米）左右，因此，覆晶接合的訊號傳輸 距離大幅縮短，覆晶接合導線電感（Lead Inductance)較 傳統打線接合或捲帶自動接合爲小（如，M. Warrior, Proc. Electronic Components Conference Vol.l, ( 1990 Proc. 40th Electronic Components and Technology Conf. ) IEEE Piscataway，N.J·，V.S.A，1990, P.460.所描述。）》焊錫重 流時，焊錫隆點承受高於焊錫熔點30~50°C左右之溫度， 例如共晶成份之63錫-37鉛的熔點爲183°C，重流溫度約爲 200〜240°C左右，一般之晶片線路電極多爲鋁薄膜，鋁和錫 在228°C左右形成共晶反應（Eutectic Reaction)，共晶成 -6 - 本紙张尺度適州屮國國家標準（CNS ) Α4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝. -踉· 405195 A7 B7 五、發明説明（4 ) 份爲含97.8 wt% Sn，如此則鋁電極薄膜易被侵蝕’晶片與 基板之接合迅即失效，因此在焊錫與鋁電極間需有適當的 中間層。 焊錫和鋁之間的中間層稱爲隆點底層金屬UBM (Under Bump Metallurgy)或 BLM (Ball Limiting Metallurgy)，主要功 能包括提供作爲擴散障礙層（Diffusion Barrier)，黏合層 (Adhesive Layer)，以及抗氧化層或潤濕層；擴散障礙層 之作用爲防止發生如上述之焊錫與電極（如鋁）的反應， 黏合層之作用是增進多層膜間之結合力，抗氧化層或潤濕 層之作用爲防止擴散障礙層及黏合層於鍍焊錫之前發生 氧化，並促進與焊錫之潤濕性。爲達到上述各項功能，UBM 通常是兩種或兩種以上的材料或多層薄膜與鍍層所組 成》決定UBM材料選擇之因素包括電極材料種類如鋁或 銅，以及焊錫材料種類與成份。UBM之多層薄膜或鍍層組 合，其製作方式通常採用物理氣相蒸鍍，無電鍍（化學 鍍），電鍍等，同時配合微影（Lithography )與蝕刻技術， 以能選擇性地於所需接點位置製作焊錫隆點，因此選擇 UBM薄膜材料時，也必須慮及是否能有適當之製程以配 合。 目前所知的焊錫隆點，焊錫仍以錫鉛爲主，綜合考量 機械性質，潤濕性、熔點等特性需求，錫鉛仍是蕞佳選擇。 IBM是最早硏發成功覆晶接合技術者，焊錫隆點採用 Cr/Cu/Au爲UBM，Cr兼有障礙層與黏合層作用，Cu則 提供與焊錫接合的黏合層，此因Cu與焊錫中的錫易反 -7 - 本紙張尺度適/ίΗ7國國家標率TCNS ) A4規格（210X297公釐） ----_l·----装------訂------柬 (請先聞讀背面之注意事項再填寫本頁) 405195 A7 _B7__ 五、發明说明（5 ) 應，形成固溶甚或生成金屬間化合物（Intermetallic Compound)，但是Cu易氧化，氧化之後降低潤濕性，因此 先鍍上黃金薄膜以防止氧化，黃金薄膜與焊錫有絕佳潤濕 性。 IBM (如，K. J. Pultlitz，IEEE Trans, CHMT，Vol.13, No.4, Dec. 1990, P.647所描述）的覆晶接合基板是多層氧化鋁陶瓷 基板，導通孔（Via)塡充鉬（Mo)，鉬易氧化且與焊錫 潤濕性不佳，因此先鍍一層無電鍍鎳以增進焊錫性 (Solderability )，但是鉬不易直接施行無電鍍鎳，必須先 進行鈀（Pd)活化；無電鍍鎳與鉬再經熱處理以增加接合 強度：無電鍍鎳層亦經無電鍍方式鍍上一層黃金薄膜，一 方面防止無電鍍鎳氧化，另一方面增加其與焊錫的潤濕 性。 經淺部中夾消价合作.ίι卬繁 (請先聞讀背面之注意事項再填筠本頁) 焊錫隆點是製作於晶片上，晶片經過鈍化 (Passivation )以保護非接點部位，繼之藉金屬光罩之助 以真空蒸鍍方式依序蒸鍍Cr(鉻）、Cu(銅），以及Au (黃 金）於焊錫接點部位’接點大小是直徑120 μπι，.接著亦以 真空蒸鍍焊錫隆點，焊錫是以鉛·錫或鉛-銦合金爲蒸鍍 源’金屬的蒸氣壓不同會造成甫鍍著的焊錫隆點成份不均 勻，因此必須施以重流，重流一方面可使焊錫隆點成份均 勻，另一方面藉表面張力作用，使焊錫凝聚成球形，這對 後續的接合很重要。基板與晶片即藉對位與再次重流以接 合。¾1¾ 'in the middle of the ir: J ^ -T disappeared in cooperation ii India fi 405195 A7 B7 V. Description of the invention (1) Field of the invention The present invention relates to a flip-chip bonding solder joint with copper / electroless nickel / solder combination. Point and its manufacturing method. This solder bump can be fabricated in a silicon semiconductor integrated circuit using aluminum as an electrode or copper as an electrode. Background of the Invention After the semiconductor technology entered the sub-micron era, the signal input / output connection (input / output connection) of silicon wafers has increased significantly, and the size of sand wafers has continued to grow at an annual rate of 1.13 times (eg, ί. H. Lau and YH Pao, Solder Joint Reliability of BGA, CSP, Flip, and Fine Pitch SMT Assemblies, as described in Chapter 1, McGraw-Hill, 1997), but electronic products have moved towards thin, light and short goals, which has made the past two decades, The electronic assembly technology cooperates with the development of high-integration assembly technology; the Pin Count of Insertion Mount Technology applied before 1985 is mostly less than 50, and the developed after 1985 Surface Mount Technology not only makes component modules thinner, but also significantly increases the number of pins. Today's PQFP (Plastic Quad Flat Package) is commonly 208 or 256, which can even reach 300 Above, in terms of the number of pins, the pinning technique that can be achieved by the peripheral bonding technology such as PQFP seems to have reached a saturation level. On the one hand restricted by the limited length of the periphery, i.e. outside the limited space, on the other hand the press mold and the stress caused by the problems are not easy to overcome, and therefore has multiple and changed by etching in order to produce an iron-nickel alloy, a copper alloy substituent. The size of this paper is suitable for the National Sample (CNS) A4 specification (210X297 mm) of the middle store in Shizhou ----- ^ ------ ^ ------ 1T ------ ^ (please first Read the notes on the back and fill in this page) ίί 中央 il '^'-^. H Industry and cooperation cooperation. = Tl 印 5! 405195 a7 _B7__ 5. Description of the invention (2) Surface bonding technology of the lead frame peripheral joint The number of pins is no longer easy to increase. At the same time, the increase in the number of pins will reduce the pitch. It will affect the electrical properties. In the past five years, the BGA (Ball Grid Array) has been assembled in an area array. The ball replaces the lead frame, shortens the telecommunications transmission distance, and increases the pitch or number of pins. At the same time, its process is easier than the traditional lead frame to join, so it has gradually replaced part of the lead frame installation market. The BGA technology substrate and the silicon wafer Electrical connection is currently mostly wire-bonded. With the introduction of the chip scale packaging (CSP) concept under development, component modules with high pin counts will be in urgent need of Flip Chip Bonding is used in conjunction with BGA technology to make the so-called Flip Chip BGA (or C4BGA). Direct chip Attachment (DCA) is used for die bonding to make chip on board (COB) bonding. Since flip chip bonding is all three of the current wafer bonding technologies (the other two are wire bonding) Among bonding and tape-and-wafer automatic bonding), the only one who can use the array structure can best meet the needs of high-pin structure. Therefore, the electronic structure industry has gradually established this industrial structure. The chip-to-substrate bonding method of flip-chip bonding technology can be bonded by Electrical Conductive Adhesive or Solder Bump. The conductive adhesive technology is limited in the bursting stage due to the poor electrical properties of the conductive adhesive. Time is not easy to spread. Solder bump bonding technology usually requires the production of solder bumps on the wafer, and then bonding the wafer to the pads of the substrate. The production of solder bumps and their quality are the key factors that affect the success of flip-chip bonding technology. This paper scale is applicable to China National Standards (CNS) A4 specification (210X297mm); Packing ------ Order ------ Line--1 (Please read the precautions on the back before filling this page ) 405195 V. Description of the invention (3) The flip-chip bonding technology is characterized by making full use of the surface area of the wafer as the I / O position, which greatly improves the construction efficiency. This technology (such as H. Lau, Flip Chip Technologies, Chapter 1, (Described by McGraw-Hill, 1996) The wafer and the substrate must be made with I / 0 (Input / 0utput) solder bumps and solder pads, respectively, and the wafers must be aligned by Die Bonder. The solder pad connected to the substrate is reheated to re-melt the solder into a spherical shape to join the solder pad. The solder is remelted. The surface tension of the solder liquid is used to further assist the alignment of the wafer and the substrate during melting. This step is called Reflow. After reflow, the wafer is bonded to the substrate. After bonding, the gap between the wafer and the substrate can be filled with a proper underfill to protect the contacts and improve reliability. The solder bumps made before the flip-chip bonding wafer are made on the electrode (Electrode) of the chip circuit. They are the input / output (I / O) points of the signal between the chip and the substrate. The function is the same as the traditional wire bonding gold wire. The overall height of the solder bump is about 100 μιη (microns), so the signal transmission distance of the flip-chip bonding is greatly shortened, and the lead-inductance of the flip-chip bonding wire is smaller than the traditional wire bonding or tape automatic bonding (such as M Warrior, Proc. Electronic Components Conference Vol.l, (1990 Proc. 40th Electronic Components and Technology Conf.) IEEE Piscataway, NJ ·, VSA, 1990, P.460 .. The point withstands temperatures higher than the melting point of the solder by about 30 ~ 50 ° C. For example, the eutectic composition of 63 tin-37 lead has a melting point of 183 ° C, and the reflow temperature is about 200 ~ 240 ° C. Generally, there are many wafer circuit electrodes It is an aluminum thin film. Aluminum and tin form an eutectic reaction at about 228 ° C, and the eutectic becomes -6.-This paper is sized to the National Standard of China (CNS) Α4 (210X297 mm) (please first Read the precautions on the back and fill in this page again) -Packing.-踉 · 405195 A7 B7 V. Description of the Invention (4) The part contains 97.8 wt% Sn, so the aluminum electrode film is easily eroded. Therefore, an appropriate intermediate layer is required between the solder and the aluminum electrode. The intermediate layer between solder and aluminum is called Under Bump Metallurgy (BBM) or Ball Limiting Metallurgy (BLM). Its main functions include providing a diffusion barrier, an adhesive layer, and an anti-resistance layer. An oxide layer or a wetting layer; the role of the diffusion barrier layer is to prevent the reaction between the solder and the electrode (such as aluminum) as described above. The role of the adhesive layer is to improve the bonding between the multilayer films and the role of the anti-oxidation layer or the wetting layer In order to prevent the diffusion barrier layer and the adhesive layer from oxidizing before the solder plating, and to promote the wettability with the solder. In order to achieve the above functions, UBM is usually composed of two or more materials or multilayer films and coatings. The factors that determine the choice of UBM materials include the types of electrode materials such as aluminum or copper, and the types and composition of solder materials. UBM's multilayer film or plating combination is usually produced by physical vapor deposition, electroless plating (electroless plating), electroplating, etc., together with Lithography and etching technology to selectively select the required contacts The location of the solder bumps, so when selecting the UBM film material, you must also consider whether there can be an appropriate process to cooperate. Currently known solder bumps, solder is still mainly tin-lead, comprehensive consideration of mechanical properties, wettability, melting point and other characteristics, tin-lead is still the best choice. IBM is the earliest successful chip-on-chip bonding technology. The solder bumps use Cr / Cu / Au as the UBM. Cr functions as a barrier layer and an adhesive layer. Cu provides an adhesive layer that is bonded to the solder. Xi Yifan-7-This paper is suitable for 7 national standards TCNS) A4 specification (210X297 mm) ----_ l · ---- Packing -------- Order ------ Cambodia (please read the precautions on the back before filling this page) 405195 A7 _B7__ 5. Description of the invention (5) It should form a solid solution or even an intermetallic compound, but Cu is easy to oxidize and reduce wetting after oxidation Therefore, the gold film is first plated to prevent oxidation, and the gold film has excellent wettability with solder. IBM (eg, described by KJ Pultlitz, IEEE Trans, CHMT, Vol.13, No.4, Dec. 1990, P.647) is a multilayer alumina ceramic substrate with vias filled with molybdenum. (Mo), molybdenum is easily oxidized and has poor wettability with solder, so a layer of electroless nickel is first plated to improve solderability (Solderability), but molybdenum is not easy to directly perform electroless nickel, and palladium (Pd) activation must be performed first; no electricity Nickel plating and molybdenum are then heat-treated to increase the bonding strength: the electroless nickel layer is also electrolessly plated with a gold film to prevent oxidation of the electroless nickel and increase its wettability with the solder. Through the cooperation of the price reduction in the shallow part. 卬 ί 繁 (please read the precautions on the back before filling in this page) The solder bumps are made on the wafer, and the wafer is passivated to protect the non-contact parts. With the help of a metal photomask, Cr (chromium), Cu (copper), and Au (gold) were sequentially vapor-deposited by means of a vacuum evaporation method. The size of the solder contact point was 120 μπι in diameter. Evaporation of solder bumps. Solder is made of lead · tin or lead-indium alloy as the evaporation source. The difference in the vapor pressure of the metal can cause uneven solder bump composition. Therefore, heavy flow must be applied. On the one hand, it can make the composition of the solder bumps uniform, and on the other hand, the surface tension can make the solder condense into a spherical shape, which is very important for the subsequent bonding. The substrate and the wafer are aligned and reflowed to join.
Motorola 公司（如 ’ M. Warrior, Proc· Electronic 本紙張尺度適用中國國家榇隼（CNS ) A4規格（210X297公釐） 405195 ；； 五、發明説明（6 )Motorola (such as ’M. Warrior, Proc · Electronic) This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) 405195; 5. Description of the invention (6)
Components Conference Vol.l, ( 1990 Proc. 40th Electronic Components and Technology Conf.) IEEE Piscataway, N.J., V.S.A, 1990, P.460.所描述。）則採用Ti-W (鈦鎢）爲黏 合層，以較厚的銅鍍層（16 μιη)與焊錫接合，但一般真 空蒸鍍不易獲致如此厚之鍍層，因‘此須配合電鍍技術》 Motorola公司的焊錫隆點製程是於晶片上真空濺鍍鋁-銅 合金爲電極（Electrode或Metal Pad)，並依序濺鍍Ti-W( 2000 A)及Cu(lOOOA) ;Ti-W也可應用於捲帶自動 接合（TAB)之黃金接點的擴散障礙層；Cu極易與焊錫反 應，焊錫性固然不錯，但1000 A厚之薄膜很容易被焊錫完 全侵蝕，Ti-W的焊錫性很差，因此必須提供足夠量的Cu， 厚達16 μηι的Cu則只有以電鍍技術才能迅速獲致，但是Ti-W極易氧化，造成電化學上的鈍化（Passivation)現象，產 生極大電阻，不利電鍍，因此先以真空濺鍍方式鍍上保護 性之Cu薄膜。此焊錫隆點製程，是以電鍍方式製作焊錫， 但與大部份電鍍製程不同的是，此製程分別鍍上一層鉛及 一層錫，再以重流方式將二者熔成焊錫隆點。Components Conference Vol.l, (1990 Proc. 40th Electronic Components and Technology Conf.) IEEE Piscataway, N.J., V.S.A, 1990, P.460. ) Uses Ti-W (titanium-tungsten) as the bonding layer, and a thicker copper plating layer (16 μm) is bonded to the solder, but it is not easy to obtain such a thick plating layer in general by vacuum evaporation. Therefore, it is necessary to cooperate with electroplating technology. Motorola Company The solder bump process is vacuum sputtering aluminum-copper alloy as an electrode (Electrode or Metal Pad) on the wafer, and sequentially sputtering Ti-W (2000 A) and Cu (lOOOA); Ti-W can also be applied to The diffusion barrier layer of the gold contact of TAB; Cu easily reacts with solder, although the solderability is good, but the 1000 A thick film is easily eroded by solder, and the solderability of Ti-W is very poor. Therefore, a sufficient amount of Cu must be provided. Cu up to 16 μηι can be quickly obtained only by electroplating. However, Ti-W is extremely susceptible to oxidation, causing electrochemical passivation, resulting in great resistance, which is disadvantageous for electroplating. First, a protective Cu film is plated by vacuum sputtering. This solder bump process uses electroplating to make solder, but unlike most electroplating processes, this process is plated with a layer of lead and a layer of tin, respectively, and the two are melted into a solder bump by heavy flow.
Hitachi 公司（如，K. Mizuishi and T. Mori, IEEE Trans. CHMT，Vol.ll，Νο·4, Dec.，1988, P.481.所描述。)於GaAs SRAM晶片製作焊錫隆點以便進行覆晶接合、，由於銅在 GaAs中很容易擴散，因此選用不含銅的UBM組合，在GaAs 上所選用的線路電極是Mo/Au/Mo組合，晶片焊錫隆點採用 鈦（Ti)或鉻（Cr)爲黏合層，鎳（Ni)，鉬（Mo)，鈀 (Pd)或鉑（Pt)等爲障礙層，最上層爲黃金薄膜以確保 -9 - 本紙張尺度適川中國國家栋準（CNS ) A4規格（210X297公釐） I . 装 訂------線，--- (請先閲讀背面之注意事項再填寫本頁) A7 B7 五 '發繼评7 ) 與焊錫的潤濕性；UBM之上蒸鍍50 μιη厚的95 Pb-5 Sn焊 錫。兩片已製作焊錫隆點的晶片則藉助熔劑（Flux )之助， 在350 °C進行重流接合。Zero X公司（如，K. Wong, K. Chi, and A. Rangappan, Plating and Surface Finishing, July 1988, P. 70 所描述。）與 Toshiba 公司（如，M.Inaba，K.Yamakawa，and N.Iwase，IEEE Trans. CHMT，Vol.13, No.1，March 1990， P.119.所描述。）都發展出以無電鍍鎳爲UBM的焊錫隆點， 前者於晶片上蒸鍍的鋁電極以鋅置換活化之後施行無電 鍍鎳（5 μιη)，繼之鍍上0.2 μιη的無電鍍金，配合助熔劑 之助，以浸焊錫製作60Sn-40Pb的焊錫隆點，所得焊錫 隆點高度爲20~30 μιη ; Toshiba公司則採用鈀（Pd )活化 再施行無電鍍鎳（2 μιη)，無電鍍鎳層熱處理（150°C，30 分鐘）之後，以浸焊錫分兩次先浸焊99 Pb-1 Sn ( 360-400 它），再浸焊63 511-37?1)( 200~240°(：)，所得焊錫隆點高 度大約20//m。日本 NTT 公司（如，K.FujwaraandM. Asahi， IEEE Trans. CHMT, Vol.CHMT-10, No.2, June 1987, P.263. 與 J. Temmyo, K. Aoki, and H. Yoshikiyo，J. Appl. Phys”Hitachi Corporation (as described by K. Mizuishi and T. Mori, IEEE Trans. CHMT, Vol.ll, No. 4, Dec., 1988, P.481.). Solder bumps are fabricated on GaAs SRAM wafers for overlaying. Because of the easy diffusion of copper in GaAs, the UBM combination without copper is selected. The line electrode selected on GaAs is a Mo / Au / Mo combination. The chip solder bumps are made of titanium (Ti) or chromium ( Cr) is the adhesive layer, nickel (Ni), molybdenum (Mo), palladium (Pd) or platinum (Pt), etc. as the barrier layer, and the uppermost layer is a gold thin film to ensure -9 CNS) A4 specification (210X297mm) I. Binding ------ line, --- (Please read the precautions on the back before filling this page) A7 B7 5'Fa further evaluation 7) Wetness; 50 μm thick 95 Pb-5 Sn solder is deposited on UBM. The two solder bumped wafers were reflow bonded at 350 ° C with the help of a flux (Flux). Zero X Corporation (as described by K. Wong, K. Chi, and A. Rangappan, Plating and Surface Finishing, July 1988, P. 70.) and Toshiba Corporation (such as M. Inaba, K. Yamakawa, and N Iwase, IEEE Trans. CHMT, Vol.13, No.1, March 1990, P.119.) Have developed solder bumps using electroless nickel as the UBM, the former being an aluminum electrode vapor-deposited on a wafer After activation with zinc replacement, electroless nickel (5 μιη) is applied, followed by 0.2 μιη electroless gold plating, with the help of flux, 60Sn-40Pb solder bumps are made with dip solder. The height of the solder bumps is 20 ~ 30 μιη; Toshiba Company uses palladium (Pd) activation and then performs electroless nickel plating (2 μιη). After heat treatment of the electroless nickel layer (150 ° C, 30 minutes), dip solder 99 Pb- 1 Sn (360-400 it), then dip solder 63 511-37? 1) (200 ~ 240 ° (:), the height of the solder bump is about 20 // m. Japan NTT company (such as K. FujwaraandM. Asahi , IEEE Trans. CHMT, Vol. CHMT-10, No.2, June 1987, P.263. And J. Temmyo, K. Aoki, and H. Yoshikiyo, J. Appl. Phys "
Vol.54, No.9, Sept.，1983, P.5282.所描述）則硏發低熔點焊 錫（共晶In-Bi-Sn，熔點60°C )隆點，晶片蒸鍍Nb ( 3000A ) 爲電極，依序蒸鍍Pb ( 1000A)與Au ( 1000A)爲UBM， 再蒸鍍51 In-33 Bi-16 Sn ( 18〜36 μπ〇爲焊錫隆點，蒸鍍之 後於70t進行重流。 如上所述’除了焊錫本身之外，UBM的製程目前大抵 分爲物理氣相真空蒸鍍以及無電鍍鎳兩系列，兩者各有可 -10 - 本紙张尺度適州中國國家標準（CNS ) A4規格（2丨0X297公釐） (锖先閱讀背面之注意事項再填K本頁) •装. 訂 谏， 405195_^_ 五、發明説明（8 ) 取之處，無電鍍鎳製程可取之處在於其設備投資小，但是 鋁容易氧化造成鈍化，於目前之鋁電極上進行無電鍍鎳， 必須先行活化，例如前述之鋅置換或鈀活化。鋅置換是於 強鹼性的氧化鋅溶液中進行，此鹼性溶液對鋁電極有很強 的侵蝕性，因此爲使用鋅置換，必須增加鋁電極的厚度至 數微米（/zm)，這與目前的半導體產品規格不符合；以鈀活 化之成本較高，而且因爲鈀活化顆粒與鋁的結合強度較 弱，可能對後續製程，尤其是重流之高溫步驟有不良影 響。 發明槪要 本發明涉及一種以銅/無電鍍鎳/焊錫組合之覆晶接合 焊錫隆點及其製法。此焊錫隆點可製作於以鋁爲電極或以 銅爲電極之矽晶半導體積體電路。本發明之特色爲以銅薄 膜取代其他常用之活化層，使極爲容易於半導體之鋁電極 或銅電極上施行無電鍍鎳。 一種依本發明內容而形成於半導體積體電路之電極上 的覆晶接合焊錫隆點包含一焊錫及介於該焊錫與該電極 之間的下方金屬，其特徵在於該下方金屬包含： 形成於該電極上的一銅墊；及 形成於該銅墊上的一無電鍍鎳層。 本發明亦揭示一種於半導體積體電路之電極上形成覆 晶接合焊錫隆點的製法，包含下列步驟： a)於一半導體積體電路上形成一銅膜； _ -11- 本紙張尺度適川中國國家榡率（CNS ) A4規格（210X297公釐） -----K—-—装------訂------柬 I - (請先閱讀背面之注意事項再填寫本頁) 舒·%:‘部中次^4'-而·，：：；.!.消费合作·ΐ·印？^ 405195 五、發明説明（9 ) b) 於該銅膜上形成一光阻層並藉由光微影技術而式樣 化該光阻層，於是使得該銅膜位於該積體電路之電極上的 區域被曝露出： c) 在該被曝露的銅膜上形成無電鍍鎳； d) 於該無電鍍鎳上形成焊錫； e) 剝離該光阻：及 f) 蝕刻移除位於被剝離光阻下方之銅膜。 較佳地，本發明的製法在其步驟f)後進一步包含g)重流 該焊錫而形成焊錫隆點》 於本發明之焊錫隆點中該銅墊的厚度較佳地爲0.1-1 微米，及該無電鍍鎳之厚度較佳地爲1-10微米。 於本發明之焊錫隆點，該無電鍍鎳層可直接位於該焊 錫的下方。選擇性地，本發明之焊錫隆點進一步包含一選 自Au，Pd，Cu，Sn，Ag及Cr所組成族群之潤濕層，其中該潤 濕層介於該無電鍍鎳層與該焊錫之間。 於本發明的焊錫隆點的製法中，該銅膜較佳地係以真 空蒸鍍或真空濺鍍方法被形成。 於本發明的焊錫隆點的製法中，該無電鍍鎳係經一次 或重覆多次的無電鍍鎳浴的處理而被形成。當該無電鍍鎳 係經重覆多次的無電鍍鎳浴的處理而被形成時，其每一次 的無電鍍鎳浴的處理所形成之厚度爲1微米以內。 於本發明的焊錫隆點的製法中，該焊錫可藉由電鍍方 式被形成。 本發明的焊錫隆點的製法可進一步在該步驟d)之前包 -12 - 本紙張尺度適州屮國國家榡皁（CNS ) Α4規格（210X297公釐） ----rL------裝------訂------來--P (請先閲讀背面之注f項再填寫本I) 柯"部中夾工消价合作^印y A7 ___-- 五、發明説明（1Q) 含一於該無電鍍鎳上形成一選自Au，Pd，Cu，Su，Ag及Cr所 組成族群之潤濕層的步驟，其中步驟d)之焊錫以波焊方式 被形成於該潤濕層上。 本發明的焊錫隆點適合被形成一以矽爲基礎之半導體 積體電路。 附圖簡要說明 透過下面的詳細描述，結合這些附圖，本發明的這些 以及其它特徵和優點將會更加明顯，其中： 圖一爲顯示本發明銅/無電鏟鎳/焊錫隆點製程的示意流程 圖。 圖二的（a)及（b)爲已經電鍍焊錫尙未重流之焊錫隆點，焊錫 墊大小是100 X 100 μιη，每一矽晶片有20 X 20 焊錫隆點，其中（b)的放大倍數較（a)大》 圖三的（a)重流之後的焊錫隆點之橫截面的放大照片，及（b) 爲（a)圖界面黑框區域之界面放大照片。 圖四的（a)、（b)爲10 μιη無電鍍鎳之銅/無電鍍鎳/焊錫隆點， 經過250°C，60分鐘長時間重流後，界面之元素電子 掃瞄分析圖，其中橫軸與焊錫隆點的深度有關，而 縱軸與元素濃度有關，其中（a)顯示Sn及Cu的濃度， 而（b)顯示Ni及A1的濃度。 圖五的（a)、（b)爲10 μιη無電鍍鎳之銅/無電鍍鎳/焊錫隆點， 經過210°C，15秒重流後，界面之元素電子掃瞄分 析，其中橫軸與焊錫隆點的深度有關，而縱軸與元 -13 - 本紙张尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -----[------裝------訂------麻--- .. * (請先閲讀背面之注意事項再填寫本頁) 紂沪部中JAi?:^r;:Jh η消价合作ίι卬來 405195 ab] 五、發明説明（n) 素濃度有關，其中（a)顯示Sn及Cu的濃度，而（b)顯示 Ni及A1的濃度。 圖六爲1.8 μιη無電鍍鎳之銅/無電鍍鎳/焊錫隆點，經過210 °C，15秒重流處理後，界面之元素電子掃瞄分析， 其中橫軸與焊錫隆點的深度有關，而縱軸與元素濃 度有關。 圖七的（a)及（b)爲二次無電鍍鎳之銅/無電鍍鎳/焊錫隆 點，無電鍍鎳厚度爲3.2 μιη，以波焊製作焊錫隆點， 經過210°C，15秒重流處理後，界面之元素電子掃瞄 分析，其中橫軸與焊錫隆點的深度有關，而縱軸與 元素濃度有關，其中（a)顯示Cu的濃度，而（b)顯示Ni 的濃度。 圖八的U)及（b)爲二次無電鍍鎳之銅/無電鍍鎳/焊錫隆 點，無電鍍鎳厚度爲1.0 μιη，以波焊製作焊錫隆點， 經過210°C，15秒重流處理後，界面之元素電子掃瞄 分析，其中橫軸與焊錫隆點的深度有關，而縱軸與 元素濃度有關，其中⑷顯示Cu的濃度，而（b)顯示Ni 的濃度。 圖九的（a)、（b)爲銅/無電鍍鎳/焊錫隆點，經過250°C，15 秒重流後之電子顯微照片，其中（b)的放大倍數較（a) 大。 圖十的（a)、（b)爲銅/無電鍍鎳/焊錫隆點，經過250°C，15 秒五次重流後之電子顯微照片，其中（b)的放大倍數 較（a)大。 -14 - 本紙張尺度適川十國囤家標準（CNS )A4規格（210X297公釐） -----r--.--A------訂------'1 (請先閱讀背面之注意事項再填寫本頁) 經沪部中央"'挲而h-1'·消於合作ilrpst __ 405195_B7__ 五、發明説明（12) 圖十一的（a)、（b)爲銅/無電鍍鎳/焊錫隆點，經過250°C，15 秒十次重流後之電子顯微照片，其中（b)的放大倍數 較（a)大。 發明之詳細說明 本發明是於鋁電極濺鍍銅薄膜技術，克服鋅置換與鈀 活化的兩種現存方式的問題，極易施行無電鍍鎳，所製作 之焊錫隆點具有極佳結合強度。目前的矽晶積體電路是於 矽晶片上製作線路之後，於訊號輸出入點製作電極，電極 材料目前以物理蒸鍍鋁薄膜爲主，IBM 1997年宣佈成功地 以銅取代鋁製作線路，可預見未來將有銅線路積體電路逐 漸商品化。無論是鋁或是銅線路，都必須經由電極 (Electrode)輸出入訊號，電極即所謂訊號輸出入點（Input/ Output; I/O)，爲與線路材料相符合，鋁線路之電極爲鋁電 極，銅線路則爲銅電極，電極均爲薄膜，其厚度爲數千埃 (Angstrom, A)。砂晶片之接合（Die Bonding)方式有很多種， 包括打線接合（Wire Bonding)，捲帶式自動接合（Tape Automated Bonding ; TAB)，以及覆晶接合（Flip Chip Bonding，又稱 Controlled Collapsed Chip Connection: C4) 等，其中以覆晶接合所能達到的I/O數最多，可達1000以 上》 覆晶接合之矽晶需製作焊錫隆點（Solder Bump)於電 極，本發明針對目前之鋁電極及銅電極提出簡易的無電鍍 鎳/焊錫隆點結構以及其製程，說明如下。 -15 - 本紙张尺度適扣t國因家栋羋（CNS > A4规格（210X297公釐） -----l·--·--装------訂------浓 (請先閲讀背面之注意事項再填寫本頁) 好"'‘部中夾^sf^h-x消於合作"卬^- A7 405195_Έ.__ 五、發明说明（13) 如圖一所示，本發明的矽晶片上是以真空濺鍍 (Sputtering Deposition)方式，依一般所知之條件先行濺鍍 鋁薄膜，鋁薄膜上繼之鍍以銅薄膜’銅薄膜厚度可爲2000 至5000A，接著藉用光罩微影（Lithography)製程，使用正光 阻，於銅薄膜上製作所需之焊錫隆點組合（Pattern) ’此焊 錫隆點組合可爲髙I/O數或低I/O數的陣列（Area Array)、或 週邊（Peripheral)、或半陣列式。於此微影製程焊錫隆點位 置被設定，亦即被暴露出的銅薄膜被作爲焊錫墊（Bump Pad)。此焊錫墊以適當酸洗例如5~20%硝酸溶液將表面氧 化物淸除，繼之使用適當的無電鍍鎳鍍浴’例如以硫酸鎳 爲金屬來源，以次磷酸鈉爲還原劑的酸性浴或鹼性浴（如， 林光隆、李傳英，”結合無電鍍與浸鍍方法製備焊錫隆點”， 中華民國專利，發明第083624號，與Kwang-Lung Lin and Chwan-Ying Lee, “Method for Producing Electroless Barrier Layer and Solder Bump on Chip”，U. S· Patent 5,583,073, Dec. 10, 1996.所描述。），於焊錫墊之銅薄膜上施行所需厚度之 無電鍍鎳，無電鍍鎳的厚度可爲丨至1〇 μπι。無電鍍鎳上再 以電鍍方式鍍所需厚度之焊錫（即鉛錫合金），此焊錫的 厚度可爲任意所需之厚度，電鍍完成之後，將光阻以有機 溶劑剝離，再以適當之蝕刻液將位於焊錫隆點間距（Pitch) 位置的銅、鋁薄膜淸除（Etch Off)，此時所得的焊錫隆點如 圖二之（a)、（b)所示’此圖中的焊錫隆點之焊錫墊大小是100 μηι X 100 μιη，每一矽晶片之焊錫隆點組合是20 X 20 個焊錫隆點，電鍍可以任何適用之焊錫電鍍浴與電鍍條件 -16 - 本紙張尺度適flit囤國家標準（CNS ) Α4規格（210Χ297公釐) ---------裝------訂------懷 I (請先閲讀背面之注意事項再填寫本頁) 405195 五、發明説明（14) 施行之。位於焊錫隆點間距位置的銅、鋁薄膜被淸除之 後，輔以適當助熔劑（Flux)於適當升溫速度以及重流溫度 下，進行重流（Reflow)，以藉表面張力之助形成焊錫隆點， 如圖三所示，圖三所示的焊錫隆點爲63Sn-37Pb成份，此焊 錫隆點成份可爲電鍍可獲致之任意成份（如* Kwang-Lung Lin and Jieh-Ting Chang, U. S. Patent 5,560,813, Oct. 1, 1996 所描述）。上述無電鍍鎳也可再鍍上適當的潤濕層如鈀、金 等，再以波焊方式製作焊錫隆點（如，林光隆，游智媚，趙 文軒，”於半導體晶圓的電極上製作焊錫隆點的連續方 法”，中華民國專利發明第091756號所描述。）。 上述焊錫隆點製程與目前採用無電鍍鎳之製程不同處 在於，由於採用銅薄膜鍍於鋁電極之上，因此後續無電鍍 鎳時，不需以目前所用的鋅置換（Zincating)或其他活化， 如鈀活化，對鋁膜進行前處理，免除鋅置換可能蝕刻鋁薄 膜之問題，也免除使用高成本之鈀活化製程：採用銅薄膜 鍍於鋁電極之上，同時也可適用於未來之銅薄膜電極，製 作無電鍍鎳/焊錫隆點製程；因此本發明提出之焊錫隆點 結構包括鋁電極或銅電極適用之銅/無電鍍鎳/焊錫。本發 明上述製程於以下實施例被進一步說明。 實施例一（一種於半導體積體電路之電極上形成覆晶接 合焊錫隆點的一般製程） 於一半導體積體電路鋁電極薄膜上濺鍍一銅薄膜（厚 度爲2000-5000A)之後，利用正型光阻劑，藉由旋轉塗佈 -17 - 本紙張尺度適用中國國家標準（CNS ) Λ4规格（210X297公t ) ----Γ-----裝------訂------棟 (請先閲讀背面之注意事項再填巧本頁) 好溁部中央訢^x'Jh-T-·消介合作"印^- 405195 五、發明説明（15) (spin coating)於該銅膜上形成一光阻層並藉由光微影技術 而式樣化該光阻層，使得該銅膜位於該積體電路之預定的 區域被曝露出。藉由此微影製程焊錫隆點位置可被設定， 被暴露出的銅薄膜被作爲焊錫墊。此焊錫墊以5〜20%硝酸 溶液酸洗，將表面氧化物淸除，繼之使用以硫酸鎳爲金屬 來源，以次磷酸鈉爲還原劑的酸性浴或鹸性浴當作無電鍍 鎳鍍浴，在被曝露的銅膜上鍍以1~ 10 μιη無電鍍鎳鍍層， 並於該無電鍍鎳鍍層上以任何習用之電鍍液電鍍焊錫（至 所需任意厚度）、剝離（lift-off)該光阻及以適當蝕刻劑（如， 硝酸溶液）蝕刻移除位於被剝離光阻下方之銅膜而形成焊 錫隆點。 於以下實施例使用本實施例一所描述之一般製程來製 作焊錫隆點。 實施例二 圖四之（a)及（b)是鋁電極濺鏟銅薄膜之後，鍍以10 μιη 無電鍍鎳鍍層，並電鍍焊錫隆點，經過於250°C，60分鐘長 時間焊錫重流之後的橫截面電子顯微分析，分析結果顯 示，鋁鍍膜完全沒有往焊錫方向擴散的跡象，顯見此10 μιη 的無電鍍鎳所組合的濺鍍銅/無電鍍鎳隆點底層金屬 (Under Bump Metallrugy)可以有效發揮擴散障礙層的效 果。此製程的銅則會像焊錫方向擴散，但並不影響無電鍍 鎳作爲擴散障礙層的效果。 本紙張X度適用中國國家標準（CNS ) A4规格（210X297公釐） -------_--A------訂------束， (請先閱讀背面之注意事項再填寫本I) 405195 ***——^—— _ ___ . _ 五、發明説明（μ ) 16 實施例三 一般正常的焊錫重流製程是於重流溫度十數秒時間內 完成，圖五之（a)及（b)所示是，鋁電極濺鍍銅薄膜之後，鏟 以10 μιη無電鍍鎳鍍層，並電鍍焊錫隆點，經過於210°C， 15秒重流之後的橫截面電子顯微鏡分析，分析結果顯示鋁 鍍膜完全沒有往焊錫方向擴散的跡象，銅也沒有擴散，顯 見此10 μιη的無電鍍鎳所組合的濺鍍銅/無電鍍鎳底層金 屬，可以有效發揮擴散障礙層的效果。 實施例四 圖六所示是以1.8 μιη的無電鍍鎳鍍層，組成濺鍍銅/無 電鍍鎳底層金屬，焊錫經210°C，15秒重流之後的橫截面電 子顯微鏡分析，分析結果顯示雖然銅有向焊錫擴散的現 象，但是鋁薄膜沒有向焊錫擴散的跡象，因此顯示1.8 μιη 的無電鍍鎳所組成的濺鍍銅/無電鍍鎳底層金屬，可以有效 發揮焊錫與鋁間擴散障礙層的效果。 實施例五 如上述的製程，但是濺鍍銅以酸淸洗之後，先於第一 無電鍍鎳鑛浴進行1〜2分鐘預鍍無電鍍鎳之後，再於第二 無電鍍鎳鍍浴進行無電鍍鎳，此二無電鍍鎳鍍浴成分可以 是相同組成，使無電鏟鎳度層厚度達所需厚度’如1~1〇 μιη，所得濺鍍銅/無電鍍鎳隆點底層金屬與其上以波焊製 作焊錫隆點之焊錫，經21(TC，15秒重流之後，焊錫隆點的 本紙张尺度通州中國國家楳準（CNS ) A4規格（210X297公釐） --------.--:展------訂------'i r //, (請先閱讀背面之注意事項再填寫本頁) 405195 五、發明説明（17) 的橫截面電子顯微鏡分析結果如圖七之（a)及（b)顯示，無電 鍍鎳層厚度爲3.2 μιη時，銅以及鋁薄膜都沒有向焊錫擴散 的跡象，因此顯示以短時間預鍍無電鍍鎳，再進行無電鍍 鎳，所獲得的濺鍍銅/無電鍍鎳隆點底層金屬，可以有效發 揮焊錫與鋁之間擴散障礙層的效果，同時也具有焊錫與銅 間擴散樟礙層的效果，因而此製程所製作之預鍍無電/無電 鍍鎳隆點底層金屬可以作爲於銅電極上製作之覆晶接合 焊錫隆點的底層金屬。 實施例六 如上述實施例四的製程，以波焊製作焊錫隆點，但無 電鍍鎳層厚度改爲1.0 μπι。如圖八之（a)及（b)所示，銅以及 鋁薄膜都沒有向焊錫擴散的跡象，因此顯示以短時間預鍍 無電鍍鎳之後，無電鍍鎳層厚度小至1 μπι即可有效發揮擴 散障礙層的效吳。 實施例七 如上述實施例一至例三之焊錫隆點結構與製程，但是 重流溫度改爲250°C，15秒，所得之焊錫隆點如圖九之（a) 及（b)所示。焊錫隆點結合強度良好，平均剪力強度可達62.9 ± 2.8g/bump以上，圖九之U)及（b)中的焊錫墊大小爲100 X 100 μηι。 實施例八 -20 · 本紙張尺度適州中國國家標準（CNS ) Α4規格（210X297公釐） -----r--„--装------訂------浓 {請先閲讀背面之注意事項再填反本頁) A7 B7 五、發明説明（18 ) 如上述實施例六之焊錫隆點，但重流次數增加爲反覆 五次，所得焊錫隆點如圖十之（a)及（b)所示。焊錫隆點沒有 任何脫落，平均剪力強度爲35.4 ± 4.1 g/bump以上。 實施例九 如上述實施例六之焊錫隆點，但重流次數增加爲反覆 十次，所得焊錫隆點如圖十一之（a)及（b)所示。焊錫隆點沒 有任何脫落，平均剪力強度爲37.6 ± 6.0 g/bump以上。 -----r--.--装------訂------涞 Μ - (請先閱讀背面之注意事項再填??'本页) :¾¾-部中呔i?.·準而W.T..消於合作11印$·! 本紙張尺度適fflt闼國家標卑-(CNS ) Α4規格（210Χ297公釐）Vol.54, No.9, Sept., 1983, P.5282.) The low melting point solder (eutectic In-Bi-Sn, melting point 60 ° C) bulges are formed, and the wafer is vapor-deposited Nb (3000A) As an electrode, Pb (1000A) and Au (1000A) were sequentially vapor-deposited as UBM, and then 51 In-33 Bi-16 Sn (18 ~ 36 μπ〇) were solder bumps. After evaporation, reflow was performed at 70t. As mentioned above, except for the solder itself, UBM's manufacturing process is currently largely divided into two series: physical vapor deposition and electroless nickel. Each of them can be used. -10-This paper is suitable for China National Standards (CNS) A4. Specifications (2 丨 0X297mm) (锖 Please read the precautions on the back before filling the K page) • Installation. Ordering, 405195 _ ^ _ 5. Description of the invention (8) Where to take it, the electroless nickel process is preferable Its equipment investment is small, but aluminum is easy to oxidize and cause passivation. Electroless nickel plating on current aluminum electrodes must be activated first, such as the aforementioned zinc replacement or palladium activation. Zinc replacement is performed in a strong alkaline zinc oxide solution. This alkaline solution is very aggressive to the aluminum electrode, so in order to use zinc replacement, the thickness of the aluminum electrode must be increased Up to several micrometers (/ zm), which does not meet the current specifications of semiconductor products; the cost of activation with palladium is higher, and because the bonding strength of palladium-activated particles and aluminum is weak, it may affect subsequent processes, especially the high temperature of heavy flow The steps have an adverse effect. SUMMARY OF THE INVENTION The present invention relates to a flip-chip bonding solder bump with a copper / electroless nickel / solder combination and a method for making the solder bump. The solder bump can be made of silicon using aluminum as an electrode or copper as an electrode Crystal semiconductor integrated circuit. The feature of the present invention is to replace other commonly used activation layers with copper films, making it extremely easy to perform electroless nickel on aluminum or copper electrodes of semiconductors. A semiconductor integrated circuit formed in accordance with the present invention The flip-chip bonding solder bump on the electrode includes a solder and a lower metal interposed between the solder and the electrode, characterized in that the lower metal includes: a copper pad formed on the electrode; and formed on the copper An electroless nickel layer on the pad. The present invention also discloses a method for forming flip-chip solder bumps on electrodes of a semiconductor integrated circuit, including the following steps: a) A copper film is formed on a semiconductor integrated circuit; _ -11- This paper is suitable for the Chinese National Standard (CNS) A4 size (210X297 mm) of Sichuan ----- K ------- --- Order ------ Cambodia I-(Please read the notes on the back before filling this page) Shu ·%: '部 中 次 ^ 4'-And ·, ::;.!. Consumer Cooperation · ΐ · India? 405195 V. Description of the invention (9) b) A photoresist layer is formed on the copper film and the photoresist layer is patterned by photolithography technology, so that the copper film is located on the electrode of the integrated circuit The area is exposed: c) forming electroless nickel on the exposed copper film; d) forming solder on the electroless nickel; e) stripping the photoresist: and f) removing the photoresist under the stripped photoresist by etching Copper film. Preferably, the method of the present invention further includes g) reflowing the solder after step f) to form a solder bump. In the solder bump of the present invention, the thickness of the copper pad is preferably 0.1-1 micrometers, And the thickness of the electroless nickel is preferably 1-10 microns. At the solder bumps of the present invention, the electroless nickel layer can be directly under the solder. Optionally, the solder bump of the present invention further comprises a wetting layer selected from the group consisting of Au, Pd, Cu, Sn, Ag, and Cr, wherein the wetting layer is between the electroless nickel layer and the solder. between. In the method for manufacturing solder bumps of the present invention, the copper film is preferably formed by a vacuum evaporation method or a vacuum sputtering method. In the method for producing a solder bump according to the present invention, the electroless nickel plating is formed by the treatment of an electroless nickel plating bath once or repeatedly. When the electroless nickel plating is formed by repeated treatments of the electroless nickel plating bath, the thickness formed by each treatment of the electroless nickel plating bath is within 1 micrometer. In the method for manufacturing a solder bump of the present invention, the solder can be formed by electroplating. The method for preparing solder bumps according to the present invention may further include -12 before the step d).-The paper size is in accordance with the standard of the State of Soap (CNS) A4 (210X297 mm) ---- rL ----- -Install ------ order ------ come --P (please read the note f on the back before filling in this I) Ke " the ministry and the price reduction cooperation ^ 印 y A7 ___-- 5. Description of the invention (1Q) Contains a step of forming a wetting layer selected from the group consisting of Au, Pd, Cu, Su, Ag, and Cr on the electroless nickel, wherein the solder of step d) is wave-welded Is formed on the wetting layer. The solder bumps of the present invention are suitable for being formed into a silicon-based semiconductor integrated circuit. Brief Description of the Drawings These and other features and advantages of the present invention will be more apparent through the following detailed descriptions, combined with these drawings, in which: Figure 1 is a schematic flow diagram showing the copper / electroless shovel nickel / solder bump process of the present invention. Illustration. (A) and (b) of Figure 2 are solder bumps that have not been reflowed, and the pad size is 100 X 100 μιη. Each silicon wafer has 20 X 20 solder bumps. (B) is an enlargement of The magnification is larger than (a) "Figure 3 (a) enlarged photo of the cross section of the solder bump after reflow, and (b) is (a) the enlarged picture of the interface in the black frame area of the interface. (A) and (b) in Figure 4 are 10 μm electroless nickel-plated copper / electroless nickel / solder bumps. After a long-term reflow at 250 ° C for 60 minutes, the elemental electronic scanning analysis of the interface is shown. The horizontal axis is related to the depth of the solder bump, and the vertical axis is related to the element concentration. (A) shows the concentrations of Sn and Cu, and (b) shows the concentrations of Ni and A1. (A) and (b) in Figure 5 are 10 μm electroless nickel-plated copper / electroless nickel / solder bumps. After reflow at 210 ° C for 15 seconds, the elements of the interface are scanned electronically. The horizontal axis and The depth of the solder bump is related to the vertical axis of Yuan-13-This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) ----- [------ 装 ----- -Order ------ Hemp --- .. * (Please read the notes on the back before filling out this page) JAi?: ^ R;: Jh η Consumer Price Cooperation 卬 卬 405195 ab] V. Description of the invention (n) The concentration of elements is related, in which (a) shows the concentrations of Sn and Cu, and (b) shows the concentrations of Ni and A1. Figure 6 is a 1.8 μm electroless nickel-plated copper / electroless nickel / solder bump. After reflow treatment at 210 ° C for 15 seconds, the elements of the interface are scanned electronically. The horizontal axis is related to the depth of the solder bump. The vertical axis is related to the element concentration. (A) and (b) of Fig. 7 are the copper / electroless nickel / solder bumps of the secondary electroless nickel. The thickness of the electroless nickel is 3.2 μm. The solder bumps are made by wave welding. After 210 ° C, 15 seconds After reflow treatment, the elemental electronic scanning analysis of the interface, where the horizontal axis is related to the depth of solder bumps, and the vertical axis is related to the element concentration, where (a) shows the concentration of Cu, and (b) shows the concentration of Ni. U) and (b) in Figure 8 are the copper / electroless nickel / solder bumps of the secondary electroless nickel. The thickness of the electroless nickel is 1.0 μm. The solder bumps are made by wave welding. After 210 ° C, the weight is 15 seconds. After the flow treatment, the elemental electronic scanning analysis of the interface shows that the horizontal axis is related to the depth of solder bumps, and the vertical axis is related to the element concentration, where ⑷ shows the concentration of Cu and (b) shows the concentration of Ni. (A) and (b) of Fig. 9 are electron micrographs of copper / electroless nickel / solder bump after 250 ° C and 15 seconds of heavy flow. The magnification of (b) is larger than that of (a). (A) and (b) in Figure 10 are electron micrographs of copper / electroless nickel / solder bump after five reflows at 250 ° C for 15 seconds. The magnification of (b) is higher than (a). Big. -14-The size of this paper is suitable for Sichuan Ten Countries (CNS) Standard A4 (210X297mm) ----- r --.-- A ------ Order ------ '1 (Please read the notes on the back before filling in this page) The Central Ministry of Shanghai " '挲 而 h-1' · Consumer Cooperation ilrpst __ 405195_B7__ V. Description of the invention (12) Figure 11 (a), (b ) Is an electron micrograph of copper / electroless nickel / solder bump after 250 ° C, ten times reflow in 15 seconds, where (b) is larger than (a). Detailed Description of the Invention The present invention is based on the technology of sputtering copper film on aluminum electrodes, which overcomes the problems of two existing methods of zinc replacement and palladium activation. It is extremely easy to implement electroless nickel, and the solder bumps produced have excellent bonding strength. The current silicon integrated circuit is to make electrodes at the signal input and output points after making the circuit on the silicon wafer. The electrode material is currently mainly physical vapor-deposited aluminum film. IBM announced in 1997 that it has successfully replaced copper with aluminum to make circuits. It is foreseen that there will be commercialization of copper circuit integrated circuits in the future. No matter it is aluminum or copper circuit, it is necessary to input and output signals through the electrode (Electrode). The electrode is the so-called signal input / output point (Input / Output; I / O). In accordance with the circuit material, the aluminum circuit electrode is an aluminum electrode. The copper circuit is a copper electrode, and the electrodes are thin films with a thickness of thousands of angstroms (Angstrom, A). There are many kinds of die bonding methods, including wire bonding, tape automated bonding (TAB), and flip chip bonding (also known as Controlled Collapsed Chip Connection: C4), etc. Among them, the number of I / Os that can be achieved by flip-chip bonding is the highest, which can reach more than 1,000. "Silicon-on-chip bonding requires the production of solder bumps for the electrodes. The present invention is directed to current aluminum electrodes and The copper electrode proposes a simple electroless nickel / solder bump structure and its process, as described below. -15-The size of this paper is suitable for the country of China (CNS > A4 size (210X297 mm)) ----- l ·-· --installation ------ order ----- -Rong (Please read the precautions on the back before filling this page) Good "'' in the middle ^ sf ^ hx eliminates cooperation" 卬 ^-A7 405195_Έ .__ 5. Description of the invention (13) As shown in Figure 1 It is shown that the silicon wafer of the present invention is vacuum sputtered (Sputtering Deposition), and an aluminum film is sputtered in accordance with generally known conditions. The aluminum film is then plated with a copper film. The thickness of the copper film can be 2000 to 5000 A. Then use the lithography process and use a positive photoresist to produce the required solder bump combination on the copper film. 'This solder bump combination can be 髙 I / O number or low I / O number. Area Array, Peripheral, or semi-array type. In this lithography process, the solder bump position is set, that is, the exposed copper film is used as a solder pad. This solder pad The surface oxides are removed by appropriate pickling, such as a 5-20% nitric acid solution, followed by a suitable electroless nickel plating bath, such as nickel sulfate as the metal source, An acidic or alkaline bath with sodium hypophosphite as a reducing agent (eg, Lin Guanglong, Li Chuanying, "Preparing solder bumps by combining electroless plating and dip plating methods", Republic of China Patent, Invention No. 083624, and Kwang-Lung Lin and Chwan-Ying Lee, "Method for Producing Electroless Barrier Layer and Solder Bump on Chip", as described in U.S. Patent 5,583,073, Dec. 10, 1996.). Nickel plating, the thickness of electroless nickel can be 丨 to 10μπι. Electroless nickel is then plated with a desired thickness of solder (ie, lead-tin alloy). The thickness of this solder can be any desired thickness. After completion, peel off the photoresist with an organic solvent, and then remove the copper and aluminum films at the pitch of the solder bumps (Etch Off) with an appropriate etching solution. At this time, the solder bumps obtained are shown in Figure 2 (A), (b) 'The solder pad size of the solder bumps in this picture is 100 μη X 100 μιη, the solder bump combination of each silicon wafer is 20 X 20 solder bumps, and electroplating can be applied to any Solder plating bath And Plating Conditions-16-This paper is suitable for the national standard (CNS) A4 specification (210 × 297 mm) of the Flit store --------- Installation ------ Order ------ 怀 I ( (Please read the notes on the back before filling this page) 405195 V. Description of Invention (14) Implementation. After the copper and aluminum films located at the distance between the solder bumps are removed, supplemented with an appropriate flux (Flux) at an appropriate heating rate and a reflow temperature, reflow is performed to form a solder bump by surface tension. As shown in Figure 3, the solder bump shown in Figure 3 is a 63Sn-37Pb component. This solder bump component can be any component that can be obtained by electroplating (such as * Kwang-Lung Lin and Jieh-Ting Chang, US Patent 5,560,813, Oct. 1, 1996). The above electroless nickel can also be plated with a suitable wetting layer such as palladium, gold, etc., and then solder bumps can be made by wave soldering (eg, Lin Guanglong, You Zhimei, Zhao Wenxuan, "making solder bumps on the electrodes of semiconductor wafers" Point continuous method ", described in ROC Patent Invention No. 091756.). The difference between the above solder bump process and the current process using electroless nickel is that the copper film is used to plate on the aluminum electrode. Therefore, the subsequent electroless nickel plating does not need to be replaced with zinc or other activation. If the palladium is activated, pre-treating the aluminum film avoids the problem that zinc replacement may etch the aluminum film, and also eliminates the use of a high-cost palladium activation process: a copper film is used to plate the aluminum electrode, and it can also be applied to future copper films Electrodes are used to produce electroless nickel / solder bumps; therefore, the solder bump structure proposed by the present invention includes copper / electroless nickel / solder suitable for aluminum electrodes or copper electrodes. The above process of the present invention is further explained in the following examples. Embodiment 1 (a general process for forming flip-chip bonding solder bumps on electrodes of a semiconductor integrated circuit) After sputtering a copper film (thickness: 2000-5000A) on an aluminum electrode film of a semiconductor integrated circuit, a positive electrode is used. Type photoresist, by spin coating -17-This paper size applies to Chinese National Standard (CNS) Λ4 specification (210X297g t) ---- Γ ----- installation ------ order-- ---- Building (please read the precautions on the back before filling out this page) 中央 中 中 欣 ^ x'Jh-T- · elimination cooperation " 印 ^-405195 V. Description of the invention (15) (spin coating) forming a photoresist layer on the copper film and patterning the photoresist layer by photolithography technology, so that the copper film is exposed in a predetermined area of the integrated circuit. Through this lithography process, the solder bump position can be set, and the exposed copper film is used as a solder pad. This solder pad is acid-washed with a 5-20% nitric acid solution to remove the surface oxides. Then, an acid bath or an alkaline bath with nickel sulfate as the metal source and sodium hypophosphite as the reducing agent is used as electroless nickel plating. Bath, plating the exposed copper film with 1 ~ 10 μm electroless nickel plating layer, and electroplating solder (to any desired thickness), lift-off with any conventional plating solution on the electroless nickel plating layer The photoresist is etched and removed with a suitable etchant (eg, a nitric acid solution) to remove the copper film under the stripped photoresist to form a solder bump. In the following embodiments, the general process described in the first embodiment is used to make solder bumps. Example 2 (a) and (b) of Figure 4 are aluminum electrode sputtered copper film, and then plated with 10 μm electroless nickel plating, and the solder bumps are plated. After a long time solder reflow at 250 ° C for 60 minutes, Subsequent cross-section electron microscopy analysis showed that the aluminum coating film showed no sign of diffusion in the solder direction, and the sputtered copper / electroless nickel bulge underlayer metal (Unbump Metallrugy) combined with this 10 μm electroless nickel was evident. ) Can effectively play the effect of the diffusion barrier layer. Copper in this process will diffuse in the direction of solder, but it will not affect the effect of electroless nickel as a diffusion barrier. The X degree of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -------_-- A ------ order ------ beam, (Please read the Note for refilling this I) 405195 *** —— ^ —— _ ___. _ 5. Description of the invention (μ) 16 Embodiment 3 The normal solder reflow process is completed within ten seconds of the reflow temperature. The fifth (a) and (b) shows the cross-section of the aluminum electrode after the copper film is sputtered, and the shovel is plated with a 10 μm electroless nickel plating, and the solder bump is plated, after 210 ° C, 15 seconds of reflow. Electron microscope analysis, the analysis results showed that the aluminum coating film showed no signs of diffusion in the solder direction, and copper did not diffuse. It was obvious that the combined copper / electroless nickel base metal of this 10 μm electroless nickel plating can effectively play a diffusion barrier. Effect. Example 4 Figure 6 shows a cross-sectional electron microscope analysis of a 1.8 μm non-plated nickel plating layer, consisting of a sputtered copper / electroless nickel base metal, after the solder has been reflowed at 210 ° C for 15 seconds. Copper diffuses to the solder, but the aluminum film shows no signs of diffusing into the solder. Therefore, it shows that the sputtered copper / electroless nickel base metal composed of 1.8 μm electroless nickel can effectively play the role of the diffusion barrier between solder and aluminum. effect. The fifth embodiment is the same as the above process, but after the sputtered copper is washed with acid, first electroless nickel plating is performed in the first electroless nickel plating bath for 1 to 2 minutes, and then electroless in the second electroless nickel plating bath. The composition of the two electroless nickel plating baths can be the same, so that the thickness of the non-shovel nickel layer can reach the required thickness, such as 1 to 10 μm. Wave soldering is used to produce solder bumps. After 21 (TC, 15 seconds of reflow, the paper size of the solder bumps is Tongzhou China National Standard (CNS) A4 specification (210X297 mm) -------- .--: Exhibition ------ Order ------ 'ir //, (Please read the precautions on the back before filling this page) 405195 V. Cross-section electron microscope analysis of invention description (17) The results are shown in Figures 7 (a) and (b). When the thickness of the electroless nickel layer is 3.2 μm, neither copper nor the aluminum film has diffused to the solder. Therefore, it is shown that the electroless nickel is pre-plated in a short time, and then the electricity is not applied Nickel plating, the obtained sputtered copper / electroless nickel bump base metal can effectively play the barrier of diffusion between solder and aluminum It also has the effect of a diffusion barrier layer between solder and copper. Therefore, the pre-plated electroless / electroless nickel bump base metal produced by this process can be used as the bottom layer of the flip-chip bonding solder bump produced on the copper electrode. The sixth embodiment is the same as the process of the fourth embodiment, and the solder bumps are made by wave welding, but the thickness of the electroless nickel layer is changed to 1.0 μm. As shown in (a) and (b) of the figure, copper and aluminum films There are no signs of diffusion into the solder, so it is shown that after the electroless nickel is pre-plated for a short time, the thickness of the electroless nickel layer is as small as 1 μm to effectively exert the effect of the diffusion barrier layer. The structure and manufacturing process of the solder bumps, but the reflow temperature was changed to 250 ° C for 15 seconds. The solder bumps obtained are shown in (a) and (b) of Figure 9. The solder bumps have good bonding strength and average shear force. The strength can reach 62.9 ± 2.8g / bump or more. The size of the solder pads in U) and (b) in Figure 9 is 100 X 100 μηι. Example 8-20 · The paper size is in accordance with the Chinese National Standard (CNS) Α4 specification (210X297 mm) ----- r-„-installation ------ order ------ concentrated {Please read the precautions on the back and fill in the reverse page) A7 B7 V. Description of the invention (18) As in the solder bump of the sixth embodiment above, but the number of reflows increased five times, the solder bump obtained is shown in Figure 10. As shown in (a) and (b). The solder bumps did not fall off, and the average shear strength was 35.4 ± 4.1 g / bump or more. The ninth embodiment is the solder bumps of the sixth embodiment, but the number of reflows increases as Repeated ten times, the resulting solder bumps are shown in (a) and (b) of Figure 11. The solder bumps did not fall off, and the average shear strength was 37.6 ± 6.0 g / bump or more. ----- r- -.-- install ------ order ------ 涞 Μ-(Please read the precautions on the back before filling in this page): ¾¾- 部 中 呔 i?. · 准 和 WT . Eliminated by cooperation 11 printed $! This paper is suitable for fflt 闼 National Standard-(CNS) Α4 size (210 × 297 mm)