經濟部中央標準局員工消費合作社印製 I?05 ^ 五、發明説明（I ) 本發明是有關於一種強化靜電放電（Electroitatic Discharge，ESD)保護電路之金氧半電晶體（M0S)結構及其 製造方法，且特別是有關於一種可用以解決電晶體在驟回 狀態（Snapback)因爲電流推擠（Current Crowding)現象而限 制靜電放電能力之金氧半電晶體結構。 積體電路的製程中，靜電放電常是導致積體電路損壞 的主要原因。目前，靜電放電的問題已成爲深次微米積體 電路故障的主要原因之一。爲了克服靜電放電所產生的問 題’乃將晶片嵌入式(On-Chip)的靜電放電保護電路加諸於 互補式金氧半積體電路(以下以CMOS簡稱之）的輸出輸入 靜墊上。但是靜電放電保護電路的防護功能也隨著半導體 製程的發展而嚴重的衰退下來。所以，如何有效提昇靜電 放電保護電路的效率乃爲目前業界所亟盼的。 金氧半電晶體元件，不論是閘極接地式金氧半電晶體 (Gate Grounded M0S)或是閘極藕接式金氧半電晶體（Gate Coupled M0S)，在積體電路中已常被作爲靜電放電保護電 路中的主要元件。金氧半電晶體的靜電放電保護能力，幾 乎視筒電壓驟回機制（Snap-back Mechanism)而定，此高電 壓驟回機制係用以在汲極(Drain)與源極（Source)之間傳導 巨大的靜電放電電流。在此以N型金氧半電晶體爲例，起 初’在汲極接面產生的高電場會造成撞擊離子化（Inlpact Ionization)’而使得少數載子（Minority Carriers)流向基底 (Substrate)或P型井的接觸窗(Contact)，然後在P型井區 產生區域電位（Local Potential)。當此區域基底電位比鄰接 _—__ 3 氏張尺度ϋ中®ΐ家標準（CNS ) A4規格（210X297公釐） - (請先閱讀背面之注意事項再填离本頁) 訂Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs I? 05 ^ V. Description of the Invention (I) The present invention relates to a metal-oxide-semiconductor (M0S) structure with enhanced Electrostatic Discharge (ESD) protection circuit and its structure. The manufacturing method, and in particular, relates to a gold-oxygen semi-transistor structure that can be used to solve the problem that the transistor is in a snapback state due to the current crowding phenomenon and the electrostatic discharge capability is limited. In the manufacturing process of integrated circuits, electrostatic discharge is often the main cause of damage to integrated circuits. At present, the problem of electrostatic discharge has become one of the main reasons for the failure of deep submicron integrated circuits. In order to overcome the problem caused by electrostatic discharge, an on-chip electrostatic discharge protection circuit is added to the input and output static pads of a complementary metal-oxide-semiconductor circuit (hereinafter abbreviated as CMOS). However, the protection function of the electrostatic discharge protection circuit has also deteriorated with the development of semiconductor processes. Therefore, how to effectively improve the efficiency of the electrostatic discharge protection circuit is currently urgently expected by the industry. Metal-oxide-semiconductor devices, whether they are gate grounded MOSFETs (Gate Grounded M0S) or gate-connected metal-oxide semiconductors (Gate Coupled M0S), have been often used as integrated circuits The main component in ESD protection circuits. The electrostatic discharge protection capability of metal-oxide semiconductors is almost determined by the snap-back mechanism of the barrel voltage. This high-voltage snap-back mechanism is used between the drain and the source. Conducts a huge electrostatic discharge current. Here, an N-type metal-oxide semiconductor is taken as an example. At first, the high electric field generated at the drain junction will cause impact ionization (Inlpact Ionization) and cause minority carriers to flow to the substrate or P. The contact window of the well is used to generate a local potential in the area of the P well. When the basal potential of this area is higher than the adjacent _—__ 3's scale standard Chinese Standard (CNS) A4 (210X297 mm)-(Please read the precautions on the back before filling out this page) Order
At1 . 經濟部中央標準局員工消費合作社印製 2991twf/005 Λ/4Q4(]4|_____ 五、發明説明（>) 的源極電位高出約0.6V時，源極接面就變成順偏(Forward Bias)。此順偏的源極接面會將少數載子注入P型井中，最 後少數載子到達汲極接面又進一步增強撞擊離子化，如此 連續循環的結果，使金氧半電晶體進入一低阻抗（驟回）狀 態，以傳導巨大的靜電放電電流。 隨著從汲極流向源極接面的電流之增加，最後將產生 電流推擠（Current Crowding)的現象或稱電流壓縮（Current Constriction)現象，使靜電放電電流延著汲極/源極接面間 的若干狹窄路徑，經由閘極下方流入最弱點（Weakest Spot)。狹窄推擠路徑沿線的高電流密度會引發熱和更多的 載子產生，結果區域溫度昇高到矽或鋁的熔點溫度，而對 矽或接觸窗造成永久破害。我們最期望的是靜電放電電流 均勻地從汲極流向源極，並且延著整個閘極邊緣平均分 散。如果延著閘極邊緣有一弱點(Weak Spot)產生，例如氧 化物間隙壁(Oxide Spacer)不均勻等，則靠近弱點處發生電 流推擠，在汲極擴散區靠近弱點處將率先崩潰（Break Down) ’結果因而導致元件損壞。 請同時參照第1圖與第2圖，第1圖繪示乃傳統靜電 放電保護電路之金氧半電晶體結構剖面圖，第2圖繪示乃 第1圖中金氧半電晶體的佈局上視圖。金氧半電晶體1〇 之源極擴散區11與汲極擴散區〗2形成於一基底13(或P 型井）中。來自於銲墊或VDD匯流排14的靜電放電電流， 經由汲極擴散區12與基底13分別流向閘極15、源極11 與接觸窗16流入Vss匯流排17,而達到靜電放電的功效。 _ 4 本紙張尺度適用巾關.¾ ( CNS ) A4^ ( 210X297公楚1 ~~~— (請先閱讀背面之注意事項再填寫本頁)At1. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 2991twf / 005 Λ / 4Q4 (] 4 | _____ 5. When the source potential of the invention (>) is about 0.6V higher, the source junction becomes forward biased (Forward Bias). This forward-biased source junction will inject minority carriers into the P-well, and finally the minority carriers reach the drain junction to further enhance the impact ionization. As a result of this continuous cycle, the gold-oxygen half-electricity The crystal enters a low impedance (snapback) state to conduct a huge electrostatic discharge current. As the current flowing from the drain to the source interface increases, the phenomenon of current crowding or current compression will eventually occur (Current Constriction) phenomenon, which causes the static discharge current to extend along several narrow paths between the drain / source interface and flow into the weakest spot (Weakest Spot) under the gate. The high current density along the narrow pushing path will cause heat and As more carriers are generated, the temperature of the region rises to the melting point of silicon or aluminum, which causes permanent damage to the silicon or contact window. What we most expect is that the electrostatic discharge current flows uniformly from the drain to the source, and And spread evenly along the entire gate edge. If a weak spot (such as Oxide Spacer) is generated along the gate edge, a current push occurs near the weak point, and it diffuses at the drain. The area near the weak point will be the first to break down (Break Down). As a result, the component will be damaged. Please refer to Figure 1 and Figure 2 at the same time. FIG. 2 is a top view of the layout of the metal-oxide-semiconductor semiconductor in FIG. 1. The source-diffusion region 11 and the drain-diffusion region of the metal-oxide semiconductor 10 are formed on a substrate 13 (or a P-type well). ). The electrostatic discharge current from the pad or VDD bus 14 flows through the drain diffusion region 12 and the substrate 13 to the gate 15, source 11 and contact window 16 and flows into the Vss bus 17 to achieve electrostatic discharge. Efficacy. _ 4 This paper size is suitable for towels. ¾ (CNS) A4 ^ (210X297 公 楚 1 ~~~ — (Please read the precautions on the back before filling this page)
經濟部中央標隼局貝工消費合作社印聚 2 9 9 ltwf/ 0 05 A7404G41_bL_______ 五、發明説明（·）） 第3圖繪示乃金氧半電晶體的電流-電壓崩潰特性曲線 圖，請參照第3圖，金氧半電晶體在達到崩潰電壓VB之 後，即進入所謂的驟回（Simp-back)狀態。此時之電晶體係 以崩潰模式運作，然並未被損壞，係以理想之電流-電壓 崩潰特性曲線30放電。在此一狀態下，電阻係數極小， 可以很快地將靜電放電電流旁路（Bypass)掉，此即靜電放 電的特性。 然而，在上述金氧半電晶體結構中，當靜電放電電流 均勻地從汲極流向源極，並且延著整個閘極邊緣平均分 散，如果延著閘極邊緣有一弱點(Weak Spot)產生時，例如 是第2圖中之弱點A，靠近弱點A處發生電流推擠，使得 汲極擴散區12靠近弱點A處先行崩潰，導致元件損壞， 而得到如第3圖所示之電流-電壓崩潰特性曲線32,在此 一驟回狀態之電阻係數幾等於〇甚或小於〇，無法有效利 用電晶體之驟回狀態，使得靜電放電的能力大大地降低。 由上述可知，傳統靜電放電保護電路之金氧半電晶體 結構具有下列缺點： 1. 金氧半電晶體之靜電放電能力，由於電流推擠的產 生而大大的降低； 2. 傳統上，會以形成大的接觸窗與閘極間隙（Spacer)， 來提高靜電放電的能力，而增加了元件面積；以及 3. 在製程上，爲了要提高靜電放電的能力，更需以額 外的靜電放電光罩在源極擴散區與汲極擴散區中進行所謂 的靜電放電摻雜（ESD Implant)，增加製程的成本與複雜 5 (請先閲讀背面之注意事項再填寫本頁) -* 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 2991twf/005 A7404C41_bL____ 五、發明説明（if ) 度。 有鑑於此，本發明的主要目的就是在提供一種強化靜 電放電保護電路之金氧半電晶體結構及其製造方法，使得 靜電放電電流得以均勻分佈，避免弱點的產生，用以有效 利用金氧半電晶之驟回狀態，強化靜電放電的能力。 根據本發明的目的，提出一種強化靜電放電保護電路 之金氧半電晶體製造方法，用以在一半導體基底上，定義 出一元件區。首先，形成一閘極於元件區；接著，進行低 濃度之一第一型離子摻雜，用以在源極區與汲極區形成輕 摻雜汲極區；之後，形成間隙於閘極兩側；並覆蓋一第一 光罩於汲極區的中央部份以進行高濃度之第一型離子摻 雜，形成源極區與汲極區。此一金氧半電晶體結構等效於 在汲極區串接一電阻。另外，覆蓋第一光罩的步驟，可以 僅覆蓋於與閘極鄰接之部份汲極區，亦可達到相同效果。 根據本發明的另一目的，提出一種強化靜電放電保護 電路之金氧半電晶體製造方法，用以在一半導體基底上， 定義出一元件區。首先，形成一閘極於該元件區；接著， 進行低濃度之一第一型離子摻雜，用以在源極區與汲極區 形成輕摻雜汲極區；之後，形成間隙於閘極兩側；並覆蓋 一第一光罩於源極區與汲極區的中央部份以進行高濃度之 第一型離子摻雜，形成源極區與汲極區。此一金氧半電晶 體結構等效於各在源極區與汲極區串接一電阻。另外，覆 蓋第一光罩的步驟，可以僅覆蓋於與閘極鄰接之部份源極 區與汲極區，亦可達到相同效果。不需利用形成大的接觸 6 - I - - I I — i. I I--——-I I - _ I , 1 -/ Lv - . t (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 經濟部中央標準局員工消費合作社印製 2 9 9 1 twf/ 0 05 λ7 404^41_ 五、發明説明（Γ) 窗與閘極間隙，來提高靜電放電的能力，因而大大地減少 元件使用面積，並強化靜電放電保護的能力。 另外，根據本發明的目的，提出一種強化靜電放電保 護電路之金氧半電晶體結構，其中，位於閘極間隙下方之 源極區係一第一輕摻雜汲極結構；位於閘極間隙下方之汲 極區與汲極區中央部份亦係第一輕摻雜汲極結構，但在汲 極區之其它部份係一高濃度之第二摻雜結構，使得金氧半 電晶體結構等效於在汲極區串接一電阻。抑或在汲極區 中，位於閘極間隙下方之汲極區以及與閘極相鄰之部份係 第一輕摻雜汲極結構，汲極區之其它部份係一高濃度之第 二摻雜結構，亦具有相同之等效電路。 根據本發明的再一目的，提出一種強化靜電放電保護 電路之金氧半電晶體結構，其中，位於閘極間隙下方之源 極區與源極區中央部份係一第一輕摻雜汲極結構，在源極 區之其它部份係一高濃度之一第二摻雜結構；位於閘極間 隙下方之汲極區與汲極區中央部份亦係第一輕摻雜汲極結 構，但在汲極區之其它部份係一高濃度之第二摻雜結構， 使得金氧半電晶體結構等效於在源極區與汲極區各串接一 電阻。抑或在源極區與汲極區中，位於閘極間隙下方之源 極區與汲極區以及與閘極相鄰之部份係第一輕摻雜汲極結 構，源極區與汲極區之其它部份係一高濃度之第二摻雜結 構，亦具有相同之等效電路。均可降低因爲電流推擠效應 所產生弱點之影響，以利用電晶體之驟回狀態，強化靜電 放電保護的能力。 7 (請先閱讀背面之注意事項再填寫本頁) 装- 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 2 9 9 1 twf/0 05 4〇4〇4ΐ A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（A ) 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下·· 圖式之簡單說明： 第1圖繪示乃傳統靜電放電保護電路之金氧半電晶體 結構剖面圖； 第2圖繪示乃第1圖中金氧半電晶體的佈局上視圖； 第3圖繪示乃金氧半電晶體的電流-電壓崩潰特性曲線 圖； 第4A圖與第4B圖所示乃傳統所使用之二種部份靜電 放電保護電路圖；以及 第5A至5E圖繪示依照本發明實施例的一種強化靜電 放電保護電路之金氧半電晶體結構製程剖面圖。 標號說明： A :弱點 Nl, N2, N3, P1 :電晶體 VDD :電壓源 10 :金氧半電晶體 12 :汲極擴散區 14 :銲墊或VDD匯流排14 16 :接觸窗 30, 32 :電流-電壓崩潰特性曲線 40, 46 :節點 42 :銲墊 44:內部電路 51 :元件區 I/P, I/Pl, I/P2 :輸入端 Rl, R2, R3 :電阻 Vss :相對接地端 11 :源極擴散區 13, 50 :基底 15, 52 :閘極 Π : Vss匯流排 (讀先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 2991twf/005MAH44______ 五、發明説明（q) 52 :閘極 53 :源極區 54 :汲極區 55 :輕摻雜汲極區 56 :間隙 57, 58, 59, 60 :光罩 實施例 本發明提供一種強化輕摻雜汲極(Lightly Hoped Drain, LDD)元件之靜電放電保護的結構與方法，其靜電放電的 效能至少比傳統靜電放電的能力大5倍以上。本發明利用 在輕摻雜汲極電晶體中之內建(Built-in)輕摻雜汲極電阻， 來解決在突加電壓（Zap)產生靜電放電時，由於電流推擠造 成區域溫度昇高而導致元件損壞的問題。 第4A圖與第4B圖所示乃傳統所使用之二種部份靜電 放電保護電路圖。在第4A圖中，電晶體N1之源極端耦 接至相對接地端Vss ;汲極端串聯一電阻R1 ;電阻R1並 與一電晶體P1串接；電晶體P1之源極耦接至電壓源VDD ; 電晶體N1與電晶體P1之閘極共接至一輸入端Ι/P;電阻 R1與電晶體P1串接之節點40經由銲墊42耦接至內部電 路44，用以保護內部電路44，將靜電電流放電。在第4B 圖中，電晶體N2在汲極端與源極端各串連一電阻R2與 電阻R3 ;電阻R3耦接至電壓源VDD ;電阻R2耦接至另 一電晶體N3的汲極，並將電晶體N3的源極耦接至相對 接地端Vss ;電晶體N2之閘極耦接至一第一輸入端I/P1 ; 電晶體N3之閘極耦接至一第二輸入端I/P2 ;電阻R2與電 晶體N3串接之節點46經由銲墊42耦至內部電路44，用 以保護內部電路44，將靜電電流放電。 9 1 H— - - 1^1 I- IN ! 1^1 I - I------I T« -a - -./ - . / !-, » 1 (請先閲讀"面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局貝工消費合作社印繁 2 9 9 ltwf/0 05 ^04041 _ b77 五、發明説明（g) . 依據第4A圖與第4B圖所示之電路，請參照第5A至 5E圖’其繪示依照本發明實施例的一種強化靜電放電保 護電路之金氧半電晶體結構製程剖面圖。在本實施例中， 僅以N型金氧半電晶體作說明，p型金氧半電晶體之形成 可以相同方法來達成。 第一實施例： 首先’如第5A圖所示，在半導體基底50上方之元件 區51形成一閘極52。其方法例如是以傳統形成閘氧化層 後’再沉積一多晶矽層，並加上光阻蝕刻去除部份多晶矽 層與鬧氧化層而留下閘極52之結構。此處之元件區51包 括源極區53與汲極區54。然後進行N型離子摻雜，在半 導體基底50之源極區53與汲極區54中先形成所謂的輕 慘雜汲極區55。之後，並在閘極52兩側形成間隙56。 接著’請參照第5B圖，以一小塊光罩57覆蓋在部份 汲極區54上方的中央部份，並進行高濃度之N型離子摻 雜’得到第5B圖所示之源極區53與汲極區54。此一電 晶體之等效電路如第4A圖所示串接之電晶體N1與電阻 R1，係一般常用之靜電放電保護電路。 另外’在完成第5A圖之製程後，接著參照第5C圖， 除了以一小塊光罩57覆蓋在部份汲極區54上方之中央部 份並以一小塊光罩Μ以相同方式覆 3 ^央部份，再進行高濃度之N_子摻雜，得到第fc 之源極區53與汲極區54。此—電晶體之等效電路 如桌4B圖所示串接之電阻μ、電晶體μ與電阻部 ____ 10 CNS ) Α4^(·21〇χ 297^¥)~^~~-- (請先閲讀背面之注意事項再填』巧本頁) ，1Τ 經濟部中央標準局員工消費合作社印製 2991twf/005 A7^〇4G4j_bi______ 五、發明説明（y ) 份。 在此一實施例中所得到之電阻，係一經由自我對準之 方法所形成之一輕摻雜汲極電阻。 第二實施例： 在完成第5A圖所示之製程後，另參照第5D圖，以一 小塊光罩59覆蓋住部份汲極區54上方與閘極52相鄰處， 然後再進行高濃度之N型離子摻雜，得到第5D圖所示之 源極區53與汲極區54。此一電晶體之等效電路如第4A 圖所示串接之電晶體N1與電阻R1，係一般常用之靜電放 電保護電路。 如同第一實施例中之說明，另外，在完成第5A圖之 製程後，接著請參照第5E圖，以一光罩60同時各覆蓋在 部份汲極區54上方與閘極52相鄰處以以源極區53上方 與閘極52相鄰處，再進行高濃度之N型離子摻雜，得到 第5E圖所示之源極區53與汲極區54。此一電晶體之等 效電路亦如第4B圖所示串接之電阻R2、電晶體N2與電 阻R3部份。 在此一實施例中所得到之電阻，係一以延長輕摻雜汲 極之方法所形成之一輕摻雜汲極電阻，不會有如第3圖所 示之電流-電壓崩潰特性曲線32情形發生，得以有效利用 電晶體之驟回狀態。 在上述實施例中，由於輕摻雜汲極電晶體之內建輕摻 雜汲極電阻，大大地強化了電晶體之靜電放電保護能力， 相較於傳統之靜電放電能力而言，至少可接受5倍以上的 HI I— I 11 ^^^1 κ» HH m - t r t (請先閱讀背面之注意事項再填{IT本頁) 本紙張尺度適用中國國家梯準（CNS ) A4規格（210X297公釐） 經濟部中央標隼局員工消費合作社印製 2991twf/005 A7MM4i________ 五、發明説明（γ) 突增電壓。 因此，本發明的特徵之一是提供一金氧半電晶體結構， 用以當靜電放電電流均勻地從汲極流向源極時，得以延著 整個閘極邊緣平均分散，降低因爲電流推擠效應所產生弱 點之影響，以利用電晶體之驟回狀態。 本發明的特徵之二是利用在輕摻雜汲極電晶體中之內 建輕摻雜汲極電阻，來解決在突加電壓（Zap)產生靜電放電 時，由於電流推擠造成區域溫度昇高而導致元件損壞的問 題，強化靜電放電保護的能力。 本發明的特徵之三是不需利用形成大的接觸窗與閘極 間隙，來提高靜電放電的能力，因而大大地減少元件使用 面積。 本發明的特徵之四是不需再以額外的靜電放電光罩在 源極擴散區與汲極擴散區中進行所謂的靜電放電摻雜，減 少製程的成本與複雜度。 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 I I—I - -- - I I - - —^― T - - I : -——-I I * -I (請先閱讀背面之注意事項再填寫本頁) 12 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）The Central Bureau of Standards, the Ministry of Economic Affairs, the Shellfish Consumer Cooperative, Printed Poly 2 9 9 ltwf / 0 05 A7404G41_bL_______ V. Description of the Invention (·)) Figure 3 shows the current-voltage collapse characteristic curve of a metal-oxygen semi-transistor. In FIG. 3, after the metal-oxide semiconductor transistor reaches the breakdown voltage VB, it enters a so-called Simp-back state. At this time, the transistor system operates in a collapse mode, but is not damaged, and is discharged with an ideal current-voltage collapse characteristic curve 30. In this state, the resistivity is extremely small, and the electrostatic discharge current can be bypassed quickly, which is the characteristic of electrostatic discharge. However, in the above-mentioned gold-oxygen semi-electric crystal structure, when the electrostatic discharge current flows uniformly from the drain to the source and is evenly distributed along the entire gate edge, if a weak spot (Weak Spot) is generated along the gate edge, For example, it is the weak point A in FIG. 2. A current push occurs near the weak point A, so that the drain diffusion region 12 collapses near the weak point A, leading to component damage, and the current-voltage collapse characteristic shown in FIG. 3 is obtained. Curve 32, the resistivity in this snapback state is almost equal to or even smaller than 0, and the snapback state of the transistor cannot be effectively used, so that the electrostatic discharge capacity is greatly reduced. From the above, it can be known that the metal-oxide-semiconductor structure of the traditional electrostatic discharge protection circuit has the following disadvantages: 1. The electrostatic discharge capacity of metal-oxide semi-crystals is greatly reduced due to the generation of current; 2. Traditionally, Form a large contact window and gate gap (Spacer) to increase the electrostatic discharge capacity and increase the component area; and 3. In the manufacturing process, in order to improve the electrostatic discharge capacity, an additional electrostatic discharge mask is needed The so-called electrostatic discharge doping (ESD Implant) is performed in the source diffusion region and the drain diffusion region, which increases the cost and complexity of the process 5 (Please read the precautions on the back before filling this page)-* This paper size is applicable to China National Standard (CNS) A4 Specification (210X297 mm) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 2991twf / 005 A7404C41_bL____ 5. Description of the invention (if). In view of this, the main object of the present invention is to provide a gold-oxygen semi-electric crystal structure for strengthening an electrostatic discharge protection circuit and a manufacturing method thereof, so that the electrostatic discharge current can be uniformly distributed, the generation of weak points is avoided, and the metal-oxygen half is effectively used. The sudden return of the transistor to strengthen the ability of electrostatic discharge. According to the object of the present invention, a method for manufacturing a metal-oxide semiconductor transistor for strengthening an electrostatic discharge protection circuit is proposed, which is used to define a device region on a semiconductor substrate. First, a gate is formed in the element region. Then, a first type ion doping at a low concentration is performed to form a lightly doped drain region in the source region and the drain region. Then, a gap is formed between the gate and the gate region. And cover a first photomask on the central portion of the drain region to perform high-concentration first-type ion doping to form a source region and a drain region. This metal-oxide-semiconductor structure is equivalent to a resistor in series with the drain region. In addition, the step of covering the first photomask can cover only the drain region adjacent to the gate, and the same effect can be achieved. According to another object of the present invention, a method for manufacturing a metal-oxide semiconductor transistor for strengthening an electrostatic discharge protection circuit is provided, which is used to define a device region on a semiconductor substrate. First, a gate is formed in the element region; then, a first-type ion doping at a low concentration is performed to form a lightly doped drain region in the source region and the drain region; thereafter, a gap is formed in the gate. On both sides; and covering a central portion of the source region and the drain region with a first photomask for high-concentration first-type ion doping to form the source region and the drain region. The metal-oxide semiconductor structure is equivalent to a resistor connected in series in the source region and the drain region. In addition, the step of covering the first photomask can cover only the source region and the drain region adjacent to the gate, and the same effect can be achieved. No need to use to make a large contact 6-I--II — i. I I --——- II-_ I, 1-/ Lv-. T (Please read the precautions on the back before filling this page) This paper Standards are applicable to China National Standard (CNS) A4 (210X 297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 2 9 9 1 twf / 0 05 λ7 404 ^ 41_ 5. Description of the invention (Γ) The gap between the window and the gate , To improve the ability of electrostatic discharge, thereby greatly reducing the area of component use, and strengthen the ability of electrostatic discharge protection. In addition, according to the purpose of the present invention, a metal-oxide semi-transistor structure for strengthening an electrostatic discharge protection circuit is proposed, wherein a source region located below a gate gap is a first lightly doped drain structure; and is located below the gate gap The drain region and the central part of the drain region are also the first lightly doped drain structure, but the other part of the drain region is a high-concentration second doped structure, making the gold-oxygen semi-electric crystal structure, etc. Effective in series with a resistor in the drain region. Or in the drain region, the drain region located below the gate gap and the portion adjacent to the gate are the first lightly doped drain structures, and the other portions of the drain region are a high concentration second doped regions. Miscellaneous structure also has the same equivalent circuit. According to still another object of the present invention, a metal-oxide-semiconductor structure for strengthening an electrostatic discharge protection circuit is proposed, in which a source region located under a gate gap and a central portion of the source region are a first lightly doped drain Structure, in the other part of the source region is a high concentration of a second doped structure; the drain region below the gate gap and the central part of the drain region is also the first lightly doped drain structure, but The other part of the drain region is a high-concentration second doped structure, so that the gold-oxygen semitransistor structure is equivalent to a resistor connected in series in the source region and the drain region. Or in the source region and the drain region, the source region and the drain region below the gate gap and the portion adjacent to the gate are the first lightly doped drain structures, the source region and the drain region. The other part is a high-concentration second doped structure, which also has the same equivalent circuit. Both can reduce the impact of weak points due to the current pushing effect, in order to take advantage of the sudden return state of the transistor to strengthen the ability of electrostatic discharge protection. 7 (Please read the notes on the back before filling out this page) Binding-The size of the paper is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) 2 9 9 1 twf / 0 05 4〇4〇4ΐ A7 B7 Economy Printed by the Ministry of Standards and Staff ’s Consumer Cooperatives V. Invention Description (A) In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings, The detailed description is as follows: The diagram is briefly explained: Figure 1 shows the cross-section of the structure of the metal-oxide-semiconductor in the traditional electrostatic discharge protection circuit; Figure 2 shows the layout of the metal-oxide-semiconductor in the first figure Top view; Figure 3 shows the current-voltage collapse characteristic curve of a metal-oxide semiconductor transistor; Figures 4A and 4B are two types of traditional electrostatic discharge protection circuit diagrams traditionally used; and Figures 5A to FIG. 5E is a cross-sectional view of a metal-oxygen semi-electric crystal structure manufacturing process of an enhanced electrostatic discharge protection circuit according to an embodiment of the present invention. Explanation of symbols: A: Weak points Nl, N2, N3, P1: Transistor VDD: Voltage source 10: Metal oxide semiconductor transistor 12: Drain diffusion region 14: Solder pad or VDD bus 14 16: Contact window 30, 32: Current-voltage collapse characteristic curve 40, 46: node 42: pad 44: internal circuit 51: component area I / P, I / Pl, I / P2: input terminals Rl, R2, R3: resistance Vss: relative to ground terminal 11 : Source diffusion region 13, 50: Substrate 15, 52: Gate Π: Vss bus (read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 2991twf / 005MAH44 ______ 5. Description of the invention (q) 52: Gate 53: Source region 54: Drain region 55: Lightly doped drain region 56: Gap 57, 58, 59, 60: Examples of photomasks The present invention provides a structure and method for strengthening electrostatic discharge protection of Lightly Hoped Drain (LDD) elements. The electrostatic discharge efficiency is at least 5 times greater than the traditional electrostatic discharge capacity. the above. The present invention utilizes a built-in light-doped drain resistor in a lightly-doped drain transistor to solve the temperature rise in the region caused by the current push when an electrostatic discharge is generated by a sudden voltage (Zap). This can cause problems with component damage. Figures 4A and 4B show two types of conventional electrostatic discharge protection circuit diagrams. In Figure 4A, the source terminal of transistor N1 is coupled to the opposite ground terminal Vss; the drain terminal is connected in series with a resistor R1; resistor R1 is connected in series with a transistor P1; the source of transistor P1 is coupled to a voltage source VDD The gate of transistor N1 and transistor P1 are connected to an input terminal I / P in common; the node 40 where resistor R1 and transistor P1 are connected in series is coupled to internal circuit 44 via soldering pad 42 to protect internal circuit 44; Discharge static current. In Figure 4B, transistor N2 is connected in series with a resistor R2 and a resistor R3 at the drain and source terminals; resistor R3 is coupled to the voltage source VDD; resistor R2 is coupled to the drain of another transistor N3, and The source of transistor N3 is coupled to the opposite ground terminal Vss; the gate of transistor N2 is coupled to a first input terminal I / P1; the gate of transistor N3 is coupled to a second input terminal I / P2; The node 46 connected in series with the resistor R2 and the transistor N3 is coupled to the internal circuit 44 through the bonding pad 42 to protect the internal circuit 44 and discharge the electrostatic current. 9 1 H—--1 ^ 1 I- IN! 1 ^ 1 I-I ------ IT «-a--. /-. /!-,» 1 (Please read " Front Note Please fill in this page again for this matter) This paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm). Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, India. 2 9 9 ltwf / 0 05 ^ 04041 _ b77 V. Description of the invention ( g). According to the circuits shown in FIGS. 4A and 4B, please refer to FIGS. 5A to 5E, which are cross-sectional views of the metal-oxide-semiconductor structure of an enhanced electrostatic discharge protection circuit according to an embodiment of the present invention. In this embodiment, only the N-type metal-oxide semiconductor is described as an example, and the formation of the p-type metal-oxide semiconductor can be achieved by the same method. First Embodiment: First, as shown in FIG. 5A, a gate electrode 52 is formed on an element region 51 above a semiconductor substrate 50. The method is, for example, to deposit a polycrystalline silicon layer after the traditional formation of a gate oxide layer, and add photoresist etching to remove a part of the polycrystalline silicon layer and the oxide layer, leaving the structure of the gate electrode 52. The element region 51 here includes a source region 53 and a drain region 54. N-type ion doping is then performed to form a so-called lightly-drained drain region 55 in the source region 53 and the drain region 54 of the semiconductor substrate 50 first. Thereafter, gaps 56 are formed on both sides of the gate electrode 52. Next, please refer to FIG. 5B, cover a central portion above a portion of the drain region 54 with a small mask 57 and perform a high concentration of N-type ion doping to obtain the source region shown in FIG. 5B. 53 与 载 极 区 54。 53 and the drain region 54. The equivalent circuit of this transistor is the transistor N1 and resistor R1 connected in series as shown in Fig. 4A, which are commonly used electrostatic discharge protection circuits. In addition, after the process of FIG. 5A is completed, and then referring to FIG. 5C, except that a small mask 57 is used to cover the central portion above the partial drain region 54 and a small mask M is covered in the same manner. 3 ^ central part, and then perform a high concentration of N_ sub-doping to obtain the fc source region 53 and the drain region 54. This—The equivalent circuit of the transistor is the resistor μ, the transistor μ and the resistor ____ 10 CNS connected in series as shown in the table 4B. Α4 ^ (· 21〇χ 297 ^ ¥) ~ ^ ~~-(Please Read the precautions on the back before filling in the “Smart page”), printed by 2991twf / 005 A7 ^ 〇4G4j_bi ______ of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs (5) copies of the invention description. The resistance obtained in this embodiment is a lightly doped drain resistance formed by a self-alignment method. Second embodiment: After the process shown in FIG. 5A is completed, and referring to FIG. 5D, a small mask 59 is used to cover a portion of the drain region 54 adjacent to the gate electrode 52, and then the height is increased. The N-type ions are doped at a concentration to obtain the source region 53 and the drain region 54 shown in FIG. 5D. The equivalent circuit of this transistor is the transistor N1 and resistor R1 connected in series as shown in Figure 4A, which are commonly used electrostatic discharge protection circuits. As described in the first embodiment, in addition, after the process of FIG. 5A is completed, then referring to FIG. 5E, a photomask 60 is simultaneously overlaid on a portion of the drain region 54 adjacent to the gate 52 at the same time. The source region 53 and the gate electrode 52 are adjacent to each other, and then a high concentration of N-type ions is doped to obtain the source region 53 and the drain region 54 shown in FIG. 5E. The equivalent circuit of this transistor is also the resistor R2, transistor N2 and resistor R3 connected in series as shown in Fig. 4B. The resistance obtained in this embodiment is a lightly doped drain resistance formed by a method of extending the lightly doped drain, without the current-voltage collapse characteristic curve 32 shown in FIG. 3. Occurrence can effectively use the snapback state of the transistor. In the above embodiments, the lightly doped drain transistor has a built-in lightly doped drain resistor, which greatly enhances the electrostatic discharge protection capability of the transistor. Compared with the traditional electrostatic discharge capability, it is at least acceptable. 5 times or more HI I—I 11 ^^^ 1 κ »HH m-trt (Please read the precautions on the back before filling in the {IT page) This paper size is applicable to China National Standard (CNS) A4 (210X297) (%) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 2991twf / 005 A7MM4i________ V. Description of the Invention (γ) A sudden increase in voltage. Therefore, one of the features of the present invention is to provide a gold-oxygen semi-transistor structure, which can evenly disperse the entire gate edge when the electrostatic discharge current flows from the drain to the source evenly, reducing the current pushing effect. The effect of the weak point to take advantage of the snapback state of the transistor. The second feature of the present invention is to use the built-in lightly doped drain resistor in the lightly doped drain transistor to solve the temperature rise caused by the current pushing when the electrostatic discharge is generated by the sudden voltage (Zap). This leads to the problem of component damage and strengthens the ability of electrostatic discharge protection. The third feature of the present invention is that it is not necessary to use a large gap between the contact window and the gate to increase the electrostatic discharge capability, thereby greatly reducing the area of the component. The fourth feature of the present invention is that there is no need to perform so-called electrostatic discharge doping in the source diffusion region and the drain diffusion region with an additional electrostatic discharge mask, thereby reducing the cost and complexity of the process. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. II—I---II--— ^ ― T--I: -——- II * -I (Please read the notes on the back before filling out this page) 12 This paper size applies to Chinese National Standards (CNS) A4 specifications (210X297 mm)