經濟部中央標準局貝工消费合作社印榘 402810 a7 4232twf.doc/008 __B7___ 五、發明说明（I ) 本發明是有關於一種積體電路的製造方法’且特別是 有關於一種電容器的製造方法。 目前爲了滿足縮小結構尺寸的需要’一種在固定面積 的基底上增加其表面積的方法已被提出’此增加表面積的 方法係採用在基底表面形成半球型矽晶粒的方式。以動態 隨機存取記憶體爲例’電容器爲動態隨機存取記億體 (DRAM)藉以儲存訊號的心臟部位，如果電容器所儲存 的電荷愈多，讀出放大器在讀取資料時受雜訊干擾的影響 也將愈小，且再更，新（Refresh)儲存電荷的頻率亦將大大 地降低。故而，在有限的單位面積內增加電容器的面積， 以使整個儲存於電容器內的電荷數量增加，爲改善此一問 題的有效方法。而在基底上形成半球型矽晶粒適足以達成 此目的。 半球型矽晶粒的形成方式可以區分爲兩種。其中的一 種方式係以化學氣相沈積法在晶片的表面上全面性沈積一 層半球型砂晶粒層。而另一種方式則是選擇性地在晶片的 非晶砂(Amorphization)表面上形成一層半球型砂晶粒，由 於此方式所形成之半球型矽晶粒具有選擇性，因此，泛稱 爲選擇性半球型矽晶粒。當半球型矽晶粒應用於電容器， 用以增加下電極之表面積時’採用化學沈積方式形成之半 球型矽晶粒層，必需再經由額外的微影與蝕刻製程，以定 義其圖案。而選擇性半球型矽晶粒則由於具有選擇性之特 性，則不需要額外的微影成像與蝕刻製程定義其圖案，因 此，亦是目前積體電路元件廣泛採用的一種方式。 3 本紙張尺度適用中國國家標準（CNS )八4祝格（210X297公釐) ------ ---------|定，~-------訂------線' ^ -/i 』 * (請先閱讀脅面之注意事項再填寫本頁) 經濟部中央搮率局工消费合作社印製 402810 A7 4232twf.doc/008 B7 五、發明説明（π) 第1圖’係繪示習知一種藉由半球型矽晶粒的形成以 增加電容器之儲存電容量的剖面示意圖。其製造的方法係 以化學氣相沉積法在已形成—層複晶矽層1〇2的基底上， 形成一層半球型矽晶矽晶粒層104,其後，再於基底100 上形成介電層106與另一層複晶矽層1〇8。 由於沉積半球型矽晶粒時，其製程的溫度裕度 (Temperature Window)非常窄。—旦溫度控制不當，所形成之 半球型矽晶粒則會產生彼此相連的現象。因此，在後續於 基底100上形成介電層106時，所形成之介電層106並無 法塡入半球型矽晶粒104彼此之間的空隙110，不但會使 得所能增加的電容値產生限制、亦會使得元件可靠度下 降。 因此’本發明提供一種電容器的製造方法，可以避免 彼此相連之半球型矽晶粒，致使介電層無法完全覆蓋半球型 砂晶粒所造成的可靠度問題。 本發明提出一種電容器的製造方法，其作法係在基底 上形成一層作爲下電極之用的導體層。接著，再於導體層 上形成半球型矽晶粒。其後，以緩衝溶液進行回蝕刻步驟， 以使半球型矽晶粒彼此分離。然後，在基底上再形成一層 介電層，並於此介電層上再形成另一層導體層，以作爲電 容器之上電極。 依照本發明實施例所述，上述之半球型矽晶粒的形成 方法可以以化學氣相沉積法形成，亦可以選擇性半球型矽 晶粒之方法獲致。而上述之緩衝溶液係以去離子水進行稀 4 本紙張尺度適用中國國家榡準（CNS > A4祝格（210X297公釐1 (請先閲讀背面之注意事項再填寫本頁) 訂 線 經濟部中央標率局舅工消費合作社印裝 402810 at 4232twf.doc/008___B7 ___ 五、發明説明（5 ) 釋者，其與去離子水的比例爲重量百分比爲20 : 1，進行 回蝕刻的時間約爲1〇秒至50秒。以本發明之方法可以使 得原本相連的半球型砂晶粒有效的分離。因此，可以使得 後續形成之介電層完全覆蓋於其表面，以有效提昇電容 値，避免習知因半球型矽勒粒彼此相連’而致使介電層無 法完全覆蓋半球型矽晶粒覆蓋所造成的可靠度問題。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例’並配合所附圖式’作詳 細說明如下： 圖式之簡單說明： 第1圖，係繪示習知一種藉由半球型矽晶粒的形成以 增加電容器之儲存電容量的剖面示意圖；以及 第2A圖至第2D圖爲依照本發明實施例一種藉由半球 型矽晶粒的形成以增加電容器之儲存電容量的製造流程的 剖面示意圖。 圖式標記說明： 100、200 :基底 102、108 :複晶矽層 104、204、204a :半球型砍晶粒層 106、206 :介電層 102、202、208 :導體層 1 1 0 :空隙 實施例 本發明實施例中，係以化學氣相沉積法所形成之半球 5 本紙張尺度適用中國國家標準（CNS ) M祝格（2ΐ〇χ297公釐） ---------IR.------訂------線 j ( (請先閲讀脅面之注意事項再填寫本頁) 402810 A7 4232twf.doc/00S B7 五、發明説明（仏） 型矽晶粒作爲說明。然而，在實際的應用上，並不限定於 化學氣相沉積法所形成者，亦可以適用於以選擇性方法所 形成之半球型矽晶粒。 第2A圖至第2D圖爲依照本發明實施例一種藉由半球 型矽晶粒的形成以增加電容器之儲存電容量的製造流程的 剖面示意圖。 首先，請參照第2A圖，在基底200上形成一層導體 層202以作爲電容器下電極之用。基底200包括半導體之 基材以及形成於半導體基材上的場效電晶體、介電層以及 連接電容器下電極至半導體基材的節點接觸窗（NodeSeal of the Bayer Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 402810 a7 4232twf.doc / 008 __B7___ V. Description of the Invention (I) The present invention relates to a method for manufacturing an integrated circuit ', and particularly to a method for manufacturing a capacitor. At present, in order to meet the need for reducing the size of the structure, a method of increasing the surface area of a fixed-area substrate has been proposed. This method of increasing the surface area adopts a method of forming hemispherical silicon crystal grains on the surface of the substrate. Take dynamic random access memory as an example. 'The capacitor is the heart of the dynamic random access memory (DRAM) memory signal. If the capacitor stores more charge, the sense amplifier will be disturbed by noise when reading data. The effect will be smaller, and even more, the frequency of refresh storage charge will be greatly reduced. Therefore, increasing the area of the capacitor within a limited unit area to increase the amount of charge stored in the capacitor as a whole is an effective method to improve this problem. The formation of hemispherical silicon grains on the substrate is adequate for this purpose. There are two ways to form hemispherical silicon grains. One way is to deposit a layer of hemispherical sand grains on the surface of the wafer by chemical vapor deposition. The other method is to selectively form a layer of hemispherical sand grains on the amorphous sand surface of the wafer. Because the hemispherical silicon grains formed by this method are selective, they are generally called selective hemispherical. Silicon die. When hemispherical silicon grains are used in capacitors to increase the surface area of the lower electrode, a hemispherical silicon grain layer formed by chemical deposition must be subjected to additional lithography and etching processes to define its pattern. Selective hemispherical silicon crystals, due to their selective nature, do not require additional lithography imaging and etching processes to define their patterns. Therefore, they are also a widely used method for integrated circuit components. 3 This paper size applies to Chinese National Standard (CNS) 8 4 Zhuge (210X297 mm) ------ --------- | fixed, ~ ------- order --- --- line '^-/ i 』* (Please read the precautions before filling in this page before filling out this page) Printed by the Central Government Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives 402810 A7 4232twf.doc / 008 B7 V. Description of the invention (π (1) FIG. 1 is a schematic cross-sectional view showing a conventional method for increasing the storage capacity of a capacitor through the formation of hemispherical silicon crystal grains. Its manufacturing method is to form a hemispherical silicon crystal silicon crystal grain layer 104 on a substrate having a multi-layered silicon layer 102 formed by a chemical vapor deposition method, and then, a dielectric is formed on the substrate 100. Layer 106 and another polycrystalline silicon layer 108. As hemispherical silicon grains are deposited, the temperature window of the process is very narrow. -Once the temperature is not controlled properly, the formed hemispherical silicon grains will be connected to each other. Therefore, when the dielectric layer 106 is subsequently formed on the substrate 100, the formed dielectric layer 106 cannot penetrate into the space 110 between the hemispherical silicon grains 104, which not only limits the capacitance that can be increased. , Will also reduce component reliability. Therefore, the present invention provides a method for manufacturing a capacitor, which can avoid the reliability problem caused by the hemispherical silicon grains connected to each other, so that the dielectric layer cannot completely cover the hemispherical sand grains. The invention proposes a method for manufacturing a capacitor. The method is to form a conductor layer on the substrate as a lower electrode. Next, hemispherical silicon crystal grains are formed on the conductor layer. Thereafter, an etch-back step is performed with a buffer solution to separate the hemispherical silicon crystal grains from each other. Then, a dielectric layer is formed on the substrate, and another conductive layer is formed on the dielectric layer to serve as an electrode on the capacitor. According to the embodiment of the present invention, the above-mentioned method for forming hemispherical silicon grains can be formed by a chemical vapor deposition method, or can be obtained by a method of selective hemispherical silicon grains. The above buffer solution is diluted with deionized water. This paper size is applicable to Chinese national standards (CNS > A4 Zhuge (210X297 mm1 (please read the precautions on the back before filling this page)) Printed by the Central Standards Bureau, Masonry Consumer Cooperative, 402810 at 4232twf.doc / 008 ___ B7 ___ V. Description of the Invention (5) Explainer, its ratio to deionized water is 20: 1 by weight, and the time for etch back is about 10 seconds to 50 seconds. With the method of the present invention, the originally connected hemispherical sand grains can be effectively separated. Therefore, the subsequently formed dielectric layer can completely cover its surface to effectively increase the capacitance and avoid the conventional knowledge. The reliability problem caused by the inability of the dielectric layer to completely cover the hemispherical silicon grains because the hemispherical silicon lumps are connected to each other. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, The following is a detailed description of a preferred embodiment 'in conjunction with the accompanying drawings' as follows: A brief description of the drawings: Figure 1 shows a conventional method for forming a hemispherical silicon grain by A cross-sectional view of increasing the storage capacity of a capacitor; and FIGS. 2A to 2D are cross-sectional views of a manufacturing process for increasing the storage capacity of a capacitor through the formation of hemispherical silicon grains according to an embodiment of the present invention. Explanation of symbols: 100, 200: substrates 102, 108: polycrystalline silicon layers 104, 204, 204a: hemispherical cleaved grain layers 106, 206: dielectric layers 102, 202, 208: conductor layers 1 1 0: void embodiments In the embodiment of the present invention, 5 hemispheres formed by the chemical vapor deposition method are applied to the Chinese paper standard (CNS) M Zhuge (2ΐ〇χ297 mm) --------- IR.- ----- Order ------ Line j ((Please read the precautions of the flank surface before filling in this page) 402810 A7 4232twf.doc / 00S B7 V. Description of the invention (仏) Type silicon crystals are used as explanation However, in practical applications, it is not limited to those formed by chemical vapor deposition, but can also be applied to hemispherical silicon crystal grains formed by selective methods. Figures 2A to 2D are in accordance with the present invention. Embodiment A method for increasing the storage capacity of a capacitor by the formation of hemispherical silicon grains A schematic cross-sectional view of the manufacturing process. First, referring to FIG. 2A, a conductor layer 202 is formed on the substrate 200 as a capacitor lower electrode. The substrate 200 includes a semiconductor substrate and a field effect transistor formed on the semiconductor substrate. , Dielectric layer, and node contact window connecting the lower electrode of the capacitor to the semiconductor substrate (Node
Contact)，在圖式中並未將其--繪示出來。導體層202 之材質例如爲複晶矽，其形成的方法例如是化學氣相沉積 法。此複晶矽層中具有摻雜，以賦予其導電之特性。摻雜 的形成可以在沉積的同時（In-Situ)形成，或是以離子佈植 的方式形成。 經濟部中央橾準局貝工消费合作社印製 (諳先閲讀矿面之注意事項再填寫本頁) 接著，請繼續參照第2A圖，在導體層202上形成一 層半球型矽晶粒層204。此半球型矽晶粒層204的形成方 法例如是以矽烷（SiH4)爲氣體源，經由低壓化學氣相沉積 法，在攝氏570度至580度之間進行沉積者。較佳的是在 形成半球型矽晶粒層204之後，會再於攝氏7〇〇度至85〇 度之間進行回火者。 其後，請參照第2 B圖，進行半球型矽晶粒層204的 回蝕刻步驟，以使彼此相連的半球型矽晶粒層204予以分 離，而形成如圖所示之半球型矽晶粒層204a。此回蝕刻步 6 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公釐） 經濟部中央標準局貝工消费合作社印製 402810 4232twf.doc/008 發明説明（< 驟例如是以緩衝溶液執行之，較佳的緩衝溶液係以去離子 水進行稀釋者’其與去離子水的比例爲重量百分比爲20 : 1 ’進行回飽刻的時間約爲10秒至50秒。以本發明之方法 可以使得原本相連的半球型矽晶粒2〇4有效的分離，因 此’可以使得後續形成之介電層完全覆蓋於其表面，以有 效提昇電容値’避免習知因半球型矽晶粒彼此相連，而致 使介電層無法完全覆蓋半球型矽晶粒覆蓋所造成的可靠度 問題。 然後’請參照第2C圖，在半球型矽晶粒層204a之表 面上形成一·層介電層206。此介電層2〇6之材質例如是氧 化砂層、氮化矽層/氧化矽層（NO)結構 '氧化矽層/氮化 矽層/氧化矽層（ΟΝΟ)結構或五氧化二鉅（Ta205 )、Pb(Zr， Ti)〇3 ’即PZT '以及（Ba, Sr)Ti03 ’即BST等高介電常數 的材料。 接著’請參照地2D圖，以典型的微影成像與蝕刻技術 定義上述之導體層202與半球型矽晶粒層2(Ma與介電層之 圖案。在介電層206的表面上形成另一層導體層208，此 導體層208之材質例如是複晶矽，其形成的方法例如爲化 學氣相沉積法。而且複晶矽層中具有摻雜，以賦予其導電 之特性。摻雜的形成可以在沉積的同時（In-Situ)形成，或 是以離子佈植的方式形成。 本發明經由一道蝕刻程序，可以使得原本彼此相連的 半球型矽晶粒彼此分離，因此後續形成之介電層可以將複 晶矽層之表面完全地覆蓋，並不會有習知半球型矽晶粒之Contact), which is not shown in the diagram. The material of the conductive layer 202 is, for example, polycrystalline silicon, and a method for forming the conductive layer 202 is, for example, a chemical vapor deposition method. The polycrystalline silicon layer is doped to give it conductivity. The doping can be formed at the same time as the deposition (In-Situ), or by ion implantation. Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative (read the precautions on the mine surface, and then fill out this page). Then, continue to refer to Figure 2A to form a hemispherical silicon grain layer 204 on the conductor layer 202. The method for forming the hemispherical silicon grain layer 204 is, for example, silane (SiH4) as a gas source, and a low pressure chemical vapor deposition method is used to deposit between 570 ° C and 580 ° C. Preferably, after the hemispherical silicon grain layer 204 is formed, tempering is performed at a temperature between 700 ° C and 8500 ° C. Thereafter, referring to FIG. 2B, the etch-back step of the hemispherical silicon grain layer 204 is performed, so that the hemispheric silicon grain layers 204 connected to each other are separated to form a hemispherical silicon grain as shown in the figure Layer 204a. This etch back step 6 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 402810 4232twf.doc / 008 Description of the invention (< For the execution of the solution, the preferred buffer solution is diluted with deionized water. Its ratio to deionized water is 20: 1 by weight. The time for performing the full-saturation process is about 10 seconds to 50 seconds. The method can effectively separate the originally connected hemispherical silicon grains 204, so 'the dielectric layer formed later can completely cover the surface, so as to effectively increase the capacitance' and avoid the conventional hemispherical silicon grains. They are connected to each other, so that the dielectric layer cannot completely cover the hemispherical silicon grains. The reliability problem is caused. Then, please refer to FIG. 2C, forming a layer of dielectric layer on the surface of the hemispherical silicon grain layer 204a. 206. The material of the dielectric layer 206 is, for example, a sand oxide layer, a silicon nitride layer / silicon oxide layer (NO) structure, a silicon oxide layer / silicon nitride layer / silicon oxide layer (ON) structure, or a pentoxide. (Ta205), Pb ( Zr, Ti) 〇3 'that is, PZT' and (Ba, Sr) Ti03 ', which are materials with high dielectric constants such as BST. Then,' Please refer to the 2D map of the ground to define the above-mentioned conductive layer with typical lithography imaging and etching techniques. 202 and a pattern of a hemispherical silicon grain layer 2 (Ma and a dielectric layer. Another conductive layer 208 is formed on the surface of the dielectric layer 206. The material of the conductive layer 208 is, for example, polycrystalline silicon. The method for forming the conductive layer 208 is It is a chemical vapor deposition method. Moreover, the polycrystalline silicon layer has doping to give it conductivity. The doping can be formed at the same time as the deposition (In-Situ) or by ion implantation. The invention can separate the originally connected hemispherical silicon grains from each other through an etching process, so the subsequent formation of the dielectric layer can completely cover the surface of the polycrystalline silicon layer, and there is no conventional hemispherical silicon crystal. Grain
{請先閱讀背面之注意事項再填寫本頁} X. 訂 本紙張尺度適用中國國家標準（CNS ) Μ規格（210X297公釐） 402810 —_ 4232twf.doc/00^ 五、發明説明（4) =所形成之空論法被介輸麵鎖關。因此，本發 方法可以有效地藉由半球型矽晶粒層的形成以增加電 谷器之T存電容値’並能解決習知元件之可靠度問題。此 2 ’由於本發明之方法可以解決半球型矽晶粒彼此相連所 衍生的問g ’因此’本發明可以增加形成半球型矽晶粒之 溫度裕度，降低製程的困難度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍內’當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 飞--^---^丨訂------線' 'Ίβί'..· (請_先閱讀t-面之注意事項再填寫本頁) 經濟部中央橾準局貝工消费合作社印製 8 本紙張尺度逋用中國國家榇準（CNS ) A4祝格（210X297公釐）{Please read the precautions on the back before filling in this page} X. The size of the paper used in the book is applicable to the Chinese National Standard (CNS) M specification (210X297 mm) 402810 —_ 4232twf.doc / 00 ^ 5. Description of the invention (4) = The formed air theory is locked by the media. Therefore, the method of the present invention can effectively increase the T storage capacitance of the valley device by the formation of a hemispherical silicon grain layer and can solve the reliability problem of conventional devices. This 2 'because the method of the present invention can solve the problem caused by the connection of hemispherical silicon crystal grains to each other, therefore,' the present invention can increase the temperature margin for forming hemispherical silicon crystal grains and reduce the difficulty of the process. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. 'Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. Fly-^ --- ^ 丨 Order ------ line '' Ίβί '.. · (Please read the precautions for t-face before filling out this page) Printed 8 paper sizes, using China National Standard (CNS) A4 Zhuge (210X297 mm)