TW401605B - The method of reforming substrate surface and manufacturing the semiconductor device - Google Patents
The method of reforming substrate surface and manufacturing the semiconductor device Download PDFInfo
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- TW401605B TW401605B TW087107422A TW87107422A TW401605B TW 401605 B TW401605 B TW 401605B TW 087107422 A TW087107422 A TW 087107422A TW 87107422 A TW87107422 A TW 87107422A TW 401605 B TW401605 B TW 401605B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
- C23C16/0209—Pretreatment of the material to be coated by heating
- C23C16/0218—Pretreatment of the material to be coated by heating in a reactive atmosphere
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
- C23C16/0227—Pretreatment of the material to be coated by cleaning or etching
- C23C16/0236—Pretreatment of the material to be coated by cleaning or etching by etching with a reactive gas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
- H01L21/31612—Deposition of SiO2 on a silicon body
Description
401605 A7 --------B7 五、發明説明(!) 本發明係有關於在薄膜沈積之前重整基材表面與半 導體元件之製造方法及其裝置,特別是有關於採用 〇3/TEOS(Tetraethyl〇rth〇Silicate)系統反應氣體之化學氣 相沈積法沈積薄膜時之一種在薄膜沈積之前重整基材表 面與半導體元件之製造方法及其裝置。 近來,形成於基層(base layer)的薄膜性質與基層的 表面狀況有相當大的依存關係。 尤其,採用Os/TEOS系統氣體之化學氣相沈積法所 沈積之CVD膜的性質與基層的表面狀況有相當大的依存 關係,譬如’基層表面為親水性(hydrophilic)時,則會明 顯地降低薄膜的成長速率’並使所沈積薄膜呈現多孔性。 因此’會劣化在基層表面所沈積薄膜之流動性 (fluidity)、平坦度、嵌入能力、以及步階覆蓋能力。 而造成不規則沈積者是因為在〇3氣體與TEOS氣 體反應時所產生的中間產物為親水性之聚合物,且業經 證明一薄膜是不能沈積於一具親水性之基層表面上。 為避免上述對於基層表面的依存關係,習知之方法 如 經濟部中央標準局員工消費合作社印紫 (1) 採用諸如nh3、h2等氣體之電漿處理方法; (2) 以低濃度〇3形成絕緣膜做為基層的方法; (3) 以電漿化學氣相沈積法形成絕緣膜做為基層的 方法; (4) 在薄膜沈積前以酒精(alcohol)處理基層表面的 方法。 本紙張尺度適用中國國家標準(CNS ) A4規掊(210X297公浼) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(2 ) 然而’上述方法存在著下列問題: (1) 在採用諸如NH3、H2等氣體之電漿處理方法中, 當欲沈積薄膜於諸如通孔(via_holes)及接觸孔(contact_ holes)等非常狹窄之區域時,無法獲致嵌入及步階覆蓋能 力佳之薄膜。 (2) 以以低濃度A形成絕緣膜做為基層的方法中, 在諸如通孔和接觸孔之非常狹窄區域内,报難形成形成 絕緣膜做為基層。 (3) 再者,在以電漿化學氣相沈積法形成絕緣膜做 為基層的方法中,如同第(2)項所述,在諸如通孔和接觸 孔之非常狹窄區域内,很難形成形成絕緣膜做為基層。 (4) 在薄膜沈積前以酒精處理基層表面的方法中, 在再造之重整效果不佳,此外,亦無法保持基材表面重 整處理後之效果。 因此,本發明之目的,在於提供一種薄膜沈積前重 整基材表面的方法、以及製造半導體元件的方法及其裝 置,可以藉由重整基層表面後保持沈積於基層上薄膜之 流動性、平坦度、嵌入能力、以及步階覆蓋能力等效果, 尤其是當沈積於諸如基層通孔與接觸窗之非常狹窄區域 内時,可提昇所形成薄膜的嵌入能力和步階覆蓋能力。 本發明中,對於基層表面重整,係於一反應室内以 含有鹵素元素之氣體重整基層表面,接著,在經過重整 之基層表面沈積薄膜。 根據本案發明人之實驗,發現與習知技術相較.,當 本紙張尺度適用中國國家CNS ) Λ4規格^x 297^t -------___ (請先閱讀背"面之注命事項再填寫本頁)
、1T A7 A7 經濟部中央標準局員工消費合作社印製 五、發明説明(3 ) ----- 以含有鹵素元素之氣體重整基層表面 重,表面之效果,此外,能提昇沈崎層長: 之他動性、9平坦度、換入能力、以及步階覆蓋能力。 甚至是當沈積於諸如基層通孔與接觸窗之非常狹窄 區域内時’更能提昇所形成薄膜的嵌入能力和步階覆蓋 能力。 再者,當對基層表面施行重整時加熱基層,能提昇 沈積於基層表面上薄膜之流動性、平坦度、巍入能力、 •以及步階覆蓋能力。 特別是當以職或以上之溫度加熱時,更能提昇 上述之效果。 為讓本發明之上述和其他目的、特徵、和優點能更 月』易K ’下文特舉—較佳實施例,並配合所附圖式, 作詳細說明如下: 圖示之簡單說明: .第1A-1C Η係顯示本發明一實施例重整基材表面方 I 法的剖面圖; 第2圖係顯示根據本發明實施例重整基材表面方法 在形成基材熱氧化矽膜後熱氧化矽膜表面狀況之圖 示; 第3Α-3Β圖係顯示根據本發明實施例重整基材表面 方法在重整前基材熱氧化矽膜表面狀況之圖示; 第4A-4F圖係顯示顯示根據本發明實施例重整基材 表面方法基材熱氧化矽膜與一反應氣體sic、的反應圖 ---------- - 6 本紙張尺度適用中國國家標準(CMS ) A4規格(---
五 401605 A7 B7 經濟部中央標準局貝工消費合作社印製 ‘發明説明(4) 示; 第5圖係顯示根據本發明實施例重整基材表面方法 —冷壁系統式CVD薄膜沈積設備的架構示意圖; 第6圖係顯示根據本發明實施例中,設置於半導體 疋件製造③備之重整氣體供應裝置的詳細侧視圖; 第7Α-7Β圖係顯示根據本發明實施例之半導體元件 製造設備一熱壁系統之反應設備的剖面圖; 第8圖係顯示根據本發明實施例經重整處理後一 〇3/teos氧化石夕膜的剖面圖;以及 第9圖係顯示根據比較例未經重整處理之一 CVTEOS氧化石夕膜的剖面圖。 符號說明: 1石夕a日圓,la〜基材熱氧化石夕膜;2〜〇3/TE〇s氧化 石夕膜;61〜反應室;62〜承載台;〇〜氣體供應裝置;64〜 氣體分佈板·’ 65〜釋出設備;66〜重整氣體供應裝置;67〜 薄膜沈積氣體供應裝置;68a' 68b、68c〜導管;的〜選擇 閥;71〜溫度調節器;72〜蒸發容器;73〜流量表;74、75〜 閥。 實施例: 下文便配合所附圖式,對本發明之實施例作詳細說 明。 第5圖係顯示根據本發明實施例重整基材表面方法 -冷壁系統式CVD薄膜沈積設備的架構示意圖,第6圖 係顯示根據本發明實施财,設置於半導體元件製造設 (請先閱讀背面之注意事項再填'寫本頁:> ,I -I . - I S - — I -I - - -.....I · —、玎------線---------------- A7 A7 經濟部中央標準局員工消費合作社印製 __ 五、發明説明(5 ) ~~ 備之重整氣體供應裝置的詳細側視圖。 一承載台62設置於由不鏽鋼製成之一反應室 内,用以承载一矽晶圓1,一加熱器(加熱裝置)嵌入於承 載台62内,用以加熱矽晶圓1。 一導官68a係自一氣體供應裝置63引入〇3/te〇S 氣體(用以沈積薄膜之氣體)及用以重整基層表面之氣體 至反應室61。一氣體分佈板64將〇3/te〇S氣體及用以 重整基層表面之氣體釋出及於承載台62上之石夕晶圓1, 氣體分佈板64設置於反應室61内連接導管68a之另一 端。再者’一釋出設備65連接反應室61,用以調整反 應室61内壓力。 氣體供應裝置63包括一重整氣體供應裝置66、一 薄膜沈積氣體供應裝置67、一導管68b、以及一選擇閥 69(—選擇裝置)。 當重整表面基材時’重整氣體供應裝置66供應重 整氣體至反應室61内,在重整基層表面後,薄膜沈積氣 體供應裝置67供應沈積薄膜之〇3/TE〇s混合氣體。 導管68b和68c分別連接氣體供應裝置66和67, 此外’此等導管68b和68c與導管68a連接延伸至反應 室61内。 此等導管68a、68b和68c等之連接部份設置有選 擇閥69,此閥69選擇流通之路徑,致使自導管68b引 入重整氣體至導管68a、或自導管68c引入薄膜沈積氣 體至導管68a。 (請先閲讀背赶之注意事項再填寫本頁) 訂 dw VI. 本紙張尺度適财 CNS) A4· (21Qx·^^^ 401605 經濟部中央標隼局員工消費合作社¥製 A7 B7 五、發明説明(6) 藉由選擇閥69之選擇,經導管68a選擇性地引入 整氣體或薄膜沈積氣體。 重整氣體供應裝置66之詳細結構即如下述。 重整氣體供應裝置66包括:用以容納諸如sicl4、 SiBi:4、SiF4 4液態源之一蒸發容器72、以及用以調整蒸 發容器72液態源溫度之溫度調節器71,如第6圖所示, 溫度調節器71係設置於蒸發容器72之周圍。再者,重 整氣體供應裝置66包括用以引入ν2、Η〗、Ar等氣體至 蒸發容器72液態源做為載氣之導管68d,而載氣在液態 源以氣泡型態所產生之源氣體(重整氣體),以導管68b V引出瘵發容器72。一流量表73用以量測n2、、Ar ,氣體之流量,一閥74設置於導管68d上,用以施行流 量之調整。閥75設置於導管68b上,亦用以施行流量之 調整。在蒸發容器72處所產生之重整氣體經由導管68b 引入反應室61。 接下來,將詳述本發明實施例基材表面重整方法。 第1A-1C圖係顯示本發明一實施例重整基材表面方 法的剖面圖。 第2圖係顯示根據本發明實施例重整基材表面方法 在形成一基材熱氧化矽膜後熱氧化矽膜表面狀況之圖 不’第3Λ-3Β圖係顯示根據本發明實施例重整基材表面 方法在重整前基材熱氧化矽膜表面狀況之圖示,第4A_4F 圖係顯示顯示根據本發明實施例重整基材表面方法基材 熱氧化矽膜與一反應氣體Sici4的反應圖示。 (請先閱讀背皆之注意"事項再填寫本頁)
释 I 丁 一
s N 公 4i>i605 A7 137 經濟部中央標隼局員工消費合作杜印製 五、發明説明(7 ) ~— 首丨置於—氧化爐内,在氧氣氛下加 “、、至u〇〇〇c,經此處理後’即如第1A圖所示,形成孰 【化石夕膜此熱氧化補1a絲為供沈«膜用之 土層,在第2圖所示基材熱氧化石夕膜1&剛形成後,基材 熱氧化矽膜1 a表面之矽具有懸鍵(dangHng b〇nd)。 此一步驟中,可採用電漿辅助CVD法、低壓cVD 法或類似者。此時,在基材熱氧化石續面與空氣(含 有濕氣)接觸,會有如第3A圖所示Si鍵與〇H形成si_〇H 鍵、或是如第3B圖所示Si鍵與h2〇形成Si_H2〇鍵, 因而使基材熱氧化矽膜la變成親水性。 接著,將第1B圖所示之矽晶圓丨置於反應室61内 之承载台62上,以内建之加熱器加熱至1〇〇0(:或以上的 溫度,然後,自重整氣體供應裝置66將包含sicl4之重 整基材表面氣體供應至反應室61内,而重整基材表面氣 體散佈至形成於矽晶圓1上之基材熱氧化矽膜la表面。 此時,可推斷出有兩種反應會發生於基材熱氧化矽 膜la與基材熱氧化矽膜1&表面上重整基材表面氣體間, 第1B圖所示之符號,’x”表示反應發生之處。 以下所述的反應狀況分為基材熱氧化矽膜la以Si_ OH鍵結者與基材熱氧化矽膜la以si_H2〇鍵結者。 首先’就以Si-OH鍵結者的反應狀況做一說明。 如第4 A圖所示’因經加熱之基材熱氧化石夕膜丨a表 面暴露於SiCl4,Si-OH鍵-OH内-Η與SiCl4 之-Cl產生 HC1。經此反應,基材熱氧化矽膜丨a表面Si鍵結處留存 10 本紙張尺度適用中國國家標準(CNS ) Λ4規輅(210X 297公漦) 請 先 閱 讀 背 面― 之 注 .1 寫 本 頁 . 訂 Μ Μ 經濟部中央標準局員工消費合作社印聚 五、發明説明() ' —--- 8 / 的〇與自S1CI4移除之-C1產生SiCl3。再者,因為基材 熱氧化矽膜la表面溫度為100cC或以上,故所產生的HCl 會自基材熱氧化石夕膜la表面反應區處釋出。
SiCl4+OH->SiCl3+HCl+〇2-基材熱氧化矽膜la表面之氧和si鍵結為Si〇。 接著,如第4B圖所示,所產生之siCl3與基材熱氧 化矽膜la表面之Si_〇反應,而如第4C圖所示以ci取 代〇產生Si〇Cl2* Si-c卜
SiCl3+〇2->SiOCl2+Cl· 藉由使此一反應,由於基材熱氧化矽膜la表面已 画素化’呈現卻水性(hydrophobicity)。 甚者,縱然〇未被C1取代而留存,而如第4D圖 所示表面業經氧化仍呈卻水性。 在基材熱氧化矽膜la表面之矽與H2〇鍵結的情況 下,S1CI4與He如同第4E圖般反應,經由與第4A_4D 圖相同之反應程序,產生siocl2、HC卜以及c卜
SiCl4+H2〇->SiOCl2+2HCl+Cl- 結果’由於基材熱氧化矽膜i a表面之矽與C1鍵結, 故將基材熱氧化矽膜la表面如第4F圖所示予以氯化, 呈現卻水性。 經過上述重整製程後,無須對基材熱氧化矽膜la 表面施行諸如清洗之步驟,而可緊接著施行薄膜沈積之 步驟。因此,在上述重整步驟施行後,停止導入重整氣 體,而自薄膜沈積氣體供應裝置67處供應〇3/TE〇s混 (讀先閱讀背面之注意事項再填寫本頁) 訂 -^ ;y-------- 本紙張尺度適用中國國
JLL (210X297公筇) 經濟部中央標準局員工消費合作社印製 A7 --- ---B7 五、發明説明(9 ) — 合氣體進入反應室61内,做為薄膜沈積氣體。 再者,矽晶圓1經加熱至約為400〇C4更高的温度, 致使〇3得與TEOS反應。 將此條件保持一段時間,即如第丨圖所示,形成一 (VTEOS氧化矽膜2於基材熱氧化矽膜1&上。此〇3/te〇s 氧化矽膜2是A氣體與TE〇s氣體反應而得。 本實施例中,係在將基材熱氧化矽膜la表面重整 呈卻水性後,方以氣體施行薄膜沈積,故能提昇〇3/te〇s 氧化矽膜2之流動性、平坦度、嵌入能力、以及步階覆 蓋能力。 由於採用含鹵素之重整氣體,故特別能維持重整效 果。也就是說,甚或基材表面經施行重整後,置至空氣 下24小時後方進行〇3/TEOS氧化矽膜2之沈積,仍能 維持CVTEOS氧化矽膜2之流動性、平坦度、嵌入能力、 以及步階覆蓋能力。 由於基材熱乳化石夕膜la表面溫度為iOMC或更高, 故可提昇卻水性。此例中,在重整步驟中所產生silan〇1(此 處為Si(OH)4),在1〇〇。(:或更高之溫度下會分解。再者, 若在低於100°C之溫度下對產生之sjian〇i進行分解時, 則會拉長停留於基材熱氧化梦膜1 a表面的時間,使得自 親水性至卻水性之轉換變得較為困難。 下文所舉實例就第8圖做一描述。此例中,將本發 明應用於具有窄溝槽之基層。此外,沈積於未經重整處 理基層上之一比較例示於第9圖。 本紙張尺度適用中國國家標準(CNS ) Λ4规格(210x 297公錄) (請先閱讀背面之注意事項再填离本頁)
經濟部中央標準局員工消費合作社印製 401Θ05 A7 ______J37 五、發明説明(10 ) ~~" 第8圖係顯示根據本發明實施例經重整處理後一 〇3/TEOS氧化賴的剖面圖,第9.圖係顯示根據比較例 未經重整處理之一 〇3/TEOS氧化矽膜的剖面圖。 如第8圖所示,寬度约〇_1μιη、深度約〇·—之溝 槽3係形成於石夕曰曰』! i作為基材之基材熱氧化石夕膜 内。然後,將〇3/TEOS氧化矽膜2形成於基材表面上, 而檢視CVTEOS氧化石夕膜2之嵌入能力和步階覆蓋能力 是否已然提昇。 开乂成基材熱氧化矽膜I a之加熱溫度係設定於 1100oC。 基材表面重整處理之條件係以20oc之液態81(;:14做 為液態源,而將N2氣體以每分鐘5升之速率,以氣泡形 式引入液態Sick内約兩分鐘。再者,對矽晶圓丨之加熱 溫度經設定為250°c。 ^再者,〇3/TEOS氧化矽膜2的薄膜沈積條件,係將 薄膜沈積氣體内包含〇3/TEOS混合氣體的臭氧濃度設定 於所謂〇2内5%〇3之高濃度,對石夕晶圓i之加熱溫度經 設定為400〇c。 由第8圖可知,若根據本發明先對基材表面進行重 整處理則〇3/TEOS氧化矽膜2表面係為平坦化而盔孔 洞之情事。 … 相較之下,若無基材表面未經重整處理,則由第9 圖去氧化石夕膜2表面有孔洞存在,無發獲致平坦之表面。 已如上述,當經重整之基層la具有諸如溝槽3 ---Γ----一. 13 本紙張尺度適财 „ : #_丨 (請先聞讀背16之注意事項再填寫本頁)
、1T 線 B7 401605 五、發明説明(u) 窄下凹區域時,則以含鹵素氣體重整基層表面,則可提 昇膜2形成於溝槽3之嵌入能力和步階覆蓋能力。 本實施例中,雖然用以重整基材表面之反應室與用 以沈積CVTEOS氧化矽膜2之反應室同為反應室61,卻 也可以個別反應室為之。 再者’反應室61可以是單一晶圓處理反應室、亦 或是一爐管式整批(batch)處理設備。 另外’雖然本實施例以一冷壁式系統反應設備為 之,部也可以第7圖所示之熱壁式系統反應設備行之, 第7A圖所示為一水平式爐管,第7B圖所示為一水平式 爐管。 此例中,一加熱器或一紅外線加熱設備設置於鄰i 反應室處,可做為熱壁式系統之加熱裝置。 經濟部中央標準局員工消費合作社印製 此外,雖然可以通式A、表之Sicl4氣體做為重j 氣體,其他諸如以通式Λ、表之Si]u、Μ%、证彳等資 體亦可使用。再者,以通式AHnC1“(n為i、2、3中」 一者)表示之SiHCl3、SiH2Cl2、SiHcl3等也可使用η 可使用通式為ARnX4-n(m為自然數)表示: s (CmH2m+1)Cl3、Si(CmH2m+1)2ci2、Si(CmH2m+1)3Cl 等氣體 再者,上述之通式中,A代表Si、Ge、或Sn之一 X 代表 I、Br、F、^riir·^ _ 次C1中之一,R代表CmH2m+1之- 者。 此外,雖然做為絕緣層之氧化發層係形成於基」 ’亦可使用其他諸如磷♦玻璃(PSG)、财玻璃(BSG) 本紙張纽剌 A7 B7 五、發明説明(12) 硼磷矽玻璃(BPSG)中之一者。當沈積PSG時,以〇3和 TEOS 混合氣體與 TMP(P(OCH3)3)或 tmop(po(och3)3) 做為薄膜沈積氣體;當沈積BSG時,以〇3和TEOS混 合氣體與TMB(B(OCH3)3)做為薄膜沈積氣體;當沈積 BPSG時,以〇3和TEOS混合氣體、與TMB以及TMP 或TMOP做為薄膜沈積氣體。 如上所述,根據本發明係將基層表面置於包含鹵素 元素之基層表面重整重整氣體下用以重整基層表面後, 在經重整之基層表面上以薄膜沈積氣體施行薄膜沈積。 由於採用了含鹵素之基層表面重整氣體,故重整基 層表面之效果得以維持’由於能形成嵌入與步階覆蓋能 力極佳之薄膜於具有諸如溝槽等極窄下凹區域之基層表 面上,故可實現元件之小型化及增加密度。 雖然本發明已以較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之 精神和範圍内,當可作更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 -----:---L--0_ — -- ^ (諳先閱讀背面之注意事項再填寫本頁) 、-=5 經濟部中央標準局貝工消費合作社印製
Claims (1)
- B8 C8 PkO六、申請專利範圍 1. 一種製造半導體元件之裝置,包括 一反應室,用以重整一基層之表面, 沈積一膜於該基層之該表面; 一承載台,S置於該反應室β,用以承載該基層; -重整氣體供應裝置,_供應重整該基層該表面 之氣體通入該反應室,該氣體係選自由AX4、AHCh 、 以及ARnX4_n等所組成之群組(其中,a代表選自由以、 Ge、以及Sn等所組成之群組,X代表選自由卜Br、f、 以及Cl等所組成之群組,R代表中之一者,字 符η為1、2、以及3中之一者,字符m為一自然數); 一薄膜沈積氣體供應裝置,用以供應該薄膜沈積氣 體入該反應室;以及 經濟部中央標準局員工消費合作社印製 經該重整後再 一選擇裝置’用以選擇重整該基層該表面之該氣體 與該薄膜沈積氣體中之一者,通入反應室該内。 2. 如申請專利範圍第1項所述之該製造半導體元件 之裝置’尚包括一加熱裝置用以加熱該基層。 3_如申請專利範圍第2項所述之該製造半導體元件 之裝置’其中,該加熱裝置是建置於該承載台内之—加 熱器’或是設置於緊鄰該反應室處之一加熱器或紅外線 加熱裝置。 4·一種重整基材表面的方法,其中,一基層之表面 係曝置於重整該基層該表面之氣體下,該氣體係選自由 AX4、AHnCl4_n、以及ARnX4.n等所組成之群組(其中,A 代表選自由Si、Ge、以及Sn等所組成之群組,X代表 16 本紙張尺度適用中國國家檩準(CNS ) A4規格(210X297公釐) (請先閎讀背面之注意事項再填寫本頁}2m十1 請專利範圍 j自由I、Br、F、以及Cl等所組成之群組,R代表cmH_ 中之_春 ^ 香’字符η為1、2、以及3中之一者,字符m為 —自然數)。 、5.如申請專利範圍第4項所述之該重整基材表面的 套其中’該基層尚包括一下凹區域。 6·如申請專利範圍第4項所述之該重整基材表面的 、/、中’當該基層該表面曝置於重整該基層該表面 之該氣體下時,對該基層加熱。 7. 如申請專利範圍第6項所述之該重整基材表面的 方法’其中’該基層經加熱至1〇〇〇c或更高的溫度。 8. 如申請專利範圍第6項所述之該重整基材表面的 方法’其中,該入\係選自由SiCl4、Sil4、siBr4、以及 S1F4等所組成之群組。 9·如申請專利範圍第4項所述之該重整基材表面的 方法,其中,該AHnCl4_n係選自由SiHCl3、SiH2Cl2、以 及SiHgCl等所組成之群組。 10. 如申請專利範圍第4項所述之該重整基材表面 的方法’其中,該ARnX“係選自由Si(CmH2m+i)cl3、 Sl(CmH2m+1)2Cl2、以及 Si(CmH2m+1)3Cl 等所組成之群組(其 中,字符m為一自然數)。 11. 一種製造半導體元件之裝置,以申請專利範圍第 4項所述之該重整基材表面的方法,重整一基層之表面 後’以化學氣相沈積法形成一絕緣層於該基層該表面。 12. 如申請專利範圍第U項所述之該製造半導體元 17 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貞工消費合作社印製 . S, Γ B ^^1 ml n^i In ^n· m m m* In nn ml nn ^ J. 1^1 n m· nn m ^n· —^n i m ABCD 六、申請專利範圍 件之裝置,其中,該絕緣層係選自由Si02膜、PSG膜、 BSG膜、以及BPSG膜等所組成之群組。 13.如申請專利範圍第12項所述之該製造半導體元 件之裝置,其中,用以形成該絕緣膜之一薄膜沈積氣體, 是至少包含一 TEOS氣體和一 03氣體之一混合氣體。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐)
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US (1) | US6514884B2 (zh) |
EP (1) | EP0947604B1 (zh) |
JP (1) | JP2975917B2 (zh) |
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