4 1 9〇t\vf. d〇c/〇〇8 — B7 * - .. -..- -....... 五、發明説明（f ) 本發明是有關於一種積體電路的結構及其製造方法， 且特別是有關於一種快閃記憶體（flash memory)的結構及 其製造方法。 非揮發性記憶體(Nonvolatile memory)現係應用在各種 電子元件的使用上，如儲存結構資料、程式資料及其它可 以重複存取的資料。而在可程式非揮發記憶體上，最近更 是強調可電除且可編程唯讀記憶體（EEPROMs)，可電除且 可編程唯讀記憶體是個人電腦中和電子設備所廣泛採用的 記憶體元件。傳統的EEPROM記憶體係以浮置閘（floating gate)電晶體結構來完成，其具有可寫入、可抹除和可保存 數據的優點，但也有存取速度較慢的缺點。然近來發展的 快閃記憶體（fiash memolT)結構之可電除且可編程唯讀記 憶體已具有較快的存取速度。 經濟部中央標準局員工消費合作社印製 (锖先閱讀背面之注意事項再填寫本頁) 第1圖是傳統以淺溝渠隔離結構製造之快閃記憶體記 憶單元的結構剖面圖’傳統快閃記憶體主要由一浮置閘極 電晶體構成，其係先在隔離區之半導體基底100上形 成一淺溝渠隔離結構102，用以隔離出主動區（active area)101。之後，在主動區的基底100上形成有一穿 隨氧化層（tunneHng oxide)104，且一浮置聞（floating gate)106形成於穿隧氧化層1〇4上，而在浮置閘106上形 成一控制閘（control gate)108。其中，在控制閘1〇8與浮置 閘106間形成一介電層11〇。由穿隧氧化層104、浮置閘 106、控制閘108與介電層110的堆疊閘極結構，組成了 一快閃記憶體之閘極結構。 3 本紙張尺度適用中國國家標準（CNS ) A0見格（210:^297公釐） 4 1 90twf.doc/008 經濟部中央標準局員工消費合作社印製 kl B7 五、發明説明（>) 其中當_行熱氧化法(thermal oxidation)形成穿隧氧化 層1〇4時，淺溝渠隔離1〇2之溝渠112的開口頂端角落(t〇p comer)將承爱應力（stress)的作用，而導致在開口頂端角落 處所形成的穿隧氧化層104品質降低，使堆疊閘極的電荷 儲存能力下降’進而使快閃記憶體的使用壽命減短。 此外’脅知的淺溝渠隔離1〇2與基底1〇〇具有平坦的 表面’因此所形成快閃記憶體中的介電層110表面較爲平 坦；換句話說，即介電層u〇與浮置閘1〇6、控制閘1〇8 的接觸面積小。堆疊閘極的耦合率（c〇upHng ratio)係與浮 置鬧與控制閘間的電容値，與浮置閘與基底之間的電容値 有關。浮置閘與控制閘間的電容値愈大，其堆疊閘極的耦 合率也愈高。由此看來’習知所形成的快閃記憶體中，介 電層no與浮置閘106、控制閘108的接觸面積小，如此 浮匱閘與控制閘間的電容値亦小，而使堆疊閘極的耦合率 無法提昇’因此穿隧氧化層104的穿透效率（tunnel efficient) 亦無法增進。 有鑑於此’本發明的目的之一，就是解決習知利用淺 溝渠隔離，.其溝渠的開口頂端角落承受嚴重的應力作用所 造成丨夬閃記丨思體可罪度的問題。如此可提昇穿險氧化層的 品質’增長快閃記憶體的使用壽命。 , 本發明之另一目的，就是在提供一種快閃記憶體的結 構及其製造方法，增加浮置閘與控制閘間的電容値，提昇 堆疊閘極的耦合率（coupling ratio)，故使穿隧氧化靥的穿 透效率（tunnel efficient)亦因此而增進。 本紙張尺度適用中國國家標準（CNS.) Α4ϋ格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁)4 1 9〇t \ vf. D〇c / 〇〇8 — B7 *-.. -..- -....... V. Description of the invention (f) The present invention relates to an integrated circuit A structure and a manufacturing method thereof, and more particularly, to a structure of a flash memory and a manufacturing method thereof. Nonvolatile memory is currently used in the use of various electronic components, such as storing structural data, program data, and other data that can be repeatedly accessed. On programmable non-volatile memory, recently, more emphasis has been placed on removable and programmable read-only memory (EEPROMs). The removable and programmable read-only memory is widely used in personal computers and electronic devices. Body components. The traditional EEPROM memory system is completed by a floating gate transistor structure, which has the advantages of writable, erasable and storable data, but also has the disadvantage of slower access speed. However, the recently developed flash memory (fiash memolT) structure is electrically removable and programmable read-only memory has a faster access speed. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (锖 Please read the precautions on the back before filling this page) Figure 1 is a structural cross-sectional view of a traditional flash memory memory unit manufactured with a shallow trench isolation structure. 'Traditional flash memory The body is mainly composed of a floating gate transistor. A shallow trench isolation structure 102 is first formed on the semiconductor substrate 100 in the isolation area to isolate the active area 101. After that, a tunneling oxide layer 104 is formed on the substrate 100 in the active area, and a floating gate 106 is formed on the tunneling oxide layer 104 and formed on the floating gate 106. A control gate (control gate) 108. Among them, a dielectric layer 11 is formed between the control gate 108 and the floating gate 106. The gate structure of the flash memory is formed by the stacked gate structure of the tunneling oxide layer 104, the floating gate 106, the control gate 108 and the dielectric layer 110. 3 This paper size applies the Chinese National Standard (CNS) A0, see the standard (210: ^ 297 mm) 4 1 90twf.doc / 008 Kl B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (>) where When the thermal oxidation method is used to form the tunneling oxide layer 104, the shallow top trench isolation top corner (t0p comer) of the trench 112 will bear the effect of love, and As a result, the quality of the tunneling oxide layer 104 formed at the top corners of the openings is reduced, and the charge storage capacity of the stacked gates is reduced, thereby reducing the service life of the flash memory. In addition, the known shallow trench isolation 102 and the substrate 100 have a flat surface, so the surface of the dielectric layer 110 in the flash memory formed is relatively flat; in other words, the dielectric layer u and the The contact area of floating gate 106 and control gate 108 is small. The coupling gate coupling ratio (coupHng ratio) is related to the capacitance 値 between the floating gate and the control gate, and is related to the capacitance 値 between the floating gate and the substrate. The larger the capacitance 値 between the floating gate and the control gate, the higher the coupling rate of its stacked gates. From this point of view, in the flash memory formed by the conventional knowledge, the contact area between the dielectric layer no and the floating gate 106 and the control gate 108 is small, so that the capacitance between the floating gate and the control gate is also small, so The coupling rate of the stacked gates cannot be improved, so the tunnel efficiency of the tunneling oxide layer 104 cannot be improved. In view of this, one of the objects of the present invention is to solve the problem of susceptibility caused by severe stress caused by the severe stress on the top corners of the openings of trenches. This can improve the quality of the puncture-resistant oxide layer 'and increase the life of the flash memory. Another object of the present invention is to provide a flash memory structure and a manufacturing method thereof, which increase the capacitance 增加 between the floating gate and the control gate, and improve the coupling ratio of the stacked gates. As a result, the tunnel efficiency of thorium oxide is improved. This paper size applies to the Chinese National Standard (CNS.) Α4ϋ 格 (210X297 mm) (Please read the precautions on the back before filling this page)
經濟部中央標準局員工消費合作社印製 4 1 90twl'.doc/008 A 7 -----一 B7 "·· 五、發明説明（、） ' ~—--一 爲達上述之目的，本發明提供一種快閃記憶體的製造 方法，在半導體基底上依序形成墊氧化物層與圖案化之罩 幕層。接著在罩幕層側壁形成間隙壁，之後再以罩幕餍與 間隙壁爲罩幕，在基底中形成溝渠。續在基底上形成絕緣 層’去除罩幕層上之部分絕緣層而形成包括間矽壁的τ字 形溝渠隔離結構，暴露出罩幕層，其中部份T字形溝渠隔 離結構延伸至基底上。接著去除罩幕層與罩幕層下方之墊 氧化層，並在基底上形成穿隧氧化物層。之後在該穿隧氧 化物層上形成定義之第一導電層，作爲浮置閘，續在浮置 閘上形成介電層，在介電層上形成定義之第二導電層，作 爲控制閘，完成快閃記憶體堆疊閘極的製作。 此外，本發明提供一種快閃記憶體之結構，此結構包 括：提供一半導體基底，此基底上包括隔離區與主動區。 T字形淺溝渠隔離結構，位於隔離區之基底中，其中部份 T字形淺溝渠隔離結構延伸至基底上。穿隧氧化物層’位 於主動區上。浮置閘，位於穿隧氧化物層上且部份浮置閘 位在T字形淺溝渠隔離結構上。介電層’位在浮置閘上。 控制閘，位在介電層上。如此藉由τ字形淺溝渠隔離結構 增加介電層與浮置閘、控制閘的接觸面積’使得浮置閘與 控制閘之間的電容値變大’使堆疊閘極的耦合率（coupling ratio)得以增加。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式’作詳 細說明如下： 5 I -I-^-1¾------IT------一 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4蜾格（210X297公釐） A7 B7 4I90t\vf.doc/008 五、發明説明（t//) 圖式之簡單說明： 第1圖係顯示習知一種快閃記憶體之結構剖面圖； 第2A-2F圖係繪示根據本發明較佳實施例快閃記憶體 之製造流程剖面圖； 圖式之標記說明： 100、 200 :基底 101、 209 :主動區 102、 210a :淺溝渠隔離結構 103、 207 :隔離區 104、 212 :穿隧氧化物層 106、214 :浮置閘 108、218 :控制閘 110、216 :介電層 112、208 :溝渠 202 :墊氧化物層 204 :罩幕層 206、210 :絕緣層 206a :間隙壁 211 : T字形淺溝渠隔離結構 實施例 第2A-2F圖所示，爲本發明一較佳實施例快閃記憶體 之製造流程圖。 請參照第2A圖’首先提供一半導體基底.200 ’在基 底200上形成一墊氧化物層（pad oxide layer)202與一罩幕 6 本紙張尺度適用中國國家標準（CNS ) Α4祝格（210X297公整） ! , Θ—I— (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 1 90twl'.doc / 008 A 7 ----- 一 B7 " ·· V. Invention Description (,) '~ ----To achieve the above purpose, The invention provides a method for manufacturing a flash memory, in which a pad oxide layer and a patterned mask layer are sequentially formed on a semiconductor substrate. Next, a gap wall is formed on the side wall of the mask layer, and then a trench is formed in the substrate by using the mask 餍 and the gap wall as a mask. Continue forming an insulating layer on the substrate to remove a part of the insulating layer on the mask layer to form a τ-shaped trench isolation structure including a silicon wall, exposing the mask layer, and a part of the T-shaped trench isolation structure extends to the substrate. Then, the mask layer and the pad oxide layer under the mask layer are removed, and a tunneling oxide layer is formed on the substrate. Then a defined first conductive layer is formed on the tunneling oxide layer as a floating gate, a dielectric layer is continuously formed on the floating gate, and a defined second conductive layer is formed on the dielectric layer as a control gate. Complete the production of flash memory stacked gate. In addition, the present invention provides a structure of a flash memory. The structure includes: providing a semiconductor substrate including an isolation region and an active region on the substrate. The T-shaped shallow trench isolation structure is located in the base of the isolation area, and some of the T-shaped shallow trench isolation structure extends to the base. The tunneling oxide layer 'is located on the active region. A floating gate is located on the tunneling oxide layer and part of the floating gate is located on the T-shaped shallow trench isolation structure. The dielectric layer is located on the floating gate. The control gate is located on the dielectric layer. In this way, the contact area between the dielectric layer and the floating gate and the control gate is increased by the τ-shaped shallow trench isolation structure, so that the capacitance 値 between the floating gate and the control gate becomes larger, and the coupling ratio of the stacked gates is increased. To increase. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail in conjunction with the accompanying drawings' as follows: 5 I -I-^-1¾- ----- IT ------ One (Please read the notes on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) A4 grid (210X297 mm) A7 B7 4I90t \ vf. doc / 008 V. Brief description of the invention (t //) diagrams: Fig. 1 is a sectional view showing the structure of a conventional flash memory; Figs. 2A-2F are diagrams showing preferred embodiments according to the present invention Flash memory manufacturing process cross-sectional view; Symbols of the drawings: 100, 200: substrate 101, 209: active area 102, 210a: shallow trench isolation structure 103, 207: isolation area 104, 212: tunneling oxide layer 106, 214: Floating gates 108, 218: Control gates 110, 216: Dielectric layers 112, 208: Ditch 202: Pad oxide layer 204: Cover layer 206, 210: Insulating layer 206a: Spacer 211: T-shaped Figures 2A-2F of an embodiment of a shallow trench isolation structure are shown in a flowchart of a flash memory manufacturing process according to a preferred embodiment of the present invention. Please refer to Figure 2A, 'First provide a semiconductor substrate. 200' on the substrate 200 to form a pad oxide layer 202 and a mask 6 This paper size applies Chinese National Standard (CNS) Α4 Zhuge (210X297 Round)!, Θ—I— (Please read the notes on the back before filling this page)
、1T 經濟部中央標準局員工消費合作社印製 4 I90t\vf.doc/008 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（ 層（mask layer) ’其中墊氧化物層202例如以熱氧化法 (thermal oxidation)形成，而罩幕層例如以低壓化學氣相沉 積法（low pressure chemical vapor deposition,LPCVD)在塾 氧化物層2〇2上形成一氮化矽層。接著，以一光阻（未顯 示)進行微影蝕刻製程，定義罩幕層，而形成如第2A圖所 示之罩幕層2〇4。然後，將光阻去除。之後，在基底200 上形成一絕緣層206覆蓋罩幕層204,絕緣層例如爲氧化 物層。絕緣層206的形成，例如以常壓化學氣相沉積法 (atmospheric pressure CVD, APCVD)所形成。 請參照第2B圖，接著，回蝕刻絕緣層206，例如以 罩幕層204作爲一鈾刻終止層(st〇p layer)，或是以時間模 式(time control mode)控制回蝕刻絕緣層206的時間，使得 絕緣層206在罩幕層204的側壁上形成一間隙壁206a。 請參照第2C圖，隨後，以罩幕層206與間隙壁206a 爲罩幕’較佳以乾触刻法（dry etching)，例如包括Cl2、HC12 與SiCl4爲主要氣體來源的電漿，對基底200與墊氧化物 層2〇2進行蝕刻，而在基底200中形成溝渠（trench)208。 仍請參照第2C圖，接著，在基底200上形成另一絕 緣層210 ’絕緣層210覆蓋罩幕層204與間隙壁206a，且 塡滿溝渠208。絕緣層210的形成，例如以常壓化學氣相 沉積法（atmospheric pressure CVD, APCVD)或 LPCVD 在基 底2〇0沉積一 TEOS-氧化物層，之後，再接受高溫密化 (densify)的步驟，使TEOS-氧化物層較爲緻密。絕緣層210 的形成’亦可以加強式電漿化學氣相沉積法（plasma Q—ΐτ#-----------.— (請先聞讀背面之注意事項再填寫本買) :11T Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 I90t \ vf.doc / 008 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (mask layer) where the oxide layer 202 is for example The silicon oxide layer is formed by thermal oxidation, and the mask layer is formed, for example, by a low pressure chemical vapor deposition (LPCVD) method, to form a silicon nitride layer on the hafnium oxide layer 202. Then, A photoresist (not shown) is subjected to a lithographic etching process to define a mask layer to form a mask layer 204 as shown in FIG. 2A. Then, the photoresist is removed. Then, an insulation is formed on the substrate 200. The layer 206 covers the mask layer 204, and the insulating layer is, for example, an oxide layer. The insulating layer 206 is formed, for example, by atmospheric pressure CVD (APCVD). Please refer to FIG. 2B, and then, back The insulating layer 206 is etched, for example, the mask layer 204 is used as a uranium stop layer, or the time for etching back the insulating layer 206 is controlled in a time control mode, so that the insulating layer 206 is on the mask. Side wall of layer 204 A gap wall 206a is formed. Please refer to FIG. 2C, and then use the mask layer 206 and the gap wall 206a as a mask 'preferably dry etching, for example, including Cl2, HC12 and SiCl4 as the main gas source The plasma is used to etch the substrate 200 and the pad oxide layer 202, and a trench 208 is formed in the substrate 200. Still referring to FIG. 2C, another insulating layer 210 is formed on the substrate 200 ' The insulating layer 210 covers the mask layer 204 and the gap wall 206a, and fills the trench 208. The insulating layer 210 is formed, for example, by atmospheric pressure CVD (APCVD) or LPCVD on a substrate 200. The TEOS-oxide layer is then subjected to a densify step to make the TEOS-oxide layer denser. The formation of the insulating layer 210 can also be enhanced by plasma CVD. ΐτ # -----------.— (Please read the notes on the back before filling in this purchase): 1
本紙張尺度適财S目家檩) Α峨格（2“公酱）- 4190t\vf.doc/008 ___________B7 五、發明説明（6 ) enhanced CVD，PECVD)進行，而在基底200上形成一結構 較爲緊密的氧化物層。 請參照第2D圖，之後，以化學機械硏磨法（chemical mechanical polish，CMP)硏磨第2C圖中之絕緣層210，以 罩幕層2〇4爲終止層，去除罩幕層204上之絕緣層21〇。 續再去除罩幕層20§與墊氧化物層2〇2，則塡入溝渠2〇8 的絕緣層210在經硏磨後，形成了包括間隙壁206a與淺 溝渠隔離210a之T字型淺溝渠隔離結構211，如第2D圖 所示。T字型淺溝渠隔離結構211定義出快閃記憶體之主 動區域（active area)209與隔離區207。在罩幕層206以氮 化矽爲材質時，去除罩幕層206的步驟例如以包括熱磷酸 的濕蝕刻法(wet etching)進行。而墊氧化物層202的去除 步驟則例如以氫氟酸（hydrofluoric acid)與氟化氨 (ammonium fluoride)的混合液作爲倉虫刻液的濕倉虫亥1J法進 行。 經濟部中央標準局員工消費合作社印製 I (請先閲讀背面之注意事項再填寫本頁) 此T字型淺溝渠隔離結構211之高度Η約爲1000_2〇00 埃(Angstrom)，較佳爲1500埃。Τ字型淺溝渠隔離結構211 覆蓋住溝渠208的頂端角落（top corner) ’在後續形成穿遂 氧化層(tunneling oxide layer)時’因受到T字型淺溝渠隔 離結構211的保護，使後續形成的穿遂氧化層不會遭受應 力（stress)的作用，如此便能確保後續形成的穿遂氧化層品 質。因此穿遂氧化層品質得以提高’而元件使用壽命增長’ 儲存電荷能力下降問題亦獲得解決。 接著，請參照第2E圖’在暴露出的基底表面上形成 8 本紙張尺度適用中國國家標準（CNS ) A4祝格（210 X 297公酱） 4 1 90twr.d〇c/008 A7 -----B7 五、發明説明Π ) 一穿隧氧化物層212，以供電子進出浮置閘之用，例如以 熱氧化法形成。接著，在基底200上形成一導電層，例如 爲摻有雜質的複晶矽層。導電層厚度約爲800-2500埃， 較佳約爲1500埃。再定義導電層，而形成如第2E圖所示 之導電層214，覆蓋住穿隧氧化物層220與部分T字型淺 溝渠隔離結構211，而作爲快閃記憶體之一浮置閘（floating gate)。 請參照第2F圖，在基底200上形成一介電層216，例 如爲氧化物-氮化物-氧化物層(ΟΝΟ)。ΟΝΟ層216的等效 厚度約爲120-300埃之間，較佳的ΟΝΟ層等效厚度約爲160 埃。亦即ΟΝΟ層216之k値（介電常數）相當於厚度約 12〇_3〇〇埃氧化層之k値。在此步驟中，因形成T字形的 淺溝渠隔離結構211，將部份作爲浮置閘的導電層214高 度往上提昇，而使介電層216與導電層214、後續形成的 控制閘的接觸面積增加，進而使浮置閘與後續形成之控制 閘的電容値增加，如此可提昇快閃記憶體之堆疊閛極的耦 合率（coupling ratio)，而穿透效率亦因此而增進。 仍請參照第2F圖，之後，在介電層216上再形成一 導電層218，例如爲摻有雜質的複晶矽層。導電層218作 爲快閃記憶體之一控制閘。至此，完成快閃記憶體包括有 浮置閘218，介電層216與控制閘2U之一堆疊閘極結構。 本發明利用T形的淺溝渠隔離結構的形成，將部份作 爲浮置閘的導電層高度往上提昇，使介電層與浮置閘、後 續形成的控制閘的接觸面積增加，使得浮置閘與控制閘之 9 (請先閱讀背面之注意事項再填寫本頁) L--u__------IT------ 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4祝格（210X297公釐） 1 9〇tvvf.doc/008 A7 B7 五、發明説明u ) 間的電容値增大，進而使堆疊閘極的耦合率（coupling ratio) 增加，故穿透效率亦因此而增進。 此外，本發明以T形的淺溝渠隔離結構將所形成溝渠 的頂端角落覆蓋住，使在以熱氧化法形成穿遂氧化層時， 因受到T字型淺溝渠隔離結構的保護，使頂端角落不會遭 受應力的作用，確保了穿遂氧化層的品質。因此儲存電荷 能力下降問題獲得解決，進而使元件使用壽命增長。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本育) ---..--^3 裝------訂------ΐιν---- 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家榇準（CNS ) A4規格（210X297公釐）The paper scale is suitable for wealth and money. Α 格 （2 “公 酱） -4190t \ vf.doc / 008 ___________B7 V. Description of the invention (6) Enhanced CVD (PECVD) is performed, and a structure is formed on the substrate 200 A relatively tight oxide layer. Please refer to Figure 2D, and then use chemical mechanical polish (CMP) to polish the insulating layer 210 in Figure 2C, and use the mask layer 204 as the termination layer. , Remove the insulating layer 21 on the mask layer 204. Continue to remove the mask layer 20§ and the pad oxide layer 202, and then after the honing, the insulating layer 210 in the trench 208 is formed. The T-shaped shallow trench isolation structure 211 with the partition wall 206a and the shallow trench isolation 210a is shown in Figure 2D. The T-shaped shallow trench isolation structure 211 defines the active area 209 and the isolation area of the flash memory. 207. When the mask layer 206 is made of silicon nitride, the step of removing the mask layer 206 is performed by, for example, wet etching including hot phosphoric acid. The step of removing the pad oxide layer 202 is, for example, hydrogen. A mixture of hydrofluoric acid and ammonium fluoride is used as a worm The wet wet worm 1J method of liquid is printed. I printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). The height of this T-shaped shallow trench isolation structure 211 is about 1000_2. 00 Angstroms, preferably 1500 Angstroms. The T-shaped shallow trench isolation structure 211 covers the top corners of the trenches 208 'during the subsequent formation of a tunneling oxide layer' due to the T-shape The protection of the shallow trench isolation structure 211 prevents the subsequent formation of the tunneling oxide layer from being stressed, so as to ensure the quality of the subsequent tunneling oxide layer. Therefore, the quality of the tunneling oxide layer is improved. Increasing the service life of components 'The problem of reduced storage charge capacity was also solved. Then, please refer to Figure 2E' to form 8 paper sizes on the exposed substrate surface. This paper size is applicable to Chinese National Standard (CNS) A4 Zhuge (210 X 297 male sauce) ) 4 1 90twr.d0c / 008 A7 ----- B7 V. Description of the invention Π) A tunneling oxide layer 212 is used for the entrance and exit of the floating gate by the electron donor, for example, it is formed by the thermal oxidation method. Then, At the base A conductive layer is formed on 200, such as a polycrystalline silicon layer doped with impurities. The thickness of the conductive layer is about 800-2500 angstroms, preferably about 1500 angstroms. The conductive layer is further defined to form a conductive layer as shown in FIG. 2E. The layer 214 covers the tunneling oxide layer 220 and a part of the T-shaped shallow trench isolation structure 211 and serves as a floating gate as one of the flash memories. Referring to FIG. 2F, a dielectric layer 216 is formed on the substrate 200, such as an oxide-nitride-oxide layer (ONO). The equivalent thickness of the ONO layer 216 is between approximately 120 and 300 angstroms, and the equivalent thickness of the preferred ONO layer is approximately 160 angstroms. That is, the k 値 (dielectric constant) of the ONO layer 216 is equivalent to the k 値 of the oxide layer having a thickness of about 120-30 angstroms. In this step, the T-shaped shallow trench isolation structure 211 is formed, and a portion of the conductive layer 214 serving as a floating gate is raised upward, so that the dielectric layer 216 is in contact with the conductive layer 214 and the control gate formed subsequently The increase of the area further increases the capacitance of the floating gate and the subsequent control gate. This can increase the coupling ratio of the flash memory's stacking pole, and the penetration efficiency can be improved accordingly. Still referring to FIG. 2F, a conductive layer 218 is formed on the dielectric layer 216, such as a polycrystalline silicon layer doped with impurities. The conductive layer 218 functions as a control gate of the flash memory. So far, the completed flash memory includes a floating gate structure including a floating gate 218, a dielectric layer 216, and a control gate 2U. The present invention utilizes the formation of a T-shaped shallow trench isolation structure to raise the height of a part of the conductive layer as a floating gate to increase the contact area between the dielectric layer and the floating gate and the control gate formed subsequently, making the floating Gates and Control Gates 9 (Please read the precautions on the back before filling out this page) L--u __------ IT ------ Printed on this paper by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Chinese National Standard (CNS) A4 Zhuge (210X297 mm) 1 90tvvf.doc / 008 A7 B7 V. Description of the invention u) The capacitance 値 increases, which in turn increases the coupling ratio of the stacked gates (coupling ratio) Therefore, the penetration efficiency is also improved. In addition, the present invention covers the top corners of the formed trench with a T-shaped shallow trench isolation structure, so that when the tunnel oxide layer is formed by the thermal oxidation method, the top corners are protected by the T-shaped shallow trench isolation structure. Will not suffer the effect of stress, ensuring the quality of the tunnel oxide layer. Therefore, the problem of reducing the stored charge capacity is solved, and the service life of the component is increased. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling in this education) ---..-- ^ 3 Pack -------- Order ------ ΐιν ---- Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The paper size of the paper is applicable to China National Standard (CNS) A4 (210X297 mm)