TW399250B - A planarization method for the inter-polysilicon layer of semiconductor structure - Google Patents

A planarization method for the inter-polysilicon layer of semiconductor structure Download PDF

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TW399250B
TW399250B TW86114325A TW86114325A TW399250B TW 399250 B TW399250 B TW 399250B TW 86114325 A TW86114325 A TW 86114325A TW 86114325 A TW86114325 A TW 86114325A TW 399250 B TW399250 B TW 399250B
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Taiwan
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glass layer
layer
undoped
silica glass
spin
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TW86114325A
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Chinese (zh)
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Liang-Ji Yau
Jung-Ru Li
Yuan-Feng Chen
Wei-Ruei Lin
You-Luen Du
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Vanguard Int Semiconduct Corp
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Abstract

This is a planarization method for inter-polysilicon layer of semiconductor structure. Firstly, a undoped silicon glass layer is formed on polysilicon area of semiconductor device, which is made for inter-polysilicon layer. Then, a SOG layer is spin-coated above the undoped non-dopant silicon glass. Finally, the SOG layer is etched back. Thus, an inter-polysilicon layer of semiconductor structure having high planarity is formed.

Description

經濟部中央揉準局男工消費合作社印製 A7 _________ B7_ 五、發明説明() 5-1發明領域: 本發明係有關於一種平坦化製裎,特别是有關於 一種使用無掺雜梦玻球層,以平坦化介多晶發(jnterpo丨y) 層之方法。 5·2發明背景: 使用於製造大型積體電路(VLSI)之矽晶片之表 面原本是平坦的’然而’經過許多之製程以後(例如成長.、 沈積各種絶緣或導電層 >,則會形成不平坦之晶片表面。 例如’金屬氧化半導體(MOS)電晶體之閘極厚度只有 100-250埃’而場氧化區則厚達10000埃以上。此不平坦 現象導致了許多的問題。首先,不平坦表面使得晻梯覆蓋 (step coverage)不良,並因而導致導線澌裂開路。再者, 不平坦現象使得於微影製程當中,無法適當的將圈案轉印 至晶片上。 特别的是,爲了降低最小製程尺寸,微影技術趨 向於使用短波長之光源,例如深紫外線(Deep Ultraviolet, DU V)。不幸的是,波長的減少使得決定非平坦晶片很重 要參數之一的東焦深度(Depth of Focus, D0F)也跟著減 少》囡而,用以製造電路之微影步骒次數需要随之增加, 因而增長了製造所需時間及增加費用成本。 本紙張尺度通用中國國家梯準(CNS > Α4规格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央揉準局貝工消费合作社印製 A7 _____B7_ 五、發明説明() 根據上面所述,因此平坦化技術變得更加重要。 使用臭氡-四乙基矽酸里(TEOS)或低壓四乙基矽酸鹽方 法所沈猜之硼磷矽玻璃(BPSG)通常被用來作爲介多晶矽 氧化(interpolyoxide,IPO>層,用以平坦化介於多晶梦之 間的半導體層。不幸的是,此硼磷矽玻璃通常會產生自摻 雜現象(autodoping effect),亦即用嶙矽玻璃層内的硼離 子會擴散至其底下的多晶矽層内,因而破埭了其濃度分 佈。再者,用以密集化(densify)此硼磷《夕玻璃之溫度通 常很高(约大於850 ·〇),S而浪费了製程成本。 5·3發明目的及概迷: 鑒於上述之發明背景中,傳統的平坦化方法所產 生的諸多缺點,本發明的主要目的在提供一種平坦化介多 晶矽《interpoly)層之方法。根據本發明其中一實施例,首 先,形成一無摻雜矽玻璃層於半導體基板上之多晶矽區 域,其中無摻雜矽玻璃層係以氡化反應臭氧-四乙基矽酸 鹽(TE0S)而形成,且無摻雜矽玻瑀層係作爲介多晶矽 層β接著,密集化此無摻雜矽玻璃層,再形成一旋塗玻球 層於無摻雜矽玻璃層上。最後,回蝕旋塗玻璃層,因而平 坦化具有介多晶矽層之半導體結構。 在本發明另一實施例中,首先,形成一無掺雜矽 玻瑞廣於半導體基板上之多晶發區域,其中此無掺雜_^玻 lr_-裝11------r,. (請先閲讀背面之注意事項再填寫本頁)Printed by A7 ________ B7_ of the Men ’s Consumer Cooperatives of the Central Bureau of the Ministry of Economic Affairs. 5. Description of the invention (5-1) Field of the invention: The present invention relates to a flattened plutonium, especially to the use of non-doped dream glass balls. Layer to planarize the jnterpoy layer. 5.2 Background of the Invention: The surface of a silicon wafer used to make a large-scale integrated circuit (VLSI) was originally flat. However, after many processes (such as growth, deposition of various insulating or conductive layers), it will form Uneven wafer surface. For example, the gate thickness of a metal oxide semiconductor (MOS) transistor is only 100-250 angstroms and the field oxide region is more than 10,000 angstroms. This unevenness causes many problems. First, The flat surface makes poor step coverage and leads to cracks and open wires. In addition, the unevenness makes it impossible to properly transfer the circle to the wafer during the lithography process. In particular, In order to reduce the minimum process size, lithography technology tends to use light sources with short wavelengths, such as Deep Ultraviolet (DU V). Unfortunately, the reduction in wavelength makes the east focal depth (one of the most important parameters for non-flat wafers) ( Depth of Focus (D0F) has also been reduced ", and the number of lithography steps used to manufacture circuits needs to increase accordingly, thus increasing the time required for manufacturing and increasing The cost of this paper is the same as the standard of China National Standard (CNS > Α4 (210X297mm) (please read the precautions on the back before filling this page). Order printed by the Central Labor Bureau of the Ministry of Economic Affairs and printed by Aigong Consumer Cooperative. _____B7_ 5. Description of the invention () According to the above, the flattening technology becomes more important. The borophosphosilicate that was conjectured using the odor-tetraethylsilicic acid (TEOS) or low-pressure tetraethylsilicate method. Glass (BPSG) is often used as an interpolyoxide (IPO) layer to planarize semiconductor layers between polycrystalline dreams. Unfortunately, this borophosphosilicate glass usually produces self-doping (Autodoping effect), that is, the boron ions in the silica glass layer will diffuse into the polycrystalline silicon layer underneath, thereby breaking its concentration distribution. Furthermore, it is used to densify this The temperature is usually very high (approximately greater than 850 · 0), and S is a waste of process costs. 5.3 Objectives of the invention and its fans: In view of the above-mentioned background of the invention, the conventional planarization method has many disadvantages, the present invention The main purpose is to provide a method for planarizing an interpoly layer. According to one embodiment of the present invention, first, an undoped silica glass layer is formed on a polycrystalline silicon region on a semiconductor substrate, and the undoped silica glass layer is formed. It is formed by tritiation of ozone-tetraethyl silicate (TE0S), and the undoped silica glass layer is used as the polycrystalline silicon layer β. Then, the undoped silica glass layer is densely formed, and then a spin coating is formed. The glass ball layer is on the undoped silicon glass layer. Finally, the spin-on glass layer is etched back, thereby planarizing the semiconductor structure with the polycrystalline silicon layer. In another embodiment of the present invention, first, an undoped sapphire polycrystalline region is formed on a semiconductor substrate, where the undoped _ ^ glass lr_-pack 11 ------ r, . (Please read the notes on the back before filling this page)

經濟部t央棣率局貝工消費合作社印製 A7 _____B7 _ _五、發明説明() 璃層係以氧化反應臭氧-四乙基矽酸里(丁E0S)而形成,且 無摻雜矽玻璃層係作爲介多晶矽層。接著,形成一旋塗玻 璃層於無摻雜矽玻璃層上,並密集化無摻雜矽玻璃層。最 後,回蝕旋塗玻璃層,因而平坦化具有介多晶矽層之半導 雄結構。 5_4圈式簡單説明: 第一圈顯示根據本發明其中一實施例之剖面圖。 第二圈類示本發明最後形成之結構刦面圈。 5-5發明詳説明: 第一圈薄示矽基板10之剖面圖,在其上以傳统 方法形成場氧化區(FOX)12及多晶矽閘極區14Α。在此圈 式中,爲了圈式的簡化,因此源極及汲極並未畫出。在場 氧化區12上面形成另一多晶矽區域14B,用以連接至字 線(word line)。 以低壓四乙基矽酸麝(LPTE0S)或電漿加強化學 氣梱沈積法(PECVD),選擇性的形成氮氧化物層 (oxynitride,SiOxNy) 17於基板10、場氧化區12及多晶 矽區域14A和14B表面上,以提供一隔離濕氣層。 本紙張尺度適用中國國家梂準(CNS ) A4规格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁}Printed by the Ministry of Economic Affairs of the Central Government Bureau of Shellfish Consumer Cooperatives A7 _____B7 _ _V. Description of the invention () The glass layer is formed by the oxidation reaction of ozone-tetraethylsilicic acid (butyl E0S), and is doped without silica glass. The layer system acts as a polycrystalline silicon layer. Next, a spin-coated glass layer is formed on the undoped silica glass layer, and the undoped silica glass layer is densely formed. Finally, the spin-on-glass layer is etched back, thereby planarizing the semiconductor structure with the polycrystalline silicon layer. Brief description of the 5_4 circle type: The first circle shows a cross-sectional view of one embodiment of the present invention. The second type of ring shows the structure of the present invention. 5-5 Detailed description of the invention: The first circle is a thin cross-sectional view of a silicon substrate 10 on which field oxide regions (FOX) 12 and polycrystalline silicon gate regions 14A are formed by a conventional method. In this loop, for the sake of simplicity, the source and drain are not shown. Another polycrystalline silicon region 14B is formed on the field oxide region 12 for connection to a word line. Selective formation of oxynitride (SiOxNy) 17 on substrate 10, field oxidation region 12 and polycrystalline silicon region 14A by low pressure tetraethylsilic acid (LPTE0S) or plasma enhanced chemical vapor deposition (PECVD). And 14B surface to provide a moisture barrier. This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page}

經濟部中央標準局属工消费合作社印— A7 B7 五、發明説明() 接著,形成一槻裏層(linear layer)16,例如低 臭氡濃度形成之氧化層,於氮氧化物層(〇xynitride)17上 面,用以減少多晶矽之敏感度。在本實施例中,此低臭氧 濃度氧化層1 6係以傳統低壓次大氣磬化學氣相沈積法 (LPSACVD)所形成,其厚度大約爲1000埃。 於形成此櫬襄層(linear layer) 16之前或之後, 可以選擇性的以氮氣-¾漿加以處理,用以提高襯哀層16 之品質或改善其表面敏感度。接著,於櫬裏層16上形成 一厚約2000-8000埃之無掺雜矽玻璃(Undoped Silica G lass, USG>層18,作爲介多晶矽(interpoly)層。根據本 發明實施例,此無摻雜矽玻璃層1 8係以傳统次大氣壓化 學氣相沈積法(SACVD),於溫度约350-450艺下,經由氣 化反應臭氧-四乙基矽酸里(TE0S)並以丁式反應沈積而 得:Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives — A7, B7 V. Description of the Invention () Next, a linear layer 16 is formed, such as an oxide layer formed by a low-odor plutonium concentration, in a nitrogen oxide layer (〇xynitride ) 17 above to reduce the sensitivity of polycrystalline silicon. In this embodiment, the low ozone concentration oxide layer 16 is formed by a conventional low-pressure sub-atmospheric ytterbium chemical vapor deposition (LPSACVD) method, and has a thickness of about 1000 angstroms. Before or after the linear layer 16 is formed, it may be optionally treated with a nitrogen-¾ slurry to improve the quality of the liner layer 16 or improve its surface sensitivity. Next, an undoped silica glass (Undoped Silica Glass, USG) layer 18 is formed on the silicon layer 16 to a thickness of about 2000-8000 angstroms as an interpoly layer. According to the embodiment of the present invention, this undoped silicon Heterosilicate glass layer 18 is deposited by conventional sub-atmospheric chemical vapor deposition (SACVD) method at a temperature of about 350-450 ° C through a gasification reaction of ozone-tetraethylsilicic acid (TE0S) and a butyl reaction. Instead:

Si(C2Hs〇)4 + 12〇3 = Si〇2 +8CO2 +IOH2O + AO z 値得注意的是,使用無摻雜矽玟璃層18可以大 大的減少了傳统硼磷矽玻璃(BPSG)所產生的自摻雜現 象。 當無捧雜梦玻璃廣18之厚度太厚時(例如大於 5000埃),則可以選擇性再形成一蓋層(cap I aye r)20(例 如電漿強化四乙基矽酸鹽(PETE0S)或PE Si lane)於無掺 本纸張尺度逍用中國國家揉率(CNS > A4规格(210X297公釐> (請先聞讀背面之注意事項再填寫本頁) 訂 A7 ______B7五、發明説明() 雜矽玻璃層18上,用以防止無摻雜矽玻璃層18之龜裂 接著,加一高溫使密集化(densify)此無摻雜矽 玻瑞層18 ^在本實施例中,溫度大约爲700-850 ·<〇,加 溫時間大約爲5-120分鐘。値得注意的是,相較於傳統硼 碎矽玻璃(BPSG)所需之密禁化溫度(大於850 t:),本發 明所需之溫度較低,因而節省了不少的製程成本》再者, 此密集化加溫步驟可以遲至接下來之旋塗式玻璃(spin-on glass, SOG) 步驟完成後才 實施。 以傳統旋塗式玻璃(spin-on glass, S0G)技術形 成一具有平坦表面之旋塗玻璃層22於無摻雜矽玻璃層 18(或蓋層20)上面。此旋塗玻瑀層22之厚度大約爲 100 0-5000埃》於形成此旋塗玻璃層22時,係以傳统光 阻旋塗方法,旋塗例如poly si loxzne polymer之材質於無 摻雜矽玻填層18(或蓋層20)上面一次或者視情形塗佈兩 次》對於較厚(大於3000埃)的旋塗玻璃層22,則可以使 用低溫過火(curing)或烘培以避免其龜裂。 (請先閲讀背面之注意事項再填寫本頁}Si (C2Hs〇) 4 + 12〇3 = Si〇2 + 8CO2 + IOH2O + AO z It should be noted that the use of undoped silicon glass layer 18 can greatly reduce the traditional borophosphosilicate glass (BPSG). The resulting self-doping phenomenon. When the thickness of Wuhan Mimeng Glass 18 is too thick (for example, greater than 5000 angstroms), a cap I aye r 20 (such as plasma strengthened tetraethyl silicate (PETE0S)) can be selectively formed. Or PE Si lane) on the non-admixed paper scale and use the Chinese national kneading rate (CNS > A4 size (210X297 mm) (please read the notes on the back before filling this page). Order A7 ______B7 V. Invention Explanation () The hetero-silicon glass layer 18 is used to prevent cracking of the undoped silica glass layer 18. Next, a high temperature is applied to densify the undoped silica glass layer 18 ^ In this embodiment, The temperature is about 700-850 · < 〇, and the heating time is about 5-120 minutes. It should be noted that compared with the traditional borosilicate glass (BPSG), the confinement temperature (greater than 850 t: ), The temperature required by the present invention is relatively low, thus saving a lot of process costs. Furthermore, this intensive heating step can be as late as after the subsequent spin-on glass (SOG) step is completed Only implemented by traditional spin-on glass (S0G) technology to form a spin-on glass with a flat surface The layer 22 is on the undoped silica glass layer 18 (or the cover layer 20). The thickness of the spin-coated glass layer 22 is about 100 0-5000 Angstroms. When the spin-coated glass layer 22 is formed, a conventional photoresist is used. Spin coating method, spin coating a material such as poly si loxzne polymer on the undoped silicon glass filling layer 18 (or cover layer 20) once or twice as appropriate. For thicker spin coating glass (greater than 3000 angstroms) Layer 22, you can use low temperature curing (curing) or baking to avoid cracking. (Please read the precautions on the back before filling this page}

經濟部中央橾準局負工消费合作杜印製 最後,回蝕此旋塗玻瑞層22、蓋層20及部份無 摻雜矽玻璃層18,總共約4000-8000埃的厚度,直到無 掺雜矽玻璃層18之表面變爲平坦,因而形成如第二圈所 示的結構。在本實施例中,係使用傳統電漿蝕刻法,例如 活性離子蝕刻法,及使用蝕刻劑CF4,CHF3,NF3,C2Fe 本紙張度適用中國國家標準(CNS ) A4規格(210X297公釐) A7 B7 五、發明説明() 等,使得旋塗玻璃層2 2/無掺雜矽玻璃層18之蝕刻比例 大约爲0.7-2.0。 以上所述僅爲本發明之較佳實施例而已,並非用 以限定本發明之申請專利範園;凡其它未脱離本發明所揭 示之精神下所完成之等效改變或修飾,均應包含在下述之 申請專利範面内。 H I II - - I - I I I - Is— - - ..-! i In X 、" (請先閱讀背面之注意事項再填寫本頁) 經濟部中央橾準局負工消费合作社印装 本紙張尺度適用中國國家梂準(CNS ) A4規格(210X297公釐)At the end of the work, consumer cooperation with the Central Bureau of Standards and Technology of the Ministry of Economic Affairs, Du printed, and finally etched back the spin-on Berry layer 22, the cover layer 20 and a part of the undoped silica glass layer 18, a total thickness of about 4000-8000 Angstroms, until no The surface of the doped silica glass layer 18 becomes flat, thereby forming a structure as shown in the second circle. In this embodiment, the conventional plasma etching method is used, such as reactive ion etching method, and the etchant CF4, CHF3, NF3, C2Fe are used. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7 5. Description of the invention () etc., so that the etching ratio of the spin-on glass layer 2 2 / undoped silica glass layer 18 is about 0.7-2.0. The above is only a preferred embodiment of the present invention, and is not intended to limit the patent application scope of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall include Within the scope of patent application below. HI II--I-III-Is—--..-! I In X 、 " (Please read the notes on the back before filling out this page) Printed paper size of the Central Consumers' Bureau of the Ministry of Economic Affairs and Consumer Cooperatives Applicable to China National Standard (CNS) A4 (210X297 mm)

Claims (1)

Μ Β8 C8 D8 六、申請專利範圍 1. 一種平坦化具有介多晶矽(interpoly)層之半導體結構 的方法’至少包含下列步驟: 形成一無摻雜矽玻璃層於一半導體基板上,該無摻雜 矽玻璃層係作爲該介多晶矽層; 形成一旋塗玻璃層於該無摻雜矽玻璃層上;及 回蝕該旋塗破璃層直到該無摻雜矽玻璃層之表面爲 平坦,因而平坦化具有該介多晶矽層之該半導體結構。 2. 如_請專利範圍第彳項之方法,於形成該無摻雜矽玻璃 層之前,更包含形成一櫬裏層於該多晶矽區域及該基板 上0 3. 如申請專利範圓第2項之方法,其中上述之櫬裏層係由 低壓次大氣壓化學氣相沈積法(LPSACVD)所形成。 4_如申請專利範圍第2項之方法,於形成該櫬襄層之前, 更包含形成一気氧化物層。 5. 如申請專利範園第2項之方法,於形成該櫬襄層之前或 之後’更包含以氮氣-電漿處理該槻裏層。 經濟部中央標準局貝工消费合作社印製 6. 如申請專利範圍第1項之方法,其中上述之無摻雜矽玻 璃層係以氧化反應臭氧-四乙基矽酸鹽(T EOS)而形成。 本紙張尺度通用申國國家揉準(CNS ) A4規格(210X297公兼) S9925C六、申請專利範圍 Α8 Β8 C8 D8 7·如申請專利範園第6須之方法,其中上述之無摻雜發玻 璃層係以次大氣壓化學氣相沈積法(SACVD)所形成。 8. 如申請專利範圍第】項之方法更包含形成一蓋層於該 無掺雜發玻璃層上。 .9. 如申叫專利範圍第彳項之方珐,於形成該旋塗玻璃層之 前,更 '包含密集化該無掺雜矽破璃層。10. 如申請專利範面第9項之方法,其中上述之無掺雜矽 玻璃層係於溫度约700-850 10予以密集化。 it— (請先閲讀背面之注意事項再填寫本頁) 經濟部中央棵準局貝工消费合作社印製 11.如申請專利範固第1項之方法,於形成該旋塗玻璃層 之後,更包合密集化該無摻雜矽玻璃層。 12·如申請專利範圍第11項之方法,其中上述之無掺雜矽 玻璃層係於溫度約700-850 ·ς:予以密集化。 13. 如申請專利範圍第1項之方法,更包含烘培該旋塗玻璃層。 14. 如申請專利範面第1項之方法,其中上述之旋塗玻璃 層係以電漿製程予以回蝕。 本紙張尺度適用中困國家棣率(CNS ) A4現格(210X297公釐) 39925C A8 B8 C8 D8 六、申請專利範圍 15. —種平坦化具有介多晶矽(丨nterP〇|y)層之半導體結構 的方法,至少包含下列步驟: 形成一無掺雜矽玻璃層於一半導體基板上,該無摻雜 梦玻璃層係以氧化反應臭氧-四乙基矽酸鹽(TEOS)而形 成,且該無掺雜>6夕玻璃層係作爲該介多晶石夕房; 密集化該無摻雜矽玻璃層; 形成一旋塗玻璃層於該無摻雜矽玻璃層上;及 回蝕該旋塗玻璃層直到該無摻雜矽玻璃層之表面爲 平坦,因而平坦化具有該介多晶矽層之該半導體結構。 16. 如申請專利範圍第15項之方法,其中上述之無摻雜矽 玻璃層係以次大氣壓化學氣相沈積法(SACVD)所形成。 • — /1 (請先閲讀背面之注意事項再填寫本頁) 17.如申請專利範圍第15項之方法,其中上述之無摻雜矽 玻璃層係於溫度約700-850 *C予以密集化。 經濟部中央標準局貝工消费合作社印製 1 8· —種平坦化具有介多晶矽(interpoly)層之半導體結構 的方法,至少包含下列步驟: 形成一無摻雜矽玻璃層於一半導體基板上,該無掺雜 石夕玻璃層係以氡化反應臭氧-四乙基矽酸鹽(TEOS)而形 成,且該無摻雜矽玻璃層係作爲該介多晶矽層; 形成一旋塗玻璃層於該無摻雜矽玻璃層上; 密集化該無掺雜矽玻璃層;及 回蝕該旋塗玻璃層直到該無摻雜矽玻璃層之表面爲 本紙張尺度適用中國國家標準(CNS ) Α4規格(2丨0Χ297公釐) 39926C ?8s D8 六、申請專利範圍 平坦,因而平坦化具有該介多晶矽層之該半導體結構。 19. 如申請專利範圍第18項之方法,其中上述之無摻雜石夕 玻璃層係以次大氣壓化學氣相沈積法(SACVD)所形成。 20. 如申請專利範園第18項之方法,其中上述之無摻雜石夕 玻璃層係於溫度約700-850 eC予以密集化。 (請先閲讀背面之注意事項再填寫本頁) •7裝_ 、1T ^ ί— k_L _ 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)M Β8 C8 D8 Scope of patent application 1. A method of planarizing a semiconductor structure having an interpoly silicon layer (at least) includes the following steps: forming an undoped silicon glass layer on a semiconductor substrate, the undoped A silica glass layer is used as the polycrystalline silicon layer; forming a spin-coated glass layer on the undoped silica glass layer; and etching back the spin-coated broken glass layer until the surface of the undoped silica glass layer is flat and thus flat Forming the semiconductor structure having the polycrystalline silicon layer. 2. If the method of item (i) of the patent scope, before forming the undoped silica glass layer, it further includes forming an inner layer on the polycrystalline silicon region and the substrate. A method in which the above-mentioned caliper layer is formed by a low pressure sub-atmospheric pressure chemical vapor deposition method (LPSACVD). 4_ According to the method of claim 2 in the scope of patent application, before forming the rhenium layer, it further comprises forming a rhenium oxide layer. 5. According to the method of applying for the second item of the patent fan garden, before or after the formation of the maggot layer, it further comprises treating the maggot layer with a nitrogen-plasma. Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperatives. 6. As described in the method of the first patent application, wherein the undoped silica glass layer is formed by the oxidation reaction of ozone-tetraethylsilicate (T EOS). . This paper standard is universally applied by the Chinese National Standard (CNS) A4 (210X297) and S9925C VI. Application scope of patent A8 B8 C8 D8 7. If the method of applying for the sixth paragraph of the patent fan garden, the above-mentioned non-doped hair glass The layer is formed by sub-atmospheric chemical vapor deposition (SACVD). 8. The method according to item [Scope of the Patent Application] further comprises forming a capping layer on the undoped hair glass layer. .9. If the square enamel as claimed in item (1) of the patent scope is included, before the spin-on glass layer is formed, it further includes the dense doped silicon broken glass layer. 10. The method according to item 9 of the patent application, wherein the above-mentioned undoped silicon glass layer is densified at a temperature of about 700-85010. it— (Please read the precautions on the reverse side before filling out this page) Printed by the Central Labor Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative 11. If the method of applying for patent Fangu No. 1 is applied, after forming the spin-coated glass layer, more The inclusion denses the undoped silica glass layer. 12. The method according to item 11 of the scope of patent application, wherein the above-mentioned undoped silicon glass layer is at a temperature of about 700-850 ° D: is denser. 13. The method of claim 1 further includes baking the spin-on-glass layer. 14. The method of claim 1 in the patent application, wherein the spin-on-glass layer is etched back using a plasma process. This paper is applicable to the rate of CNS A4 (210X297 mm) 39925C A8 B8 C8 D8 in the middle and poor countries. 6. Application for patent scope 15. —A kind of flattened semiconductor structure with polycrystalline silicon (nterP0 | y) layer The method includes at least the following steps: forming an undoped silica glass layer on a semiconductor substrate, the undoped dream glass layer is formed by an oxidation reaction of ozone-tetraethyl silicate (TEOS), and the The doped > 6 glass layer is used as the mesocrystalline polycrystalline silicon chamber; the non-doped silica glass layer is densely formed; a spin-on glass layer is formed on the undoped silica glass layer; and the spin coating is etched back The glass layer is flat up to the surface of the undoped silica glass layer, thereby planarizing the semiconductor structure having the dielectric polycrystalline silicon layer. 16. The method of claim 15 in which the above-mentioned undoped silicon glass layer is formed by a sub-atmospheric chemical vapor deposition (SACVD) method. • — / 1 (please read the precautions on the back before filling this page) 17. If the method of patent application No. 15 is applied, the above-mentioned undoped silica glass layer is densified at a temperature of about 700-850 * C . A method for flattening a semiconductor structure with an interpoly silicon layer is produced by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, including at least the following steps: forming an undoped silicon glass layer on a semiconductor substrate, The undoped silica glass layer is formed by tritiated ozone-tetraethyl silicate (TEOS), and the undoped silica glass layer is used as the mesopolycrystalline silicon layer; On the undoped silica glass layer; dense the undoped silica glass layer; and etch back the spin-coated glass layer until the surface of the undoped silica glass layer is the paper standard applicable to the Chinese National Standard (CNS) A4 specification ( 2 丨 0 × 297 mm) 39926C? 8s D8 6. The scope of patent application is flat, so the semiconductor structure with the dielectric polycrystalline silicon layer is flattened. 19. The method according to item 18 of the application, wherein the above-mentioned undoped glass layer is formed by a sub-atmospheric chemical vapor deposition (SACVD) method. 20. For the method of applying for patent No. 18 in the patent park, wherein the above-mentioned undoped glass layer is densified at a temperature of about 700-850 eC. (Please read the notes on the back before filling out this page) • 7 packs _ 、 1T ^ ί— k_L _ Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs This paper is printed in accordance with Chinese National Standard (CNS) A4 (210X297 mm )
TW86114325A 1997-10-01 1997-10-01 A planarization method for the inter-polysilicon layer of semiconductor structure TW399250B (en)

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