TW395145B - Planar type resistor capacitor and the manufacturing method thereof - Google Patents

Planar type resistor capacitor and the manufacturing method thereof Download PDF

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Publication number
TW395145B
TW395145B TW87116057A TW87116057A TW395145B TW 395145 B TW395145 B TW 395145B TW 87116057 A TW87116057 A TW 87116057A TW 87116057 A TW87116057 A TW 87116057A TW 395145 B TW395145 B TW 395145B
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Taiwan
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substrate
flat
capacitor
layer
resistance
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TW87116057A
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Chinese (zh)
Inventor
Wen-Yan Lin
Shr-Ting Huang
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Compeq Mfg Co Ltd
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Priority to TW87116057A priority Critical patent/TW395145B/en
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Publication of TW395145B publication Critical patent/TW395145B/en

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Abstract

This invention relates to a planar type resistor capacitor and the manufacturing method thereof(2), first to form the copper layer on the surface and the bottom face of the high dielectric coefficient base material using plate-pressing technique and forms the substrate. Next are the steps of photoresist coating, image transfer, etching on the substrate to form planar type capacitor, and finally with the printing of the electrical conductive layer with high resistance coefficient to a suitable position of the substrate to form the planar type resistor. A large amount of surface space of the printed circuit can be released via the above-mentioned built-in planar type resistor and capacitor, the density of passive device can be increased and the parasite capacitance, inductance and resistance in the transmission line can be decreased to improve the signal transmission quality.

Description

A7 A7 B7 五、發明説明(/ ) 、本發明係關於—種平板式電阻電容及其 工種編刻印刷法於-基板上同時形成的平丄 按,印刷電路板於表面或内 線路,各線路主要用於電子元㈣μ =上刀別形成有 。麸而产.次却子70件間的電氣連接或信號傳送 备:貝° ’、.、發展及功能性要求大-幅提升的趨勢下, I兩=象·其_為電路表面黏著元件的數量大幅增 心度印刷電路的需求日趨殷切,但前述趨勢 電路’相鄰元件間的距離縮短,# 而古 時’元相發聽奸㈣機率大幅提升, 訂 而直接影響電路工作的穩定性。 升 不丄信號可能必須透過 m心、進傳輪(如透過導通孔構成電氣連接或 ^ 虎傳輸),而增多了線路阻抗不匹配的情況及線路雜訊 經 濟 部 中 央 標 準 員 工 消 費 合 作 社 印 製 降低3並=/ €^件數量增加’將使生產良率相對 降低並因而提高製造成本。 表二::元件數量的增加’亦不到於印刷電路板 可知’尚密度印刷電路所衍生的各項問題,為 ’簡^公司提出了在印刷電路板中内 1 X取代间密度印刷電路中於表面所設的電 凡件,其技術原理主要係根據以下的公式:A7 A7 B7 V. Description of the invention (/) The present invention is about a flat-type resistor and capacitor and its type of engraving and printing method on a flat flat surface formed on a substrate at the same time. The printed circuit board is on the surface or inner circuit. It is mainly used for the electronic element ㈣μ = formed by the upper knife. Produced from bran. Electrical connection or signal transmission between 70 pieces of hyphae. Under the trend of large-scale development and functional requirements, I two = elephants and its _ are the components of circuit surface adhesion components The demand for printed circuits has increased sharply, but the distance between adjacent components in the aforementioned trend circuits has been shortened, and the probability of listening to gangsters has increased significantly, which directly affects the stability of circuit work. Rise and fall signals may have to pass through the M core and the transmission wheel (such as electrical connection through the through hole or ^ tiger transmission), which increases the situation of line impedance mismatch and line noise reduction printed by the Central Standard Staff Consumer Cooperative of the Ministry of Economic Affairs 3 and = / € ^ Increase in the number of pieces' will reduce the production yield relatively and thus increase the manufacturing cost. Table 2: The increase in the number of components 'is not less than the printed circuit board can know' the various problems derived from high density printed circuits. The technical principle of the electrical parts provided on the surface is mainly based on the following formula:

L W 經濟部中央標準局員工消費合作社印製 、發明説明(>) R = (£)x "、中R—電阻值’ p =電阻係數,t =厚度,w=寬度 由前述公式中可以看出,藉由L(長度)、w(寬度)的改 ‘可用以5周整R(電阻值),因此,画脇公司以不同 (電阻係數)/ t f厘#、 (尽度)’並利用L(長度)、W(寬度)的 、以生產所須阻抗值的電阻(R )。 且利用目前運用十分^遍的多層印刷電路製造技術, :電阻製作於印刷電路板之結構中而形成内建電阻,而内 於印刷電路板結構巾的電阻,可有效取代印刷電路板表 /斤須的電阻元件’因此可減少印刷電路板表面的元件數 Ϊ及面積佔有率。 . 既有建内阻外,電容亦經常以其他方式形成,以 既有的多層印刷電路板而言,其經常令兩個不同電位的電 源層(如VCC及GND)查 >+ „ W, ^ 罪近,利用其二者所在的大銅面產 附加電谷’ IX調節電壓。其公式係如下列: C(電容)=(介電係數)χ Α(面積) mm) ,因!中,“介電係數)係受材料特性所左右 ^ (面積)與d (距離)的改變可以栌制產生 所須的電容。 乂控制產生 刷二=,將電阻及電容等被動元件内建埋置於印 * ,以有效減少表面元件數量並釋出 別以不…: 建電阻及埋置電容係分 °、如·手段達成’未能在同一製程中完成,造成 (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, and a description of the invention (>) R = (£) x ", R = resistance value 'p = resistivity, t = thickness, w = width can be determined from the above formula It can be seen that the change of L (length) and w (width) can be used to round R (resistance value) in 5 weeks. Therefore, the drawing company has different (resistance coefficient) / tf # #, (extent degree) 'and Use L (length), W (width) to produce the required resistance (R). And with the current multi-layer printed circuit manufacturing technology that is used very often, the resistors are made in the structure of the printed circuit board to form a built-in resistor, and the resistor built in the structure of the printed circuit board can effectively replace the printed circuit board table / jin. The required resistive element can therefore reduce the number of components and the area occupancy of the surface of the printed circuit board. Existing built-in resistance, capacitors are often formed in other ways. For existing multilayer printed circuit boards, they often make two power supply layers with different potentials (such as VCC and GND) look up > + „W, ^ Sin is near, using the large copper surface produced by the two of them to adjust the voltage. IX adjust the voltage. The formula is as follows: C (capacitance) = (dielectric coefficient) x Α (area) mm), because !, "Dielectric constant" is controlled by the change of material characteristics ^ (area) and d (distance), which can restrain the required capacitance.乂 Control the production of brush ==, embed the passive components such as resistors and capacitors in the printed circuit board * to effectively reduce the number of surface components and release the irresistible ...: The resistors and embedded capacitors are built in °, such as 'Failed to complete in the same process, causing (please read the precautions on the back before filling this page)

經濟部中央標準局員工消費合作杜印製 不便’且由於前述内建電容及電阻分 的基材上,亦有浪費材料不當增加成本之嫌。 、门 因此,本發明主要目的在提供一種利 一基板上同時形成平板式電阻及電容之方法。/ p刷法於 本發明次—目的在提供—種平板式電阻電容之製造方 、主要先利用壓板技術於高介電係數美+ 成銅層而構成基板丨 “緣基材表底面分別形 又於基板上依序進行光阻塗佈、影 :積,電係數及厚度固定的條件下,經由二 面積可取得所需電容; 利到層 導電==板式電容後’利用印刷方,式將高電阻係數的 導電層Ρ在基板上之適當位置’即構成平板式電阻。 至古明又:目的在於:前述平板式電阻、電容可運用 …電路以交流終端法,減少線路上之反射雜訊。 決定本^明再的在於前述平板式電容係根據下列公式 、。· =225χεΓΧτ,其中£r為基枯之介電係數,Α為埋 置電容^積’ 1則為高介電係數基材之厚度(mil); 又前述内建電阻係根據下列公式決定: p A (T)x (y),其中/0指尚電阻係數層之電阻係數 L、w ' T分別為高電阻係數導電層長度、寬度與厚度 〜為使貴審查委員進一步瞭解前述目的及本發明之技 術特徵,茲附以圖式詳細說明如后: (一)圖式部分:It is inconvenient for the consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs to make prints, and because of the aforementioned built-in capacitors and resistors, there is also the possibility of wasting materials improperly and increasing costs. Therefore, the main object of the present invention is to provide a method for simultaneously forming a flat-plate resistor and a capacitor on a substrate. / p brush method in the present invention-the purpose is to provide-a type of flat-type resistor and capacitor manufacturers, mainly using the pressure plate technology at high dielectric constant beauty + copper layer to form a substrate 丨 "Edge substrate surface and bottom surface respectively On the substrate, photoresist coating, shadow: product, electrical coefficient and thickness are fixed in sequence, and the required capacitance can be obtained through two areas; it is good for layer conductivity == plate capacitor. The conductive layer P of the resistivity at a proper position on the substrate constitutes a plate-type resistor. To Gu Ming again: the purpose is: the aforementioned plate-type resistors and capacitors can use the circuit to use the AC termination method to reduce reflection noise on the line. What determines this is that the above-mentioned flat capacitor is based on the following formula: · = 225χεΓχτ, where £ r is the dielectric constant of the substrate, and A is the buried capacitor ^ 1, which is the substrate of the high dielectric constant substrate. Thickness (mil); The built-in resistance is determined according to the following formula: p A (T) x (y), where / 0 refers to the resistivity of the resistivity layer L and w 'T are the lengths of the high-resistivity conductive layers, respectively. , Width and thickness ~ Your reviewing committee further understands the foregoing objectives and the technical features of the present invention, and attaches detailed descriptions as follows: (1) Schematic part:

第- -圖: 第二 -圖A 第i L圖A 第五圖 E :係本發明之製程步姐意圖。 第二圖A〜C:係本發明平板式電阻冬 第四圖:係本發平㈣輕域频=驟Γ相 ::高頻電路上所設交流終端法之線::圖。 第六圖 例圖 一)圖號部分: 1 0 )基板 1 2 ) ( 1 3 )銅 1 5 )樹脂 3 0)影像資料 R電阻 施 (1 1 )基材 (14)導電層 (2 0.)光阻 (4 0)傳輸線 C電容 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 有關本發明用以製作平板式電 ί=:圖所示,其包括有「基板製作」、:= = 、「去除光阻」、「印刷導電 有關「基板製作」步驟請參閱第二圖Α所示,該基板 (1 0)係用以製作的平板式電容之基礎材料,主要二於 一基材(11)表面及底面分別形成一鋼層(12)(工3 )。 y光阻塗佈及影像轉移」步驟:請參閱第二圖B所示 ’其係於基板(1 〇 )之表面及底面分別塗佈以光阻(2 0 ) (ph〇t〇-resister),隨後利用光罩將設計完成的影 GJ- ·油------1T------____________ _ I I-I - -- -1 m · 本紙張尺度適用中國國家標準(CNS) 公釐)Figure--Figure: Figure-Figure A Figure ll Figure A Figure F-Figure E: The intention of the step in the process of the present invention. The second picture A ~ C: is the flat-type resistor winter of the present invention. The fourth picture: is the flat frequency of the present invention. The sixth illustration (Figure 1) Figure number part: 1 0) substrate 1 2) (1 3) copper 1 5) resin 3 0) image data R resistance application (1 1) substrate (14) conductive layer (2 0.) Photoresistance (4 0) transmission line C capacitor (please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs about the invention used to make flat-type electricity. There are "substrate production", ==, "removal of photoresist", "printing and conducting. For the" substrate production "steps, please refer to the second figure A. The substrate (1 0) is the basis for the production of flat capacitors. Material, mainly formed a steel layer (12) on the surface and bottom surface of a substrate (11) (work 3). y Photoresist coating and image transfer "steps: Please refer to the second figure B ', which is coated on the surface and bottom of the substrate (10) with a photoresist (2 0) (ph〇t〇-resister) , And then use the photomask to design the finished shadow GJ- · oil ------ 1T ------____________ _ I II---1 m · This paper size applies Chinese National Standard (CNS) mm )

、發明説明( 經 部 t 央 標 準 Μ 員 工 消 合 社 印 製 資料(3 0 )轉移至光阻(2 〇 ) 料(3 0)涵蓋範圍内的光阻,又象=解去除影像資 所製成平板式電容之容值,具體的電 ( 3 〇)攸關 式取得: 7冤奋值係透過下列的公 C = 225xsrx~ t 於前述公式中,為基材(工 為銅層(1 2 ) f 1 Q)之"電係數,A 基材⑴)i二二之。面積⑽,μ為高介電係數 «設=::::)(以一式取得所需容值 積。又与傻資祖r 〇 ( 1 3 )的範圍,進而決定其 積又衫像貧枓(3 〇)並 /、囬 置,如第三圖A所干,仂#丄 疋千板式電阻的預定位 形影像資料(30),影像資料央的凸字 ,兩局部銅層小的面積’經兹刻完成 ,並構成雷裔2 印刷方式形成平板式電阻 J = ::Γ。前述影像資料(3〇)的兩個區域, 位置,因此,前述的影:資傳輸線或穿孔預設 容及雷艇的旦,你回 像貝科(3 0 )係將製作平板式電 -及電阻的影像圖案合而為一,其亦可分別進行, (2〇;':'刻」步驟:經轉移影像資料(30)至光阻 即針對該影像資料(3 〇)涵蓋之銅層(2、 Explanation of the invention (The Ministry of Economics and Standards Standards M Employees' Printing Co., Ltd. printed materials (30) transferred to the photoresist (20) photoresist within the coverage of the material (30), and it looks like the solution of removing the image assets The capacitance value of the plate-type capacitor is obtained in a specific electrical manner (30). The value of 7 is calculated through the following public C = 225xsrx ~ t In the foregoing formula, it is the base material (the copper layer is 1 2 ) f 1 Q) " Electrical coefficient, A substrate ⑴) i 22 two. The area ⑽, μ is a high dielectric constant «set = ::: :) (to obtain the required capacitance product in one formula. It is also in the range of the silly ancestor r 〇 (1 3), and then determines its product as poor. (30) and / or resetting, as shown in the third figure A, the pre-shaped image data of the ## thousand plate resistor (30), the convexity of the central image data, the small area of the two local copper layers. It is completed in a short time and forms the Lei Ze 2 printing method to form a plate-type resistor J = :: Γ. The two areas and positions of the aforementioned image data (30), therefore, the aforementioned shadow: transmission line or perforation preset content and Thunder boat, once you return to Beco (30), you will combine the image patterns of making flat-type electrical and electrical resistance into one, which can also be performed separately. (2〇; ':' 刻 '' Step: After transfer The image data (30) to photoresist refers to the copper layer (2) covered by the image data (30).

所_ , ^進仃蝕刻,經蝕刻步驟完成後係如第二圖C 柘:雷又Γ元成「去除光阻」步驟後,即如第二圖D (平 板式電阻。卩分如第三圖6所示)。 il — ά------訂------,! (諳先鬩讀背面之注意事項再填寫本頁) .本紙張纽適 B7 發明説明(占 經完成前述步驟後,即板 :別形成特定面積的銅層…)(13 :2二(13)間即介著固定厚度、介電係數 11)形成一預定容值的平板式電容。 』( .—刷導電層」步驟:此步驟係 電容的基板(.1 〇)卜Μ1 e /取百千板式 有高電阻係數的導電膏=:式在特定位置上印刷具 瓜咕— 电貧以構成平板式電阻,如策··阁p 其係於基材(11)上之特定位 :像貝枓(30)範圍内)以印刷方式印上一導電二 4),該導電層(ι4) 等¥層(1 或導電高分子膏忍4二'具有高電阻係數的鶴金屬膏 連接,而構成-平1:=層,(12)構成電氣 值可由下列公式取Γ 該平板式電阻的實際阻 R”x全令Φ 、 其中P係指前述導電層(1 w 經 濟 部 t 央 標 準 工 消 費 A 社 印 製 執為r導電層(…之長度、寬二因: =二「印二導電層」步驟時,只須控制導電層(= 二二予又即可製作所須阻值的平板式電阻。 不因::四圖所示,為確保前述平板式電阻之阻值 」步驟,主要係於基板(1〇;^=1口=塗佈難 外塗佈—層樹腊(15),令該導 離,避免其因與空氣接觸而改變阻值。4) 一隔 以前述同時形成有平板式電阻、電容之基板(10) 本纸張) A4,Therefore, after the etching step is completed, it is as shown in the second figure C. 雷: After the ray element is removed into the photoresist step, it is as shown in the second figure D (flat-type resistor. The point is as the third figure). Figure 6). il — ά ------ Order ------ ,! (Please read the precautions on the reverse side before filling out this page). This paper Niu Shi B7 invention description (occupies the plate: do not form a copper layer of a specific area after completing the previous steps ...) (13: 2 (13) In a short time, a plate capacitor with a predetermined capacitance is formed with a fixed thickness and a dielectric constant of 11). ”(.—Brush conductive layer” step: This step is the substrate of the capacitor (.1 〇) BM1 e / take a hundred thousand plate type conductive paste with high resistivity =: type printed with a specific position on a specific position-electric poor In order to form a flat-type resistor, such as a policy, it is attached to a specific position on the substrate (11): like a bead (30), printed on a conductive layer 4), the conductive layer (ι4 ) Equal layer (1 or conductive polymer paste forty-two's crane metal paste connection with high resistivity, and constitute-flat 1: = layer, (12) the electrical value of the composition can be taken from the following formula The actual resistance R "x full order Φ, where P refers to the aforementioned conductive layer (1 w printed by the Ministry of Economic Affairs, T.C., Standard Industrial Consumer A, and printed as r conductive layer (the length and width of the two factors: = two" printed two conductive "Layer" step, you only need to control the conductive layer (= 22, and then you can make the plate resistance of the required resistance value. Not because: As shown in the four figures, in order to ensure the resistance value of the aforementioned plate resistance "step, mainly On the substrate (1〇; ^ = 1 mouth = coating is difficult to apply externally-layer of wax (15), to make this conductive away, to avoid its modification due to contact with air Resistance .4) a spacer plate is formed simultaneously to the resistor, the capacitor substrate (10) of the present paper) A4,

五、發明説明(;? 經濟部中央標準局員工消費合作社印製 = Π=,並進行壓板、鑽孔等…製程, ρ 了構成具備内建平板式電阻、 ,將有助於降低傳輸線上的寄生電容tr刷電路板 阻,而提供較佳的信號傳輪路徑,再者:::感及寄生電 電路板表面_阻及電容數量而 路 空間,供作電氣祕、錢傳輸或 ^料板之表面 途。另由於在同一基板上同時形功能升級用 方便於運科,更可有效減少㈣^式電錢電阻’除 芩效減'材枓浪費,降低製造成本。 電容=二外’在具體用途方面,前述平板式電阻、 路中之交流終端法,以減少反射雜訊 :五圖所不,係傳統高頻電路中於傳 :=串接有電阻R及電容。,以消除信號傳輸過程; =射雜訊,確保信號傳輸品f,即—般所稱的交流終端 2傳統高頻電路中,必須在印刷電路板上以外接方式 站。阻只及電容。,與一般高密度印刷電路相同,太多 楚面黏著元件,將造成韻干擾、良率降低及成本提高 攸:題°㈣本發明之平板式電阻、電容運用於前述交流 端去即可有效解決因電路密度太高衍生之各項問題。 如第六圖所示,該傳輸線(4 〇 )係連接至導電層( 工^)端的銅層(12)上,而與導電層(14)構成 ^平板式電阻呈電氣連接,又導電層(14)另端的鋼層 1 2)又隔著基材(1 i )與基板(丄〇)底層的銅層 (13)構成一電容,又令底面的銅層接地, ------ J, Y---—-- (請先M讀背面之注意事咳再填寫本頁) 訂 ----Φ___..V. Description of the invention (;? Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs = Π =, and performing plate pressing, drilling, etc ... processes, ρ has a built-in flat-type resistor, which will help reduce the transmission line The parasitic capacitance tr brushes the circuit board resistance, and provides a better signal transmission wheel path. Furthermore: ::: Sensing the surface of the parasitic electrical circuit board and the amount of capacitance and path space for electrical secrets, money transmission or material board In addition, because the simultaneous shape function upgrade on the same substrate is convenient for transportation, it can also effectively reduce the waste of material in the , ^ type electric resistance, and reduce the manufacturing cost. Capacitance = two externals. In terms of specific applications, the aforementioned flat-type resistors and AC termination methods in the circuit are used to reduce reflected noise: not shown in the five pictures, which are used in traditional high-frequency circuits: = resistors R and capacitors are connected in series to eliminate signal transmission Process; = noise emission, to ensure the signal transmission product f, which is the so-called AC terminal 2 traditional high-frequency circuits, must be externally mounted on the printed circuit board. Resistance and capacitance., And general high-density printing Same circuit Too many adhesive components on the surface will cause rhyme interference, yield reduction and cost increase: Problem: The flat-type resistors and capacitors of the present invention are applied to the aforementioned AC terminal to effectively solve the problems caused by the high circuit density. As shown in the sixth figure, the transmission line (40) is connected to the copper layer (12) at the end of the conductive layer, and the conductive layer (14) is electrically connected to the conductive layer (14) and is conductive. The steel layer at the other end of the layer (14) 1 2) forms a capacitor through the substrate (1 i) and the copper layer (13) at the bottom of the substrate (丄 〇), and grounds the copper layer at the bottom, ----- -J, Y ------ (please read the note on the back before you fill in this page) Order ---- Φ ___ ..

A7 B7 五、發明説明(岌) 即可利用該串接的平板式電RER與電容C消除反射雜訊。 由於該電阻R、電容c均内建於基板(1 〇)中,故不致 對電路密度造成影響。 -由上述可知’本發明係利用多層基板配合蝕刻印刷法 以同時形成平板式電阻、電容,而電阻、電容等被動元件 在叙印刷電路板上使用的數量甚多,而利用本發明將其 内建於基板中’除可顯著減少印刷電路板表面的元件數目 外,更可令印刷電路板表面釋出更多的空間,供電氣連接 ^號傳輸或其他加H力能升級料,由此可見,本發 :利=:電阻、電容之方式,可有效解決電路密度過高 'Πί:問Γ故已具備高度的產業利用價值與進步 並付合發明專利之要件,爰依法提起申請。 (諳先閱讀背面之注意事項再填寫本頁) J_ ----Μ.--------ΓΙΚ^Μ*.A7 B7 5. Description of the invention (岌) The serially connected flat-type electric RER and capacitor C can be used to eliminate reflected noise. Since the resistor R and the capacitor c are built in the substrate (10), the circuit density is not affected. -From the above, it is known that the present invention uses a multi-layer substrate in combination with an etching printing method to simultaneously form flat-plate resistors and capacitors, and a large number of passive components such as resistors and capacitors are used on printed circuit boards. Built in the substrate, in addition to significantly reducing the number of components on the surface of the printed circuit board, it can also free up more space on the surface of the printed circuit board. Power supply gas connection ^ number transmission or other H forces can be used to upgrade materials, which can be seen This issue: the method of benefit =: resistance and capacitance can effectively solve the problem of excessive circuit density 'Πί: ask Γ, so it already has a high degree of industrial use value and progress and meets the requirements of invention patents, and filed an application according to law. (谙 Please read the notes on the back before filling this page) J_ ---- Μ .-------- ΓΙΚ ^ Μ *.

-I— I I ! I 經濟部中央標準局員工消費合作衽印製-I— I I! I Printed by the Consumers' Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs

1%----1. ..--- I I— ·1% ---- 1. ..--- I I- ·

Claims (1)

AS B8 C8 D8AS B8 C8 D8 申請專利範圍 1.一種平板式電阻電容 一於高介電係數基材造方法㈡略包括有·· 之^驟;〆土表&面分別形成銅層以構成基板 £ 之 注 意 事 項 再 § 窝 本 頁 1 一 =板上塗佈綠並麟影轉敎挪; 面積’而分別在基_成適當 面積的銅層而構成平板式電容之步驟; " 厂去除光阻步驟; 阻之=基板上印刷具高電阻係鱗I相狀平板式電 f 4㈣㈣i項所述平板式電阻電容之製 == 該基板之歸具制定的料純與厚度,可 、、二控制相錄銅層之面後以取得所需容值之電容。 ^ t L ί«t ϊ 11' i - 2m ^ 干板式電合之谷值係根據C = 225x&x△決 兮電係數基材之厚度。向檟t為内 經濟'那中夬標隼局員工消費合作社印製 迭方、2如ΐ料鄉圍第1項所辭板式輕電容之製 。方去(二),戎平板式電阻阻值係根據κ=ρχ^(^(土)決定 ,其中ρ指導電層之電阻係數,L、w、x分別為^電層 的長、寬、厚度。 … 、方如申請專利範圍第1項所述.平板式電阻電容之製 造方法(―),該基板上之導電層係由鎢金屬或導電高分子構 成。 6 ·如申請專利範圍第工、4或5項所述平板式電阻 ( CNS ) ( 210X29VIFPatent application scope 1. A method for manufacturing a flat-plate resistance capacitor on a high-dielectric-constant substrate includes the following steps: The copper layer is formed on the surface and the surface of the substrate to form a substrate. 1 on this page = coating green on the board and changing the shadow; steps to form a flat capacitor with a copper layer of appropriate area on the substrate; " step of removing photoresistance in the factory; resistance = substrate The above is printed with a high-resistance scale I-phase flat-plate type electric f 4㈣㈣i. The system of the flat-type resistance capacitor described above == The substrate is provided with the specified material purity and thickness, which can be controlled by the surface of the copper layer. To obtain the required capacitance. ^ t L ί «t ϊ 11 'i-2m ^ The valley value of the dry-plate electric coupling is determined by C = 225x & x △. Xiang 槚 t printed for the internal economy, that is, the Consumers' Cooperatives of the Standards Bureau of the People's Republic of China. 2 It is a system of light-weight capacitors resigned as described in item 1 of ΐLiu Xiangwei. (2). The resistance value of the Rong plate resistance is determined according to κ = ρχ ^ (^ (土), where ρ guides the resistivity of the electrical layer, and L, w, and x are the length, width, and thickness of the electrical layer, respectively. …, As described in item 1 of the scope of patent application. Manufacturing method of flat-type resistor and capacitor (―), the conductive layer on the substrate is composed of tungsten metal or conductive polymer. 4 or 5 panel resistors (CNS) (210X29VIF A8 B8 C8 D8 經濟部中央標準局員工消費合作社印製 S95145 —----- ¥、申請專利範圍 製造:¾•法㈡’料電I外塗佈㈣脂 我變阻值。 乂防止氧化_ 美材^—種平板式電阻電容Qm於-高介電係數 面分別形成有適當面積的銅層,令相對鋼層 阻係數的ΐί式電容’又於基板上的適當位置氣有具高電 8 ·如申請翻範㈣7項所述之平板d 積=固定的介電魏與厚度―,經控制銅層之面 積τ取仔所需容值之..電容。 9 .如申請專利範圍第7或8項 / 容㈡’該平板式電容之容值係根據c = 225_t^,電 ' t成疋,其中 +為基封之介電係數,A為銅層之+ 基材之厚度。 、 m 1為喊電係數' 1q .如申請專利範圍第7項所述 ㈡,該平板式電 中、格導電層之電阻係數,L、W、T分別為^ 、寬、厚度。 勺等電層的 =·Μ請專利範圍第7項所述之平板 (τ) ’料電層係由鎢金屬或導t高分子構成。 電 1: 2 ·'如申請專利範圍第7 ' 1〇或丄丄 變阻值。 石止氣化改A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs S95145 —----- ¥, patent application scope Manufacture: ¾ • method 'material I coated with grease I change the resistance value.乂 Prevent oxidation _ beautiful material ^-a kind of flat-type resistance capacitor Qm on the high-dielectric constant surface is formed with a copper layer of a suitable area, so that the relative resistance of the steel layer of the 'type capacitor' in the appropriate position on the substrate With high electricity 8 · As described in the application of the reference ㈣ 7 of the flat d product = fixed dielectric Wei and thickness ― controlled area of the copper layer τ to take the required capacitance. 9. If item 7 or 8 of the scope of the patent application is applied, the capacitance of the flat capacitor is based on c = 225_t ^, and the electric capacity is t, where + is the dielectric coefficient of the base seal, and A is the copper layer. + Thickness of substrate. , M 1 is the electrical coefficient '1q. As described in item 7 of the scope of the patent application, the resistivity of the conductive layer of the flat-type electric cell, L, W, and T are ^, width, and thickness, respectively. The flat layer (τ) 'material layer described in item 7 of the patent scope of the isoelectric layer is composed of tungsten metal or t-polymer. Electric 1: 2 · 'as in the patent application range 7' 10 or 丄 丄 variable resistance value. Shizhe gasification reform J In mV wm^i T^I nn I (請先閱讀背面之注意事項再4寫本頁) 、*! 容 每 長 容 本紙張纽適用) α· ( 2ig^騰疫)J In mV wm ^ i T ^ I nn I (Please read the precautions on the back before writing this page 4), *!
TW87116057A 1998-09-28 1998-09-28 Planar type resistor capacitor and the manufacturing method thereof TW395145B (en)

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