TW394993B - Method for etching the bottom anti-reflective coating on semiconductor silicon wafer - Google Patents

Abstract

This is a method for etching the bottom anti-reflective coating on semiconductor silicon wafer.The BARC is located between a photoresist and a poly-silicon coating. After partial removal, a pattern is developed on the photoresist layer, which serves to define the BARC and the poly-silicon coating. The dry etching process is accomplished by exposing the wafer to 10-60 sccm oxygen gas (standard cubic centimeter per minute) and 20-80 sccm chlorine gas to completely remove the patterned BARC.

Description

The invention provides a method for etching a semiconductor wafer by etching a semiconductor wafer with a bottom anti-coating method. Method, especially a -reflective In the semiconductor manufacturing process, yellow light (lithography) and etching (etj) are two very important processes: the yellow light process is a pattern (ph0t〇) on the pattern (pattern) After exposure and development, it is transferred to a semiconductor-resistance photoresist (ph〇t〇_resist). The etching process is to remove the substances on the surface of the semiconductor wafer that are not covered by the photoresist, such as silicon = 111 con) , Silicon monoxide, etc., and then removed by etching, and then the photoresist J is so. All integrated circuit patterns on the semiconductor wafer can be processed. The photoresist is first transferred to the photoresist through the photomask, and then the soil and + conductor sheet are formed. Above. Therefore, how to accurately transfer the pattern on the photomask to the semiconductor through the yellow light 2 engraving material is an important issue in the research of semiconductor manufacturing processes. Jingmai read Figure 1. Figure 1 is a schematic diagram of exposure and development of a conventional semiconductor wafer 10 without an anti-reflection underlayer. The wafer 10 is coated with a photoresist 12, and the pattern on the photomask 15 is transferred to the wafer i 0 through the action of light 14. The exposed area 16 on the photoresist 12 will undergo a chemical change, and then the area i6 will be chemically reacted with the developer to be removed, leaving unexposed areas. A specific pattern is formed on the film 10. However, when the photoresist 12 is exposed and developed, most of the non-parallel light passes through the photomask 5 and is reflected by the light-reflective substance on the surface of the semiconductor wafer 10, so that the photoresist 12 should not be exposed.

V. Description of the invention (2) The light area will be affected by these reflected light and will change chemically. The pattern formed on the semiconductor wafer 10 will be different from the pattern on the original photomask. This pattern error will increase as the semiconductor process shrinks (shrinking), resulting in the line width of the photoresist after exposure and development (af ter

development inspection critical dimension (referred to as ADI CD) is difficult to control. At present, the semiconductor process has entered the sub-micron generation. In response to the defects of the foregoing problems, the method of coating photoresist on semiconductor wafers has also gradually evolved from ordinary single-layer photoresist coating. Add top anti-reflective coating, and now even add anti-reflective bottom layer. Please refer to FIG. 2. FIG. 2 is a schematic diagram of exposure and development of a conventional semiconductor wafer 10 having an anti-reflection underlayer. As shown in FIG. 2, the antireflection bottom layer 20 located between the photoresist 12 and the wafer 10 is an organic photoresist. With the special material characteristics of the antireflection bottom layer 20 and the adjustment of the coating thickness, the antireflection bottom layer 20 will absorb. The light is reflected so that the photoresist 12 is not affected by the reflected light. Only the areas 17 to be exposed will be removed by a chemical reaction, so that the error between the pattern formed on the wafer 10 and the desired pattern is reduced. Please refer to FIG. 3 and FIG. 4. FIG. 3 is a schematic diagram of a conventional polycrystalline silicon gate semiconductor wafer 22 with an anti-reflection bottom layer. FIG. 4 is a conventional etching method of the anti-reflection bottom layer by using the conventional semiconductor wafer 22 shown in FIG. 3. Schematic diagram of the poly-line cross-section. The semiconductor wafer 22 includes a silicon substrate 30 and a gate oxide layer.

I: \ ACC \ Two-dimensional code \ NAU \ NAU-09. PTD Page 5 V. Description of the invention (3) oxide) 32, polycrystalline silicon (pi〇y silic〇n) 34, anti-reflection bottom layer 20 and photoresist 1 The 2 ° light passes through the mask to transfer the pattern on the semiconductor wafer 22, and the anti-reflective bottom layer 20 is not removed with the exposure and development. Therefore, the etching process must first perform the step of etching the anti-reflective bottom layer 20, and then etch the polycrystalline silicon. 34 'finally stops on gate oxide layer 32. It is known that the mixed gas used in the method of the anti-reflection bottom layer of the semiconductor wafer is mainly hydrogen bromide (HBr), oxygen (02), and helium (he 1 ium, He). The etching method of the mixed gas etching method has an etch selectivity of only about 4 for the anti-reflective bottom layer 20 and polycrystalline silicon 34, that is, under this silver etch condition, the etching rate of the anti-reflective bottom layer 20 is about polycrystalline silicon. 3 4 times. Because the main anti-reflective bottom layer 20 is subjected to main etch during the etching, and the remaining anti-reflective bottom layer 20 is removed, that is, over etch. However, the etching selection ratio is only about 4, so when the money is engraved, the effect of etching on the lower polycrystalline silicon 34 will be caused, causing the side-wall of the polycrystalline stone 34 to be tilted and not smooth. Finally, after the polysilicon 34 is etched, the bias of the polysilicon 34's line width (after etch inspection critical dimension (AEI CD) for short) and the photoresistance line width (ADI CD) before the etching will increase. The main object of the present invention is to provide a method for etching the anti-reflection bottom layer of a semiconductor wafer. The present invention can improve the button selection ratio of the anti-reflection bottom layer 20 to polycrystalline silicon 3 4, make the polycrystalline silicon side more flat, and make AD I CD and

I: \ ACC \ Two-dimensional code \ NAU \ NAU-09.PTD page 6.

V. Description of the invention (5) Spar evening layer 34. In the method of the present invention, a dry etch process of the anti-reflective bottom layer 20 is performed in an environment where oxygen of 10 to 60 sccm (standard cubit centimeter per minute) is passed and gas of 20 to 80 seem is passed. In addition, the pressure of the dry etching process ranges from 3 to 10 mm torr, and the temperature ranges from 50 to 75. (:, The top power range is 100 to 300 watts, and the bottom power range is 50 to 200 watts. Because the gas passed in the dry etching process mentioned above will be simultaneously The anti-reflective bottom layer 20 and the polycrystalline silicon 34 produce an etching reaction, and as the oxygen gas is added, the rate at which the chlorine gas eats the polycrystalline dream 34 will decrease. Therefore, after experimental verification, the present invention etches the anti-reflective bottom layer at 20 o'clock. The flow rate of chlorine gas and oxygen gas can make the etching selection ratio of the antireflection bottom layer 20 to the polycrystalline silicon 34 reach more than 10. In this way, when the method of the present invention is used to improve the etching selection ratio of the antireflection bottom layer 20 to the polycrystalline silicon 34, In the etching process of the anti-reflection bottom layer 20, it is not easy to etch the polycrystalline silicon 34, so the sides of the polycrystalline silicon 34 will not be tilted, the sides will be flat, and the deviation between AE CD and ADI CD will be reduced. The invention is applicable Below 0.35em, define the process of the anti-reflection bottom layer and the polycrystalline silicon layer. Compared with the conventional anti-reflection bottom dry etching method, the method for etching the anti-reflection bottom layer of the semiconductor wafer according to the present invention is Dry-etching process under an oxygen gas into 1〇 to 6〇 sccm, and leads to a 20 to 80 seem of gas gas environment under process conditions of the present invention 'antireflective underlayer of polysilicon 34 is etched 2〇

I: \ ACC \ Two-dimensional code \ NAU \ NAU-09.PTD Page 8 394993___ V. Description of the invention (6) The engraving selection ratio will be greatly increased, and the sides of polycrystalline stone will be flat after etching, and AEI CD Deviations from ADI CD will also be reduced. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent. '

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Claims (1)

394993 VI. Scope of patent application 1. A method for bottom anti-reflective coating of a semiconductor chip, which is located on a photoresist layer and a polycrystalline silicon (P 1 0ysi 1 i con) layer In between, the photoresist layer is partially removed to form a pattern, which is used to define the anti-reflection bottom layer and the polycrystalline silicon layer. The method includes the following steps: 10 to 60 seem (standard cubic centimeter per minute) of oxygen and a dry etch process under an atmosphere of 20 to 80 seem gas to completely remove the anti-reflective underlayer with the pattern. 2. The method according to item 1 of the scope of patent application, wherein in the dry etching process, 'the pressure range is 3 to 10 millimeter torr (m torr) and the temperature range is 50 to 75 ° C'. ) Ranges from 100 to 300 watts, and bottom power ranges from 50 to 200 watts. 3. The method according to item 1 of the patent application, wherein the anti-reflective bottom layer is composed of an organic photoresist. 4. The method of claim 3 in the patent application range, wherein the dry etching process selects the etching resistance ratio of the anti-reflective bottom layer to the polycrystalline silicon layer (selectivit can reach more than 10 "