TW394958B - Memory repeat circuit of high-density memory having redundant columns and rows for address storage failure - Google Patents

Abstract

A device repeating structure is suitable for high-density IC memory, such as mask-type read-only memory which employs small layout, two repeating transistor cells. The invention uses the device repeating structure to repair column and row failure. Such memory, using a failed column or a failed row, provides the failed column or row in the memory with a small layout near the memory matrix. A group of redundant columns and rows is arranged beside two new transistor floating gate cell array. The replacement of a selected column or row refers to selecting a logic module. In a row replacement mode, one memory cell in the redundant column is used to show that the row must be replaced and that the data read from the word line that replaces the failure row is effective. In a column replacement mode, one memory cell in the redundant row is used to show that the column must be replaced, and to show that the induced data in the word line that replaces the failure column is effective.

Description

-~~~ -—— 11 -__ 87113071__Hand Yue Yue _ Modification _ V. Description of the Invention (1) _ Field of the Invention: 3 The present invention relates to the design of integrated circuit memory, especially for high-density memory arrays such as Mask type read-only memory. BACKGROUND OF THE INVENTION: In the manufacture of integrated circuit memory components, it is common to provide a repeating interval on the memory on the main array for the array interval that replaces the defect. Therefore, there will be the amount, row, or column of the memory cell on the integrated circuit memory element. After the device is manufactured, all areas on the main array, whether good or bad, must be determined by testing. If it passes the test failure interval, it must replace the chip function of the test failure interval with this repeated interval to store a bit address, and use the electronic circuit that has information on this storage address to reach the repeated interval that replaces the defective array interval. design. This procedure significantly improves the manufacturing yield of integrated circuits. Prior art in this field is U.S. Patent Nos. 3,753,244, 4'047,163, and 4 255057, and have been published, such as

McKinney "A 5V 64K EPROM Utilizing Redundant

Circuitry ", published at 1 980 IEEE Internationai Solid-State Circuits Conference, pp. 146-147. The circuit design of the repeating interval is not widely used in high-density read-only memory, such as mask-type read-only memory. Because the read-only memory cell in a single-frame read-only memory uses a manufacturing step to edit the program, it is not possible to use other read-only memory cells as an extra replacement interval. Indeed, after testing with data from the failure interval, these additional intervals of the read-only memory cell cannot be programmed. So unlike programmable

_Case No. 87113071_ Revised Year of the Month_ V. Description of the Invention (2)-Memory, the memory elements of these arrays are designed to be able to edit programs after manufacture, and repetitive elements are available, but only Read memory circuits cannot use repetitive components.

In read-only memory circuits, a single polycrystalline silicon floating gate transistor has been proposed as a repeating element. For example, an application filed to the United States Patent Office on April 1, 2, 997, with a case number of 08/825, 8 70 (PCT application number PCT / US96 / 1 7300) is entitled " MEMORY REDUNANCY CIRCUIT USING SINGLE POLYSILICON FLOATING GATE TRANSISTORS AS REDUNDANCY ELEMENTS " The inventor is Yiu, eta 1. One problem with using a single polysilicon suspension gate transistor as a repeating component is the very dense memory structure of the curtain read-only memory market. Therefore, in order to comply with the array structure of the curtain read-only memory, the floating gate repeating elements must be arranged in a very dense space. This prevents the curtain-type read-only memory array with a floating pole repeating 70 pieces in the prior art from being fed high. He, a unit cell built on the basis of 埶 孑 bismuth λ ^ ^ 间 间 间 间 可 可 可: can = come to edit the program ... polycrystalline nightmare _) is the unit cell, except the J program only read A good way to memory often core cell. The replacement of memory-only arrays is not as the density of the memory array increases; the cost of applying repetitive components to read-only: body :: 'and improving components to improve yield will not be more compatible than borrowing. important. Good manufacturing yield improved by reset

__Case No. 8liiML__5: _3_i-M- V. Description of the Invention (3)-Purpose and Summary of the Invention: The present invention is to provide a repeating element structure suitable for high-density integrated circuit circuit memory design. This repeating element structure is based on a repeating unit cell with two transistors, which has a relatively small layout compared to the prior art. Modules with row or column failures can be repaired using the repeating element structure of the present invention. Furthermore, the repeating element structure of the present invention can be fabricated using a typical single-metal single-crystal single-crystal, read-only memory system. Another object of the present invention is to use a relatively small layout of extra rows or columns adjacent to the array to supply failed rows or columns in memory. This significantly saves space on the integrated circuit 'because it illustrates the need for a set of additional • address memory arrays in a component to register invalid row or column addresses. In a better system, an additional set of rows and columns is placed next to the array using the two new transistor suspension gate cells. The replacement of one of the selected elements' rows or columns includes a selection logic module. In the replacement column mode, a memory cell line in the extra row is used to show that this column must be replaced and to validate the data read from the character line of the replaced invalid column. In the superseding row mode, a 5th memory cell is used in the extra column to show that this row must be replaced and to validate the sensing data from the character line of the superseding row. Therefore, the present invention provides an integrated circuit memory including at least one array of read-only memories coupled with an array of bit lines and a set of word lines. Several signal amplifiers are coupled to a set of bit lines that sense data values stored in an array relative to the selected row of addresses. Several word line drivers are coupled to a set of word lines and drive a row of memory cells in a bit-relative array with a read potential ^ One programmable memory cell ~

Case No. 87113071 Amendment of the fifth month, description of the invention (4) Outer and programmable bit line couples are also included, and the combination of the character line device and the extra font unit outside the cell line coupling is as follows: Capacity from information. Or the data in the drive coupling list, such as the ability to output data through a large device. If the circuit contains a memory cell signal, an additional driver is placed on the bit line. The driving material of the element line and an extra line with an external signal, logic and, they are anti-material, and coupled with an additional signal from an additional selection line mentioned above and a set of character lines , As well as a line of bit lines and an extra and extra device. A list of programmable memory cells is coupled. This row contains programmable word lines for crystal memory and extra logic lines for extra word lines. Drivers for extra word lines are included. They are specific to program memory that is stored in a set of word lines. The output of the zigzag line dipole is used to instruct several signals to be amplified (such as replacing a specific row in this array) to output additional signal amplifiers and extra word lines should be stored in an additional one of the programmable memory cell. The output of a specific bit line amplifier in a group of bit lines is used to instruct the release of several signals (such as replacing specific columns in this array) and output in a preferred embodiment. Replacement. Used in repeated columns or rows, the present invention also provides a bit line including a combination, and a group of character lines is replaced by an ion implant and parallel to a group of character lines to repeat the abnormal core crystal The word lines are far away from this. The present invention also provides a new floating gate memory cell in an array. Therefore, a set of memory arrays and a set of character pairs coupled with array pairs and arrays. A hidden diffusion provides the word lines of diffusion on a substrate adjacent to the array. A repeating character line is a character line used to cell-couple a group of character lines.

Page 7 Case No. 87113071 Date of Amendment V. Description of the Invention (5). Hidden diffusion character lines. The first and second hidden diffusion regions between the repeating character line and the hidden diffusion character line, and a portion of the repeating unit cell formed between the channel regions of the first and second hidden diffusion regions. A floating gate layout hides the diffused word line here and extends to a repeating word line between the hidden diffused word line and the first hidden diffused area and a channel region between the first and second hidden diffused areas . A third hidden diffusion region is located adjacent to the repeating word line and opposite the second hidden diffusion region. Therefore, the second hidden diffusion region can be regarded as a source terminal, and the third hidden diffusion region can be regarded as a drain terminal. The repeating word line can be regarded as a gate transistor. A first contact window is between the first hidden diffusion region and a first bit line in a group of bit lines, and a second contact window is between the third hidden diffusion region and a group of bit lines. The second bit line of the bit lines. In a preferred system, the character lines in a group of character lines contain at least a conductive metal such as polycrystalline silicon, and the repeated character lines contain at least the same conductive metal, so that the same mask step can be used. The group of word lines includes at least a metal line formed on a metal layer overlying the polycrystalline silicon. The first and second contact windows include at least first and third hidden diffusion regions and first and second bit lines on the metal layer. According to another aspect of the present invention, a bit line in a group of bit lines includes an array of vertical conductors covering an array of memory cells, and the group of word lines. The first and second bit lines include the bit lines extending vertically to the first and second contact windows, in particular, within the repeating unit cell. In the integrated circuit memory, several repeating unit cells are supplied as above, meeting all levels of memory arrays, because the circuit layout supports bit lines on the repeating unit cells. More than a repeating unit cell is needed in order to replace one

Page 8 Case No. 87113071 Modified repeating circuit structure Makes easy layout and reads the memory to study, the complex circuit is achieved. Programmable memory of the present invention having simple blocks of components is the suspension of the prior art. The suspension of the prior art is the invention of the present invention. The invention has the fifth aspect of the invention. (6) Screen-type read-only memory cell According to another preferred replacement line of the present invention, the read-only memory cell phase of the mask type. Expanded word lines on an array according to this preferred embodiment. According to another aspect of the present invention, the transistor in the repeating unit cell is accompanied by a single array of memory. The body element of the present invention is made in a curtain mode. Only the weight of the invention is important. Briefly explain the diagram: The read-only memory row shown in the first figure replaces the module brother—the circuit layout shown in the fourth figure shown in the third figure and the fifth figure shown in the fourth figure. Bits are fully loaded, for example when there are two for each metal bit line. In an embodiment, the repeating cell line provides one, and the hidden long diffused word lines are parallel to the word lines in the array and vertically extend on the channel area. In the preferred embodiment, a repeating row and a repeating row are supplied. The read-only memory for high-density curtains is small and efficient. The improvement of the production yield can be provided by the title. The various benefits will be described in the following description drawings and invention details in the scope of application rights. Note: Repeating one of the rows and columns with a programmable cell The figure contains substituted columns and rows with selectable column modules or cells. The design of the floating gate repeats the unit cell. Floating gate repeats the circuit layout of the unit cell. Suspended gate unit cell of two transistors. Suspended gate unit cell of two transistors

Page 9 Amendment No. 87113071 V. Description of the invention (7) The sixth diagram is a block diagram of the present invention with integrated circuits. The seventh figure shows a block diagram with integrated circuits of the present invention. Figure 8 shows a column of the invention. Figure 9 shows a block diagram of a column of Figure 8. The tenth figure shows one row of the present invention. The eleventh figure shows one block diagram of the tenth figure. Description of drawing number: 1 0 read-only memory array 1 2 bit lines 1 4 additional columns 16, 18, 20 lines 1 9 signal amplifier 1 0 0 first bit line 1 0 2 repeated word line 1 0 5 hidden diffusion Line 1 0 7 Suspension gate 11 0, 111 Metal contact window 2 0 0 First bit line 2 0 2 Hidden diffused character line 204, 205 Repeated character line-Replacement of the mask type read-only memory-Replacement of the column The block diagram of the operation of the mask-type read-only memory to replace the module. Block diagram of the operation of the replacement module. The timing of the operation of the module instead of the module 1 1 word line 1 3 extra line 1 5 decoder 1 7 decoder 2 1 control logic 1 0 1 second bit line 1 0 3 third bit line 1 0 6 N-type well 1 0 8, 1 0 9 hidden diffusion area 11 2 back contact window 2 0 1 second bit line 203 second hidden diffusion line 21 0, 2 11 bit line

Amendment on page 10 of case number 87113071 _ V. Description of the invention (8) 2 2 0, 221 contact window 22 2 hidden diffusion area 223 second hidden diffusion area 224 third hidden diffusion area 2 2 5 suspension gate structure 3 0 0 Array 310, 311, 312, 313, 314 Hidden diffusion word line 320 > 321 '322' 323, 324 '32 5' 326 '327, 328' 3 29, 334, 3 3 5 Repeat unit cell 40 1 Line 40 6 Vertical expansion 40 8 Second repeating data 41 0 ~ 4 1 5 Repeating unit cell 42 3 Contact window 801 (replace column) Boxes 803, 804 Area 80 6 Second unit cell 808 Fourth unit cell 8U, 812, 813 Diffusion area 820 signal amplifier circuit 831 additional signal amplifier 83 3 lines 8 5 1 graphics 853, 856, 858 graphics 870 select transistors 872, 873, 875 lines 3 5 0, 3 5 1, 3 5 2, 3 5 3 local bits Element line 400 array 402 Arrow 407 First repeating data 40 9 line 4 2 1 Ground line 8 0 0 (replaces row) Box 8 0 2 Ground bit line 80 5 First cell 8 0 7 Third cell 8 1 0 replaces the word line driver 8 1 4, 8 1 5 cell 821 line 8 3 2 selects the module circuit 850 time interval 852, 854, 860 time 855, 857, 859 points 87 1 circuit

Page 11 Case No. 8Ή13071_ Month Revision V. Description of the Invention (9) 887 graphics 8 9 5, 8 9 6 time period 874 signal amp repeat control logic 8 7 6 display line module replacer 8 8 1, 8 8 3 880, 882, 884, 885, 886, 890, 892 89 893 data 894 line 897 time interval invention detailed description: The first figure shows the present invention has a read-only memory with one of the repeating rows and columns using a programmable cell element. Therefore, this element contains a curtain-type read-only memory array 10 such as U.S. Patent No. 5, 1 1 7, 389 " FLAT CELL READ-ONLY INTEGRATED CIRCUIT " The inventor is D.H. Yiu. Maybe other read-only memory can be used, including the use of a mask-style program to edit the program. According to the repeating circuit structure shown in the first figure, the array includes a set of word lines 11 and a set of bit lines 12 that can be reached by the respective unit cells in the array. There is an extra row 1 3 and an extra column 1 4 in the element. The extra row 1 3 contains a row containing a programmable memory cell coupled to a group of character lines 11 by extending the character line 11 A. This extended word line 11 A is coupled with a column of decoders 15 which are the addresses of lines 16 to drive the word lines of a group of word lines 11 in the array. In this embodiment, the character lines in a group of character lines 11 are driven by an extended character line 11 A coupled with an additional row 1 3. The additional row 14 is coupled with a group of bit lines 12 in the extended bit line 1 2 A in the array, so that at least the programmable memory cell is coupled with each bit line of a group of bit lines 12 . Extension bit line 1 2 A is coupled with decoder 1 7 of a row

Page 12 ____ Case No. 87Π3071 V. Description of the invention (10) Month and year Amendment «‘ This decoder 17 is based on the address on line 18 to select a specific row in the array. Several signal amplifiers 19 and decoders 17 are coupled to provide data such as output on line 20. According to the present invention, the control logic 2 includes an additional word line driver including a replacement column including an additional row 1 ^ additional signal amplifier and an additional column i 4. The $ Editor responds to the memory cell stored in the extra row 3 and is coupled to a specific word line of a group of word lines 11 as indicated by the input f of the additional signal amplifier to make several signal amplifiers have Ability to output data from a specific list of amounts). In the row-replacement mode, the "7" reaction is stored in the memory cell in the additional row 14 and the specific character line of the line 12 is coupled as follows: The outputs of the signal amplifiers in the several signal amplifiers 19 instruct the extra signal amplifier wheels in the several signal amplification logics 21 to be replaced in the control in a specific column of this array). Xingchuan Ru control logic 21 includes-module selection circuit, in the preferred embodiment, the contents of the addressable memory cell to move = set up rows at the time of manufacture. Another 70 rows and replacements

—-N Therefore, in testing a defect in the read-only memory array 10 shown in the first figure, a memory element is stored, and a column address or a row address is stored in the programmable storage h. . This defect is listed in row 14, especially in this preferred embodiment. (External row 13 or the path provided by the editing program circuit. The editing process borrows the data from the defect row to provide editing for the floating gate unit cell.裎 ^ ^ replaces column 14. This path is provided by using a charge pump in the chip.

Amend __Case No. 87113071 V. Description of the invention (Π) The output of the supplier, or it is covered by other previous techniques. -The repeating circuit shown in the first figure is the storage of the defective column or row address in the replacement column or row. Other systems replace the column component address comparator and the one-bit output buffer with defective addresses. Logic circuits that replace the defective columns or rows instead of columns and rows may be provided by other prior art. The second and third figures are not the circuits and circuits of the two repeating unit cells of the single suspension gate transistor of the prior art. The four complex cells and the accompanying memory array shown in the second figure are the first. Yuan line 100 is coupled with a second bit line ιι. The drain of the first floating gate transistor M1 and the source of the second floating gate transistor M2 are connected to the second bit line i 〇 丨Coupling. Repeating the character line! 〇〗 and a second character line 103 are coupled to the control gate transistors M1 and M2 respectively. The control gate includes a hidden diffusion control gate coupled to a rear contact window ( As described below) is coupled to the repeating word line. The second figure is the circuit layout of the unit cell of the first figure. As shown in the third figure, a repeating word line 1 0 2 Crystalline silicon. A hidden diffusion line 105 and a repeating word line 〇〇2 run across the array in parallel. This hidden diffusion line 105 is an independent p-type diffusion line, which is supplied in an N-type well. A 11 T-shaped " floating gate electrode 107 has a first area covering the hidden diffusion line 105, and a second area expanding downward As for the area above the channel of the floating gate. A hidden diffusion area 丨 08 provides the source of the floating gate, and a hidden diffusion area 109 provides the drain of the floating gate. A channel area is at this floating gate 10 7 Bottom. The metal contact windows 丨 丨 and i 丨 丨 provide contacts between the hidden diffusion regions 108 and 109 and the metal bit lines 100 and 101.

Page 14 Case No. 87113071 Rev. V. Description of the Invention (12) Hidden diffusion region 1 0 5 Provides a polycrystalline silicon metal plug diffused to the hidden diffusion region to repeat word lines through a back contact window 1 1 2 In contact with the repeating character line 102. In the repeated cell of this prior art, in addition to providing the back contact window by a metal region 1 12, the metal contact windows 1 10 and 1 1 1 are used to make contact with the metal bit lines. When the cell between bit lines 100 and 100 is suitable, the circuit layout will be quite large. The circuit design of the cell region according to the prior art is approximately 5.9 micrometers higher than the upper 6.4 micrometers.

It is desirable to provide a smaller, denser floating gate repeating unit cell. In addition, it is desirable to provide a suitable repeating cell structure of repeating rows and columns. The fourth figure shows the repeating unit cell of the present invention. In the fourth figure, the two unit cells are between a first bit line 2 0 0 and a second bit line 2 0 1. Here, In the embodiment, the first bit line 2 0 0 is a ground line and the second bit line 2 0 1 is a data line. The first repeating unit cell includes the suspended gate transistor M 2 and the flow-through gate transistor M 1. The drain of transistor M 2 is coupled to this first bit line 2000. The source of transistor M2 is connected to the source of transistor M1. The drain of the transistor M 1 is connected to the second bit line 201. A hidden diffusion character line 202 is a control gate for the floating gate cell M2. A specular imaging unit cell (as shown in the fourth figure) includes a suspended unit cell M4 and a galvanic crystal M3. The drain M4 of the floating gate transistor is connected to a first bit line 200. The source M4 of the floating gate transistor is coupled to the source M3 of the floating gate transistor. The drain M3 of the current-carrying crystal is connected to the second bit line 20 1. The control gate M4 of the suspended gate transistor and a second hidden diffusion line 203. Repeating character lines

Page 15-Case No. 87113071_Year Month Day Amendment_: V. Description of the invention (13) 204 and 205 are connected to the gate electrode JJ3 of the flow transistor and Ml. By controlling the repeating word lines, the flow-through transistors M3 and Mb are used to reach a unit cell. This repeating word line raises its potential to be the same as the hidden diffusion word line. The circuit layout of the repeating unit cell shown in the fourth figure is shown in the fifth figure. The fifth figure shows that four unit cells are coupled with a group of four-bit lines such as bit line 2000, bit line 201, bit line 21, and bit line 21. These bit lines cover the top of the array, and include bit lines that extend vertically to the masked read-only memory array. The contact windows 2 2 0 and 2 2 1 provide a first cell contact between the bit line 2 0 0 and the bit line 2 0 1. The contact window 2 2 0 and a hidden diffusion region 222. A second hidden diffusion region 223 is between the contact windows 22 0 and 221. A third hidden diffusion region 224 separates the hidden diffusion region 224 and the hidden diffusion region 223 through the contact window 221 and the metal wire 20 and a channel region. The repeating word line 204 covers a channel region between the hidden diffusion region 224 and the hidden diffusion region 223. This is a transistor built on the corresponding transistor M1 of the fourth figure. At the same time, a channel area separates the hidden diffusion area 2 2 2 and the hidden diffusion area 2 2 3. A polycrystalline silicon suspension gate structure 2 2 5 covers the channel region between the hidden diffusion region 2 2 2 and the hidden diffusion region 2 2 3 as an expansion. It extends from the vicinity of the hidden diffusion area 22 2 to the hidden diffusion word line 202. The floating gate structure 2 2 5 includes a portion of a hidden diffusion word line 2 0 2 extending between the first bit line 2 0 0 and the second bit line 2 0 1. The hidden diffusion word line 2 0 2 acts as a control gate for this floating gate unit cell and passes through the floating gate element 2 2 5 and the passage between the hidden diffusion region 222 and the hidden diffusion region 223 Regional overlap

Page 16 Γ --- Year-Month-Day 仏 V. Description of the Invention (14) ~ ~-Combination. The transistor M3 and the floating gate transistor M4 are arranged in a mirror imaging element near the contact window 22. A cell trip is between bit line 2 丨 0 and bit line 2 丨 丨. As shown in the fifth figure, the circuit layout of the repeating unit cell is about 5.3 micrometers and 2.9 micrometers wide for the process of the 0.4 micron mask-only read-only memory. This width is only half as shown in the third picture of the previous art. a The repeating unit cell shown in the fifth figure does not have a back contact window in the third figure. This makes the cell circuit layout denser and can be compatible with the decoder without any modification under the bit line metal of the flat read-only memory at this stage. Furthermore, for the process of 0.4 micron flat read-only memory, the circuit layout area is only one and a half of the previous technology. The current consumption of the unit cell of the fifth figure is only slightly larger than that of the unit cell of the second figure. In any case, this difference is not enough to constitute degradation to normal timing. The sixth figure shows the replacement of the present invention and the supply. The sixth figure is a part of the mask-only read-memory cell array 300. The array 300 includes a set of word lines WLO, WL1 and a set of bit lines GLO, BLO, GL1, BL1, GL2. " Between the parent bit lines, such as GLO and BLO, there are two flat read-only memory cells. The unit cell of the flat read-only memory is detailed in US Patent No. 5,117,389. In the array 300, there are local bit lines 350, 351, 352, and 35. The left and right rows are used to select transistors when the path is as described in U.S. Patent No. 5,11,389. This bit line contains a replacement portion that vertically expands from the array 300 to the integrated circuit. This replacement part contains several hidden diffusion character lines, including hidden diffusion character lines 310, 311, 312, 31 3, and 314. In array 300, hide

Page 17 Case No. 87113071 Month, day Amendment _: 5. Description of the invention (15) The diffuse character line is parallel to the character lines WLO, WL1. Several repeated character lines RWL0-RWL7 are parallel to the far away hidden diffusion character lines. The hidden diffusion word lines are polycrystalline silicon, as in the array 300, the word lines WLO, WL1. The repeating unit cell is as described in the third and fourth figures. Therefore, the repeating unit cell 3 2 0 and the repeating unit cell 321 are between the hidden diffusion word line 310 and the repeated word line RWL0. The repeating unit cell 3 2 2 and the repeating unit cell 3 2 3 are between the hidden diffused character line 3 1 1 and the repeated character line RWL 1. The repeating unit cells 3 2 4 and 3 2 5 are between the hidden diffused word line 31 1 and the repeated word line RWL2. The repeating unit cells 32 6 and 32 7 are located between the hidden diffusion word line 3 1 2 and the repeating word line RWL3. The repeating unit cells 328 and 3 2 9 are between the hidden diffusion word line 31 2 and the repeating word line RWL4. The repeating unit cells 3 3 0 and 3 3 1 are between the hidden diffusion word line 3 1 3 and the repeating word line RWL5. The repeating unit cells 334 and 335 are between the hidden diffused character line 31 4 and the repeated character line RWL7. Therefore, in the array 300, there are sixteen repeating unit cells coupled with eight repeating word lines. This will be used to replace two defective columns in the array 300. To control the array, all hidden diffused character lines 3 1 0-3 1 4 are coupled together or driven in parallel. The repeating word lines RWL0-RWL make eight repeating arrays instead of two normal word lines. The repeated character lines i and RWL3 are driven. Repeated character lines RWL4 and RWL6-start driving When repeated character lines RWL5 and RWL7-start driving. In the main array 300, since there are two unit cells for each bit line, there are left row and right row decoding structures to supply, as in the prior art. The left and right decoding structures (as shown in the seventh figure) are used to drive the repeated word lines RWL0 and RWL2 to select the unit cell 3 2 0 on the left of the bit line BL0 or the bit line BL 0 The right side of the unit cell 3 2 4.

____ Case No. 87Π3071_ Year, month, and month of amendment ___- 5. Description of the invention (16) As shown in the fifth figure, the horizontal position of the repeating unit cell is the layout of the bit lines of this group in the array 3 0 0 More suitable. The bit line provides a vertical expansion by repeating the rows, and this row can easily decode the replacement of the abnormal column in the array 300. Figure 7 shows a component layout using a replacement line. According to this embodiment, the array 400 is described in U.S. Patent No. 5 1 7389. There are several character lines. The character line driver can be shared with eight character lines, columns. Therefore, this word line WL0 is coupled to the unit cell as shown in line 40 1 in seven other rows. Therefore, if it is a vertical position of less than eight rows in the array, the vertical position of the repeating unit cell is suitable between the drives. The character line WL1 and the other lines shown in arrow 402 are coupled to the seven other rows in the unit cell. Yuan line. At the same time, the word line WL2 includes a vertical extension 406. In the device, the repeating bit line includes a first repeating data line 40 7, —the second repeating data line 408 and the ground line 421, and the repeating bit line includes a metal line such as a bit line in a main array. This hidden diffused word line provides the control gate for this floating gate transistor in the array with the word lines WL0-WL2, and within the repeating cell 4 1 0-4 15. All hidden diffused character lines BDWL s are coupled with line 409. The repeating unit cells 4 1 0 and 4 11 share a contact window 4 2 3 to a ground line 4 2 1. Repeating bit lines 4 0 7 and 4 8 are coupled to the repeated control gates for use in place of rows. According to the layout of the seventh figure, if one row in the main array can be replaced, eight sets of repeated rows are needed. Figure 7 shows only two lines. The eighth, ninth, tenth, and eleventh circles show the replacement of columns and rows by the control logic of the present invention. For the replaced columns, the extra rows are used to identify the invalid rows, and for the replaced rows, , Additional columns are used for identification

Case No. 87113071 Month, Amendment V. Description of Invention (Π) Its invalidation. See Figures 8 and 9 for operations on column substitution. In the eighth figure, the unit cell in the replaced row is shown in box 800 and the unit cell in the replaced column is shown in box 801. In the replacement row box 80 0, a repeated bit line RBL0, a ground bit line 802, and a repeated bit line RBL1 are shown. In the array, the character lines WL0 and WL1 cross the repeated rows of blocks 8 0 0 and expand to the regions 80 3 and 8 0 4. A first unit cell 805 and a second unit cell 806 are interposed between the ground line 802 and the bit line R B L 0. A third unit cell 708 and a fourth unit cell 808 are coupled between the ground line 802 and the bit line RBL1. In this embodiment, the unit cell 805 edits the program at a high starting potential. At this time, the unit cells 806, 807, and 808 have a low starting potential. In the substitute column block 801, the duplicate character line RWL0 and the duplicate character line RWL1 are coupled with a substitute character line driver 810. Meanwhile, the unit cell in the replacement column 801 is coupled to the bit line, which, in the main array, includes the ground line GL0, the data line BLO, and the ground line GL1. By expanding the regions 8 11, 8 1 2 and 8 1 3 respectively. Therefore, in the repeated column block 801, the unit cells 8 1 4 and 8 1 5 are connected with the bit lines G L 0 and B L 0 to the repeated word lines r w L 0 and RWL1. The bit line includes a bit line BL0 coupled to a signal amplifier (shown in block 820). In an actual system, the row selection circuit and other circuits include a signal amplifier interposed between the arrays. This signal amplifier is provided for signal data output on the line 8 2 1. The control logic of the present invention includes an additional signal amplifier 831 and a selection module circuit 832 in addition to the repeated word line driver 8 10. Extra signal ampere 831 and repeating bit line RBL0 and RBU.

Page 20 __ Case No. 87113071 V. Description of the invention (18) Che Yueyue Correction In the column module, the timing operation of the circuit is shown in the ninth figure. In the ninth figure, a time interval of 850 is valid for passing an address of one of the main arrays. The hidden diffusive character lines of the repeating columns and rows are located at a high potential as shown in the figure 851. In this embodiment, the sister code causes the word line WL0 to be driven to a reading potential within time 852 when the word line WL1 is maintained at the ground potential as shown in the graph 853. In time 854, the bit line GL0 is driven to the ground potential while the bit line BL0 is maintained at the pre-charge potential in order to select a row between the bit lines BL0 and GL0. For column substitution, the state of unit cell 805 coupled to bit line RBL0 and bit line WL0 is induced at point 855. Because the unit cell 8 0 5 has a high starting potential, the induced ampere 8 3 1 will cause the repeated word line RWL0 to drive a read potential at point 857. The repeating bit line R B L1 is maintained at this ground potential as shown in the figure 8 5 6. The repeating word line RBL1 is maintained at this ground potential as shown in a graph 858. While driving the repeated word lines, the decoders in this row cannot be activated for the word lines WL0 and WL1. This causes the signal amplifier circuit 820 to sense the data on the bit line BL0 at point 859, with the result that the data output is read from the replacement column 801 within the time gw. In this example, the replacement cell 8 14 in the repeating sub-line RWL 0 is regarded as a read-only memory cell position through the word line wL0 and between the bit lines GL 0 and BL 0 One of the addresses. The logic of the two hosts M1 and M1 is also derived from the online 83: signal makes it impossible to start. For this column of decoders in a normal array, when a specific column is reached, it will save an extra 8 η 1 & ib. ... It detects that a particular row will be picked up by an additional row 80. In this embodiment of the present invention, for each of the two, it is necessary Have

_ Case number 87113071_ V. Description of the invention (19)

Fixed Substitute rows can be used with a single-line editor to indicate a particular row in this array where a substitute row is used.

From the appropriate parameters of the tenth and eleventh diagrams to the elements of the eighth diagram, the organization of the replacement line can be understood. For example, the replacement row 800 and the replacement column 800 J are shown. A Y-select transistor 870 is activated in order to activate the signal of the replacement column as a discriminator of the replacement row. At the same time, the output of the signal amplifier circuit 820 on line 821 is supplied to a " reverse " circuit 8n. " Reverse " The output of circuit 871 is supplied on line 8 72 to provide the data value stored in the replacement line 8 00. This normal signal female training 820 also supplies its output to the line, such as the Xi signal to a signal amp repeat control logic 874. The signal amp repetitive control logic 8 7 4 should respond to the output of the additional signal amplifier 8 3 1 and the signal REDS on line 8 7 3 to generate one of the control signals DAF on line 8 75. This line 8 7 5 疋 controls The reverse circuit 8 7 1 in order to determine the appropriate information to provide to the line 8 7 2 is shown in place of the line 8 0 0. At the same time, a module selection circuit, such as a display line, the addressable memory of the module replacer 8 7 6 and the control logic 8 7 4 are coupled to start the line replacer.

Figure 11 shows the timer for the replacement line. The address of a replacement module in one line is invalid during the period 880 shown in Figure 11. This hidden diffused character line is charged to the supply potential as shown in figure 881. This column decoding causes a bit line in the array to drive an interpretation potential of the word line WL0 between time periods 882. The sub-element line WL1 maintains this ground potential as shown in the figure 883. The bit line G L0 drives the ground potential at the time period 884 to select a row between the bit line GL0 and the bit το line BL0 in the array. In order to activate the replacement line, this selection transistor 870 will be accompanied by a control signal which is at ground potential during time period 88 5

Page 22 ___Case No. 87113071_Year Month 3 Work 5. Invention Description (20) YRP to drive. At the same time, the word line RWL0 is driven instead of the word line RWL0—the potential is read. The replacement column RWL1 is at a ground potential as shown in Figure 887, and when coupled to the repeated RWL0 column is used to select a repeated row. Along with the repetition of the sub-line R W L 0 and the bit line BL0 to the reading potential in the repeating array, the signal Amp 8 2 0 generates this output r e D S at the time period 8 9 0 to correspond to the data 891 on the bit line BL0. The repeating signal amp 831 and the signal amp control circuit 874 generate a signal DAF in the time period 892 to correspond to the data 8 93 of the repeating bit ^ RBL0. The repeat bit line RBL1 is maintained at a ground potential as shown by line 8 9 4. In the time period 89 5, the control signal YRP and the replacement word line RWL0 are driven to the opposite state. This connects the main array to this signal amp circuit 8 2 0, and the circuit 8 (Π) that turns off the extra rows. In the time period 896 bit lines BL 0 reflect the actual data of the rows stored in the array are displayed by the word line WL 0 In the defective row. In any case, the DAF signal in the time period 892 shows the actual data output. The signal Amp 820 supplies the signal on line 82 1, this line 82 丨 may have incorrect data because it is invalid in the time interval 897. How, the DAF signal generates the bounce circuit 871, or the data stored in the array. This should be stored as 10 but reversed by the bounce circuit 8 71. If the data in the array is correct, the knife may not be bounced. The inverted and substituted rows of circuit 8 71 store a value. This actual array data is correct for this column. Therefore, in this ΐ !! ，, if four data bits are read in a particular row, 11 丨, but This is expected to be 10 1 0, and then repeated rows will be stored 〇i 〇 Bu This causes this jump 4 to reverse the data stored in the second and fourth columns to the correct value. Or, right read 0 0 in the array 0, but the correct information is 101〇 Then repeat

Page 23 _Case No. 87113071_ Year Month Amendment _ V. Description of the Invention (21) The information in line (1) is 1 0 1 0. This causes the first and third bits in the array to be inverted from 1 to 0. The present invention allows the use of additional rows and columns to replace the registration of additional addresses for the storage of this address for failed columns and rows, such as prior art. In any case, this single repetitive unit cell can be adapted to use more failed addressing techniques. A repeating structure provides a repeating cell with two transistors with a circuit layout that is only half the space of the prior art. Both invalid rows and invalid columns are suitable for use with the repeating structure of the present invention. At the same time, this repeating array can be used not only for password replacement but also for the supply of invalid address registration. Various modifications and choices of this invention will become apparent to those technologies that do not depart from the spirit of this invention in this field. I should understand that this invention is not intended to be improperly restricted by the specific examples described therein. Such examples and contents are expressed in the manner of examples. Within the scope of this invention, it is only intended to be limited by the scope of the following patent applications.

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Claims (1)

_Case No. 87113071_Amendment of the Year and Month_ 6. Scope of Patent Application 1. A integrated circuit memory including at least: an array of read-only memory cells; a set of bit lines coupled with the array; several A signal amplifier coupled to the group of bit lines, and the signal data is stored at a relative address in a selected row in the array; a group of word lines coupled to the array; a plurality of word line drivers coupled to the driver A group of word lines, the driver drives a row of memory cells that take a read potential to a relative address in the array, a row of programmable memory cells coupled to the group of word lines, including a coupling to An extra bit line for the trip of the programmable memory cell and an extra signal amplifier coupled to the extra bit line; a row of programmable memory cells coupled to the set of bit lines, including a coupling to An extra word line on the trip of the program memory cell and an extra word line driver coupled to the extra word line; and a logic coupled to the extra signal amplifier and the extra word line driver, The extra word line driver is to reflect the data stored in the extra row of the programmable memory cell, and the logic is coupled with a specific bit line in a set of bit lines to pass the extra The output of the signal amplifier indicates that several signal amplifiers are capable of outputting data from an additional row (such as replacing a specific row in this array). 2. The integrated circuit memory according to the first item of the claim, wherein the programmable memory cell in the additional column includes at least: a diffusion word line isolated from the additional word line; Page 25_Case No. 87113071_ Amendment Date 6 、 Applicable Patent Scope: The Second and the First Intervals of the Expansion Line The area is extended from the source of the third terminal of the expansion path to the first phase of the area. The area of the area is extended and the area of the second area is dispersed and expanded and the hidden line is hidden. In the neighboring areas of the area, the area is separated and expanded, and the terminal end is integrated into a crystal. When the electricity is turned off, the area is dispersed, and the area is hidden, and the hidden line is the ternary word. 1Β-1 The expansion of the edge and the periphery of the spear j and the spread of the scattered characters in the domain line area hide and conceal the concealment, and the concealment and dispersal of the floating line pole spread gate in the local line and the hidden concealment. Expansion of the area in the area of the area of the area of the road. Enlargement of the area. Separation of the area. Enlargement of the first area. The second area is the first. The first line and the second line of the second line are the ones, and the first line of the first line and the first area of the field are scattered. In the possession of three-membered hidden line. Grouping this line should be like Yuanyuan Sanru L »ground, body # 体 忆 彳 忆 己 一己 is0 '= 0 containing electricity, electric body to body product description, 1- > i' bit β term item 2 1 The first 丨 the perimeter of the perimeter t, it is already. 巳 β Deaf 彳 彳 彳, 权 青青 目 = 0 t-5 Bozhong I- Zhonghai-6 The line should be its own = ° Read Wei Cheng Ke-style curtains contain cell crystals with as few as columns. The memory cell is called aB. The memory is only five. The electrical volume of the seed contains as little as., The unit cell of the line element array is a d crystal unit. The memory array reads the array. Only the 1 and storage materials are required. & ϋ # 讯 线 ； The meta-address bit group selects the big one to select the largest pair in the middle. 1 Page 26_Case No. 87113071_Amendment of the month of the year_ Sixth, the scope of the patent application is a set of word lines coupled with the array; several word line drivers are coupled to the set of word lines, and the driver drives a Take the read potential to the row of memory cells at the relative address in the array, a row of programmable memory cells coupled to the set of word lines, including a row coupled to a programmable memory cell Extra bit line and an extra signal amplifier coupled to the extra bit line; a row of programmable memory cells coupled to the set of bit lines, including an extra line coupled to a row of programmable memory cells A word line and an extra word line driver coupled to the extra word line; and a logic device coupled to the extra signal amplifier and the extra word line driver, wherein the extra word line driver is responsively stored in a programmable memory The data in the extra rows of the bulk cell, and the logic device is coupled to a specific bit line in a set of bit lines to indicate the use of additional signal amplifier outputs to direct the use of several signals The amplifier has the ability to output data from an additional row (such as replacing a specific column in this array). 6. The integrated circuit memory according to item 5 of the scope of application rights, including an extra line coupled with the program memory unit cell to the extended characters in the set of character lines in the set of character lines in the array Line, wherein the programmable memory cell in the additional row includes at least: a diffusion word line isolated from the additional word line; a line between the diffusion word line and the additional word line The first and second diffusion regions, and a channel region between the first and second diffusion regions, Page 27_Case No. 87113071_Amended in January / Year_; 6. The scope of patent application is a third diffusion area adjacent to the extra word line and opposite to the second diffusion area, so the second hidden diffusion area can be regarded as a The source terminal, the third hidden diffusion region can be used as a drain terminal, and the repeating word line can be used as a gate transistor;-the floating gate layout hides the diffusion word line and extends between the hidden diffusion A character line and a repeating character line around the first hidden diffusion region and a channel region between the first and second hidden diffusion regions; and a first contact window between the first hidden diffusion region and a The first bit line in the group of bit lines and a second contact window are between the third hidden diffusion region and a second bit line in the group of bit lines. 7. The integrated circuit memory according to item 6 of the scope of application right, wherein the first bit line includes at least one ground line. 8. The integrated circuit memory according to the fifth item of the claim, wherein the array of the read-only memory cell includes at least a mask-type programmable read-only memory cell. 9. An integrated circuit memory including at least: an array of read-only memory cells; a set of bit lines coupled to the array; a plurality of signal amplifiers coupled to the set of bit lines, and signal data stored in The relative address in the selected row in the array; a set of word lines coupled with the array; a number of word line drivers coupled to the set of word lines, the driver driving a read potential to the array Relative address memory Page 28_Case No. 87113071_Amendment of the month of the year_ Sixth, the scope of the patent application unit; a row of programmable memory cells coupled to the group of word lines, including a coupled to programmable memory An extra bit line for the trip of the unit cell and an additional signal amplifier coupled to the extra bit line; a row of programmable memory cells coupled to the set of bit lines, including a coupled to a programmable memory cell The extra word line of the cell and an extra word line driver coupled to the extra word line; and a logic device coupled with the extra signal amplifier and the extra word line driver, wherein the logic device has a first module , Where the first module reflects data stored in an extra row of the programmable memory cell, and the logic is coupled with a specific bit line in a set of bit lines to pass the additional The output of the signal amplifier indicates that several signal amplifiers are capable of outputting data from an additional row (such as replacing a specific column in the array), a second module, wherein the second module is a reactive storage Data in additional rows of the programmable memory cell, and the logic is coupled to a specific bit line in a set of bit lines to direct the use of additional signal amplifier outputs to indicate the use of several signals The amplifier is capable of outputting data from an additional row (such as replacing a specific column in this array), and a module selection circuit selected by the first and second modules. 10. The integrated circuit memory according to item 9 of the scope of the application right, wherein the programmable memory cell in the additional column includes at least: a diffusion word line isolated from the additional word line; First and second between the diffused character line and the additional character line Page 29_Case No. 87113071_Amendment of the month of the year_ Six. Patent application scope diffusion area and a channel area between the first and second diffusion areas; one adjacent to the extra word line and the second The diffusion region is opposite to the third diffusion region, so the second hidden diffusion region can be used as a source terminal, the third hidden diffusion region can be used as a drain terminal, and the repeating word line can be used as a gate transistor; a suspension The gate layout here hides the diffused character line and extends to the hidden diffused character line and a repeating character line around the first hidden diffused area and the channel area between the first and second hidden diffused areas; And a first contact window is between the first hidden diffusion region and a first bit line in the set of bit lines, and a second contact window is between the third hidden diffusion region and a The second bit line of the group bit lines. 11. The integrated circuit memory of claim 10, wherein the first bit line in the group of bit lines includes at least one ground line. 12. The integrated circuit memory according to item 9 of the scope of application right, wherein the array of the read-only memory cell includes at least a mask-type programmable read-only memory cell. 13. The integrated circuit memory as described in the ninth item of the scope of application rights, including an extra line coupled with the program memory unit cell to the extended word in the set of word lines in the set of word lines in the array Element line, wherein the programmable memory cell in the additional row includes at least: a diffusion word line isolated from the additional word line; between the diffusion word line and the additional word line First and second Page 30_ Case No. 87113071 6. The scope of the patent application is to modify the diffusion area and a channel area between the first and second diffusion areas; one adjacent to the extra word line and opposite to the second diffusion area The third diffusion region, so the second hidden diffusion region can be used as a source terminal, the third hidden diffusion region can be used as a drain terminal, and the repeated word line can be used as a gate transistor; The hidden diffusion character line and a repeating character line extending between the hidden diffusion character line and a periphery of the first hidden diffusion area and a channel region between the first and second hidden diffusion areas; and a first The contact window is between the first hidden diffusion region and a first bit line in the set of bit lines, and the second contact window is between the third hidden diffusion region and a bit line in the set The second bit line. 14. The integrated circuit memory according to item 13 of the scope of application right, wherein the first bit line in the set of bit lines includes at least one ground line. Page 31