KR100723569B1 - Phase change memory device - Google Patents

Abstract

The phase change memory device includes a semiconductor substrate; A plurality of cell arrays stacked on a semiconductor substrate, each cell array being aligned in a first direction of the matrix, memory cells arranged in a matrix to store, as data, resistance values determined by the phase change of the memory cells Bit lines for commonly connecting one ends of the plurality of memory cells, and word lines for commonly connecting the other ends of the plurality of memory cells aligned in a second direction of the matrix; A read / write circuit formed below the cell arrays on the semiconductor substrate, for reading and writing data of the cell arrays; First and second vertical wires disposed outside first and second boundaries in a first direction defining a cell layout area of the cell arrays, for connecting bit lines of the cell arrays to a read / write circuit, respectively; And third vertical wires disposed outside one of the third and fourth boundaries in the second direction defining the cell layout area of the cell arrays, for connecting the word lines of the cell arrays to the read / write circuit, respectively. .

Cell Arrays, Memory Cells, Word Lines, Bit Lines, Stacking, Read / Write Circuits, Vertical Wiring, Phase Changes, Chalcogenides

Description

Phase change memory device {PHASE CHANGE MEMORY DEVICE}

The present invention relates to an electrically rewritable phase change memory device that stores, as information, a resistance value determined due to a phase change between a crystalline state and an amorphous state of a memory material as information.

In the industry, EEPROM flash memories are known as large capacity, multifunctional nonvolatile semiconductor memories. In this kind of semiconductor memories, miniaturized circuits with a minimum processing dimension of 100 nm or less in the memory plane have been realized. To further increase the memory capacity, further refinement is needed to increase the number of cells in the unit area. However, it is not easy to progress further refinement.

Some approaches to increasing memory capacity without advancing miniaturization, for example, assembling a plurality of memory chips in a stack or forming a three-dimensional memory chip with memory cell arrays stacked on top of a silicon substrate. Methods have been investigated. However, the conventionally proposed cell array stacking methods are simply stacking planar cell arrays. In this case, N times capacity can be obtained by stacking N layers, but cell accesses must be performed independently for individual cell arrays. Thus, accessing a plurality of cell arrays at one time is not easy.

As future advanced next-generation memory technologies, phase change memory has been proposed that utilizes phase transitions between the crystallized and amorphous states of the chalcide-based glass material (see, for example, Jpn. J. Appl. Phys. 39 (2000) PP. 6157-6161 Part 1, NO. 11, November 2000 "Submicron Nonvolatile Memory Cell Based on Reversible Phase Transition in Chalcogenide Glasses". This type of memory takes advantage of the fact that the resistance ratio of the amorphous state to the crystalline state of the chalcogenide is greater than 100: 1 so that such different resistance value states can be stored as information. This phase change is reversible and any change can be controlled by properly designing the heating scheme, in which case the heating technique can be controlled by the amount of current passing through the material.

In order to increase the capacity of such phase change memory, a method of integrating its cell array and read / write circuit has become an important technical issue. In addition, how to design read / write circuits capable of high-speed data input / output is also an important technical issue.

A phase change memory device according to one mode embodying the present invention,

Semiconductor substrates;

A plurality of cell arrays stacked on top of the semiconductor substrate, each cell array arranged in a matrix manner to store, as data, resistance values determined by the phase change of the memory cells, aligned in a first direction of the matrix Bit lines for commonly connecting one ends of the plurality of memory cells, and word lines for commonly connecting the other ends of the plurality of memory cells aligned in a second direction of the matrix;

A read / write circuit formed below the cell arrays on the semiconductor substrate, the read / write circuit for reading and writing data of the cell arrays;

First and second vertical wires disposed outside first and second boundaries in a first direction defining a cell layout area of the cell arrays, for connecting bit lines of the cell arrays to a read / write circuit, respectively; And

It is disposed outside one of the third and fourth boundaries in the second direction defining the cell layout area of the cell arrays, and has third vertical wires for connecting the word lines of the cell arrays to the read / write circuit, respectively.

1 is an equivalent circuit of a cell array according to an embodiment of the present invention.

2 is a plan view of a four-layer stacked cell array.

3 is a cross-sectional view taken along the line I-I 'of FIG. 2 when a Schottky diode is used in the memory cell.

4 is a cross-sectional view taken along the line I-I 'of FIG. 2 when a PN junction diode is used in the memory cell.

5 is a three-dimensional equivalent circuit of a cell array.

6 is a perspective view showing the layout relationship between cell blocks and their read / write circuits.

7 is a cross-sectional view illustrating an interconnection relationship between bit lines and a read / write circuit.

8 is a cross-sectional view showing a relationship between word lines and a read / write circuit.

FIG. 9 is a diagram illustrating a unit configuration of four-layer stacked cell arrays.

10 shows the layout of the read / write circuit.

11 is a diagram illustrating a word line selection circuit portion.

12 is a diagram illustrating a portion of a bit line selection circuit.

13 is a diagram showing a layout of a word line selection circuit portion and a bit line selection circuit portion.

14 is a perspective view illustrating a bit line forming process.

15 is a perspective view showing a memory cell forming process.

16 is a perspective view showing a word line forming process.

17A to 17C are cross-sectional views illustrating a word line forming process in detail.

18 is a cross-sectional view showing a capacitor and diode relationship of a read / write circuit and a cell array.

19 is a diagram illustrating a write pulse generation circuit for generating a negative logic write pulse applied to a bit line.

FIG. 20 is a diagram illustrating operational wave forms for the description of the write pulse generation circuit.

FIG. 21 is a diagram illustrating an input / output relationship of a write pulse generation circuit for two cell arrays activated at the same time.

FIG. 22 is a logic pulse generation circuit for generating the input logic pulses of FIG. 21.

23 shows waveforms of write pulses for two pairs of cells.

Embodiments of the present invention will be described below with reference to the drawings.

Figure 1 shows a cell array of a phase change memory according to one embodiment, relating to a 3x3 cell matrix. A plurality of word lines WL are provided in parallel, and a plurality of bit lines BL are provided in a direction crossing the word lines WL. Memory cells MC are disposed at individual intersections of these lines. The memory cell MC is a series-connection circuit of the variable resistance element VR and the diode SD. The variable resistance element VR may be operable to store a resistance value formed of a chalcogenide and determined due to a phase transition between crystal and amorphous states as binary data in a nonvolatile manner. In this embodiment, it may be the case that the diode SD is a Schottky diode, but alternatively, a PN-junction diode may be used. One end of the memory cell MC is connected to the bit line BL, and the other end is connected to the word line WL. In this figure, the diode SD is arranged so that the word line WL side is an anode, but what is needed here is to obtain cell selectivity based on the potential relationship between the word line WL and the bit line BL. Therefore, the polarity of the diode SD can be reversed.

As described above, the data is stored as meaning of the resistance value for the resistance element VR of each memory cell MC. For example, in the non-selection state, all word lines WL are set to the "L" level, while all bit lines BL are set to the "H" level. In one example, the "H" level is 1.8V and the "L" level is 0V. In this non-selected state, the diodes SD of all the memory cells MC are in a reverse-biased state and thus off-state, so that no current flows in the resistance elements VR. Considering the case of selecting the memory cell MC disposed at the center of the cell array of FIG. 1 surrounded by a dotted line, the selected word line WL is "H" while the selected bit line BL is "L". Is set to ". Thereby, in the selected cell, the diode SD is in a forward-biased state and current can flow.

At this time, since the amount of current flowing through the selected cell is determined by the phase of the chalcogenide constituting the resistance element VR, two-value or binary data can be read by detecting whether the amount of current is large or small. . As an example, increasing the amount of current by raising the "H" level potential of the selected word line or lowering the "L" level potential of the selected bit line more than the potential in the read mode, and then heating the cell portion due to this current. Note that it is also possible to generate a phase transition in the chalcogenide of the resistive element VR using. In this manner, a specific cell of the cell array may be selected and information of the cell may be rewritten.

In this way, in the cell of this embodiment, access can be performed by setting the potential levels for only one word line WL and one bit line BL. If a transistor is provided for cell selection, a signal line for selecting the gate of the transistor in the cell array is required, but this signal line is unnecessary in this embodiment. In addition, in terms of diodes inherently simpler than transistors, in addition to the advantages of a simple diode structure, a cell array is simpler in configuration due to the reduction in the number of signal lines needed, thereby enabling higher integration of cells. have.

Although the basic cell array configuration has been described above, a three-dimensional cell array structure in which a plurality of cell arrays are stacked on top of a semiconductor substrate may be used in this embodiment. Such a three-dimensional cell array will be described later.

2 and 3 show the layout of a three-dimensional (3D) cell array comprising four-layer stacked cell arrays (MAO to MA3) and a cross section along its II ′ line. In these figures, the same reference numbers are used for the same parts or components of the individual cell arrays, which reference numbers are to be distinguished between the cell arrays by adding suffixes of "a" and "b" thereto. In addition, by adding the suffixes of "ab", "bc" and "cd" it can also be distinguished between the shared portions of each of the two cell arrays.

The silicon substrate 10 is covered with an insulating film such as a silicon dioxide film. On the substrate, a plurality of bit lines BL 12a are arranged in parallel with each other. The columnar memory cells MC are arranged on each bit line 12a, each of which has a variable resistance device VR made of a chalcogenide layer 13a and stacked thereon. It has a Schottky diode (SD). Word lines WL 18ab are formed in a direction perpendicular to the bit lines 12a to commonly connect upper ends of the memory cells MC, thereby forming a first cell array MAO. do.

In detail, the memory cells MC may pattern the stacked layers of the chalcogenide 13a, the resistance electrode 14a, the n ⁺ -type silicon layer 15a and the n-type silicon layer 16a. It is formed by. An interlayer dielectric layer 17 is embedded around the memory cells MC to planarize the cell array MAO.

In order to form a more desirable Schottky diode, it should be appreciated that a metal film for Schottky contact to n-type silicon layer 16a may be formed in addition to word line 18ab.

The second memory cell array MA1 is formed to share the word lines WLO 18ab with the first memory cell array MA0. Specifically, columnar memory cells MC formed by patterning stacked films of n-type silicon film 16b, n ⁺ -type silicon film 15b, resistive electrode 14b, and chalcogenide 13b. ) Is arranged on each word line 18ab, each of the columnar memory cells MC having a Schottky diode SD and a chalcogenide layer 13b stacked thereon. The cell layout is the same as that of the first cell array MAO. A Schottky junction is formed between the word line 18ab and the n-type silicon 16b. Bit lines BL1 12ab are patterned to jointly connect chalcogenide layers 13b arranged along a direction perpendicular to word lines 18ab. An interlayer insulating layer 19 is embedded around the memory cells MC to planarize the cell array MA1.

A stack structure of the third and fourth cell arrays MA2 and MA3 is periodically formed similarly to the first and second cell arrays MAO and MA1. The bit lines BL1 12bc are shared between the second cell array MA1 and the third cell array MA2. The third cell array MA2 and the fourth cell array MA3 share word lines WL1 18cd. The bit lines BLO 12a of the lowermost cell array MA0 and the bit lines BL3 12d of the uppermost cell array MA3 are each prepared independently.

As described above, to configure the memory cell MC, a PN junction diode may be used instead of the Schottky diode. Corresponding to FIG. 3, another 3D cell array with PN junction diodes Di is shown in FIG. 4. As shown in FIG. 4, in each of the memory cells arranged between the bit lines and the word lines, a PN junction diode Di is formed of the n-type silicon layer 25 and the p-type silicon layer 26. do. The rest is similar to FIG. 3.

5 shows a three-dimensional equivalent circuit of a 3D cell array formed as described above. In order to prevent mutual interference of the bit lines, two bit lines each constitute one pair, and another bit line is disposed between the pair of bit lines. BL00, / BL00, BL01, / BL01, ... are bit line pairs of the first cell array MA0; BL10, / BL10, BL11, / BL11, ... are shared bit line pairs between the first and third cell arrays MA1 and MA2; BL20, / BL20, BL21, / BL21, ... are shared bit line pairs between the third and fourth cell arrays MA2 and MA3. In addition, WLO (WLOO, WL01, ...) are shared word lines between the first and second cell arrays MA0 and MA1; WL1 (WL10, WL11, ...) are shared word lines between the third and fourth cell arrays MA2 and MA3.

In the above-described 3D cell array in which a plurality of phase-change memory cells are integrated, variation in cell characteristics causes a problem. Specifically, the data state of a cell using the phase-transition of chalcogenide varies due to its history, environment, and the like. For example, data "0" (high resistance state) is written by amorphous-rich state chalcogenide layer, while data "1" (low resistance state) is crystal-rich state chalcogenide layer. It is filled in by making a speech. In this case, the initial states of the individual cells differ from each other due to their histories and positions.

In view of the above-described aspects, in this embodiment, two cells arranged adjacently store complementary data in such a manner that data "0" is stored in one cell and data "1" is stored in another cell. One cell pair is configured. The read operation is performed by detecting a difference between cell currents of two cells forming one pair. By using this method, even if there is a partial overlap between the high and low resistance state distributions of the entire 3D cell array, cell data can be read / written accurately.

In Fig. 5, two cell pairs are shown symbolically, which share the word line WL00 of the cell array MA0 and connect to a pair of bit lines BLO0 and / BLOO, respectively. Two cells constitute one pair of cells, one of which is a true cell "T-cellO" and the other of which is a complementary cell "C-cell0", and the word of the cell array MA1. Two cells that share a line WL10 and are connected to a pair of bit lines BL10 and / BL10, respectively, constitute another pair of cells, one of which is a true cell T-cell1. ) And the other is complementary cell (C-cell1). In every pair of cells, the positive logic value of the binary data is stored in the true cell and the negative logic value is stored in the complementary cell. Similar pairs of cells are selected in the cell arrays MA2 and MA3. In Fig. 5, cell currents at individual selection points are indicated by arrows.

So far, the cell array configuration has been described. In the present invention, a read / write circuit for reading and writing (or programming) cell data is first formed on the silicon substrate 10, and the above-described 3D cell array is formed. In detail, the 3D cell array is stacked on top of the read / write circuit.

6 is a schematic perspective view showing the stacked state of the cell blocks 100 and the read / write circuit 200 and the interconnection relationship therebetween. Each cell block 100 corresponds to the 3D cell array described above. That is, the 3D cell array is divided into a plurality of cell blocks 100 having a predetermined capacity, if necessary. In FIG. 6, two cell blocks 100 are arranged along the direction of bit lines.

As shown in FIG. 6, the read / write circuit 200 used for reading and writing data of the cell block 100 is placed under the cell block 100. The read / write circuit 200 is formed with its main part disposed in a rectangular cell layout area 210 set on the substrate 10 on which the cell blocks 100 are stacked. The cell layout area 210 is defined by two boundaries Al and A2 in the bit line direction and two boundaries B1 and B2 in the word line direction.

The group of the bit lines BLO of the first cell array MA0 and the group of the bit lines BL2 of the fourth cell array MA3 may be arranged along the boundary A1 (ie, vertical lines). Through the paths 101 vertically passing through the substrate, to the bit line selection circuit 201 which is drawn towards the first boundary A1 and is arranged along the boundary A1 of the read / write circuit 200. Connected. The group of bit lines BL1 shared by the second and third cell arrays MA1 and MA2 is connected to the second boundary through the vertical lines 102 disposed along the second boundary A2. It is drawn out toward (A2) and connected to another bit line selection circuit 202 disposed along the boundary A2 of the read / write circuit 200.

The reason that the bit lines BL0 and BL2 are drawn to the same side through the vertical lines 101 and commonly connected to the bit line select circuit 201 is due to the fact that the bit lines of these groups are not activated at the same time. In detail, the cell arrays MAO and MAl are activated simultaneously because they share word lines WL0. Similarly, cell arrays MA2 and MA3 are simultaneously activated because they share word lines WL1. However, since the cell arrays MA2 and MA3 share the bit lines BL1, the lower cell arrays MAO and MA1 and the upper cell arrays MA2 and MA3 are not simultaneously activated. The bit line selection circuits 201 and 202 include bit line decoders / multiplexers BL-DEC / MUX.

The word lines WL0 and WL1 are drawn out toward the third boundary B1 through the vertical lines 103 and 104 disposed along the boundary B1, respectively, to form the read / write circuit 200. The word line selection circuit 208 is arranged along the boundary B1. The word line select circuit 208 has word line decoders / multiplexers WL-DEC / MUX.

The central portion of the read / write circuit 200 acts as a global bus region 207, in which I / O data lines and write pulse signal lines are arranged along the direction of the word lines across this region. Between this global bus region 207 and the bit line select circuits 201 and 202, sense amplifier arrays 203 and 204 are disposed, respectively. Signal lines formed in the global bus region 207 are shared by sense amplifier arrays 203 and 204. The sense amplifiers of sense amplifier arrays 203 and 204 are connected to bit line select circuits 201 and 202 via signal lines disposed in local bus regions 205 and 206, respectively. Thus, some bit lines selected from the bit lines BLO or BL2 by the bit line selection circuit 201 are connected to the sense amplifier array 203. Similarly, some bit lines selected from bit lines BL1 are connected to sense amplifier array 204 by bit line select circuit 202.

The I / O data lines and the write pulse signal lines arranged in the global bus area 207 are drawn out toward the fourth boundary B2 of the cell layout area 210. Along this boundary B2, a write circuit 209 for applying write pulses to selected cells is arranged. The write circuit 209 includes a transistor circuit 209a formed on the silicon substrate 10 and a diode circuit 209b formed on the substrate using the same steps as forming a cell array, as described below.

As described above with reference to FIG. 6, the bit lines and word lines of the cell array are connected to the read / write circuit 200 formed on the substrate 10 through vertical interconnect lines 101 to 104. Connected. In practice, these interconnect lines 101-104 are contact plugs embedded in an interlayer insulating film formed around the cell array. Structural examples of interconnect lines are shown in FIGS. 7 and 8. 7 shows a connection state between the bit lines and the read / write circuit 200 through the cross section along the bit lines of the cell array. 8 illustrates a connection state between the word lines and the read / write circuit 200 through the cross section along the word lines of the cell array.

As shown in Figs. 7 and 8, the read / write circuit 200 has necessary transistors and interconnect lines of metal formed on the interlayer insulating film 11a covering the transistors. The read / write circuit 200 is covered with an interlayer insulating film 11b, on which four-layer cell arrays are formed. Therefore, the interlayer insulating films 11a and 11b constitute the insulating film 11 shown in FIGS. 3 and 4.

As shown in FIG. 7, the vertical wirings 101 used to connect the bit lines BLO and BL2 drawn out toward the boundary A1 of the cell layout region 210 to the bit line selection circuit 201 are formed. Contact plugs 101a to 101e embedded in the interlayer insulating films 17, 19, 20, and 21. Similarly, the vertical wirings 102 used to connect the bit lines BL1 drawn toward the boundary A2 of the cell layout region to the bit line selection circuit 202 are formed between the interlayer insulating films 11, 17, and 19. Contact plugs 102a to 102c embedded in the. As shown in FIG. 8, the vertical lines 103 used to connect the word lines WL0 drawn out toward the boundary B1 of the cell layout region to the word line select circuit 208 are interlayer insulating films 11. And contact plugs 103a and 103b embedded in 17). The vertical lines 104 used to connect the word lines WL1 drawn to the same side as the word lines WL0 to the word line select circuit 208 are buried in the interlayer insulating films 11, 17, and 20. Contact plugs 104a-104d.

7 and 8, the bottom contact plugs 101a, 102a, 103a and 104a of the stacked cell arrays are connected to the metal wires of the read / write circuit 200, but these are directly connected to the source / drain diffusion layers of the transistors. It can also be connected to. 7 and 8 show an example in which contact plugs are formed of a metal film used for bit lines and word lines. In the following, the assembly steps will be described. Additionally, it will be appreciated that contact plugs may be formed from other metal films that are different from bit lines and word lines or polycrystalline silicon films.

The one cell block of FIG. 6 includes, for example, 512 bit lines BL and 128 word lines WL for one cell array. As described above, in this embodiment, two memory cells store one bit of data. In this case, one cell block has a memory space of 256 columns Col × 128 rows. The memory capacity can be increased by increasing the number of cell blocks to be arranged. In order to realize high-speed access in such a large memory, it is necessary to perform parallel access on many-bit data. For example, in order to perform 32-bit parallel access, one cell block is divided into two parts in the word line direction and 32 parts in the bit line direction, as shown in FIG. Cells unit UC (UCO to UC63) blocks are obtained. As a result, each cell unit UC has a capacity of 32IO x 4 Col x 4 Row x 4. In the global bus region 207, data lines and write pulse signal lines for 6410 data input / output are disposed.

FIG. 10 shows a schematic layout of the read / write circuit 200 when the cell block configuration described above in connection with the one cell block 100 of FIG. 6 is used. On the word line selection circuit WL-DEC / MUX 208 disposed on the right side of FIG. 10, one from each of the 128x2 word lines 301 of the cell block 100 (i.e., one at the top and one at the bottom). Row address (RA) signal lines 301 running vertically are arranged to select one). The write circuit 209 disposed on the left side of FIG. 10 outputs write pulses supplied to bit lines selected in the write mode. Write pulse signal lines (WP) 305 that carry the write pulses are arranged to run laterally on the global bus region 207. Parallel to the write pulse signal lines 305 on the global bus area 207, main data lines 304 are arranged to which read data is transferred. One cell unit is selected in one cell block, and cell data of two adjacent layers of each cell unit are activated at the same time. Thus, data lines 304 for 32IO x 2 = 64IO are prepared.

On the lower and upper ends of the read / write circuit 200, bit line select circuits 201 and 202 are disposed, respectively, and column address (CA) signal lines 302 and 303 are located on individual regions. It is arranged to proceed to the side. One of the bit line selection circuits, i.e. circuit 201, selects 32 bit line pairs from 512 bit line pairs (= 64IO x 4) in the upper two cell arrays, and the other 32 bit line pairs are selected from 512 bit line pairs in the two cell arrays. Thus, in the respective local bus regions 205 and 206, to apply the write pulses of the write pulse signal lines 305 to the bit lines selected by the individual bit line select circuits 201 and 202. Four pairs of current passing lines (BP, / BP) for common 4-column (= 8 bit lines) data passing through the regions of the sense amplifier arrays 203 and 204 are arranged. In addition, 64 pairs of local data lines (DL, / DL) for four column data are arranged on individual local bus regions 205 and 206, which are arranged in the sense amplifier arrays 203 and 204. It is connected to the individual sense amplifiers.

One circuit portion 310 to be connected to 4 Row x 2 (= 8 word lines) and another circuit portion 312 to be connected to 4 Col (= 8 bit lines), each surrounded by a dotted line in FIG. And in Figure 12, respectively.

The two multiplexers MUXO and MUX1 respectively have lower word lines WLO shared by the cell arrays MAO and MA1 and upper word lines shared by the cell arrays MA2 and MA3, respectively. Select gate circuits for selecting WL1). The eight word lines input to the multiplexer MUXO correspond to the lower word lines for the two cell units of FIG. 9. The decoder DEC consists of decode gates G; Gl, G2,... To select one of the 32 cell units. The multiplexer MUXO comprises a select gate consisting of PMOS transistors QP (QP11 through QP14, QP15 through QP18, ...) driven to select one from four word lines by the select signals S10 through S13. Has a circuit 401. In order to forward-bias the cell diode with the selected bit lines, a high level voltage (positive logic pulse) is applied to the selected word line. The multiplexer MUX0 has a reset circuit 402 composed of NMOS transistors QN (QN11 to QN14, QN15 to QN18, ...) for holding non-select word lines at low level (Vss). The multiplexer MUX1 is configured similarly to the multiplexer MUX0.

The sense amplifier SA shown in FIG. 12 is one of the 32 sense amplifiers of the sense amplifier array 203 shown in FIG. The four pairs BL0, / BL0 to BL3, / BL3 of eight bit lines connected to the sense amplifier SA are those selected from the bit line group BLO or BL2 shown in FIG. As described above, since the lower two cell arrays MAO and MA1 and the upper two cell arrays MA2 and MA3 are not activated at the same time, the sense amplifier SA is connected to the lower cell arrays MAO, MA1) and the upper cell arrays MA2, MA3 together.

The sense amplifier SA is a CMOS flip-flop type current sense amplifier in which the PMOS transistor QP30 is activated. Its two nodes N1 and N2 are each connected directly to a pair of global data lines 304 (GBi, / GBi). The drains of the sense NMOS transistors QN61 and QN62 are connected to the data lines DL and / DL through the NMOS transistors QN31 and QN32 which are controlled to be turned on during the read operation by the read control signal R, respectively. Is optionally connected. When starting the data sensing operation, nodes N1 and N2 are connected to each other via transistor QN73. After the cell currents are delivered to the sense transistors QN61 and QN62, their drains are clamped to Vss through the NMOS transistors QN71 and QN72 which are controlled to be turned on by the clock CLK. The data lines DL and / DL are connected to a pair of bit lines selected by the bit line decoder / multiplexer BL-DEC / MUX.

The bit line decoder / multiplexer BL-DEC / MUX decodes signals S20 through 4 to select a pair for connecting to the data lines DL and / DL, respectively, from four pairs of bit lines. It has a select gate 403 made up of NMOS transistors QN51 to QN54 and Q55 to Q58 controlled by S23. The bit line decoder / multiplexer (BL-DEC / MUX) also has a reset circuit 404 consisting of PMOS transistors QP51 to QP54 and QP55 to QP58 to maintain the non-select bit lines at a high level of Vdd. .

The pair of data lines DL and / DL are driven through the NMOS transistors QN41 and QN42 which are driven to be turned on by the write control signal W during the data read operation and the data signal lines BP and / BP. Through the pair of signal lines WPi and / WPi of the write pulse signal lines 305.

In the above-described configuration, when the data read operation is performed, the word lines selected by the select gate circuit 401 become "H" and the bit line pairs selected by the select gate circuit 403 become "L". . The cell currents from the selected complementary cells of the selected bit line pair are then drained to the NMOS transistors of the sense amplifier SA through the data lines DL and / DL and through the NMOS transistors QN31 and QN32. Delivered to the field. During this operation, the NMOS transistors QN71 and QN72 remain off. Thereafter, the clock CLK becomes " H " to turn on the NMOS transistors QN71 and QN72, whereby the drains of the sense NMOS transistors QN61 and QN62 are clamped to Vss. As a result, the differential voltage generated between nodes N1 and N2 due to the difference in cell currents is positively feedbacked, thereby amplifying one node to Vdd and another node to Vss. The amplified cell data is output to the main data lines GBi and / GBi as described above.

In the data write mode, a positive logic write pulse of Vdd level is applied to the selected word line. At the same time, negative logic write pulses of the Vss level or the boosted level are applied to the selected bit line pair via the write pulse signal lines WPi and / WPi. These positive and negative logic write pulses are applied to selected and complementary cells to have a predetermined overlap state at levels corresponding to the data to be written therebetween, thereby performing a write operation. In the following, the write circuit and its operations will be elaborated.

Since one word line is commonly connected to a plurality of pair cells, the word line is required to supply a large amount of current to the pair cells. Considering these current values, the driveability of the word line decoder, the self-resistance of the word line, the transistor size, and the like must be designed. It should be appreciated that the word line multiplexer MUX0 for the eight word lines shown in FIG. 11 and the bit line decoder / multiplexer DEC / MUX for the eight bit lines shown in FIG. 12 have the same circuit configuration. Thus, these circuit regions can be realized to have the same layout as shown in FIG. In FIG. 13, transistors QP11 to QP18, QN11 to QN18, select signals S10 and S13, and a low level power supply Vss in the circuit of FIG. 11 are shown and correspondingly, the circuit of FIG. 12. Transistors QN51 to QN58, QP51 to QP58, select signals S20 to S23, and high level power supply Vdd in are shown in parentheses. Although the individual transistors corresponding to each other are different conduction-types, the same layout can be used for these circuits.

The vertically running wiring 410 in FIG. 13 is the gate lines of the transistors that function as the select lines and the power lines of Vdd and Vss. These can be formed simultaneously by patterning the polysilicon film. The power supply lines Vss and Vdd need only be fixed at the potential as needed to secure the non-selection bit lines and word lines so that they are not floating, so they need not be low resistance. Therefore, the same polysilicon film used as the gate electrodes can be used for these lines. Although the wirings 411 that run to the side are indicated by simple straight lines, they are metal wires that are in contact with the sources and drains of the transistors. The contacts 412 to which the vertical interconnect lines (ie, contact plugs) 101 to 104 shown in FIG. 6 are connected serve to connect the metal wires 411 to the bit lines and the word lines. .

The bit lines and word lines of the cell array described above are preferably formed to have a line / space of 1F / lF (F: minimum device-spec size). These bit lines and word lines are as shown in FIG. 6. It is connected to the read / write circuit 200 on the substrate while maintaining the line pitch. In this case, the metal wires 411 shown in FIG. 13 are formed to have the same line / space of 1F / 1F. In contrast, the transistors disposed in the middle of the metal wires 411 should have a large area to supply a necessary current. In view of this point of view, in FIG. 13, each transistor is formed to have a gate width of three pitches of the metal lines 411.

When the transistor size and the metal wiring pitch are determined as described above, in order to effectively arrange the transistors, select signal lines S10 (S20) and Sll (S21) suffixed according to an address order of 0, 1, 2, and 3 , S12 (S22) and S13 (S23) are arranged in the order of S10 (S20), S12 (S22), S11 (S21) and S13 (S23). As a result, the transistor arrays QP11 (QN51) and QP13 (QN53) selected by the selection signal lines S10 (S20) and the transistor arrays QP12 (QN52) selected by the selection signal lines S11 (S21). The transistor arrays QP15 (QN55) and QP17 (QN57) selected by the selection signals S12 (S22) are disposed between the QP14 (QN54). By using such a transistor arrangement, it is possible to arrange large size transistors in a metal wiring region in which wirings are arranged at small pitch without idle spaces.

Next, with reference to FIGS. 14-16, the bit lines, word lines and their contacts to the read / write circuit 200 are simultaneously formed by using the dual damascene method. Will explain. FIG. 14 shows a state in which the read / write circuit 200 is formed thereon and the bit lines BLO are formed on the interlayer insulating film 11 covering the substrate 10. Simultaneously with the formation of the bit lines BLO, the contact plugs 103a and 104a are formed by a dual damascene process. These are used to connect the word lines WLO and WL1 to be stacked thereon to the read / write circuit 200. Although not shown in FIG. 14, other contact plugs for connecting the ends of the bit lines BLO to the read / write circuit 200 are also formed at the same time as the contact plugs 103a and 104a.

Next, as shown in FIG. 15, memory cells constituted by a chalcogenide and a diode each stacked on each other are formed on the bit lines BLO. Next, as shown in FIG. 16, the interlayer insulating film 17 is deposited to cover the memory cells MC, and then word lines WLO are formed on the insulating film 17 by a dual damascene process. . In this process, the contact plugs 103b and 104b to be connected to the contact plugs 103a and the word lines WL1 to be formed next are embedded, respectively.

17A to 17C show details of the embedding process of the word lines WLO and the contact plugs 103b and 104b in the cross-sectional view along the direction of the word line WL0. 17A shows a state in which the interlayer insulating film 17 is deposited to cover the memory cells MC and then planarized. Thereafter, as shown in FIG. 17B, the wiring-filling trenches 501 in the interlayer insulating film 17 by a reactive ion etching (RIE) process to embed the word line so that the top ends of the memory cells MC are exposed. ) Is formed. Further, contact holes are formed deeper than the trenches 501 at positions where the contact plugs 103a and 104a are embedded. Then, a metal layer of wiring material is deposited and processed by the chemical mechanical polishing (CMP) method. As a result, as shown in Fig. 17C, the word lines WLO and the contact plugs 103b and 104b are embedded and formed at the same time.

Subsequently, memory cell formations, interlayer insulating film depositions, wiring and contact plug formations using the damascene method are periodically performed. By using these processes, four-layer cell arrays can be stacked in such a way that the bit lines and word lines of each layer are connected to a read / write circuit on the substrate, as shown in FIGS. 7 and 8.

18 shows a circuit portion 209b structure of the read / write circuit 200 formed simultaneously with the cell arrays. As described below, the write circuit 209 should include capacitors and diodes for pulse-boosting. If these diodes are formed simultaneously in the diode forming process in the cell arrays, the structure of FIG. 18 can be obtained. The process will be detailed. As described above, the transistor circuit is formed on the substrate 10 before the cell array forming process. The MOS capacitors 510 shown in FIG. 18 are formed in the transistor circuit forming process. The diode 511 is formed by overlaying the MOS capacitors 510 using a process of forming diodes SD in the first cell array MA0. Similarly, diode 512 is formed by using a process of forming diodes SD in second cell array MA1.

In the example of FIG. 18, one diode 511 is formed such that an anode is connected to the MOS capacitor 510 below the diode 511, and another diode 512 has a cathode below the diode 512. It is formed to be connected to the MOS capacitor 510. As described above, diodes with selective polarity may be formed as present above the MOS capacitors. Between the diodes 511 and 512 and the MOS capacitors 510, interlayer insulating films 513 and 514 are embedded. Note that the metal films used in the cell array forming process may remain in the interlayer insulating films 513 and 514 if necessary.

By using this structure shown in Fig. 18, even if a large area for MOS capacitors is required, diodes can be stacked over the MOS capacitor regions, thereby reducing the chip footprint of the write circuit 209.

19 shows a write pulse generation circuit 600 used to supply a negative logic write pulse to a selected bit line via a pulse signal line WPi in the write circuit 209 described above. In Fig. 19, H and / L are positive logic pulses and negative logic pulses to be supplied to the selected word line and the selected bit line, respectively. These positive logic pulses H and negative logic pulses / L control the superposition state therebetween according to the data to be written, and the negative logic pulses are boosted in the negative direction according to the superposition state, thereby obtaining the write pulse. . The superposition state of the positive logic pulse H and the negative logic pulse / L is detected by the NAND gate G12. The output of the NAND gate G12 is delayed by a predetermined delay time through the delay circuit 605 and supplied to one input of the OR gate G11. The delay time tau 1 of the delay circuit 605 is approximately T / 2, where T is the pulse width of the positive logic pulse H and the negative logic pulse / L. The negative logic pulse / L is delayed by another delay circuit 606 by a predetermined delay time tau 2 and supplied to the other input of the OR gate G11. The delay time tau 2 of the delay circuit 606 is sufficiently small compared with the delay time tau 1 of the delay circuit 605.

The capacitor 601 is arranged in such a manner that one node Nb is connected to the output of the OR gate G11 and the other node Na is connected to the pulse signal wiring WPi. Diode 602 is connected to node Na to charge capacitor 601 to the level (eg, Vss) of negative logic pulse / L driven by negative logic pulse / L. In addition, the PMOS transistor 603 is also connected to the node Na to keep the signal line WPi at a high level in the non-select state. In other words, the transistor 603 is driven by the inverter 604 to which the negative logic pulse / L is input and maintains the on-state in the non-selected state, thereby keeping the pulse signal line WPi at Vdd. . When a negative logic pulse is generated, transistor 603 is turned off.

20, operations of the write pulse generation circuit 600 will be described later. In the non-selected state, node Nb is maintained at "H" (= Vdd) by OR gate G11 and node Na is held at "H" (= Vdd) by transistor 603. . Therefore, in this state, the write pulse signal line WPi is kept at "H". When " 1 " writing is performed, positive logic and negative logic pulses H and / L are generated simultaneously. At this time, the NAND gate G12 is maintained to output the "H" level, so that the node Nb is maintained at "H". At the same time, since the transistor 603 is turned off, the node Na is discharged through the diode 602 supplied with the negative logic pulse / L to become " L " (= Vss).

In contrast, when " 0 " writing is performed, the negative logic pulse / L is generated to have a delay time [tau] 1 (about T / 2) in relation to the positive logic pulse H. At this time, the node Nb is maintained at "H" while the node Na is discharged by the diode 602 to become "L". Then, when the negative logic pulse / L is delayed by τ2 through the delay circuit 606 and the node Nb becomes "L", at the node Na within a period of about T / 2. A negative logic write pulse boosted in the negative direction can be obtained.

The principle of data writing by using such pulse control is as follows. Upon writing " 1 ", the write current passes through the selected cell during the overlapping time T at which the positive logic pulse H and the negative logic pulse / L overlap each other. As a result, the chalcogenide of the selected cell is annealed by self-induced heat, resulting in a low resistance state of rich crystals. When writing "0", a larger amount of write current passes through the selected cell in a shorter period than when writing "1". As a result, the chalcogenide in the select cell is melted and then rapidly cooled to a high resistance state rich in amorphous.

By paying attention to one write pulse signal line WPi, the write pulse generation circuit 600 of FIG. 19 is shown. Indeed, in this embodiment, as described above, the lower two of the four cell arrays MAO to MA3 are simultaneously activated and the period of the cell arrays MAO and MA1 is activated. In the different period, the upper two cell arrays MA2 and MA3 are activated at the same time. In addition, two cells connected to different bit lines of the cell array constitute a pair of cells for storing complementary data.

21 shows write pulse generation circuits 600a through 600d and their input / output relationships thereof that supply write pulses to two pairs of bit lines in two cell arrays that are simultaneously active. The outputs of the write pulse generating circuits 600a to 600d are selected by the multiplexers MUXO and MUX1 shown in FIG. 11 and supplied to the upper two cell arrays or the lower two cell arrays. In Fig. 21, WPi @ lst and WPi @ 2nd are write pulses to be connected to bit lines (e.g., BL00 and BL10 in Fig. 5) of the first and second layers of two cell arrays simultaneously activated, respectively. Signal lines. / WPi @ lst and / WPi @ 2nd are write pulse signal lines to be connected to the remaining bit lines (for example, / BL00 and / BL10) constituting the pairs and bit lines described above, respectively. H is a positive logic pulse to be supplied to the shared word line of the two cell arrays, and / LOn, / L1n, / L0n ', and / L1n' are negative logic pulses to be supplied to the bit lines. Specifically, / LOn and / LOn 'are supplied to the pair of bit lines of the lower cell array (e.g., BLOO and / BLOO) of the two cell arrays, and / L1n and / L1n' are the two cell arrays. It is supplied to a pair of bit lines of the upper cell array (e.g., BL10 and / BL10). As described with reference to FIG. 19, overlapping states between the positive and negative logic pulses are determined based on the data to be written, and in response, the negative logic write pulse is selectively boosted and supplied to the write pulse signal line WPi. .

FIG. 22 shows a logic pulse generation circuit 700 for generating the positive and negative logic pulses shown in FIG. The logic pulse generation circuit 700 writes necessary by combining two pulses and a pulse generator 710 for generating two pulses PO and P1 having the same pulse width and pulse-shifted with each other. And has a logic gate circuit 720 for generating pulses.

Originally, the pulse generating circuit 711 generates a pulse PO having a pulse width of T, and the delay circuit 712 delays the pulse P0 to generate a pulse P1 delayed by about T / 2. The output pulse PO originally generated from the pulse generator circuit 711 becomes a positive logic pulse H to be supplied to the word lines via a driver.

The bit data BO and B1 input to the logic gate circuit 720 are write data bits to be written to pair cells of the lower cell array and the upper cell array, respectively, of the two cell arrays. If attention is paid to paired cells of the two cell arrays MAO and MA1 in Fig. 5, a detailed example can be described as follows, where BO is T-cellO and C-cellO of the cell array MA0. Write data to be written to the pair cell constituted by B1 is write data to be written in the pair cell constituted by T-cell1 and C-cell1 of the cell array MA1.

The set of AND gates G21 and G22 and the set of AND gates G31 and G32 are the pulses of the original pulse generation circuit 711 in response to whether the bit data B0 is "0" or "1". It is prepared to select the (PO) output or the pulse P1 output of the delay circuit 712. Upon receipt of this selection, one of the outputs / LOn and / LOn 'of the NAND gates G23 and G33 is negative for writing "1", whose phase is equal to the positive logic pulse H. It becomes a logic write pulse, and another becomes another negative logic write pulse for " 0 " writing, whose phase is delayed with respect to the positive logic pulse H. In other words, the outputs / LOn and / LOn 'write one T-cellO and C-cellO as one "0" and the other as "1", respectively, according to the bit data B0. Negative logic write pulses.

Similarly, the set of AND gates G41 and G42 and the set of AND gates G51 and G52 are prepared to select a pulse PO or P1. Thus, the outputs / L1n and / L1n 'of the NAND gates G43 and G53 are one of T-cell1 and C-cell1 to "O" and the other, depending on the bit data B1, respectively. Become negative logic write pulses for writing " 1 ".

FIG. 23 shows the bit lines BLOo // to which two pairs of cells T-cellO, C-cellO and T-cell1, C-cell1 are connected as shown in FIG. The negative logic write pulse waveforms obtained by the positive and negative logic pulses shown in Fig. 22, supplied to BOO, BL10 and / BL10, are shown. The four bits of data described at the beginning of the signal waveform group correspond to a first bit corresponding to T-cell1, a second bit corresponding to C-cell1, a third bit corresponding to T-cellO, and C-cellO. Is the fourth bit. The positive logic pulse H shown in FIGS. 21 and 22 is supplied as a positive logic write pulse as in the case of the word line WL0. This positive logic write pulse becomes a reference pulse, and the negative logic write pulses provided to the individual bit lines are pulse-width controlled and stepped up according to the data "0" and "1". As a result, as described above, the chalcogenide of the "0" write cell is melted and then rapidly cooled to a high resistance state, and the chalcogenide of the "1" write cell is crystallized to a low resistance state. Thus, it is possible to perform simultaneous writes to simultaneously activated pair cells of two cell arrays.

According to the present invention, it is possible to provide a phase change memory in which a three-dimensional cell array and a write / read circuit are integrally formed in a small chip area and in which a high speed read / write operation can be performed.

Claims (23)

Semiconductor substrates; A plurality of cell arrays stacked on the semiconductor substrate, each cell array arranged in a matrix manner to store, as data, resistance values determined by a phase change of memory cells, in a first direction of the matrix Bit lines for commonly connecting one ends of the plurality of aligned memory cells in common, and word lines for commonly connecting the other ends of the plurality of memory cells aligned in the second direction of the matrix; A read / write circuit formed below the cell arrays on the semiconductor substrate, for reading and writing data of the cell arrays; First and second vertical lines disposed outside the first and second boundaries in the first direction defining a cell layout area of the cell array, connecting the bit lines of individual cell arrays to the read / write circuit; Wirings; And Third vertical wires disposed outside one of the third and fourth boundaries in the second direction defining the cell layout area to connect the word lines of individual cell arrays to the read / write circuit; Phase change memory device comprising a. The method of claim 1, And each of the memory cells of the respective cell array is disposed at respective intersections of the bit lines and word lines with a stacked structure of chalcogenide and diode. The method of claim 2, The diode of the memory cell is connected in series with the chalcogenide with the polarity of the bit line side being the cathode and the word line side being the anode, In non-select mode, the bit lines and word lines are potential locked such that the diode is reverse-biased, and in data read and write modes, the selected bit line and the selected word line are in negative and positive directions, respectively. Pulse-driven phase change memory device. The method of claim 1, And the plurality of cell arrays are stacked to share bit lines and word lines with two adjacent cell arrays. The method of claim 1, And the first to third vertical wires are contact plugs embedded in an interlayer insulating film surrounding the cell arrays. The method of claim 1, Two adjacent memory cells in each cell array constitute paired cells for storing complementary data, one of which is in a high resistance value state and the other of which is a low resistance value state, And said complementary data of said pair of cells is read as one bit of data into a pair of bit lines. The method of claim 6, And the pair cell is selected such that another bit line is placed between the pair of bit lines from which its complementary data is read. The method of claim 1, The read / write circuit, A global bus region having a plurality of data lines through which read data is transferred and a plurality of write pulse signal lines for delivering write pulses to the bit lines, wherein the data lines and the write pulse signal lines define a central portion of the cell layout region. Arranged to cross in the second direction; First and second bit line selection circuits disposed along the first and second boundaries of the cell layout area, respectively, wherein bit lines of two adjacent cell arrays are connected, respectively; First and second signals disposed between the first and second bit line selection circuits and the global bus region, respectively, for sensing data of bit lines selected by the first and second bit line selection circuits; Two sense amplifier arrays; A word line selection circuit disposed along one of the third and fourth boundaries of the cell layout region and to which shared word lines of the two adjacent cell arrays are connected; And And a write circuit arranged along another one of said third and fourth boundaries of said cell layout region, said write circuit for generating said write pulses supplied to said write pulse signal lines. The method of claim 8, The shared word lines are simultaneously activated by a predetermined range selected by the word line selection circuit, and each of the bit lines of the adjacent two cell arrays is respectively predetermined by the first and second bit line selection circuits. Is selected simultaneously so that a plurality of individual memory cells of the adjacent two cell arrays are simultaneously accessed. The method of claim 9, The first and second sense amplifier arrays have sense amplifiers for simultaneously sensing data of a plurality of memory cells that are simultaneously selected in the adjacent two cell arrays, wherein the sensed data in the sense amplifiers is stored in the global bus. And a phase change memory device simultaneously transferred to the data lines of the region. The method of claim 9, And the write circuit is configured to simultaneously output write pulses to the write pulse signal lines in the global bus region to be transmitted to respective plurality of bit lines selected simultaneously in the two adjacent cell arrays. The method of claim 8, Two adjacent memory cells of each of the cell arrays constitute a pair of cells for storing complementary data, one of which is in a high resistance value state and the other of which is a low resistance value state, Each of the first and second sense amplifier arrays is configured by arranging differential current sense amplifiers connected to a pair of bit lines to which the pair cell is connected to sense a current difference due to the complementary data. . The method of claim 8, The write circuit, Positive logic pulses and negative logic pulses to be supplied to selected word lines and selected bit lines of each of the cell array, respectively, wherein the positive logic pulses and the negative logic pulses are in accordance with write data. A logic pulse generating circuit for generating-controlled to have overlapping widths therebetween; And And a write pulse generator circuit for selectively boosting the negative logic pulses output from the logic pulse generator circuit to the write pulse signal lines according to write data. The method of claim 13, The logic pulse generator circuit, A pulse generating circuit for generating two pulses having the same pulse width and phase-shifted with each other; And And a logic gate circuit for outputting the negative logic pulses and positive logic pulses whose overlapping time is determined by combinational logics determined according to write data. The method of claim 1, The plurality of cell arrays, A plurality of first bit lines parallel to each other formed on an interlayer insulating film covering the read / write circuit, a plurality of memory cells laid out on each first bit line, and the first bit line on the memory cells A first cell array having a plurality of first word lines laid out in a manner of commonly connecting a plurality of memory cells aligned in a direction crossing the plurality of memory cells; A plurality of memory cells formed on the first cell array while sharing the first cell array and the first word lines, and arranged in the same layout as the first cell array, and the first word line on the memory cells. A second cell array having a plurality of second bit lines arranged in a manner of commonly connecting a plurality of memory cells aligned in a direction crossing the plurality of memory cells; A plurality of memory cells formed on the second cell array while sharing the second cell array and the second bit lines, and laid out in the same layout as the second memory cell array, and the second on the memory cells. A third cell array having a plurality of second word lines arranged in a manner of commonly connecting a plurality of memory cells aligned in a direction crossing the bit lines; And On the memory cells and the plurality of memory cells formed on the third cell array while sharing the third cell array and the second word lines, and arranged in the same layout as the memory cells of the third memory cell array. And a fourth cell array having a plurality of third bit lines arranged in a manner of commonly connecting a plurality of memory cells aligned in a direction crossing the second word lines. The method of claim 15, And the memory cells of each of the cell arrays have a chalcogenide and a diode stacked on corresponding intersections of the first to third bit lines and the first and second word lines. The method of claim 16, The stacking order of the chalcogenide and diode is reversed between adjacent cell arrays above and below, And the diodes are formed to have polarities in which the first to third bit lines are cathodes. The method of claim 15, The read / write circuit, A global bus region having a plurality of data lines through which read data is transferred and a plurality of write pulse signal lines for delivering write pulses to the bit lines, wherein the data lines and the write pulse signal lines define a central portion of the cell layout region. Arranged to cross in the second direction; A first bit line selection circuit disposed along the first boundary of the cell layout area and in which the first and third bit lines are commonly connected; A second bit line selection circuit disposed along the second boundary of the cell layout area and to which the second bit lines are connected; A first interposed between the first and second bit line select circuits and the global bus region, respectively, for sensing data of the bit lines selected by the first and second bit line select circuits, respectively; And second sense amplifier arrays; A word line selection circuit disposed along one of the third and fourth boundaries of the cell layout area and to which the first and second word lines are connected; And And a write circuit arranged along another one of said third and fourth boundaries of said cell layout region, said write circuit for generating said write pulses supplied to said write pulse signal lines. The method of claim 18, The word line selection circuit is configured to simultaneously activate a predetermined range of one of the first and second word lines, Wherein the first and second bit line selection circuits are configured to simultaneously select a predetermined range of one of the first and third bit lines and to simultaneously select a predetermined range of the second bit lines. Memory device. The method of claim 19, The first and second sense amplifier arrays have sense amplifiers for simultaneously sensing data of a plurality of memory cells simultaneously selected in the first and second cell arrays or in the third and fourth cell arrays, And data sensed by the sense amplifiers are simultaneously transferred to the data lines of the global bus region. The method of claim 19, The write circuit may write write pulses to be transmitted to respective plurality of bit lines that are simultaneously selected in the first and second cell arrays or in the third and fourth cell arrays. A phase change memory device configured to simultaneously output to a. The method of claim 15, Two adjacent memory cells sharing the first or second word lines of each of the first to fourth cell arrays are complementary data, one of which is in a high resistance value state and the other of which is a low resistance value state. Configure pair cells for storage, And said complementary data of said pair of cells is read as one bit of data into a pair of bit lines. The method of claim 22, The pair of cells is selected such that another bit line is placed between the pair of bit lines from which its complementary data is read

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