TW392345B - Multi-state complementary flash memory cell structure, manufacturing method and operation method thereof - Google Patents

Abstract

A multi-state complementary flash memory cell is provided which forms deep N-well in P-substrate and P-well area in deep N-well for being used as the active area of complementary flash memory cell. Using the P-well area as the base, it can constitute complementary flash memory cells comprising drain, floating doping area, source and stacked gates. The stacked gates are composed of control gates and floating gates. The electricity of floating doping area and source is different from that of P-well area which is N-conductive type and the ion doping density of floating doping area is lower than that of the source. The electricity of drain and P-well are the same, which is of P-conductive type. Such a complementary flash memory cell structure can be parasitized with bipolar transistors for amplifying the current and increasing the efficiency of data reading. And, in accordance with such structure, the invention also discloses associated manufacturing method and operation method.

Description

3280twf.doc / 006

Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (/) The present invention relates to a memory structure, a manufacturing method and an operating method thereof, and in particular to a multi-state flash memory cell structure and a manufacturing method And how to do it. Please refer to FIG. 1, which shows a conventional AND flash memory. Taking this figure as an example, we can form a deep N-well 110 in a P-substrate 100, and then form a P-well 120 in the deep N-well 110. As the active area of the architecture flash memory. Then, we can use the P-type well region 120 as the basis to construct a flash memory structure, including a drain 130, a lightly doped region 140, a source 150, and a stack gate 180. The stack gate 180 can be controlled by the control gate 160 and the floating gate. The gate 170 is formed, and the drain 130, the shallow doped region 140, and the source 150 are all N-type conductive types. The ion doping concentration of the shallow doped region 140 is lower than that of the drain 130 and the source 150. In the subsequent metal connection process, the control gate 160 can be connected to the word line, the drain 130 can be connected to the bit line, and the source 150 can be connected to the source line. ); The operation method of these AND-type flash memories will be described below. The operation method of AND flash memory is as follows: When erasing (erase) operation, it is realized by using "channel FN injection of electrons". At this time, the voltages at each end point are controlled separately. The gate 160 applies a voltage of 10 volts, the source 150 and the P-well region 120 apply a voltage of 8 volts, and the drain 130 is in a floating state. In programming operation, it is realized by "edage FN ejection of electrons". At this time, the terminal voltages are respectively -10 volts applied to the control gate 160 and 6- ------ Ί,-装-· to (Please read the precautions on the back before filling out this page)

-、 1T '丨 The size of the paper is applicable to the Chinese National Standard (CNS) M specification (210 × 297). 3280twf.doc / 006 3280twf.doc / 006 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (A) Volt voltage, the P-type well area 120 is grounded, and the source electrode 150 is in a floating state. In the past literature, it has been proven that when flash memory performs the "electronic edge tunneling ejection" operation, it is often accompanied by "band-to-band tunneling". The leakage current caused by the "band-band energy tunneling effect" is affected by the acceleration of the lateral electric field, and it is easy to derive the adverse effect of "hot hole injection", which leads to the degradation of element characteristics. In summary, the flash memory used in practice is often accompanied by the "band-band-band-pass effect" when performing the "electronic edge pass-through shot" operation. This "band-band pass-through effect" The "leakage current" caused by the "effect" is affected by the acceleration of the lateral electric field, which can easily lead to the adverse effect of "hot hole injection" and cause the degradation of the tunneling oxide layer. Therefore, the object of the present invention is to provide a multi-state complementary flash memory cell structure 'to avoid the degradation of element characteristics, and to improve the memory cell access performance by a parasitic amplification circuit. Therefore, another object of the present invention is to provide a method for manufacturing a multi-state complementary flash memory cell. The manufacturing method is relative to the structure provided by the present invention. Therefore, another object of the present invention is to provide a method for operating a multi-state complementary flash memory cell. The operation method is relative to the structure provided by the present invention. In order to achieve the above and other objectives, the present invention provides a multi-state complementary flash memory cell. We can form an N-deep well in a P-type substrate, and then form a P-well area in the N-type deep well, as a complementary flash architecture. Active area of memory cells. Then 'I can use p-type wells as a basis, and complement each other. 4 Applicable Chinese Standards (CNS) --- ---------- ^ ------ 1T ----- » * · (Please read the precautions on the back before filling this page) 3280twf.d〇c / 〇〇6 A? H7 —... .............-------- V. DESCRIPTION OF THE INVENTION A > type flash memory cell includes a drain, a floating doped region 'source, and a push-pull gate. The stacking gate can be composed of a control gate and a floating gate. The electrical properties of the floating doped region and the source are different from those of the P-type well region. Low; the electrical property of the drain electrode is the same as that of the P-type well area, which is a P-type conductive type. These complementary flash memory cell structures can be parasitic with a bipolar transistor for current amplification, and relative to these structures, the related manufacturing methods and operating methods are exposed. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 FIG. 2 shows a conventional AND flash memory. FIG. 2 shows a structure diagram of a multi-state complementary flash memory cell provided according to a preferred embodiment of the present invention. FIGS. 3A to 3E show Corresponding to the structure of the complementary flash memory cell shown in FIG. 2, a method for manufacturing a multi-state complementary flash memory cell is provided; FIG. 4 ^ Paragraph of the multi-state complementary flash memory provided in FIG. 2 The circuit diagram; and S B 4) || ^^^ are used to explain the operation method using the multi-state complementary flash memory cell of the present invention. Explanation of the marks in the drawings: 30 stack gates; 100 P-type bases; 110 N-type deep wells; 120 P-type wells; This paper size applies to China National Standard (CNS) A4 specification (210X297 public) -------- -拍 衣 ------- IT -----— lacquer. (Please read the notice on the back Jii before filling out this page} Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 3280twf.doc / 006 Λ7 V. Description of the invention (f) 130 drain; 140 shallow doped region; 150 source; 160 control gate; 170 floating gate; 180 stacked gate; 200 P-type base; 210 N-type deep well; 220 P-type well area; 230 drain; 240 floating doped region; 250 source; 260 control gate; 270 floating gate; 280 stacked gate; 300 P-type base; 310 N-type deep well; 320 P-type well area; 330, 330a through oxidation Layer; 340 polycrystalline silicon; 340a floating gate; 350, 350a dielectric layer; 360 polycrystalline sand; 360a control gate; 370 N-type doped region; 370a floating doped region; 380 drain; and 390 source. Better Examples

Please refer to FIG. 2, which illustrates a structure diagram of a multi-state complementary flash memory cell according to a preferred embodiment of the present invention. Taking this figure as an example, we can form an N-type deep well 210 in the P-type substrate 200, and then form a P-type well region 220 in the N-type deep well 210 as the active area of the complementary flash memory structure. Then, we can use the P-type well region 220 as the basis to construct a complementary flash memory cell, including a drain 230, a floating doped region 240, a source 250, and a stack gate 280. The stacking gate 280 can be composed of a control gate 260 and a floating gate 270. The electrical properties and P of the floating doped region 240 and the source 250 are in accordance with the Chinese National Standard (CNS) Λ4 specification (2 丨 0X297) 3280 twf. doc / 006 3280 twf. doc / 006 Printed by the Central Laboratories of the Ministry of Economic Affairs, Shelley Consumer Cooperative, V. Description of Invention (Village) Well type 220 is different, it is N-type conductivity type, and floating doped area 240 ions The doping concentration is lower than the source 250; the drain 230 has the same electrical properties as the P-type well region 220 and is a P-type conductive type. Generally speaking, these complementary flash memory cell systems are structured at the P-type well region 220, the source 250 is located on the surface of the P-type well region 220, and the drain 230 is also located on the surface of the P-type well region 220 with a distance from The source electrodes 250 are adjacent; the stack gate 280 covers the surface of the P-type well region 220 between the source electrodes 250 and the drain electrodes 230. In addition, the floating doped region 240 is located around the drain 230 and extends to the surface of the P-type well region 220 between the source 250 and the drain 230, and is coupled to the stack gate 280; The property is the same as that of the source 250 and is between the P-well region 220 and the drain 230. In the subsequent metal connection process, the control gate 260 can be connected to a word line, the drain 230 can be connected to a bit line, and the source 250 can be coupled to a source line. ); The manufacturing method of these complementary flash memory cells will be described below. Please refer to FIGS. 3A to 3E, which illustrate a method for manufacturing a complementary flash memory cell corresponding to the complementary flash memory cell structure shown in FIG. 2. Referring to FIG. 3A, first, we can implant N-type ions into P-type substrate 300 to form N-type deep well 310, and implant P-type ions into N-type deep well 310 to form P-type well region 320. Based on the P-type well area 320, these complementary flash memory cell structures can be constructed. Referring to FIG. 3B, we can form a tunneling oxide layer 330 on the surface of the P-type well region 320, and form a polycrystalline silicon layer 340 to cover the surface of the tunneling oxide layer 330. Next, define the polycrystalline silicon layer 340 and the tunneling oxide layer 33. --------- Installation ------ Order ----- >. Line- / (Please read the back first Note: Please fill in this s) This paper size is applicable to China National County (CNS) A4 specifications (21〇297297) 3280twf.doc / 006 ΑΊ ____ H? V. Description of the invention (έ) can become a floating gate 340a, And the tunneling oxide layer 330a is between the floating gate 340a and the P-type well region 320. Please refer to FIG. 3C, we can form a dielectric layer 350 to cover the surface of the floating gate 340a, and form a polycrystalline silicon layer 360 to cover On the surface of the dielectric layer 350; as shown in FIG. 3D, after the polycrystalline silicon layer 360 is defined, it can become the control gate 360a 'and the dielectric layer 350a is between the control gate 360a and the floating gate 340a. In addition, For the sake of simplicity, we can collectively refer to the control gate 360a, the dielectric layer 350a, the floating gate 340a, and the tunneling oxide layer 330a as the stack gate 30 for the convenience of subsequent explanations. After the stack gate 30 is formed, the ion implantation can be used. In the method, an N-type doped region 370 is formed at the surface of the P-type well region 320. The N-type doped region 370 is adjacent to one side of the stack gate 30 and extends to the bottom of the stack gate 30. The tunneling oxide layer 330a is in contact. Please refer to FIG. 3E. We can use the ion implantation method to form a P-type doped region in the N-type doped region 370 as the drain 380 of the complementary flash memory cell. Among them, the ion doping concentration of the drain 380 is higher than that of the P-type well region 320. It should be noted that when the drain 380 is formed, the original N-type doped region 370 is also defined as a floating dopant. The region 370a, that is, the floating doped region 370a is located around the drain electrode 380 and extends to the bottom of the stack gate 30. In addition, we can form another N-type doped region on the surface of the P-type well region 320, and The other side of the stack gate 30 is adjacent to serve as the source 390 of the complementary flash memory cell; wherein the ion doping concentration of the source 390 is higher than that of the floating doped region 370a. Finally, a metal connection process is used. , Can connect the control brake 360a to the copybook paper size applicable Chinese National Standard (CNS) A4 specification (21〇297297) 3280twf. Doc / 006 hi H7 _ _____ 5. Description of the invention (7) Yuan line, drain electrode 380 Connected to the bit line, and source 390 is coupled to the source line to perform data encoding, reading, and erasing operations Please refer to Fig. 4, which shows the parasitic circuit diagram generated according to the complementary flash memory cell structure provided in Fig. 2. First of all, we must understand that the present invention is different from the conventional technique shown in Fig. 1 The reason is that the conventional memory cell drain is an N-type dopant, and the memory cell structure provided by the present invention is formed by a P-type dopant to form a drain. Therefore, the conventional technique shown in FIG. Flash memory cell structure, and according to the complementary flash memory cell structure provided in Figure 2, the equivalent circuit shown in Figure 4 can be derived; the equivalent circuit shown in Figure 4 will be used below Basis, explain the benefits it has obtained. It can be seen from the figure that the parasitic transistor M1 and the parasitic transistor M2 share the same control gate. In addition, the source of the parasitic transistor M1 is coupled to the well region of the parasitic transistor M2 and the drain of the parasitic transistor M2 It is coupled to the well region of the parasitic transistor M1. It should be noted that these complementary flash memory cell structures parasitic a transistor Q1, the base of transistor Q1 is coupled to the well region of parasitic transistor M1, the emitter of transistor Q1 and the parasitic transistor M1 are drawn. The collector of transistor Q1 is coupled to the source of parasitic transistor M1. The equivalent circuit of these complementary flash memory cells, in addition to having a parasitic transistor M2 equivalent to the structure shown in Figure 1, includes a parasitic transistor M1 and a transistor Q1, so the overall circuit operation Will be more complicated; generally speaking, since the drain of the parasitic transistor M2 is used as the base of transistor Q1, and the emitter of transistor Q1 is the drain of transistor M1, therefore, the amplification of transistor Q1 Function, the drain current of the transistor M1 can be applied to the paper size of the Chinese National Standard (CNS) A4 (210X297 mm) II binding " line I (please read the note on the back first and fill in this page) Printed by the Bureau of Standardization and Consumer Electronics Co., Ltd. 3280twf.doc / 006 Η7 ______ V. Description of the invention (?) Enlarged to 1 + β times of the drain current of transistor M2 because the drain of transistor M1 is coupled to the bit line Therefore, compared with the memory cell structure shown in Figure 1, the drain current of these complementary flash memory cells will increase by l + β times, so the performance of data access can be greatly improved. The operation method corresponding to the complementary flash memory cell of the present invention will be described below. Please refer to FIG. 5. FIG. 5 is a diagram for explaining an operation method using the complementary flash memory cell of the present invention. In the following, data erasure, read, and programming are described. Explain. In order to simplify the illustration and facilitate the description, the word line voltage is represented by Vwl in the following and in the figure, where the word line is coupled to the control gate in the stacking gate; V & represents the bit line voltage, where the bit The line is coupled to the drain of the memory cell; Vslj represents the source line voltage, where the source line is coupled to the source of the memory cell; VPW represents the well area voltage and is used to represent the potential of the P-type well area. The detailed operation method will be described below. Please refer to FIG. 5 (1), which shows the erase operation of the complementary flash memory cell. When the erasing operation is performed, it is completed by "channel FN ejunction of electrons", and the end point bias voltages are VWL = -l0V 'VSL = 8V, VPW = 8V, drain The pole is in a floating state (Hoating); by this, electrons can be ejected from the floating gate into a complementary flash memory cell to complete the erasing operation. Please refer to FIG. 5 (2), which shows the complementary fast Schematic diagram of the read operation of the flash memory cell. When the read operation is performed, the bias voltage of each terminal is VWL = 3 ~ 5V 'VBL = 1V, VSL = 〇V' VPW = 〇V; by this, 10 can be completed. This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X297 male) 3280twf. Doc / 006 3280twf. Doc / 006 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Bei Gong Xiao F Cooperatives 5. Description of the invention (?) Complementary flash Read operation of the memory cell. It should be noted that 'due to the parasitic bipolar transistor (Figure 4), when a complementary flash memory cell performs a read operation, the on-state current will pass through this parasitic bipolar transistor. The crystal is amplified-so the read current obtained on the bit line is faster than the traditional flash The memory cell is large, about l + β times of the past. In this way, a simpler peripheral circuit can perform faster reading operations and reduce the cost of peripheral circuit design. Please refer to Figure 5 (3), which Schematic diagram of program coding operation of complementary flash memory cells. When performing the program coding operation, 'band-to-band tunneling induced hot electron injuntion' is used. To complete, the terminal bias voltages are VWL = 8 ~ 10V, VBL = -6 ~ -3V, VSL = 0 ~ 3V, VPW = 0V; by this, electrons can be injected into the floating doped region from the floating doped region. Set the brake to complete the program coding operation. Please refer to Figure 5 (4), which shows the timing diagram of the multi-state program coding operation of the complementary flash memory cell. This multi-state program coding can be completed in two stages. In the first stage, the electron injection is performed using "band-to-band tunneling induced hot electron injunUoii". The end point biases are added to the control gate plus one. Program voltage, such as bias VPC] M, in The drain is biased with VBL, the source is biased with Vsl_, and the P-well area is grounded, where the bias is as described above. In the second stage, the voltage of the bit line is discharged to the potential of the P-type well region by the conduction of the parasitic P-type channel transistor (parasitic transistor M2 'Figure 4), so that the electrons can no longer be injected, and then reach The first self-receiving paper size applies the Chinese National Standard (CNS) A4 specification (2ΐ〇χ 297 public power) --------- ^ ------ II ------ ^ { Chu Xian read the back _Attentions ^: fill in this page) 3280twf.doc / 006 V. Description of the invention (/ C) Convergence state; the end point bias voltage is a control voltage plus a discharge voltage, such as bias voltage vDISI 'The bias voltage VBL is applied to the drain and the bias voltage Vn is applied to the source, and the P-type well region is grounded. Repeat the above multi-state program coding operation with different control gate bias voltages vDIS2 to achieve the second self-convergent state; similarly, with different control gate bias voltages VDISn, the η self-convergence state can be achieved, and the multi-state program coding can be achieved. operating. In summary, compared with the conventional flash memory "billion cells", the complementary flash memory cell provided by the present invention has at least the following advantages: 1. When the complementary flash memory cell performs a read operation The on-current will be amplified by this parasitic bipolar transistor, so the read current obtained on the bit line is increased by about l + β times compared with the traditional flash memory cell, which can be read faster than simple peripheral circuits. Fetch operation to reduce the cost of peripheral circuit design. 2. Using these complementary flash memory cell structures, no thermal holes are generated during the "erase" and "programming" operations, which can greatly improve the reliability of the tunneling oxide layer and make the complementary flash memory cell The structure is not easy to degenerate. ”Printed by the Shell Standard Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 3. Using these complementary flash memory cell structures, when performing“ programming ”operations, it is induced by the“ band-band-band tunneling effect ”. "Hot electron injection" to improve the working efficiency of memory cells. 4. Using different control gate bias voltages VDISn, it can achieve the η self-convergence state, and achieve multi-state programming operation. Although the above is a description of the structure, manufacturing method and operation method of the complementary flash memory cell constructed by the P-type well area, it is not intended to limit the paper size to the Chinese National Standard (CNS) A4 specification (210 × 297). Shovel) 3280twf.doc / 006 1Γ V. Description of the invention (//) The person who is familiar with this technology uses the N-type well area to construct a complementary flash memory cell structure, manufacturing method and operation method that are opposite to the present invention. Without departing from the spirit of the invention. • The above description is only a preferred embodiment of the present invention, but it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the appended patent application. Any equivalent changes and modifications made according to the patent application scope of the present invention shall fall within the scope of the invention patent. Order 1 · ^ 袅. (Please read the notes on the back before filling out this page) The paper standard printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs applies the Chinese national standard rate (〇 阳), \ 4 specifications (2 丨0 乂 297 to go)

Claims (1)

Printed by the Central Consumers Association of the Ministry of Economic Affairs and Consumer Cooperatives 3280twf.doc / 006 B8 _g | __ VI. Scope of Patent Application: A multi-state complementary flash memory cell structure, including: a first type I ion doping Region as a well region; a second-type ion-doped region on the surface of the first first-type ion-doped region as a source; a second first-type ion-doped region on the first At the surface of the first type ion doped region and adjacent to the source at a distance as a drain; a stack gate covering the surface of the well region between the source and the drain; and a floating The doped region is located around the drain and extends to the surface of the well region between the source and the drain and is coupled to the stack gate. The floating doped region has the same electrical properties as the source and the A floating doped region is interposed between the well region and the drain. 2. The multi-state complementary flash memory cell structure described in item 1 of the scope of patent application, wherein the well area is of type P. 3. The multi-state complementary flash memory cell structure described in item 2 of the scope of patent application, wherein the well region is doped with a Group III element. 4. The multi-state complementary flash memory cell structure described in item 1 of the scope of patent application, wherein the source is an N-type. 5. The multi-state complementary flash memory cell structure described in item 4 of the scope of the patent application, wherein the source is doped with a Group 5 element. 6. The multi-state complementary flash memory cell structure described in item 1 of the scope of patent application, wherein the well region is doped with boron. 7. The multi-state complementary flash memory cell structure described in item 6 of the scope of the patent application, wherein the drain is doped with a Group III element. —1- I · n ml I * .......-^ tfJ1- io ^ —-II (Please read the notes on the back before filling out this page) The paper size applies to Chinese National Standard (CNS) A4 Specifications (210X297mm) 328〇twf.doc / 006 A8 B8 C8 D8 Printed by the Central Consumer Bureau of the Ministry of Economic Affairs, Consumer Cooperative, 夂 Applicable patent scope ~ 8. As many as the gambling status described in 1 5 Complementary flash d 丨 cell structure ', wherein the ion doping concentration of the heteropole is higher than the ion doping concentration of the well region. 5 9. Rufu patent _ the first leg of the money-like view complementary flash " Hidden cell structure ', the ion impurity concentration of the towel electrode is higher than the ion doping concentration of the floating doped region. ~ 10. If the special contact 1 | the multi-color complementary flashing structure described in the i-th aspect described above, the stack gate includes a control gate and a floating gate, and the floating gate is between Between the control gate and the surface of the zone. U. A method for manufacturing a multi-state complementary flash memory cell for constructing the complementary flash g-memory cell at a well area. The method for manufacturing the multi-state complementary flash memory cell includes the following steps: Forming a stack gate on the surface of the well; forming a first miscellaneous region; the first doped region is located at the surface of the well region and is adjacent to one side of the stack gate; The electrical property of the region is different from that of the well region; a second doped region is formed, the second doped region is located at the surface of the first doped region, and the electrical property of the second doped region is the same as that of the well region, As a drain of the complementary flash memory cell; and forming a third doped region, the third doped region is located at the surface of the well region and adjacent to the other side of the stacked gate, and the first The electrical properties of the three doped regions are different from the well regions to serve as a source of the complementary flash memory cell. 12. The method for manufacturing a multi-state complementary flash memory cell as described in item 11 of the scope of the patent application, wherein the stacking gate includes a control gate and a floating paper scale, and is used in China National Standards (CNS) A4 specification ( 210X297 mm) -----· (Please read the precautions on the back before filling in this page)% τ I 3280twf.doc / 006 A8 B8 C8 D8 VI. Apply for a patent application. 13. The method for manufacturing a multi-state complementary flash memory cell according to item 12 of the scope of the patent application, wherein the step of forming the stack gate further comprises: forming a tunneling oxide layer to cover the surface of the well area; forming a first A polycrystalline silicon layer covers the surface of the tunneling oxide layer; defines the first polycrystalline silicon layer to become the floating gate; forms a dielectric layer covering the surface of the floating gate; forms a second polycrystalline silicon Layer covering the surface of the dielectric layer; and defining the second polycrystalline silicon layer to become the control gate 14. Rushen | Flash memory cell junction ^ 15. Multiple states complementary as described in Shen 1 Wai 4 The green well region of the flash memory cell is doped with a third group of elements. 16. The multi-state complementary flash memory cell primitive described in item p. 11 of the p. Π. The multi-state complementary flash memory cell junction source described in claim 16 is doped with a Group 5 element. 18. The multi-state complementary flash memory cell junction repair region described in claim 11 is doped with boron. The multi-state complementary fast-well area P type as described in item 11. Back gutter stitch printing of employees ’cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 19. If applying for a flash memory cell I 20. The multi-state complementary fast-stomach k-polar doping described in the flash memory cell Qin ion doping concentration item 18 Miscellaneous third group elements. Sentence Fan, the multi-state complementary fast 1¾ pole ion doping concentration described in item 11 is higher than 16 in this well area. The paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 3280twf.doc / 006 A8 B8 C8 D8 6. Application of the multi-state complementary flash memory described in the special scope item 丨 丨 The ion doping concentration of the source is higher than that of the floating doped region. 22.—Multiple) Canine-state complementary flash memory cell manufacturing method 'is used to construct the complementary flash memory cell in a well area. The method for making the multi-state complementary flash memory cell includes the following steps: Forming a stacked gate on the surface of the well region, wherein the step of forming the stacked gate further includes: forming a tunnel oxide layer to cover the surface of the well region; forming a first polycrystalline silicon layer to cover the tunnel Penetrate the surface of the oxide layer; define the first ~ polycrystalline layer to become a floating structure; form a dielectric layer to cover the surface of the floating gate; form a second polycrystalline silicon layer to cover the surface of the dielectric layer ; And \ define the second polycrystalline silicon layer to become a control gate; forming a first doped region, the first doped region is located at the surface of the well region and adjacent to one side of the stacked gate, and The electrical properties of the first doped region are different from those of the well; printed by Zhengong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs --------- ^ —--{(Please read the note on the back first Fill out this page again) to form a second doped region, the second doped region is located in the first doped region table And the electrical properties of the second doped region are the same as those of the well region as a drain of the complementary flash memory cell; and a third doped region is formed, the third doped region is located in the The surface of the well region is adjacent to the other side of the stack gate, and the electrical properties of the third doped region are different from that of the well region as a source of the complementary flash memory cell. 23 · As stated in item 22 of the scope of the patent application, the multi-state complementary fast-moving paper size is not applicable to the Chinese National Standard (CNS) A4 (210X297 mm) 3280twf.doc / 006 Α »B8 C8 D8 as described in item 22 The multi-state complementary fast pole is N type. 6. Scope of patent application The method for making flash memory cells, wherein the well area is of type P. 24. Cai J Yi You I? Stomach 231 Bei Jian shirt sincerity 3 thief flash memory cells Conclusion Well area is doped with a third group of elements. 25. Ru Shen: 'Human Flash Memory Cell: Please read 2β first. Multi-state complementary Flash Memory Cell I as described in item 25 27. If you apply for Flash Memory Knot = Construct the source system Doped with Group 5 elements. f The multi-state complementary fast well region described in item 22 is doped with boron. The multi-state complementary flash memory cell described in item 27 is doped with a Group III element. Page 29. The method for manufacturing a multi-state complementary flash memory cell according to item 22 of the application, wherein the ion doping concentration of the drain electrode is higher than the ion doping concentration of the well region. 30_ The method for manufacturing a multi-state complementary flash memory cell according to item 22 of the scope of the patent application, wherein the ion doping concentration of the source electrode is higher than the ion doping concentration of the floating doped region. 31. A method for operating a multi-state complementary flash memory cell. The multi-state complementary flash memory cell is structured on the surface of a well area and has a control gate, a source, and a drain. The well area, the control gate, the source and the drain apply a well area voltage, a word line voltage, a source line voltage, and a bit line voltage. The operation method of the complementary flash memory cell includes: The following steps: When performing an erase operation, the voltage of the character line is a low level voltage. 18 paper sizes are used in the Chinese National Standard (CNS) A4 wash grid (210X297 mm). Printed by the Office of the Consumer Cooperative 3280twf.doc / 006 A8 B8 C8 D8 Patent application scope The source line voltage and the well area voltage are higher than the low level voltage, and the drain electrode remains floating. 32. The method for operating a multi-state complementary flash memory cell as described in item 31 of the scope of the patent application, wherein the low-level voltage is -10 volts, and the source 'line voltage and the well area voltage are 8 volts. 33. A method for operating a multi-state complementary flash memory cell. The multi-state complementary flash memory cell is structured on the surface of a well area and has a control gate, a source, and a drain. The well area, the control gate, the source and the drain apply a well area voltage, a word line voltage, a source line voltage and a bit line voltage, and the operation of the multi-state complementary flash memory cell The method includes the following steps: When a reading operation is performed, the source line voltage and the well area voltage are an I, and the characters are read first. Install the low level printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Voltage, the bit line voltage is higher than the 彳 f line voltage is higher than the bit line voltage. 34. As described in item 33 of the scope of the patent application, the operation method of the memory cell, wherein the source line voltage and the well area voltage are 0 volts, the bit line voltage is 1 volt, and the word line voltage is 3 ~ 5 volts. 35. —Multi-state complementary flash memory cell operation method'The multi-state complementary flash memory cell is structured on the surface of a well area and has a control gate, a source and a drain, and The well area, the control gate, the source and the drain apply a well area voltage, a word line voltage, a source line voltage and a bit line voltage, and the operation of the multi-state complementary flash memory cell The method includes the following steps: When a coding program is performed, the well area voltage is grounded, and the bit line is 19. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm). The line is 32 80twf.doc / 006 A8 B8 C8 D8 6. The scope of the patent application is a low level voltage, the source line voltage is higher than the low level voltage, and the 50 Hz line voltage is between the source line voltage and the well area. Voltage. 36. The method for operating a multi-state complementary flash memory cell as described in item 35 of the application SP3 patent scope table, wherein the source line voltage is 0 ~ 3 volts, the well area voltage is 0 volts, and the bit line voltage It is -6 ~ -3 volts, and the word line voltage is 8 ~ 10 volts. 37. A method of operating a multi-state complementary flash memory cell. The multi-state complementary flash memory cell is structured at the surface of a well area and has a control gate, a source, and a drain, respectively. A source line voltage and a bit line voltage are applied to the source and the drain. The operation method of the multi-state complementary flash memory cell includes a multi-state coding program. The multi-state coding program includes the following steps: The well area is grounded; a program voltage pulse is applied to the control gate, the program voltage pulse is 8 to 10 volts; and a discharge voltage pulse is applied to the control gate, the discharge voltage pulse is -5 to 0 volts, the program voltage The continuous combination of the pulse and the discharge voltage pulse can discharge the bit line voltage to the potential of the well area to reach a self-convergent state. 38. A method of operating a multi-state complementary flash memory cell 'The multi-state complementary flash memory cell system is structured at the surface of a well area and has a control gate, a source and a drain, and The source and the drain apply a source line voltage and a bit line voltage. The operation method of the multi-state complementary flash memory cell includes a multi-state coding program.囷 家 梂 准 (CNS) A4 Specification (210X297mm) III ϋ ϋ I! N IIIII nn ^ I nni— J— ^ * One · s (please read the note f on the back before filling this page) Ministry of Economic Affairs Printed by the Consumer Standards Cooperative of the Central Bureau of Standards 3280twf.doc / 006 A8 B8 C8 D8 VI. Application for Patent Scope The code printing process of the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs includes the following steps: Ground the well area; At the control gate A program voltage pulse is applied, the program voltage pulse is 8 to 10 volts; and a discharge voltage pulse is applied to the control gate, the discharge voltage pulse is -5 to -4 volts, the program voltage pulse and the discharge voltage pulse Enabling the combination to obtain a continuous bit line voltage is discharged to the potential of the well region, to a first self-converged state. 39. A method for operating a multi-state complementary flash memory cell. The multi-state complementary flash memory cell is structured at the surface of a well area and has a control gate, a source, and a drain, respectively. A source line voltage and a bit line voltage are applied to the source and the drain. The operation method of the multi-state complementary flash memory cell includes a multi-state coding program. The multi-state coding program includes the following steps: The well area is grounded; a program voltage pulse is applied to the control gate, the program voltage pulse is 8 to 10 volts, and a discharge voltage pulse is applied to the control gate, the discharge voltage pulse is -3.5 to -2.5 volts, the program The continuous combination of the voltage pulse and the discharge voltage pulse can discharge the bit line voltage to the potential of the well area, and reach the second self-convergent state. 40. A method for operating a multi-state complementary flash memory cell. The multi-state complementary flash memory cell is structured on the surface of a well area and has a control gate, a source, and a drain. The source electrode and the drain electrode are applied. Please read the remarks and the matters before you / fill in (Writing 衣 This page is bound to paper size, using China National Standard (CNS) A4 size (210X297 mm) A8 3280twf.doc / 006 B8 C8 D8 6. Application scope Patent source voltage and bit line voltage. The operation method of the multi-state complementary flash memory cell includes a multi-state coding program. The multi-state coding program includes the following steps: The well area is grounded; a program voltage pulse is applied to the control gate, the program voltage pulse is 8 to 10 volts; and a discharge voltage pulse is applied to the control gate, the discharge voltage pulse is -2 to -1 volt, the program The continuous combination of the voltage pulse and the discharge voltage pulse can discharge the bit line voltage to the potential of the well area, and reach the third state of self-convergence. (Please read the note on the back before reading Write this page) Ministry of Economic Affairs Bureau of Standards 22 employees consumer cooperatives printed paper scale applicable to Chinese National Standard (CNS) A4jyt grid (210X297 mm)