經濟部中央揉準局負工消费合作杜印裝 A7 --87 ---- 五、發明説明（1 ) 本發明係有關一種積體電路，特别係有關一種可施加 於多餘記憶體陣列之行解碼器。 當半導體記憶體，如靜態隨機存取記憶體(SRAM)或動 態隨機存取記憶體(DRAM)，變得愈來愈大時’相關之多 餘（redundant)記憶體陣列之尺寸與複雜度也相對地增加° 眾所皆知，多餘記憶陣列已引起廣泛興趣’如在取代無效 陣列行或列，及行解碼器或多工器之設計上° 第5圖所示為一習知技術，其中陣列500、行解碼器 510以及感應放大器陣列520分別緊鄰著多餘陣列5〇5、 多餘行解碼器515以及多餘感應放大器525 °感應放大器 陣列輸出（SIO)501舆多餘感應放大器陣列輸出（XI〇)502則 饋入（feed)至提供最後輸出503之1〇多工器530。 另一相關習知技術為美國專利第5,257,229號，其揭露 併用多餘陣列之半導體記憶裝置。該習知技術將多餘行映 像至多重方塊(block)位址以提供行多餘性。美國專利第 5,471,426號則揭露多餘行，其可取代被多餘行解碼器所選 擇之任一記憶方塊中之一行。該設計需要額外的行解蜗器 與複雜的多工器。美國專利第5,570,318號揭露一半導體記 憶裝置，其每一方塊具有兩多餘行，各方塊有其多餘行解 碼器。 本發明之目的在於提供電路與方法，其無需額外行解 碼器，當有陣列為無效時，允許行解碼器以選擇多餘陣列。 本發明之另一目的在於使得相鄰單元在一陣列中排列 成具有相同行位址》 本紙張尺度逋用中國國家榡準（CNS ) A4规格（210X297公釐） (請先閲讀背面之注$項再填寫本頁) 袈 訂 經濟部中央揉率局貝工消费合作社印装 A7 _B7_ 五、發明説明（2 ) 本發明之又另一目的在於提供電路與方法，其可縮減 繞線、減少對額外行解碼器、多餘陣列之定址、多餘輸出 入(XIO)信號與複雜IO多工電路之需求。 為達成上述目的，本發明將上述元件置於一基本模組 之中，該模組包括一具有保險絲之行解碼器，當該保險絲 燒斷時，會立刻不選擇不良陣列而選擇多餘陣列。藉由對 各行解碼器之多餘行選擇線進行邏輯“或（OR)”運算，任一 行解碼器可選擇多餘陣列。對各基本模組之各輸出資料進 行邏輯”或”運算可簡化輸出繞線。對現階陣列結構進行複 製可得到更高階陣列結構。 為讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： 第la圖為本發明中第lb圓之高階方塊圖； 第lb囷為本發明之行解碼器之電路圈； 第2圖為本發明之行解碼器陣列之示意圖； 第3圖為本發明之陣列組合之示意圏； 第4圖為本發明之半導體記憶裝置之示意圖； 第5圖為習知技術之半導體記憶裝置示意圖；以及 第6圖為本發明之方法之方塊圖。 符號說明 10〜行解碼器；100〜預解碼電路；101、102〜信號輸 入；120〜保險絲電路；140〜行選擇電路；141、142〜輸 出 I. " ! -I -< ί - -i— I - - - --- In -II - ' '·-- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 經濟部中央橾率局貝工消费合作社印製 A7 B7 五、發明説明（3) 實施例 為了要避免“消除瑕疵”所可能帶來的困擾，多餘記憶 陣列之設計已愈來愈複雜。如此將增加電路複雜度、電路 實際評估需求、與時間延遲。本發明揭露一新方法，其使 得行解碼器陣列選擇多餘陣列而成為一般陣列之一部份。 可經由新行解碼器來達成此目的，該行解碼器會對所有多 餘陣列行選擇線進行“WIRE-OR”運算。此外，本發明也允 許感應放大器輸出（多餘或一般）與下一更高階結構之輸出 之簡單“WIRE-OR”運算。 現在請參考第la圖，其為本發明之行解碼器10之元 件之高階示意圖。預解碼(pre-decode)電路100在接點A處 與行選擇電路140相連接。保險絲電路120在接點B與接 點C處與行選擇電路140相連接。信號輸入101與102連 接至預解碼電路100之輸入端。行選擇電路140之輸出則 連接至輸出141與142。 第lb圖為行解碼電路10之示意圖，行解電路10在當 一般陣列行變成無效時將不選擇該一般陣列行，而選擇多 餘陣列行。當獨特陣列與區（section)位址被解碼時，預解 碼電路100將致能端點A »在保險絲131燒斷時，保險絲 電路120會經由端點B與C而活化多餘陣列行之選擇。控 制信號PU121由開機(power-up)電路所提供；控制信號PU 於開機之初持續為低電位以鎖住接點B與C，然後昇壓至 Vcc。行選擇電路140，其輸入端連接至接點A、B與C， 致能CS輸出信號141或CRCS輸出信號142，以選擇一般 本纸張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） ^—-^^1 HI m HI HI . 1^1 1^1 in ϋ m -'. (請先閲讀背面之注意事項再填寫本頁) A7 B7 五、發明説明（4 ) 陣列行或多餘陣列行 複數個預解碼輸入信號102饋入NAND閘。 NAND閘110之輸出連接至反相 之閉極與N通道電晶艘1Μ之_。反相器通1電:趙二 3 連接至SEC輸入減101，而其源極連接至接點a。ρ通 道電晶艘113則並聯通道電晶體112。叫 114之没極連接至端點A，其源極連接至參考電磨端^地 端預解碼電路型預解 pu輸入信號121錢入p通道電晶趙13〇之閘極。p通 道電晶艘130之源極連接至電源參考端—，其汲極連接 至保險絲m。保險絲131之另—端則連接至接地端。p 通道電晶132之源極-汲極連接於電源參考端Vcc與p通 電晶體130之汲極間。反相器133之輸入也連接至p通道 電晶艘130之汲極。反相肖133之輸出則回授至p通道電 晶體132之閘極。端點b連接至p通道電晶體13〇之沒極， 而端點C連接至反相器133之輸出端。 經濟部中央揉準局貝工消费合作社印11 . ϊ ^-- * -, * (請先閲讀背面之注意事項再填寫本頁) 端點A連接至152之一輸入端與N通道電晶 體151之閘極。端點B連接至N通道電晶體15〇之閘極明 端點C連接至NAND閘152之另一輸入端。NANDp4 152 之輸出端連接至行選擇電路之cs輸出端141。行選擇電 路之CRCS輸出端142連接至N通道電晶體151之攻極 N通道電晶體151之源極接地，而完成行選擇電路。 當在陣列辛選擇到失效行址時，因為保險絲l3l 匕被 本纸银纽適用中ϋΗ家椟準（CNS)續^ ( 21GX297公着） 經濟部中央揉準局員工消費合作社印裝 A7 B7 五、發明説明（5 ) 燒斷，在信號PU被下拉時，將導致電晶體130導通’而 強迫端點B之電位上升。反相器133使得電晶體132之閘 極與端點C之電位上升。電晶體150因而被導通，NADN 閘152將重新運作。CS輸出141現為失能，CRCS輸出 142由於包括電晶體150與151之AND閘之輸出，故其被 致能。電晶體132會藉由傾銷Vcc至接點B而分別鎖住位 於接點B之高電位與接點C低電位。這將造成永久不選擇 失效行，即使PU於功率提昇後上升至Vcc。 當SEC輸入信號101與全部預解碼輸入信號1〇2皆在 正電位時’輸出端點A也會在正電位，會就是指定行將被 選擇。如果保險絲131被燒斷，則CS輸出141將被致能（負 電位），一般陣列行之選擇動作與CRCS輸出142將被失能 (正電位）以防正選擇到多餘行。如果保險絲131被燒斷， CRCS輸出142會被致能（負電位），而允許選擇多餘陣列 行。在這同時，CS輸出141會被失能（正電位），而一般陣 列行將不被選擇。 現在請參考第2圖，其示出行解碼器陣列2〇，該行解 碼器陣列20係由標號由CD0、CD1至CDn之複數個行解 碼器電路10與CRCD電路201所構成》輸入211，其標號 為RSEC ’為CRCD電路201之輸入。電路201包括Ρ通 道電晶體202，該Ρ通道電晶體202之閘極連接至RSEC 輸入211，其源極連接至Vcc，其及極連接至CRCD輸出 212。CRCS-WIRE輸出221，為對全部CRCS輪出142與 CRCD輸出212進行WIRE-OR所得之結果。當汉咖輸入 本纸張尺度適用中國國家標牟（CNS ) A4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 装. ---訂 A7 B7 五、發明説明（6 ) 211輸入負脈衝時，具備上拉電晶艘202、小p通道電晶 體203與反相器204之CRCD電路201將失能多餘陣列行。 如果行位址選擇多餘陣列行，接點CRCS-WIRE輸出221 會被下拉以致能多餘陣列行。一旦任一 CRCS輸出142為 接地態時’ WIRE-OR之功能為強迫CRCD-WIRE輸出221 變為接地態，因而多餘陣列將被選擇。對所有多餘行選擇 線進行邏輯“或”運算的這個方法將使得相關陣列可能為無 效之任一行解碼器能在不需任何定址電路或其他電路的情 況下對多餘陣列進行定址。 需與RSEC信號之資料線等化(eqUaiizati〇n)功能合用 才能達到使多餘陣列行失能之目的。當位址改變時，位址 轉態偵測（ATD)控制信號會對資料線等化進行致能。該 ATD控制信號會強迫rSEC信號成為負電位以在任一周期 中設定CRCS-WIRE之電位為高，電路1〇會決定CRCS-WIRE電位之最後狀態’也就是當CRCS-WIRE被選擇時， 其電位會被拉低’否則持續在高電位，如前面所討論般。 經濟部中央揉率扃負工消费合作社印策 n^i- nn HJ— HH -I-J. —t^i m ·1 I I 1-- (請先閲讀背面之注項再填寫本頁) 現在參考第3圈之半導體記憶陣列組合30，其包括複 數個陣列300(其位址標示由〇至η)與在任何方面上皆相同 於陣列300之多餘陣列305。各陣列是由共享相同位址之 陣列單元之行所組成》半導體記憶陣列組合30更包括如第 2圖之行解碼器陣列20，感應放大器陣列320，與感應放 大器陣列輸出301。 行解碼器電路1〇各有其相對之陣列，多餘陣列則對應 於具有CRCS-WIRE輸出221之CRCD電路201。行解瑪 本紙張尺度逋用中國國家標準（CNS > A4规格（210X297公釐） A7 五、發明説明（7 ) 器陣列20所選擇之陣列，包括多餘_ 感應放大器阵列所放大。 會被讀出並被 感應放大器陣列包括複數感應放大器 方式排列，各感應放大器具有接 、 、 陣列-輸出之控制信號之複數輸收入陣與，由行解碼器 陣列輸出包括在數量上相等於各陣列内之陣出列 線。各輸出線為一陣列單元對全部陣列進行“OR”邏輯運算 所得之結果。也就是，陣列之各單 “WIRE-OR”運算。 J I η干π逆叮 «二::考第4圓之半導艘記憶裝置40，其包括第3 圈中之複數個相同之陣列組合3〇,這些阵列組合之標號由 ^Ν。半導想記憶裝置輪出他會傳送記憶艘資料至主 機。丰導艘記憶艘之輸出線數量相等於組合陣列或3〇5 之行内之陣列單元。半導艘記㈣之各輪出線401為感應 放大器陣列輸出301之其中一條線對全部睁列組合進行 “WIRE-OR”邏輯運算所得之結果。 經濟部中失揉率局貝工消费合作社卬裝 (請先閲讀背面之注意事項再填寫本頁) 請參考第6圖’其為本發明方法之方塊圖方塊6〇1 所示為提供行解碼器之步驟。各行解碼器係有關於一陣 列，且其提供一行選擇線以從該陣列中選擇資料。各行解 碼器也提供多餘行選擇線以從多餘陣列中選擇資料。方塊 602則對全部多餘行選擇線進行遲輯，，或，，之動作。當選擇 到陣列中之無效行時，由於行解蝎器電路中之保險絲已燒 斷(如方塊603所示），而有關於無效陣列之行解碼器之輸 入線PU將在電源開機之初被下拉以製造永久的不選擇》 本紙張又度適用中國國家橾牟（CNS ) A4规格（210X297公釐） 經濟部中央揉準局負工消费合作杜印製 A7 _B7__ 五、發明説明（8 ) 方塊604所示為將有關於無效陣列之行選擇線進行失能。 此時，在方塊605中，將多餘行選擇線下拉至邏輯“零”可 使之致能。藉由提供如方塊602之邏輯“或”之方法，各行 選擇電路之多餘行選擇線被下拉，如此可選擇具有不同I/O 之多餘陣列，如方塊606所示。對各行選擇電路之多餘行 選擇線進行邏輯“或”之方法將允許任一行解碼器，也許其 相關陣列為無效，在不需其他定址電路之情況下對該多餘 陣列定址。 本發明之上述電路與方法之優點在於：（1)提供新的行 解碼器；（2)同一陣列中之鄰近單元被安排為具有相同行位 址，也就是說，具有相同位址之單元將在同一時間内被讀 出；以及（3)將行解碼器中之保險絲燒斷將失能一般但無效 之行，而對多餘行致能。上述之方法與電路可適用於SRAM 或DRAM中。 而本發明所能防止之習知技術之缺點則如下：（1)使用 額外的行解碼器；（2)需要額外的感應放大器；（3)需要多餘 IO信號（XIO);以及（4)使用複雜XIO/IO多工器、習知技術 之結構難以實施，會佔去晶片面積，以及造成額外的累積 層。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。 10 本紙張尺適用中國國家樣率（CNS ) A4现格（210X297公釐) 雇 1^1 nl· n 11 .^n - ^ ，T , - - » (請先閲讀背面之注意事項再填寫本頁)Duty-installed A7 --87 of the Central Ministry of Economic Affairs of the Ministry of Economic Affairs ---- V. Description of the invention (1) The present invention relates to an integrated circuit, and in particular to a line that can be applied to redundant memory arrays. decoder. As semiconductor memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM), becomes larger and larger, the size and complexity of redundant memory arrays are also relatively large It is well known that redundant memory arrays have attracted wide interest, such as in the design of replacing invalid array rows or columns, and row decoders or multiplexers. Figure 5 shows a conventional technique in which the array 500, row decoder 510, and sense amplifier array 520 are located next to the redundant array 505, redundant row decoder 515, and redundant sense amplifier 525 °. It then feeds to the multiplexer 530 which provides the final output 503. Another related conventional technology is U.S. Patent No. 5,257,229, which discloses a semiconductor memory device using an excess array. This conventional technique maps redundant rows to multiple block addresses to provide row redundancy. U.S. Patent No. 5,471,426 discloses a superfluous line, which can replace one of any memory blocks selected by the superfluous line decoder. This design requires additional row wormers and complex multiplexers. U.S. Patent No. 5,570,318 discloses a semiconductor memory device in which each block has two redundant rows and each block has its redundant row decoder. An object of the present invention is to provide a circuit and a method, which do not require an additional row decoder, and when an array is invalid, the row decoder is allowed to select an extra array. Another object of the present invention is to make adjacent cells arranged in an array with the same row address. ”This paper size uses the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the note on the back first) (Please fill in this page again.) 袈 Printed by the Central Government Bureau of the Ministry of Economic Affairs, printed by the shellfish consumer cooperative A7 _B7_ V. Description of the invention (2) Another object of the present invention is to provide a circuit and method, which can reduce the winding and reduce the Requirements for additional row decoders, addressing of redundant arrays, redundant input / output (XIO) signals, and complex IO multiplexing circuits. In order to achieve the above object, the present invention puts the above components in a basic module, which includes a decoder with a fuse. When the fuse blows out, it will immediately select a redundant array without selecting a defective array. By performing a logical "OR" operation on the redundant row selection lines of the decoders of each row, any row decoder can select the redundant array. The logical “OR” operation of each output data of each basic module can simplify the output winding. The higher-order array structure can be obtained by duplicating the current-order array structure. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following exemplifies preferred embodiments and the accompanying drawings to make a detailed description as follows: Brief description of the drawings: FIG. 1a is the present invention High-level block diagram of the lb circle in the middle; lb 囷 is the circuit circle of the row decoder of the present invention; FIG. 2 is a schematic diagram of the row decoder array of the present invention; and FIG. 3 is a schematic diagram of the array combination of the present invention; FIG. 4 is a schematic diagram of a semiconductor memory device of the present invention; FIG. 5 is a schematic diagram of a semiconductor memory device of the prior art; and FIG. 6 is a block diagram of a method of the present invention. Explanation of symbols: 10 to line decoder; 100 to pre-decoding circuit; 101 and 102 to signal input; 120 to fuse circuit; 140 to line selection circuit; 141 and 142 to output I. "! -I-< ί-- i— I------ In -II-'' ·-(Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) Ministry of Economic Affairs Printed by the Central Government Bureau of Shellfisher Consumer Cooperative A7 B7 V. Description of the Invention (3) Example In order to avoid the trouble caused by "eliminating defects", the design of redundant memory arrays has become more and more complicated. This will increase circuit complexity, circuit actual evaluation requirements, and time delay. The present invention discloses a new method that allows the row decoder array to select the redundant array and become a part of the general array. This can be achieved by a new row decoder, which performs a "WIRE-OR" operation on all redundant array row select lines. In addition, the present invention also allows a simple "WIRE-OR" operation between the output of the sense amplifier (redundant or general) and the output of the next higher order structure. Please refer to FIG. 1a, which is a high-level diagram of the components of the row decoder 10 of the present invention. A pre-decode circuit 100 is connected to the row selection circuit 140 at a contact A. The fuse circuit 120 is connected to the row selection circuit 140 at the contacts B and C. The signal inputs 101 and 102 are connected to the input terminal of the pre-decoding circuit 100. The output of the row selection circuit 140 is connected to outputs 141 and 142. Figure lb is a schematic diagram of the row decoding circuit 10. When the general array row becomes invalid, the general array row will not select the general array row, but will select the redundant array row. When the unique array and section addresses are decoded, the pre-decoding circuit 100 will enable the terminal A »When the fuse 131 is blown, the fuse circuit 120 will activate the selection of the extra array rows through the terminals B and C. The control signal PU121 is provided by a power-up circuit; at the beginning of the power-on, the control signal PU is kept at a low potential to lock the contacts B and C, and then boosted to Vcc. Row selection circuit 140, whose input is connected to contacts A, B, and C, enabling CS output signal 141 or CRCS output signal 142 to select the Chinese paper standard (CNS) A4 specification (210X297 mm) for this paper size ) ^ —- ^^ 1 HI m HI HI. 1 ^ 1 1 ^ 1 in ϋ m-'. (Please read the notes on the back before filling out this page) A7 B7 V. Description of the invention (4) Array rows or redundant A plurality of pre-decoded input signals 102 of the array row are fed into the NAND gate. The output of the NAND gate 110 is connected to an inverted closed pole and an N-channel transistor 1M. The inverter is powered on: Zhao Er 3 is connected to the SEC input minus 101, and its source is connected to contact a. The p-channel transistor 113 is connected in parallel with the channel transistor 112. The electrode called 114 is connected to terminal A, and its source is connected to the reference electric mill terminal ^ ground terminal pre-decoding circuit type pre-solving pu input signal 121 into the p-channel electric crystal Zhao 13〇 gate. The source of p-channel transistor 130 is connected to the reference terminal of the power source, and its drain is connected to fuse m. The other end of the fuse 131 is connected to the ground terminal. The source-drain of the p-channel transistor 132 is connected between the power reference terminal Vcc and the drain of the p-transistor 130. The input of the inverter 133 is also connected to the drain of the p-channel transistor 130. The output of the inverting Shaw 133 is fed back to the gate of the p-channel transistor 132. The terminal b is connected to the terminal of the p-channel transistor 130, and the terminal C is connected to the output of the inverter 133. Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives 11. ϊ ^-*-, * (Please read the notes on the back before filling out this page) End point A is connected to one of the 152 input terminals and the N-channel transistor 151 Gate. Terminal B is connected to the gate of the N-channel transistor 150. Terminal C is connected to the other input of NAND gate 152. The output terminal of NANDp4 152 is connected to the cs output terminal 141 of the row selection circuit. The CRCS output terminal 142 of the row selection circuit is connected to the tap of the N-channel transistor 151, and the source of the N-channel transistor 151 is grounded to complete the row selection circuit. When the failure address was selected in the array, the fuselage l3l was used by the paper and silver button of the National Bank of China (CNS) Continued ^ (21GX297) by the Central Government Bureau of the Ministry of Economic Affairs, printed by the consumer consumer cooperative A5 B7 5. Description of the invention (5) When the signal PU is pulled down, the transistor 130 will be turned on and the potential of the terminal B will be forced to rise. The inverter 133 raises the potential of the gate and the terminal C of the transistor 132. Transistor 150 is thus turned on, and NADN gate 152 will re-operate. CS output 141 is now disabled, CRCS output 142 is enabled because it includes the output of AND gates of transistors 150 and 151. Transistor 132 will lock the high potential at contact B and the low potential at contact C by dumping Vcc to contact B, respectively. This will cause permanent failure to select the failure row, even if the PU rises to Vcc after the power is increased. When the SEC input signal 101 and all the pre-decode input signals 102 are at the positive potential, the output terminal A will also be at the positive potential, which means that the designated line will be selected. If the fuse 131 is blown, the CS output 141 will be enabled (negative potential), and the general array selection operation and the CRCS output 142 will be disabled (positive potential) to prevent positive selection to the extra rows. If the fuse 131 is blown, the CRCS output 142 will be enabled (negative potential), allowing selection of extra array rows. At this time, CS output 141 will be disabled (positive potential), and the general array row will not be selected. Please refer to FIG. 2, which shows a row decoder array 20. The row decoder array 20 is composed of a plurality of row decoder circuits 10 and CRCD circuits 201 whose numbers are CD0, CD1 to CDn. Input 211, which The reference number RSEC 'is an input to the CRCD circuit 201. The circuit 201 includes a P-channel transistor 202 whose gate is connected to the RSEC input 211, whose source is connected to Vcc, and whose sum is connected to the CRCD output 212. CRCS-WIRE output 221 is the result of performing WIRE-OR on all CRCS rounds 142 and CRCD output 212. When Hanka enters this paper, the size of the paper is applicable to China National Standards (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page). Packing. --- Order A7 B7 V. Invention Description (6 ) 211 When a negative pulse is input, a CRCD circuit 201 having a pull-up transistor 202, a small p-channel transistor 203, and an inverter 204 will disable the extra array rows. If the row address selects an extra array row, the contact CRCS-WIRE output 221 will be pulled down to enable the extra array row. Once any CRCS output 142 is grounded, the function of WIRE-OR is to force the CRCD-WIRE output 221 to ground, so the extra array will be selected. This method of logically ORing all of the redundant row select lines will allow any row decoder that may be ineffective for the relevant array to address the redundant array without the need for any addressing circuits or other circuits. It must be used in conjunction with the data line equalization (eqUaiization) function of the RSEC signal to achieve the purpose of disabling redundant array lines. When the address changes, the address transition detection (ATD) control signal enables the data line equalization. The ATD control signal will force the rSEC signal to a negative potential to set the CRCS-WIRE potential to be high in any period. The circuit 10 will determine the final state of the CRCS-WIRE potential. Will be pulled low 'otherwise it stays at high potential, as discussed earlier. Ministry of Economic Affairs, Central Government and Consumers Cooperatives, India Cooperative Policy n ^ i- nn HJ— HH -IJ. —T ^ im · 1 II 1-- (Please read the note on the back before filling out this page) Now refer to Section 3 The circled semiconductor memory array combination 30 includes a plurality of arrays 300 (addresses thereof are marked from 0 to η) and redundant arrays 305 that are identical to the array 300 in any respect. Each array is composed of rows of array units sharing the same address. The semiconductor memory array combination 30 further includes a row decoder array 20, a sense amplifier array 320, and a sense amplifier array output 301 as shown in FIG. The row decoder circuits 10 each have their opposite arrays, and the redundant arrays correspond to the CRCD circuit 201 with a CRCS-WIRE output 221. For the resolution of the paper, use the Chinese national standard (CNS > A4 size (210X297mm) A7 V. Description of the invention (7) The array selected by the array 20, including the extra _ sense amplifier array will be amplified. Will be read The inductive amplifier array includes a plurality of inductive amplifier arrays. Each inductive amplifier has a plurality of input and output arrays connected to the control signals of the array and output. The output from the row decoder array includes arrays that are equal in number to each array. Dequeuing lines. Each output line is the result of an "OR" logical operation performed on all arrays by an array unit. That is, each single "WIRE-OR" operation of the array. JI η dry π inverse «二 :: 考 第A semi-conducting semi-conductor memory device 40 includes a plurality of identical array combinations 30 in the third circle, and the number of these array combinations is denoted by ^ N. The semi-conductor wants to transfer the memory vessel data to the host when the memory device turns out. The number of output lines of the memory ship of the Fengdao ship is equal to the combined array or the array unit in the row of 305. Each round of the outgoing line 401 of the semi-conductive ship is one of the output 301 of the sense amplifier array. The result of performing "WIRE-OR" logical operation on all the open combinations. Outfitting of the Shellfish Consumer Cooperative in the Ministry of Economic Affairs (Please read the precautions on the back before filling this page) Please refer to Figure 6 ' The block diagram of the method of the present invention, block 601, shows the steps of providing a row decoder. Each row decoder is related to an array, and it provides a row selection line to select data from the array. Each row decoder also provides redundancy. Row selection line to select data from the redundant array. Block 602 performs a delayed, or, action on all redundant row selection lines. When an invalid row in the array is selected, the fuse in the scorpion circuit is deactivated by the row. It has been burned out (as shown in block 603), and the input line PU of the decoder for the row of the invalid array will be pulled down at the beginning of the power-on to create a permanent non-selection. ) A4 size (210X297 mm) A7 printed by the Central Government Bureau of the Ministry of Economic Affairs and Consumer Cooperation Du printed A7 _B7__ V. Description of the invention (8) Box 604 shows the selection line for the invalid array. At this time, in block 605, the redundant row selection line is enabled by pulling it down to logic "zero." By providing a logical OR method such as in block 602, the redundant row selection line of each row selection circuit is pulled down. In this way, redundant arrays with different I / Os can be selected, as shown in block 606. The logical ORing of the redundant row selection lines of each row selection circuit will allow any row of decoders, and its associated array may be invalid. The additional array is addressed without the need for other addressing circuits. The advantages of the above-mentioned circuit and method of the present invention are: (1) a new row decoder is provided; (2) adjacent cells in the same array are arranged to have the same row Address, that is, cells with the same address will be read out at the same time; and (3) blowing the fuse in the row decoder will disable the normal but invalid row, and enable the extra rows . The above methods and circuits can be applied to SRAM or DRAM. The disadvantages of the conventional technology that can be prevented by the present invention are as follows: (1) using additional line decoders; (2) requiring additional sense amplifiers; (3) requiring redundant IO signals (XIO); and (4) using Complex XIO / IO multiplexers and conventional technology structures are difficult to implement, will take up chip area, and cause additional accumulation layers. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. 10 This paper ruler is applicable to China National Sample Rate (CNS) A4 now (210X297 mm) Hire 1 ^ 1 nl · n 11. ^ N-^, T,--»(Please read the notes on the back before filling in this page)